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authorRonald G. Minnich <rminnich@gmail.com>2006-05-02 03:07:11 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-05-02 03:07:11 +0000
commitd3ba4aaa245b1af50f70443ba01ec0baf883995f (patch)
tree86ef1da57a3c72ff0c83f8429b74d13a6c1cb7b6 /src/mainboard
parentae3cbe951b414d9c2d2338f77e00132f7251cf94 (diff)
Fall back to pre-broken settings and setup for GX2.
We lost a few things, but this is still worth it. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/rumba/auto.c20
-rw-r--r--src/mainboard/olpc/rev_a/Config.lb1
2 files changed, 20 insertions, 1 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index fbc272ffd0..b3a9b839ee 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -102,6 +102,22 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
+static void msr_init(void)
+{
+ /* total physical memory */
+ __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
+
+ /* traditional memory 0kB-512kB, 512kB-1MB */
+ __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
+ __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
+
+ __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
+ __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
+
+ /* put code in northbridge[init].c here */
+}
+
+
static void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
@@ -109,6 +125,8 @@ static void main(unsigned long bist)
};
SystemPreInit();
+
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
@@ -122,6 +140,8 @@ static void main(unsigned long bist)
sdram_initialize(1, memctrl);
+ msr_init();
+
/* Check all of memory */
//ram_check(0x00000000, 640*1024);
}
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
index 8c5d98388a..a7962f51d0 100644
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ b/src/mainboard/olpc/rev_a/Config.lb
@@ -133,7 +133,6 @@ chip northbridge/amd/gx2
device pci 1.0 on end
device pci 1.1 on end
chip southbridge/amd/cs5536
- register "enable_gpio0_inta" = "1"
device pci d.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller