summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2024-09-24mb/google/brya/var/vell: Disable I2C6 controllerSubrata Banik
This patch disables unused I2C6 controller for the 'vell' variant of the 'brya' mainboard. BUG=b:352330495 TEST=Able to build and boot google/vell. Change-Id: I5b39e44bb64bf2285c962249c0d94a8d5325f0c7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-23mb/amd/birman_plus: Fix menuconfig option for EC firmware pathAna Carolina Cabral
Menu option wasn't showing due to wrong config flag. Change-Id: I30592a8c3e57017473511366a8cf11928e55b5e9 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-23mb/google/rex: Create kanix variantTyler Wang
Create the kanix variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:368501705 TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_KANIX Change-Id: Id74a084ed3cebb65625166e3098f43e41a63f5f9 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84432 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-23mb/google/nissa/var/nivviks: Update the power resource for NVM and VCMSowmya V
Earlier change (https://review.coreboot.org/c/coreboot/+/84019) pushed to resolve the privacy LED blinking issue regressed the camera autofocus functionality. This change updates the power resource for NVM and VCM in line with the tivviks schematics to fix the issue. BUG=b:365899407 TEST=Build and boot tivviks. Verified the Autofocus and all the camera basic sanity tests. Change-Id: Id3e256d59982ac176844e289f18ee450079704b9 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-23mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186Yang Wu
Compared to MT8186, MT8186T requires initializing the PMIC MT6319 in the DTS file, which necessitates using different SKU ID to distinguish between the MT8186 and MT8186T. For MT8186, factory pre-flashed 0x7fffffff as unprovisioned SKU ID and kernel can use the corresponding DTS file. To make MT8186T functional on unprovisioned devices, change the SKU ID to 0x7ffffeff, so that the correct DTS file will be selected by the payload. BUG=b:365730137 TEST=1. Pre-flashed 0x7fffffff and boot OS. 2. Check OS boot normally by 0x7ffffeff. BRANCH=corsola Change-Id: I91306d3abd508e104851916882fb36a4fd302036 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84342 Reviewed-by: Knox Chiou <knoxchiou@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-09-23mb/google/fatcat: Update Flash Map layoutSubrata Banik
This patch updates the fatcat flash map layout to accommodate the growth in Panther Lake IFWI blobs over Meteor Lake. Release FMD: SI_ALL: 8MB -> 9MB SI_BIOS: 24MB -> 23MB RW_UNUSED: 4MB -> 3MB Debug FMD: SI_ALL: 8MB -> 9MB SI_BIOS: 24MB -> 23MB RW_UNUSED: 3MB -> 2MB TEST=Able to build google/fatcat inside chroot. Change-Id: I8febb4df5d3b3eb07ebff8e56a1ce2dfd2f52e7d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-09-22mb/gigabyte/ga-b75-d3v: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I6012fd948b4350bda7af5390badac737553fa872 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84430 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-20mb/intel: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I08881e3fb25abca8c34a04b3bea6534c0dbf391a Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84424 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-20mb/google/dedede/var/beadrix: Add LTE only daughterboard supportKevin Yang
Due to beadrix DB has C1 port before, and add FW_CONFIG without C1 port for LTE sku. BUG=b:364431483 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Set fw config to DB_PORTS_LTE and check 1.fw_config match found: DB_PORTS=DB_PORTS_LTE <= show LTE present message 2.USB3 port 3: enabled 1 <= LTE port enable Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84232 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-19mb/google/brox: Remove psys related implementationSowmya Aralguppe
psys is not an optimal solution for no/low battery boot. Hence remove function and macros related to psys implementation. BUG=b:335046538 BRANCH=None TEST=Build and boot on brox board Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84397 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-19mb/gigabyte/ga-945gcm-s2l: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I01db9dad872cd4c9238b6c6aac73f3e6367710a4 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-19mb/system76/oryp9: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I3870bcd2482e55a5abcbd27cd0be18f25a35afbc Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84415 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-19mb/system76/mtl: Enable gfx register for GMA ACPITim Crawford
Add gfx register so GMA ACPI data is generated. Fixes brightness controls on Windows. Change-Id: I10948fb2ba670ba5232f1b116acdd1820ad0c07d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-19mb/google/nissa/var/riven: enable WIFI SARDavid Wu
According to the CL:chrome-internal:7651905, Riven will use the fw_config to separate SAR setting. CNVI + ID_0 --> wifi_sar_0.hex for WIFI6 PCIE + ID_1 --> wifi_sar_9.hex for WIFI7 BUG=b:366060274 TEST=build, enabled iwlwifi debug, and check dmesg as below. iwl_sar_fill_table Chain[0]: iwl_sar_fill_table Band[0] = 132 * .125dBm iwl_sar_fill_table Band[1] = 136 * .125dBm iwl_sar_fill_table Band[2] = 136 * .125dBm iwl_sar_fill_table Band[3] = 136 * .125dBm iwl_sar_fill_table Band[4] = 136 * .125dBm iwl_sar_fill_table Band[5] = 144 * .125dBm iwl_sar_fill_table Band[6] = 144 * .125dBm iwl_sar_fill_table Band[7] = 144 * .125dBm iwl_sar_fill_table Band[8] = 144 * .125dBm iwl_sar_fill_table Band[9] = 144 * .125dBm iwl_sar_fill_table Band[10] = 144 * .125dBm iwl_sar_fill_table Chain[1]: iwl_sar_fill_table Band[0] = 132 * .125dBm iwl_sar_fill_table Band[1] = 136 * .125dBm iwl_sar_fill_table Band[2] = 136 * .125dBm iwl_sar_fill_table Band[3] = 136 * .125dBm iwl_sar_fill_table Band[4] = 136 * .125dBm iwl_sar_fill_table Band[5] = 144 * .125dBm iwl_sar_fill_table Band[6] = 144 * .125dBm iwl_sar_fill_table Band[7] = 144 * .125dBm iwl_sar_fill_table Band[8] = 144 * .125dBm iwl_sar_fill_table Band[9] = 144 * .125dBm iwl_sar_fill_table Band[10] = 144 * .125dBm Cq-Depend: chrome-internal:7651905 Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84339 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-18mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl5}: Enable real-time tuning in FSPMario Scheithauer
The real-time feature should also be activated for all mc_ehl mainboards, as it has already been done for mainboard mc_ehl1. It improves performance in the real-time environment for these mainboards. Change-Id: I04859b2f32bc11344b0620925f2414e7a6df625e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84391 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18mb/google/brox: Switch USB-C port locationsJameson Thies
The ordering of the USB-C port locations is swapped. When facing the left panel, the correct ordering is port 1 (left) then port 0 (right). Swap the positions of the two USB-C ports to their correct values. BUG=b:349822718 TEST=Booted to OS, confirmed correct physical_location at /sys/class/typec. Change-Id: I98e3042c64aba885b602c99916734c2dbb9d66bd Signed-off-by: Jameson Thies <jthies@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84403 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18mb/facebook/fbg1701: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I60bb9e7df368b786e17bb49a6f35d27372fd21de Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84394 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18mb/msi/ms7e06: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I5cf34d8c4e27835d126eb66f2015d2e9d93b700f Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2024-09-17mainboard/google/{brox,brya}: Drop redundant CRASHLOG configSubrata Banik
This commit drops redundant CRASHLOG option for the brox and brya mainboards as SOC_INTEL_CRASHLOG config is now selected by the Alder Lake SoC directly. TEST=Able to build and boot google/brox w/o any functional impact of the crashlog feature. Change-Id: I83859d6e61a151d6930785df3466c185c69e8e66 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84366 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-17mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switchVarun Upadhyay
This patch configures the GPIO pins for ISH to notify EC about the tablet mode change in accordance with schematic_20240607. BUG=b:347811875 TEST=Build and boot google/trulo. Placed the device in tabletmode & on EC console,"tabletmode" command shows "tablet mode". Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-17mb/google/brya: Drop redundant entries of crashlog configSubrata Banik
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG) entry from BOARD_GOOGLE_BRYA0 and BOARD_GOOGLE_BRASK. BOARD_GOOGLE_BRYA_COMMON already selects a crashlog config, and brya0/brask board eventually selects the BOARD_GOOGLE_BRYA_COMMON config, making SOC_INTEL_CRASHLOG redundant. TEST=Successfully built and booted google/brya0. Change-Id: Iaff7954d4dafb4c6ca72a1521dfb434fb36b495a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84364 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-17mb/google/brox: Drop redundant entries of crashlog configSubrata Banik
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG) entry from BOARD_GOOGLE_BASEBOARD_BROX. BOARD_GOOGLE_BROX_COMMON already selects a crashlog config, and brox baseboard eventually selects the BOARD_GOOGLE_BROX_COMMON config, making SOC_INTEL_CRASHLOG redundant. TEST=Successfully built and booted google/brox. Change-Id: Idcb03d13ee3943f188246663d47f47cb8afccbd9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84363 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-16mb/google/volteer: Fix USB port definitionsMatt DeVillier
Commit bc8f5405b542 ("tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope") not only moved the USB port definitions under the XHCI device reference, but also combined multiple register definitions. In doing so, it broke the inheritance from the baseboard, since the variant overridetree registers now replaced the entire usb2_ports/ usb3_ports structs, rather than replacing individual array elements therein. This resulted in any USB ports inherited from the baseboard and not overridden by the variant being non-functional as they were not included in the resulting combined devicetree. To fix this, return to overriding individual array elements in the usb2/3_ports structs. TEST=build/boot google/drobit. Verify all USB ports present and functional. Verify mainboard/static.c in built shows all ports. Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84348 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-09-16mb/google/brox/jubilant: Update cpu power limit settingsRen Kuo
1)Modify jubilant cpu power limit setting depend on the brox baseboad settgins,refer to CL: https://review.coreboot.org/c/coreboot/+/83752 2)Update PL1,PL2, and PL4 value from jubilant thermal design PL1 = 15W PL2 = 41W PL4 = 87W BUG=b:364441688 BRANCH=None TEST=Able to successfully boot on jubilant photo SKU1 and SKU2 boards with AC w/o battery. Test on AC 65W and 45W w/o battery,and check the PL values. Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-09-14mainboard/intel/avenuecity_crb: Update full IIO configurationShuo Liu
Change-Id: I88baa159475ac57ec6a2a638ab84f76a6af4fe82 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84318 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13mb/google/brox: Fix booting to kernel without batterySowmya Aralguppe
When battery is disconnected and only adaptor is connected higher PL2 power draw causes cpu brown out and system does not boot to kernel. To avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome power spikes from SoC during boot. Remove Psys implementation as it impacts active state platform performance. BUG=b:335046538,b:329722827 BRANCH=None TEST=Able to successfully boot on 3 different Brox proto2 SKU1 and SKU2 boards with 65W, 45W and 30W adaptors for 3 iterations of cold boot. Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-13mb/google/brask/var/bujia: Fix PSYS voltage settingShon
It return 0 when google_chromeec_command() on success, so get_input_power_voltage() should return adaptor voltage instead of psys_config default value. BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= cbmem -c | grep -i PsysPmax Change-Id: I848c92752b7a7b53f47c6296aad0bdda20e9b0bd Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84333 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-12mb/google/brox: Set PCIE WLAN bluetooth companion deviceKarthikeyan Ramasubramanian
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:362672785 TEST=Build Brox firmware and boot to OS. Ensure that the BRDS table is populated under the right ACPI device scope. Scope (\_SB.PCI0.XHCI.RHUB.HS10) { Name (BRDS, Package (0x02) { 0x00000001, Package (0x0A) { 0x00000012, 0x00000001, 0x00000001, 0x7C, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70 } }) } Change-Id: I9a74a995bca8d412b85c243c7f2f98c9917b5e76 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84296 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com>
2024-09-12mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPUKarthikeyan Ramasubramanian
Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:363854853 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I386f8e88a5af661b1f4c04d2e2a34cd181608bd8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: <srinivas.kulkarni@intel.com>
2024-09-12soc/mediatek: Remove redundant struct pad_func and PAD_* definitionsYidi Lin
Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch also refactors the PAD_* macros by, - Repurposing PAD_FUNC and dropping PAD_FUNC_SEL. - Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit initialization. BUG=none TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84222 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-12mb/google/brox/variants/brox: remove PL4 value modificationSumeet Pawnikar
Remove PL4 value modification based on PsysPL3 value. BUG=None BRANCH=None TEST=Built and boot on brox system Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Ic7fbc6386769aa9f76a8665a742c97dfd790fd1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83662 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-11mb/google/brox/var/lotso: Update verb tableJian Tong
Correct the number of NID entries. BUG=b:349996984 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I5f5553a5d8014f957d6b89ac4c1039594817bf32 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84184 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-11mb/google/brox/var/jubilant: Enable ASPM for PCIe4 SSD of CPURen Kuo
Enable ASPM of CPU PCIe4 for SSD to improve power consumption. BUG=b:364441213 BRANCH=None TEST="sh -c 'lspci -vvnn || lspci -nn'" 01:00.0 Non-Volatile memory controller LnkCtl: ASPM L1 Enabled Change-Id: I4380bb8748f2847b1824e20edb19578c7aedfe4f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-11tree: Use boolean for dmi_power_optimize_disableElyes Haouas
Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11tree: use boolean for hybrid_storage_modeElyes Haouas
Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-10tree: Use boolean for lpss_s0ix_enableElyes Haouas
lpss_s0ix_enable is already defined as boolean: `git grep lpss_s0ix_enable $(find -type f -name "*.h") src/soc/intel/apollolake/chip.h: bool lpss_s0ix_enable;` Change-Id: I34bd568defe202daaad6136b9c184bc292a226b3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-09-10mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPUWentao Qin
Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:364484621, b:361828368 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage w/o this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ ``` w/ this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+ ``` Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84241 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/starlabs/starbook/adl: Add USB ACPI to devicetreeSean Rhodes
Change-Id: I7050a4d12efd65c7026abf3e45961e2061b7170a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10mb/starlabs/starbook/adl: Remove PMC GPIO routingSean Rhodes
These aren't used so remove them Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10mb/starlabs/starbook/adl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10mb/dell/snb_ivb_latitude: Move early_init.c out of variantsNicholas Chin
Now that the USB configs are in the devicetree, only the bootblock_mainboard_early_init function remains in early_init.c. It is identical between every variant except the E6230, which enabled fewer decode ranges in the LPC_EN register. Enabling the additional decode ranges probably shouldn't cause issues, so go with the majority. TEST=Timeless builds do not change with the exception of the E6230. Change-Id: Ic43915888f5893652991b7402ebab3bd3a2cf278 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-10mb/google/nissa/var/teliks: Update eMMC DLL tuning valueszengqinghong
Update eMMC DLL tuning values for improved initialization reliability. BUG=b:361013271 TEST=Cold reboot stress test over 2500 cycles Change-Id: Icd1f9c7bdec2bc99152a13ac4ce0724a26718a52 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84248 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/google/nissa/var/joxer: Use `DB_USB` to probe conn1 deviceSubrata Banik
Joxer experienced error messages during developer mode entry due to failed USB-C1 probing. This patch adds the `DB_USB DB_1C` probe directive to the `conn1` device in the overridetree, ensuring USB-C1 is only probed when `FW_CONFIG` supports the applicable hardware SKU. This should resolve the error flood seen during dev mode entry on Joxer. BUG=b:364240631 TEST=Able to build and boot google/joxer to OS without any error. w/o this patch: send_packet: CrosEC result code 9 send_packet: CrosEC result code 3 Failed to get PD_MUX_INFO port1 ret:-3 update_all_tcss_ports_states: port C1: get_usb_pd_mux_info failed send_packet: CrosEC result code 9 send_packet: CrosEC result code 3 Failed to get PD_MUX_INFO port1 ret:-3 w/ this patch: No error reported during dev mode entry Change-Id: I8cdefa01409d5a8a75032f30dacde40057e064dd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-09mb/google/zork: Add Kconfig to set IGD UMA allocation via APCBMatt DeVillier
Add a Kconfig choice to select the IGD UMA allocation, which selects a precompiled ACPB binary with the corresponding UMA value set. Default to the previous value (128MB) for non-ChromeOS builds, and 64MB for ChromeOS as that is the value used there. TEST=build/boot google/morphius, verify UMA size changes with selection via dxdiag tool under Windows. Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84237 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-08mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macroNicholas Chin
Use the AZALIA_PIN_DESC macro from include/device/azalia_device.h instead of magic numbers, as well as the enums for each of the register field values. The macros were generated by running util/hda-decoder against the original azalia logs used for the original board ports. TEST=Timeless builds for all variants did not change between main and this patch Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84099 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-09-08mb/google/kahlee: Add Kconfig to set IGD UMA allocationMatt DeVillier
Add a Kconfig choice to select the IGD UMA allocation. Default to the previous value (32MB). TEST=build/boot google/liara, verify UMA size changes with selection. Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84235 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-07mb/google/dedede/var/awasuki: Update touchscreen power sequenceTongtong Pan
Reduce resume time. BUG=b:361728839 TEST=emerge-dedede coreboot chromeos-bootimage & test touchscreen function on awasuki DUT Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84196 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-06mb/starlabs/byte_adl: Add Alder Lake N Byte Mk IISean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/byte-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-06mb/google/brask/var/bujia: Add PSYS settingShon
According to the Intel OPS spec, the DC power from display is 12~19V@8A max. It can't set PsysPmax by unknown voltage, so get voltage by ec command "ectool adcread 4" then calculate PsysPmax value. The OPS display can supply 90W power, configure psys_pl2 to limit the system power to 90W. BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk intel-rplfsp intel-adlfsp coreboot chromeos-bootimage Check adcread value by ectool adcread 4. If get 19540, PsysPmax should be 19540 * 8000 ~= 156 W. Check FSP debug log have the following message. PsysPmax = 156W Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-09-06mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCMWisley Chen
Add control for the 1.2V enable pin in VCM to comply the mipi camera power sequence. 2.8V enable --> 1.2V enable --> reset BUG=b:362386165 TEST=Run ITS test Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84211 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-06mb/google/brox/var/lotso: remove unused cam enable_gpioJian Tong
Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84198 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-06mb/google/brox/var/lotso: disable RTS5227 PCIE L0s supportJian Tong
Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1. lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled. BUG=b:359409425 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84177 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-06mb/google/brox/variants/brox: Update PL1 MinSumeet Pawnikar
Update PL1 Min value from 6W to 15W based on the brox thermal cooling capacity and hardware design. BUG=None BRANCH=None TEST=Build and boot on brox board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-05mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic supportDavid Wu
When world-facing camera is absent, coreboot need to enable GPP_R6(DMIC_WCAM_CLK) and GPP_R7(DMIC_WCAM_DATA) for 3rd dmic support BUG=b:333973512 TEST=Boot google/riven to OS and verify 3rd dmic working properly. Change-Id: I6c8780ce37b5d3987f5cdf6e6e6d0b4896b33230 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84141 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-05mb/google/brox/var/jubilant: Remove STORAGE_UNKNOWN fw_config optionKarthikeyan Ramasubramanian
With `probe unprovisioned` fw_config rule, there is no need to define an explicit STORAGE_UNKNOWN option. Hence remove it. BUG=None TEST=Build Jubilant FW image. Change-Id: I4f6ace4b39a1ee0b63486d3872b20c8da719ae4a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84095 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-04mb/google/brox/jubilant: Tune I2C timingRen Kuo
Tune I2C2 timing: Set falling time to 250ns from 400ns to meet spec: "THIGH>0.6us" BUG=b:362685374 TEST= Build jubilant firmware Measure the i2c signal on jubilant to meet spec: I2C2 THIGH from 0.494 us to 0.76 us Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84143 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-04tree: Use boolean for emmc_enable_hs400_modeElyes Haouas
Change-Id: I41a877ed7f5f3d02904dc939b32996a7f6d45373 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for disable_package_c_state_demotionElyes Haouas
Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for disable_c1_state_auto_demotionElyes Haouas
Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for skip_ext_gfx_scanElyes Haouas
Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-09-03mb/google/brox/jubilant: Generate RAM IDsRen Kuo
Generate RAM IDs of lp5 memory: 1)Hyinx 4GB*4 H58G56BK8BX068 2)SAMSUNG 4GB*4 K3KL8L80CM-MGCT BUG=None TEST=Run part_id_gen tool and check the generated files. Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-09-03mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13Ren Kuo
Modify the FP IRQ pin to GPP_D13 from GPP_F15 from HW change on EVT. The design change to follow the brox's GPE0 routing, and the FP wake source can be routed. BUG=b:363166664 TEST= Build jubilant firmware Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84124 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/lattepanda: Add support for LattePanda MuKunYi Chen
Add initial support for the LattePanda Mu board, which features: - Intel Alder Lake-N N100 processor - Samsung K3LK7K70BM-BGCP, 8GB LPDDR5 memory - Samsung KLMCG2UCTA-B041, 64GB eMMC storage - SO-DIMM 260-pin connector for function expansion This commit includes: - Basic board configuration - Memory initialization - Essential I/O setup - Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file from original BIOS - BIOS download link: https://github.com/LattePandaTeam/LattePanda-Mu located at "./Softwares/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip" Test Environment: - Carrier Board: Lite - Payload: mrchromebox/edk2 - EDK2 Version: uefipayload_202309 Test result Passed: - Windows 11 boot from eMMC - Install Ubuntu 24.04 on NVMe SSD - Ubuntu 24.04 boot from NVMe SSD - USB 3.0/2.0 functionality - Realtek RTL8111H-CG-RH Ethernet - HDMI Display - Audio over HDMI work in Ubuntu 24.04 Known Issues: - S3 sleep mode non-functional - Power-on after shutdown requires power removal - SuperIO UART not detected in Windows 11 - Audio over HDMI not work in Windows 11 - Windows 11 BSOD occurs with NVMe SSD installed: - Stop code: Machine Check Exception - NVMe SSD not working on Windows 11, except when: - KDNet Debugging enabled on NIC during boot - SSD becomes functional in this scenario Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-02mb/google/cherry: Complete PCIe reset in romstageYidi Lin
De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118 Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-02mb/google/zork: Ensure eSPI GPIOs programmed w/o vbootMatt DeVillier
On the non-vboot boot path, eSPI is configured as part of fch_pre_init(), and we need to ensure that the mainboard sets the eSPI GPIOs properly before the common SoC code performs eSPI init. Use the mb_set_up_early_espi() function to set the eSPI GPIOs at the correct time. TEST=build/boot google/zork (morphius), verify keyboard functional. Change-Id: I03efe6def37a018c3de410523be21bf008174e94 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84148 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/zork: Ensure early GPIOs programmed w/o vbootMatt DeVillier
Now that zork can boot without vboot, ensure that the GPIOs set in verstage are programmed in bootblock on the non-vboot path. The eSPI GPIOs will be set in a subsequent patch using mb_set_up_early_espi() since setting them in bootblock_mainboard_early_init() would be too late given when the SoC eSPI init takes place. TEST=build/boot google/zork (morphius) w/o vboot Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-02mb/google/nissa/var/teliks: Add fw_config fields for rtl8852becengjianeng
Add a new fw config field for wifi category as WIFI_6_8852, which is PCIe based. Also, enable WIFI_6_8852 for existing PCIe based wifi port as well as bluetooth port. BUG=b:356434907 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84138 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/nissa/var/teliks: Force audio mute to avoid screen flickcengjianeng
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG=b:360243615 BRANCH=firmware-nissa-15217.B TEST:Verfied on Teliks and cannot reproduce the issue Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84137 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
2024-09-02mb/google/brox: Remove ACPI Power Resource for Bluetooth deviceKarthikeyan Ramasubramanian
Bluetooth driver in kernel requires reset-gpio in current resource settings (_CRS) and device specific data (_DSD) ACPI objects. Hence remove ACPI Power Resource for Bluetooth device so that the concerned ACPI objects get populated. BUG=b:362817900 TEST=Build Brox Firmware image and boot to OS. Ensure that the _CRS and _DSP ACPI objects are filled in the SSDT with the required data. Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x004D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "reset-gpio", Package (0x04) { \_SB.PCI0.XHCI.RHUB.HS10, Zero, Zero, One } } } }) Change-Id: If6e679aa3f4181e7963ac53d0847b1512959b3a7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84135 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-09-02mb/google/brox/jubilant: Update dptf settingsRen Kuo
Update dptf settings from thermal design: 1) Remove fan control and active policy, since fan is controlled by EC. 2) Modify TSRs to 0:DRAM, 1:SOC, 2:Charger 3) Update Pl2 min&max values BUG=None TEST= Build jubilant firmware Generate and check ACPI SSDT.dsl $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2024-09-02mb/cwwk/adl/devicetree: enable all USB portsFelix Held
The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on the mainboard and likely also routes one USB2 port to the m.2 E key slot which is typically used for Bluetooth support when an E key m.2 WIFI + Bluetooth card is installed. This is untested, since I only have the cw-al-4l-v2.0 mainboard, but from looking at the documentation of the version 1 and looking at how things are done on the version 2 this should be correct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-02mb/google/brya: Add romstage early graphics for trulo baseboardSubrata Banik
1) Add all required changes for eSOL support. 2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo. The CSOT (MNC207QS1-1) panel is used for the devicetree. BUG=b:362895813 TEST=On-screen text message seen during MRC training on Trulo SKU1. MRC: no data in 'RW_MRC_CACHE' bootmode is set to: 0 DP PHY mode status not complete DP PHY mode status not complete DP PHY mode status not complete ... Informing user on-display of memory training Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2024-09-02mb/google/brox/var/lotso: Update verb tableJian Tong
Update verb table provided by Realtek on 20240710. Restults: SNR > 90 (spec>=90). BUG=b:349996984 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: Ic4f03d09010efa7e32713b2697d5832255f64317 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83920 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-01tree: Use boolean for s0ix_enableElyes Haouas
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-01tree: Use eist_enable as bool for newly merged filesElyes Haouas
Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84156 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30mb/qemu-{i440fx,q35}: reduce default ROM size to 8 MiBKrystian Hebel
By default, QEMU bails when trying to use bigger images mounted with '-drive if=pflash', which is required to make use of writable flash introduced in CB:82555. This changes both default size in Kconfig as well as FMAP layouts. Since QEMU 5.0.0 it is possible to change the limit of firmware size with `max-fw-size` machine configuration option, up to 16 MiB, as bigger sizes would overlap with IO APIC memory range. Default is still 8 MiB, so it makes sense to have identical default in coreboot. Error thrown by QEMU when trying to use too big ROM: qemu-system-x86_64: combined size of system firmware exceeds 8388608 bytes Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82639 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-08-30mb/qemu-q35/smihandler.c: add support for SMIs on QEMUKrystian Hebel
qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating Intel chipset. In addition, even though it implements SMI_STS register, QEMU never sets any bits in it. As there is little emulated hardware that can be generating SMI, assume that all SMIs come from APM. This source is used e.g. to disable ACPI (which wasn't working until now on QEMU) and SMMSTORE. Tested by invoking SMMSTORE commands from the payload with SMM logging. Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82558 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29mb/google/rauru: Reset USB hub in bootblockYidi Lin
We have to reset the USB hub as early as possible. Otherwise the USB3 hub may not be usable in the payload. This design has been introduced since Cherry. TEST=build pass. BUG=b:317009620 Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29mb/google/rauru: Setup USB host in ramstageMingjin Ge
Add usb host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com> Change-Id: I5d081ff3e7367b87fab5ebdcb148c9005ab583f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-29mb/google/brya/var/nova: Configure scaler I2C GPIOsKenneth Chan
According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL). BUG=b:358439747 TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C. Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-28mb/google/brox/var/lotso: Remove STORAGE_UNKNOWN fw_config optionKarthikeyan Ramasubramanian
With `probe unprovisioned` fw_config rule, there is no need to define an explicit STORAGE_UNKNOWN option. Hence remove it. BUG=None TEST=Build Lotso FW image. Change-Id: Ia170a6e006cb51e95fbaf3efe1106ca907165eca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84094 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-28mb/google/brox: Disable Thunderbolt deviceKarthikeyan Ramasubramanian
This feature is not required in Brox devices. Hence disable the concerned device. BUG=None TEST=Build Brox firmware and boot to OS. Ensure that the concerned device is disabled in the OS. Change-Id: I355852c780c552e6f9b2c28508f53580f392c1b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84093 Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
2024-08-28mb/qemu-i440fx/rom_media: Use MEM_REGION_DEV_INIT() for boot_devNico Huber
`boot_dev` can be const, and we can use MEM_REGION_DEV_INIT() as all the values are known at compile time. Change-Id: Icd3757ba4b5e8bfbee9e9c9d18bf0ee71520a8ac Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84089 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-28mb/google/nissa/var/anraggar: Force audio mute to avoid screen flickSimon Yang
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG:b=357764688 BRANCH=firmware-nissa-15217.B TEST:Verfied on Anraggar and cannot reproduce the issue Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-28mb/google/nissa/var/nivviks: Prevent camera LED blinking during bootSowmya V
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. TEST=Build and boot nivviks. Monitor the camera LED blinking during boot. Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-28tree: Use boolean for "eist_enable"Elyes Haouas
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-08-27mainboard/google/rex: Remove HAVE_ACPI_RESUME for Intel Meteor LakeSubrata Banik
This patch removes the HAVE_ACPI_RESUME config option from the Google Rex mainboard configuration. The Intel Meteor Lake SoC does not support S3 (ACPI sleep state) entry/exit, and attempting S3 validation could lead to abnormal platform behavior. This change ensures that `_S3` is not listed as a valid wake source in the DSDT (Differentiated System Description Table) after booting to the OS. BUG=b:351025543 TEST=Booted google/rex successfully and verified that the `_S3` name variable is not present in the DSDT. Change-Id: I730ade628eea84c60ba003a0c871e729b0ee0a9f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84081 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-27mb/dell: Add Latitude E6230 (Ivy Bridge)Nicholas Chin
This was adapted from CB:22693 from Iru Cai, which was based on autoport. I do not physically have this system. Someone with physical access to an E6230 running version A11 of the vendor firmware sent me the VBT after running the command `intelvbttool --inlegacy --outvbt data.vbt`. This new version of the port has not yet been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Original-Change-Id: I8cdc01e902e670310628809416290045c2102340 Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82153 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/dell: Add Latitude E6330 (Ivy Bridge)Nicholas Chin
Mainboard is QAL70/LA-7741P. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A21 of the vendor firmware. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I827826e9ff8a9a534c50250458b399104478e06c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/dell: Add Latitude E6220 (Sandy Bridge)Nicholas Chin
Mainboard is codenamed Vida. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. The VBT was obtained using intelvbttool while running version A14 (latest available version) of the vendor firmware. Tested and found to boot as part of a libreboot build based on upstream coreboot commit b7341da191 with additional patches, though these do not appear to affect SNB/IVB. The base E6430 patch was tested against coreboot main. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82131 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/dell: Add Latitude E6320 (Sandy Bridge)Nicholas Chin
Mainboard is PAL70/LA-6611P. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A22 of the vendor firmware. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82130 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/dell: Add Latitude E5420 (Sandy Bridge)Nicholas Chin
Mainboard is Krug 14". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A02 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I0283653156083768e1fd451bcf539b4e028589f4 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/dell: Add Latitude E6520 (Sandy Bridge)Nicholas Chin
Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/hp/snb_ivb_desktops: Add 8200 USDT variantRiku Viitanen
Based on autoport. data.vbt extracted from a running system using "intelvbttool --inlegacy" Like with 8200 SFF, OEM firmware write-protects itself, but not the IFD, GBE or ME regions when FDO jumper is applied. Therefore, ME can be shrunken with me_cleaner and BIOS region moved there. Tested: - Internal flashing from the latest endor BIOS (v2.33) - Sandy Bridge Pentium G630 CPU - RAM: 8+0, 8+4, 8+8 1866MHz DDR3 - SeaBIOS 1.16.2, metest86+ v6, coreinfo, nvramcui & tint payloads - libgfxinit txtmode & corebootfb - VGA, DisplayPort (DVI monitor through an adapter) - Gigabit Ethernet - All front and back USB ports - Booting Void Linux - Rebooting - Mini-PCIe WLAN (PCIe) - Both SATA ports: 2.5" & DVD - PS/2 keyboard and mouse - Fan control - TPM settings in SeaBIOS Untested: - Second Mini-PCIe slot (or is it mSATA): connector not present on my unit - MXM graphics Not working: S3: it sleeps for a few seconds and wakes up on its own Change-Id: I1cba7a5e664758eba7ea2ab8a55658b307d1d173 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79583 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/hp: Move compaq_8200_elite_sff_pc into snb_ivb_desktops variantsRiku Viitanen
Tested to still boot, SeaBIOS -> Void Linux Change-Id: I03d57c7e76ccdfccd58b2a6deab4dee87b02503a Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79545 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-26mb/dell: Add Latitude E5520 (Sandy Bridge)Nicholas Chin
Mainboard is Krug 15". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A14 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26mb/dell: Add Latitude E6420 (Sandy Bridge)Nicholas Chin
Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82126 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-26mb/dell: Add Latitude E5530 (Ivy Bridge)Nicholas Chin
Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A21 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26mb/dell: Add Latitude E6530 (Ivy Bridge)Nicholas Chin
Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the vbios obtained using intel_bios_dumper while running version A22 of the vendor firmware, which I then processed using `intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt. This was originally tested and found to be working as a standalone board port in Libreboot, though this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26nb/intel/haswell: Move SPD addresses to devicetreeKeith Hui
Introduce a sandybridge-style devicetree setting for SPD addresses, and use it instead of runtime code in mb_get_spd_map() for all haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all boards except google/slippy. Patch also covers recently added Z97 boards using Broadwell MRC. Also update util/autoport to match. abuild passes for all affected boards. autoport builds, but otherwise untested. Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 02:00:13 +0000