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authorFelix Held <felix-coreboot@felixheld.de>2024-08-10 22:06:41 +0200
committerFelix Held <felix-coreboot@felixheld.de>2024-09-02 08:57:03 +0000
commitd87321c8a5cefdf1fa5d99dbad2c0f3b1efc71b5 (patch)
tree0b07a0755aba73ba8bc32e8722132561fcbd683e /src/mainboard
parent105b5d376fa0adc4212f953756c7cb11252836ed (diff)
mb/cwwk/adl/devicetree: enable all USB ports
The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on the mainboard and likely also routes one USB2 port to the m.2 E key slot which is typically used for Bluetooth support when an E key m.2 WIFI + Bluetooth card is installed. This is untested, since I only have the cw-al-4l-v2.0 mainboard, but from looking at the documentation of the version 1 and looking at how things are done on the version 2 this should be correct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/cwwk/adl/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb
index c4c5e8c132..86a31e759f 100644
--- a/src/mainboard/cwwk/adl/devicetree.cb
+++ b/src/mainboard/cwwk/adl/devicetree.cb
@@ -6,7 +6,10 @@ chip soc/intel/alderlake
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"
register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)"
+ register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"
+ register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader
+ register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)"
register "pch_pcie_rp[PCH_RP(1)]" = "{
.clk_src = 0,