mb/hp/snb_ivb_desktops: Add 8200 USDT variant

Based on autoport. data.vbt extracted from a running system
using "intelvbttool --inlegacy"

Like with 8200 SFF, OEM firmware write-protects itself, but not
the IFD, GBE or ME regions when FDO jumper is applied. Therefore,
ME can be shrunken with me_cleaner and BIOS region moved there.

Tested:
- Internal flashing from the latest endor BIOS (v2.33)
- Sandy Bridge Pentium G630 CPU
- RAM: 8+0, 8+4, 8+8 1866MHz DDR3
- SeaBIOS 1.16.2, metest86+ v6, coreinfo, nvramcui & tint payloads
- libgfxinit txtmode & corebootfb
- VGA, DisplayPort (DVI monitor through an adapter)
- Gigabit Ethernet
- All front and back USB ports
- Booting Void Linux
- Rebooting
- Mini-PCIe WLAN (PCIe)
- Both SATA ports: 2.5" & DVD
- PS/2 keyboard and mouse
- Fan control
- TPM settings in SeaBIOS

Untested:
- Second Mini-PCIe slot (or is it mSATA): connector not present on my unit
- MXM graphics

Not working:
S3: it sleeps for a few seconds and wakes up on its own

Change-Id: I1cba7a5e664758eba7ea2ab8a55658b307d1d173
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79583
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 312 insertions, 0 deletions

diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig b/src/mainboard/hp/snb_ivb_desktops/Kconfig
index 83c784bb42..a1abac3869 100644
--- a/src/mainboard/hp/snb_ivb_desktops/Kconfig
+++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig
@@ -22,6 +22,11 @@ config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
 	select SOUTHBRIDGE_INTEL_BD82X6X
 	select BOARD_ROMSIZE_KB_8192
 
+config BOARD_HP_COMPAQ_8200_ELITE_USDT
+	select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select BOARD_ROMSIZE_KB_8192
+
 config BOARD_HP_COMPAQ_ELITE_8300_USDT
 	select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
 	select SOUTHBRIDGE_INTEL_C216
@@ -58,12 +63,14 @@ config MAINBOARD_DIR
 
 config VARIANT_DIR
 	default "compaq_8200_elite_sff" if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
+	default "compaq_8200_elite_usdt" if BOARD_HP_COMPAQ_8200_ELITE_USDT
 	default "compaq_elite_8300_usdt" if BOARD_HP_COMPAQ_ELITE_8300_USDT
 	default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION
 	default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION
 
 config MAINBOARD_PART_NUMBER
 	default "HP Compaq 8200 Elite SFF PC" if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
+	default "HP Compaq 8200 Elite USDT" if BOARD_HP_COMPAQ_8200_ELITE_USDT
 	default "HP Compaq Elite 8300 USDT" if BOARD_HP_COMPAQ_ELITE_8300_USDT
 	default "HP Z220 CMT Workstation" if BOARD_HP_Z220_CMT_WORKSTATION
 	default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION
diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig.name b/src/mainboard/hp/snb_ivb_desktops/Kconfig.name
index 43464a854e..3402776077 100644
--- a/src/mainboard/hp/snb_ivb_desktops/Kconfig.name
+++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig.name
@@ -3,6 +3,9 @@
 config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
 	bool "Compaq 8200 Elite SFF"
 
+config BOARD_HP_COMPAQ_8200_ELITE_USDT
+	bool "Compaq 8200 Elite USDT"
+
 config BOARD_HP_COMPAQ_ELITE_8300_USDT
 	bool "Compaq Elite 8300 USDT"
 
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/board_info.txt b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/board_info.txt
new file mode 100644
index 0000000000..4b531e3824
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/board_info.txt
@@ -0,0 +1,7 @@
+Category: mini
+Board URL: https://support.hp.com/us-en/product/details/hp-compaq-8200-elite-ultra-slim-pc/5037958
+ROM protocol: SPI
+ROM socketed: n
+ROM package: SOIC-8
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/data.vbt b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/data.vbt
new file mode 100644
index 0000000000..1d97055546
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/data.vbt
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/early_init.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/early_init.c
new file mode 100644
index 0000000000..d2d9762dab
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/early_init.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <superio/nuvoton/npcd378/npcd378.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
+
+void bootblock_mainboard_early_init(void) {
+	if (CONFIG(CONSOLE_SERIAL))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/gma-mainboard.ads
new file mode 100644
index 0000000000..686f7d44db
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP2,
+      HDMI2,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/gpio.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/gpio.c
new file mode 100644
index 0000000000..7f29ddc581
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/gpio.c
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio1 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/hda_verb.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/hda_verb.c
new file mode 100644
index 0000000000..027e4fd306
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0662,	/* Codec Vendor / Device ID: Realtek */
+	0x103c1496,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(2, 0x103c1496),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x99130120),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01813c30),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a11c3f),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x0221101f),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40028101),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80861496,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80861496),
+	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x58560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/overridetree.cb
new file mode 100644
index 0000000000..df10e865f7
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_usdt/overridetree.cb
@@ -0,0 +1,40 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0, 0x52, 0, 0x50}"
+
+	device domain 0 on
+		subsystemid 0x103c 0x1496 inherit
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "sata_port_map" = "0x3"
+			register "usb_port_config" = "{
+				{ 1, 0, 0 },
+				{ 1, 0, 0 },
+				{ 1, 0, 0 },
+				{ 1, 0, 0 },
+				{ 1, 0, 3 },
+				{ 1, 0, 3 },
+				{ 1, 0, 3 },
+				{ 1, 0, 3 },
+				{ 1, 0, 5 },
+				{ 1, 0, 5 },
+				{ 1, 0, 5 },
+				{ 1, 0, 5 },
+				{ 1, 0, 7 },
+				{ 1, 0, 7 },
+			}"
+
+			device ref lpc on
+				chip superio/common
+					device pnp 2e.ff on
+						chip superio/nuvoton/npcd378
+							# Parallel port
+							device pnp 2e.1 off  end
+						end
+					end
+				end
+			end
+		end
+	end
+end