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authorSubrata Banik <subratabanik@google.com>2024-09-21 10:58:38 +0530
committerSubrata Banik <subratabanik@google.com>2024-09-23 02:06:26 +0000
commit44907f28ec3a5daaecdef4d8569cae53cb86d333 (patch)
treedf913bd374cac66e3d243a12b0aed85db4d2cd65 /src/mainboard
parent29394aa78924a03665151428f11a21e79bf2ad61 (diff)
mb/google/fatcat: Update Flash Map layout
This patch updates the fatcat flash map layout to accommodate the growth in Panther Lake IFWI blobs over Meteor Lake. Release FMD: SI_ALL: 8MB -> 9MB SI_BIOS: 24MB -> 23MB RW_UNUSED: 4MB -> 3MB Debug FMD: SI_ALL: 8MB -> 9MB SI_BIOS: 24MB -> 23MB RW_UNUSED: 3MB -> 2MB TEST=Able to build google/fatcat inside chroot. Change-Id: I8febb4df5d3b3eb07ebff8e56a1ce2dfd2f52e7d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/fatcat/chromeos-debug-fsp.fmd6
-rw-r--r--src/mainboard/google/fatcat/chromeos.fmd6
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
index 5b20f00018..f34e495c2d 100644
--- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
+++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
@@ -1,9 +1,9 @@
FLASH 32M {
- SI_ALL 8M {
+ SI_ALL 9M {
SI_DESC 16K
SI_ME
}
- SI_BIOS 24M {
+ SI_BIOS 23M {
RW_SECTION_A 7680K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
@@ -32,7 +32,7 @@ FLASH 32M {
RW_FWID_B 64
}
RW_LEGACY(CBFS) 1M
- RW_UNUSED 3M
+ RW_UNUSED 2M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {
diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd
index 77f5555347..61dd8cc30c 100644
--- a/src/mainboard/google/fatcat/chromeos.fmd
+++ b/src/mainboard/google/fatcat/chromeos.fmd
@@ -1,9 +1,9 @@
FLASH 32M {
- SI_ALL 8M {
+ SI_ALL 9M {
SI_DESC 16K
SI_ME
}
- SI_BIOS 24M {
+ SI_BIOS 23M {
RW_SECTION_A 7M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
@@ -32,7 +32,7 @@ FLASH 32M {
RW_FWID_B 64
}
RW_LEGACY(CBFS) 1M
- RW_UNUSED 4M
+ RW_UNUSED 3M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {