| Age | Commit message (Collapse) | Author |
|---|
|
Enable SBU orientation handling by SoC for both USBC port0 and USBC
port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver,
but that do not flip the data lines. Hence we need to set bits for both
the USBC ports.
BRANCH:None
TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on
nivviks board and verified USBC display is working on both the ports in
normal and inverted connections.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on the latest schematic, replace amp max98357 with max98360.
BUG=b:224692387, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62887
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add wifi sar for galnat/galnat360
Use SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
galnat (sku id:0x140000)*
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
galnat360 (sku id:0x2B0000)*
BUG=b:222008376
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I868a7416a002732736cabea48ce80548ea75e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Volmar does not support Thunderbolt, therefore disable all of the TBT
devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289.
BUG=b:2233193
TEST=Build and run on DUT.
Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Configure GPIOs according to updated schematics.
- GPP_A21 from NC to TCP_DP1_CTRLCLK.
- GPP_A22 from NC to TCP_DP1_CTRLDATA.
- GPP_E22 from DDIA_DP_CTRLCLK to NC.
- GPP_E23 from DDIA_DP_CTRLDATA to NC.
BUG=b:214025396
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This sets EPP value to be 45% for all Adl RVP variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4
2.Select CS35l53 AMP driver for Vell variant.
Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c
Signed-off-by: Shon.Wang <shon.wang@quanta.corp-partner.google.com>
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:224618411
TEST=util/abuild/abuild -t GOOGLE_SKYRIM with and without APCB
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Needed so i2c communication works.
BUG=b:224618411
TEST=build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62874
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This will fix:
> [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50!
BUG=b:224618411
TEST=Compile skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5add694506ad089adcc8961f101bf507bc39a522
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use C code to generate MS0X entry and provide variant hook.
BUG=b:207144468
TEST=check SSDT table has the same entry.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x148)
}
Else
{
\_SB.PCI0.STXS (0x148)
}
}
}
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This was to merge PCIe ACPI code to WWAN device. But, now use recent
_DSD generation changes in FM driver instead. PCie generic driver is
not used for WWAN at this time.
Also, RTD3 devices are moved to overridetree.cb where WWAN is
present.
BUG=b:221250331
BRANCH=firmware-brya-14505.B
TEST=
Check that _DSD is added to WWAN device in SSDT for the variants.
Check that RTD3 is added to WWAN device in SSDT for the variants.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Follow thermal team design to update thermal table.
BUG=b:223492897
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
For galnat platform, support 2nd ELAN touchscreen via SSFC.
Define FW_CONFIG bits 39 - 40 (SSFC bits 7-8)
for touchscreen controller switch.
BUG=b:221002826
TEST=touch screen is functional.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id3501205b147c9dc3c96ce8381a3e7492ae8258e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Modify 15W SOC default power settings for kinox.
- PL2 39W
- PL4 100W
- Psys_PL2 65W
- Psys_imax_ma 5000ma
- bj_volts_mv 20000mv
BUG=b:213417026, b:222599762
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1.Assert eMMC enable pin in bootblock
2.Deassert eMMC reset pin in bootblock
BUG=b:220821454
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Follow the latest schematic change, gpio will match the baseboard.
Return the current table as override.
BUG=b:223677877
TEST=audio is functional on board_0.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Move selects from Kconfig.name to Kconfig so that the configuration is
in one place and not distributed over two files.
Change-Id: I500f6422c1f8975de8b0bcc8b95cba2bcd4ebe27
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Enable PCIe-eMMC bridge for Kinox.
BUG=b:218786363, b:211176722
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters.
BUG=b:221180425, b:222020226, b:221182596
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON`
to indicate and to make it clear that this option serves as base for
others.
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with
`INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical.
Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and
coreboot.rom remains identical.
Change-Id: I54367c7c663ad288ccdcbd4e7289546489a68f30
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is
directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP
firmware successfully.
BUG=b:222188263, b:223906569
TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint
Firmware Test.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.
Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
update the thermal setting value by measurement and
pass the thermal performance test
Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
Using the GPP_F19 as privacy switch for camera in banshee.
BUG=b:223712143, b:216110896
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
C1-state auto demotion feature allows hardware to determine C1-state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.
Also, disabling this feature results in 110 mW power savings during
video playback.
Note that C1state Autodemotion feature is not applicable for ADL-P SoC.
Hence recommendation is to keep it disabled.
BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of c1-state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.
Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.
By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.
During renaming process, this patch also removes unused variables
listed below:
-> SataEnable // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used
Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.
BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.
Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.
This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.
This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
Hoglin and Herobrine (proto1) should share majority of GPIOs.
Conslidating the QUP initializations in mainboard. Also, putting
fingerprint init in a conditional as not all devices will have an FP
sensor.
BUG=b:182963902,b:223826899
BRANCH=None
TEST=booted BIOS on hoglin and check for i2c errors in dmesg
Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
New board introduced to trogdor family.
BUG=b:223101874
BRANCH=none
TEST=make
Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com>
Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
scope enable pin while performing suspend stress and enable pin
works as expected.
test suspend stress 1000 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Pull GPP_D16 to low when suspending, otherwise it will remain active
and use power.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
DDR4 SPD data needs to be 512 byte to comply with the spec.
Though there is no vital timing data used beyond 256 byte there are some
part information which will be used to show the part info in the
coreboot log. If the buffer is too small this log shows garbage.
This patch increases the SPD buffer size from 256 byte to 512 to avoid
side effects.
Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
1. Update override devicetree based on schematics.
2. ALC5682I-VS is for audio codec.
BUG=b:218786363, b:214025396, b:212183045
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The verstage.c file contains PSP verstage specific code. We don't need
it when using x86 verstage.
BUG=b:193050286
TEST=Build and boot guybrush with x86 verstage
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This sets EPP value to be 45% for all Brya variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Update PL1, PL2, and temperature sensor values from thermal team,
as well as, we remove unused temperature sensors according to
baseboard/devicetree.cb and mainboard schematic. After we check
DTT setting, the thermal and performance test pass.
BRANCH=dedede
BUG=b:204229229
TEST=on beadrix, run following commands:
localhost /tmp # cat /sys/class/thermal/thermal_zone*/type
x86_pkg_temp
INT3400 Thermal
TSR0
TSR1
TCPU
localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp
45000
20000
32800
32800
39000
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The one USB2 port on the XHCI2 controller should have the port ID 2.0,
since it's the first USB2 port on that XHCI controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a370132960939bccec4eb69a6590d0880b04137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GFX HDA is the audio controller that provides audio output via the
external display connection, ACP is the audio coporcessor for the on-
board audio codec and XHCI2 is the third XHCI controller that provides
one USB 2.0 port. All those devices are used, so enable them in the
board's devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select GL9750 driver and add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.
BUG=b:223304292
TEST=check GL9750 can get enumerated by kernel 5.15.
01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01)
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Enable pen garage. Pen detect is active low. And wake system when
eject.
BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mappping derived from Skyrim schematic.
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Initialize trackpad on Qualcomm reference boards
BUG=b:182963902,b:223826899
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I93e866d92cf37887a98de88b4b2d768562515670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62226
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In order to copy the PSP verstage logs into x86 cbmem, we need to enable
DEBUG_SMI. This will include the CBMEM console code in SMM. I only
enable DEBUG_SMI when UART is disabled because SMM doesn't currently
save/restore the UART registers. This will result in clearing the
interrupt enable bits and makes it so you can no longer use the TTY.
BUG=b:221231786, b:217968734
BRANCH=guybrush
TEST=Build serial and non serial firmware and verify DEBUG_SMI is set
correctly.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Sets GPIO 42 to high to turn off WWAN DPR
BUG=b:216735313
BRANCH=guybrush
TEST=emerge-guybrush coreboot
make sure GPIO42 is high
Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2.
But it is programmed incorrectly in the concerned ACPI device. Pass the
correct GPIO.
BUG=b:204401306
TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object
contains the right GPIO. Ensure that the screen visibility gets updated
by pressing the privacy screen button.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4.
BUG=b:219831754
Signed-off-by: zoey wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Decrease PSysMax from 13.52 A to 11 A for Moli variant according to its power circuitry, implying Psys_Pmax = 11A * 19.5V = 214.5W
BUG=b:215258941
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Don't return 0x00 when running MWAK as it is not needed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic62eab8ae5319aff37c61fc29d701d9a36ada919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Remove the dependency on Arg0 so PTS always runs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I96c44397d62848231039330a32de781f75bb56bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
|
|
Some non-SoC code might want to know whether or not the CNVi DDR RFIM
feature is enabled. Also note that future SoCs may also support this
feature. To make the CnviDdrRfim property generic, move it from
soc/intel/alderlake to drivers/wifi/generic instead.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
|
|
Based on testing results from the thermal team, they have decided
to update PL1, PL2 and PL4 for U28 SKUs.
BUG=b:221338290
TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Fix stylus UI behavior bug.
1) it appears the kernel's gpio_key driver is not expecting
an IRQ descriptor for the `gpio` property, therefore change
to an active-low input.
2) The wakeup event was configured backwards.
Change list
- Configure GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW".
- Change wakeup_event_action from ASSERTED to DEASSERTED.
BUG=b:220992812
TEST=emerge-brya coreboot chromeos-bootimage and verify pass
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:214415048
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Config VR_DOMAIN_GT's slew rate to 1/8 as well.
BUG=b:204009588
TEST=build and verified by Power team.
Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Disable unused TCSS Port1.
BUG=b:223082190
TEST=Build
Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Enable Acoustic noise mitigation and set slew rate to 1/8
BUG=b:223082189
TEST=build and verified by power team
Change-Id: I256cc57fb54e5d62e22470a01e7efef359d57083
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash
layout for brya is of 32MB size, and nissa is expected to have 16MB SPI
NOR flash. The current composition of AP firmware exceeds 16MB. To get
an estimate of the unutilized region in the current flash layout for
nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware
size to under 16MB and to remove the RW_UNUSED regions from the final
fmd file.
Below table gives the size reduction from brya fmd to nissa fmd:
+----------------+-------------------+---------------+
| Region | Earlier size (KB) | New size (KB) |
+================+===================+===============+
| SI_ME | 5116 | 3772 |
+----------------+-------------------+---------------+
| RW_SECTION_A/B | 8192 | 4344 |
+----------------+-------------------+---------------+
| VBLOCK_A/B | 64 | 8 |
+----------------+-------------------+---------------+
| ME_RW_A/B* | 3008 | 1434 |
+----------------+-------------------+---------------+
| RW_LEGACY | 2048 | 1024 |
+----------------+-------------------+---------------+
| RW_ELOG | 16 | 4 |
+----------------+-------------------+---------------+
| SHARED_DATA | 8 | 4 |
+----------------+-------------------+---------------+
| VBLOCK_DEV | 8 | 0 |
+----------------+-------------------+---------------+
| RW_SPD_CACHE | 4 | 0 |
+----------------+-------------------+---------------+
| RW_NVRAM | 24 | 8 |
+----------------+-------------------+---------------+
| WP_RO | 8192 | 4096 |
+----------------+-------------------+---------------+
| GBB | 448 | 12 |
+----------------+-------------------+---------------+
*Based on LZMA compression on ME_RW_A/B regions. With LZMA compression,
this region can be 1434K. Without this, ~665K will be more in each of
these regions.
Patch: https://review.coreboot.org/c/coreboot/+/62358/
BUG=b:202783191
BRANCH=None
TEST=Build and boot Nivviks.
Cq-Depend: chrome-internal:4584911
Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0324747f936be27ee39e586124005530d5c424b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Discovered this chassis identification number on Dell Precision
T1650 which is much OptiPlex 9010 alike. Precision T1650 is a Mid
Tower (MT) chassis.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2266fe39606b947a3d30a9462377fd56c39c2fa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3487b0ab94e565862ed727e9a91bd1efb364d43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Guard Max Charge EC write in Kconfig so it's only used on
platforms that support it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21
No known issues.
https://starlabs.systems/pages/labtop-mk-iv-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set the GPIO configuration of moli
BUG=b:220821454
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nivviks overridetree to enable port 10 instead
of port 8, which is the external port used for bluetooth with PCIe WLAN.
BUG=b:222595137
TEST=Bluetooth works on nivviks
Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
|
|
Currently the BayHub eMMC controller is only going into its reset
state when the RTD3 sequence is initiated. This causes it to
still consume too much power in suspend states. This CL adds the
power enable GPIO into the RTD3 sequence as well, which will turn
off the eMMC controller (a true D3cold state) during the RTD3
sequence.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 100 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.
BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Mainboards accessing the cr50 over an I2C bus may want to reuse some of
the same firmware version and BOARD_CFG logic, therefore refactor this
logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses
the new tis_vendor_read/write() functions in order to access the cr50
regardless of the bus which is physically used. In order to leave SPI
devices intact, the tis_vendor_* functions are added to the SPI driver.
BUG=b:202246591
TEST=boot to OS on google/dratini, see the same FW version and board_cfg
console prints as before the change.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add GL9750 SD card reader support.
BUG=b:222402409
TEST=Build FW and check device function normally.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ied36719914de214ae7d810f3d03a508e95fbf66a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Disable unused TCSS PCIe port1
BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage
Change-Id: I2bdfdb23d010a1e24c986ab52b5cef6eedcb674e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Vell has a keyboard MCU connected to USB2 port 7. This patch enables
the port.
localhost# usb_updater2 -f
Found device.
found interface 0 endpoint 1, chunk_len 64
READY
-------
start
target running protocol version 6 (type 1)
maximum PDU size: 4096
Flash protection status: 0000
version: prism_v2.0.12137+c4ae1432f5
key_version: 1
min_rollback: 0
offset: writable at 0xc000
Current versions:
Writable prism_v2.0.12137+c4ae1432f5
BUG=b:203664745,b:211496726
TEST=Run 'usb_updater2 -f' on Vell.
Change-Id: Iad2140dbdf5e34332388f3f43b3ede3d22e73087
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
ChromeOS considers the WWAN devices to be untrusted, therefore enable
the new DmaProperty in the WWAN's _DSD to indicate to the OS that these
devices should have IOMMU restrictions applied to them.
BUG=b:215424986
BRANCH=brya
TEST=dump SSDT
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Commit ebf14826
[mb/google/hatch/var/jinlon: Switch to using device pointers]
broke jinlon boards without an electronic privacy screen (EPS) by
disabling the parent device (iGPU) instead of the EPS when determined to
be not present via SKU ID.
Commit c5a3a4a6
[mb/google/hatch (baseboard): add ACPI backlight support]
broke EPS detection by adding a duplicate iGPU device to the devicetree,
resulting in the EPS entry being skipped.
Fix both of these issues by assigning the device alias to the EPS child
device, not the parent (iGPU). Rename the alias for clarity, and combine
the duplicate device definitions for the iGPU.
Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional
in both firmware boot screens and Linux OS.
Change-Id: I0615ce361497abe6872085b0dec83292607e53dd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Commit 017b5c453a72f57ec785da1764939e24651ac5eb
[ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config]
broke tablet mode on google/caroline and cave in mainline Linux kernels
by changing the inclusion of the ChromeEC tablet mode ACPI handler. Fix
this by addding it back (using the updated name guarding the inclusion
of the tmbc ACPI).
Test: build/boot google/cave under Linux 5.16, observe tablet mode
handled correctly.
Change-Id: Ie0ae5b6a61f104b5e973383344d289cc2e2a7b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
BT didn't work due to commit 03c0853f4d58c73.
Commit 03c0853f4d58c73 accidentally set the Bluetooth USB2 port
to "empty", therefore re-enable USB2 port 9.
BUG=b:217238553, b:222238381
TEST=build and verfied BT work/suspend successfully
Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This change is to move MPTS (Mainboard Prepare To Sleep) method from
wwan_power.asl to SSDT.
MPTS is mainboard-specific method, while wwan_power.asl is meant for
WWAN from its name.
Having fixed MPTS method (i.e. DSDT) can not cover the case where device
only presents and certain CBI bit(s) is(are) set.
In Redrix and Brya, there are SKUs with or without 5G, 4G device. For
those with 4G, MPTS method should be different. For those with no WWAN
device, no MPTS is needed.
Having MPTS generating in SSDT also eliminates the need for introducing
Kconfig flags to support different devices in the future.
MPTS method is created inside mainboard_fill_ssdt function in which the
corresponding variant function is called.
This will generate the following for the mainboard:
Scope (\_SB)
{
Method (MPTS, 1, Serialized)
{
Local0 = \_SB.PCI0.RP01.RTD3._STA ()
If ((Local0 == One))
{
\_SB.PCI0.RP01.PXSX.DPTS (Arg0)
}
}
}
Test:
Check the SSDT for MPTS method under \_SB after boot to OS
Use shutdown command and check the GPIO pins from logical analyzer
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add HID driver for i2c-1 for Ilitek touchscreen.
BRANCH=None
BUG=b:187289163
TEST=Build and flash coreboot; confirm an entry for hidraw for I2C-1 for
Ilitek touchscreen.
Change-Id: I9e42c36a35654cf3e2b41f78b209f4b89e8b05bd
Signed-off-by: Rehan Ghori <rehang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
This revert commit acb17fec34a609c5b674ad0d2af04d47800530e2.
This issue was fixed in the OS, therefore the workaround can be
reverted.
BUG=b:210497855
BRANCH=firmware-brya-14505.B
TEST=build coreboot and boot into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ic836e0cf53c2f9d30bd12851be285d864b2256b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
SMMSTORE needs to have 64k size (minimum) and have 64k alignment as
enforced by asserts added in commit 1ba6049
[drivers/smmstore/store.c: Add static assertion based on fmap].
Adjust size and alignment of SMMSTORE region in FMAP to ensure those conditions are met.
Test: build google/morphius without asserts being tripped for above conditions.
Change-Id: Ied04e93379e1507f5e6b2a1b71e4098a4561e5d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
GPP_S6 was accidentally configured twice instead of configuring GPP_S7.
So configure GPP_S7 according to the schematics.
BUG=b:222218450
TEST=WCAM DMIC works on nivviks
Change-Id: I5de36aaa504a8856803c783564162c36416b50b7
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62511
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Infineon TPM 1.2 used on glados boards doesn't use a PIRQ;
Linux only works with 'tpm.tis_interrupts=0" and Windows fails to
init the TPM citing a lack of available resources. With the PIRQ
removed, both Linux and Windows are happy / the TPM is available
for use.
Test: build/boot Linux 5.16.x and Windows 11 on google/chell
Change-Id: I544695505291bbebe062df636cc8ddd139c08c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Change loglevel prefix "BIOS_ERR" to "BIOS_DEBUG".
BUG=b:220639445
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ie3de63fc13e7a5ed6a4b4617542851782fbb6f00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62508
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
After the patch that moved the generation of the PPKG object to
Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Stoneyridge with the other AMD SoCs. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=None, but equivalent change on Picasso was verified to not break
anything on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
After the patch that moved the generation of the PPKG object to
Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Picasso with Cezanne and Sabrina. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=Mandolin still boots successfully to Linux desktop and dmesg
doesn't show any any possibly related problems.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Disabled G2touch driver and add ELAN touchpanel driver for vell.
Due to incorrect BIOS setting, touch screen IC FW can't update and work.
According to ELAN's recommendations, we coreect the ELAN2513 driver's setting and change I2C address to 0x10
BUG=b:221340736
TEST=emerge-brya coreboot and can flash touch screen FW
Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
|
|
Configure GPIOs according to schematics
BUG=b:218786363
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
In order to achieve a stable eMMC interface disable the HS400 capability
of the host controller. This will result in an operating mode of maximum
HS200 (200 MHz single data rate) which leads to a more relaxed timing.
Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
google/brask is using SODIMMs for DRAM. Reading spd data is
surprisingly slow (~170 ms), therefore enable the SPD cache.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=run on the device and measure the boot time decrease.
Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Align the setting with the adlrvp
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and works correctly in the brask
Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
the device could speed up around 150ms with this feature.
Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch removes Rcomp settings. In MRC design, it checks if the
Rcomp settings from the board is 0 or null, if so, it uses the
recommended Rcomp values. Otherwise, it uses the Rcomp settings passed
from the UPD. From the change history of MRC, we're chasing a moving
target. This RCOMP setting in coreboot is an old setting while the
Rcomp settins in MRC are optimized settings. Moving forward, if there
is a new stepping, it might be changed again which increases the
maintenance effort in coreboot. IMHO, we should let MRC to set the
optimized RCOMP values for the design.
BUG=b:219378758
TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and
PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are
filled properly by MRC.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after
warm reboot.
Config GPP_B3 unlocked to make reboot works on primus. Also set
GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power
on sequence.
BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
test reboot 30 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
