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2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/intel/adlrvp: Set half_populated true for ADL-NUsha P
Alder Lake-N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. BRANCH=NONE TEST=Build and boot ADL-N RVP. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62913 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVPMeera Ravindranath
In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, this CL enables both the UFS controller and ISH. TEST=Boot to kernel and check lspci output 00:12.0 Serial controller: Intel Corporation Device 54fc 00:12.7 Mass storage controller [0109]: Intel Corporation Device 54ff Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/intel/adlrvp_n: Disable SATA controllerUsha P
Disable SATA config from devicetree for ADL-N RVP, since we are not planning to use it in chrome config. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-13mb/intel/adlrvp: Disable PM Timer for ADL-NUsha P
Keeping the PM timer enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for ADL-N boards, therefore disabling it. BRANCH=NONE TEST=Build and boot ADL-N RVP. Verify system is entering S0i3 state. localhost ~ # cat /sys/kernel/debug/pmc_core/substate_residencies Substate Residency S0i2.0 0 S0i3.0 13196801 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I44651bf55df8e71a0a5a9a33ecbb8322ecd18575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31Kconfig: Select UDK2017Patrick Rudolph
On platforms using UDK2015 select UDK2017 instead. This allows to drop UDK2015 headers. Tested using timeless builds: The produced binaries are identical. Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-30mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTORSridhar Siricilla
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. TEST=Build the coreboot for adlrvp Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-27mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-NUsha P
Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP. BRANCH:NONE TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-18mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variantsCliff Huang
This sets EPP value to be 45% for all Adl RVP variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-03-15soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC KconfigMichael Niewöhner
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to 512 in the SoC Kconfig and drop it from the mainboard Kconfigs. Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA
coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-02mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee
In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-01mb/intel/adlrvp: Enable eMMC device for ADL-N RVPKrishna Prasad Bhat
Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder Lake N RVP from devicetree. Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-25mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25mb/intel/adlrvp: Add support for MAX98373 codecUsha P
- Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/intel/adlrvp_n: Update devicetreeKrishna Prasad Bhat
Update devicetree according to schematics. TEST=Build and boot Alder Lake N RVP. Change-Id: I9faee1cb3539a0246fc6a87e15b3150533de1ee5 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-10mb/intel/adlrvp: Fix vbt loading errorLean Sheng Tan
When booting ADL RVP, coreboot is unable to load VBT binary as makefile will rename VBT binary to "vbt.bin" when building coreboot.rom. The reason for having this function is that chromeOS has emerge tool to streamline the VBT stitching process to support multiple VBTs for different RVP boards; while we only need 1 vbt for generic non-chromeOS usage. Hence add a chomeos kconfig to guard this. TEST=Able to boot ADL RVP DDR5 with DP display. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-08mb/intel/galileo/reg_access.c: Remove duplicated "ERROR" in log messagesElyes HAOUAS
Change-Id: I1b4e47cb0f0869ef0a62d1fc6adce4a11ed9b999 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-01-31mb/**/Kconfig: Properly override `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`. Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99 Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-28IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS
IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-25soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-22mb/intel/adlrvp: Add missing CAM1 RST GPIO for ADL-NUsha P
Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I79f2206bee5403c3fb1c999918fbd2177d0d07ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/61163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-21soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
The only option to make HECI1 function disable on Elkhart Lake SoC platform is using SBI under SMM mode. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-18mb/intel/adlrvp: Add wake events for AC connect/disconnectKrishna Prasad Bhat
Enable S3/S0ix wake events for AC connect/disconnect on Alder Lake RVP. BUG=None BRANCH=None TEST=Verify board wakes from S0ix on AC connect/disconnect. Change-Id: Iaf92821fd69a59624e58cb8af3896e2b6998723f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-18mb/intel/adlrvp_n: Configure EC in RW GPIOKrishna Prasad Bhat
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). BRANCH=None BUG=None TEST=Issue manual recovery and confirm DUT is entering recovery mode. Change-Id: Ib8b6be9fcda24bd2bb479b5b6c01f24a6e9c7b1f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-17mb/google/brya/variants/*: Add cpu pcie rp flagsTracy Wu
Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs), we need to set cpu pcie rp flags in devicetree now. This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in all intel projects or system will be blocked at PKGC2R with root port LTR not enable. BUG=b:214009181 TEST=Build and DUT (Kano) can enter deeper PKGC state normally. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-17src: Remove unused <cbfs.h>Elyes HAOUAS
Found using: diff <(git grep -l '<cbfs.h>' -- src/) <(git grep -l 'cbfs_allocator_t\|cbfs_load\|cbfs_ro_load\|cbfs_type_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_preload\|cbfs_unmap\|cbfs_prog_stage_load\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_type\|cbfs_file_exists\|cbfs_ro_file_exists\|mem_pool\|cbfs_cache\|cbfs_boot_device\|cbfs_boot_device_find_mcache\|cbfs_boot_device\|cbfs_get_boot_device\|cbfs_init_boot_device\|cbfs_boot_lookup\|cbfs_alloc\|cbfs_unverified_area_alloc\|cbfs_default_allocator_arg\|cbfs_default_allocator\|cbfs_cbmem_allocator\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_load\|cbfs_type_load\|cbfs_ro_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_file_exists\|cbfs_ro_file_exists\|cbfs_mdata\|cbfs_find_attr\|cbfs_file_hash' -- src/)|grep "<" Change-Id: Ib4dca6da1eb66bbba5b6e94fd623f4fcfc2f0741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-16soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-11soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons
Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-10src/mainboard/{hp,intel}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I0345aa22b2330d002c3a4bbe5fbadc57d83d73b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-04src/mb: Remove unused <string.h>Elyes HAOUAS
Change-Id: I5f2710b2034882a24a041d99e37ec364193d85e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-01src: Use 'stdint.h' when appropriateElyes HAOUAS
Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-24mb/google/taniks,vell;mb/intel/adlrvp_n_ext_ec: fix build errorFelix Held
Commit d448f8ce0fe9955e7792f54cc278897152d53590 (drivers/intel/pmc_mux/ conn: Change usb{23}_port_number fields to device pointers) changed the way the pmc_mux/conn driver gets the corresponding USB ports from the devicetree. This change didn't include the corresponding change for the Taniks and Vell variants of the Google Brya project and the Intel adlrvp_n_ext_ec board which probably weren't in the tree at the time the patch referenced above was created. This patch ports the needed change forward to those boards to fix the build of the upstream tree. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-24mb/intel/adlrvp: Configure GPIOs for Alder Lake-NUsha P
List of changes: 1. Add separate file for ADL-N GPIOs 2. Configure GPIOs as per the schematics of ADL-N RVP Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2021-12-23mb: Remove dot from end of non-sentence commentPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,' Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb: Add space before closing comment block keywordPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/intel/adlrvp_n: Add support for ADL-N LP5 RVPKrishna Prasad Bhat
Add support for Alder lake N LP5 RVP with board ID 0x7. Since SPD index 7 is unused earlier, ADL-N will use it. Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-12-23drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman
Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-23mb/intel/{adlrvp,sm}: Remove unused header `helpers.h`Subrata Banik
This patch removes unused header inclusion as <commonlib/helpers.h> from several mainboard gpio definition files. Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae Signed-off-by: subratabanik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-19mainboard: Fix comment about early GPIOsAngel Pons
These boards program the early GPIO table in bootblock, not romstage. Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15mb/intel/adlrvp_n: Add initial code for adl-n variant boardKrishna Prasad Bhat
This patch adds the following list of changes: 1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p devictree. 2. Add support for 2 mainboards as ADL-N board with default EC (Windows SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from adlrvp-p. 3. Add mainboard Kconfig to Kconfig.name file 4. Handle mainboard names in Kconfig file for ADLRVP N 5. Add config options to pick the adlrvp_n devicetree Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15Denverton-NS boards: Drop useless `thermal.asl`Angel Pons
The code in these files is meaningless, and can be dropped. Change-Id: I11571885059e8d5f930f741172c74b25faa09a15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-10mb/intel/adlrvp: Add support for external clock bufferSubrata Banik
ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are connected on the platform, an external differential buffer chip needs to be placed at the platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/brask: Set vGPIO reset typeKane Chen
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207625007 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons
The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-22mb/intel/adlrvp: Use dedicated VBT files for ADL-MBernardo Perez Priego
ADL-M has its own set of VBT files to pick during execution, this will avoid any conflict with other ADL variants. VBT files added at chrome-internal:4138272 BUG=None TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-11-19mb/intel/adlrvp: Enable CPU PCIe RP 2Meera Ravindranath
Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression) causes regression in NVMe boot on ADL-P RVP boards. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17mb/intel/adlrvp: Fix sagv point3 clipping to 4800MhzBora Guvendik
Update board type to 4 as per MRC team's input. This fixes LP5 sagv point 3 being clipped from the expected 5200Mhz to 4800Mhz. TEST=Boot to OS, verify frequency locked. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/intel/adlrvp: Fix S0ix regressionMeera Ravindranath
The following changes are needed to fix S0ix regression on RVP 1) Disable Clk src 3 2) Disable Ext FIVR settings TEST=Boot adlrvp to OS, confirm S0ix is working. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-12mb/google,intel: Add ChromeOS GPIOs to onboard.hKyösti Mälkki
Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11intel/strago: Fix some CHROMEOS guardsKyösti Mälkki
MAINBOARD_HAS_CHROMEOS always evaluates true for this board. The commentary about get_write_protect_state() was wrong, it's currently only called in ramstage. Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/BReka Norman
During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is copied to CSE_RW, so the sizes of these regions need to match. BUG=b:189177538 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-11-09pci_mmio_cfg: Always use pci_s_* functionsNico Huber
When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-11-09ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/intel/adlrvp: Configure EC in RW GPIOAnil Kumar
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). Branch=none Bug=none Test=Issue manual recovery and confirm DUT is entering recovery mode on ADL-M RVP. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01soc/intel/braswell: Set GNVS DPTE via devicetreeAngel Pons
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-10-29Revert "mb/intel/adlrvp: Remove EC region"Bernardo Perez Priego
This reverts commit 0a1602217fd0d60c59a497cb83a23b44cf4973d9. EC region is required in order to provide unified coreboot image for Chrome and Windows SKU RVP's. Also removing EC region causes a regression for ADL-P platforms. With this patch EC region is included back into flash map. Change-Id: I0f7f2b5dd392b08e1978a3b3f3236eac0dab1f12 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-26intel/adlrvp: Add sub-regions to SI_ME in chromeos.fmdFurquan Shaikh
This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20mb/intel/adlrvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: If68c118f22579cc0a3db570119798f0f535f9804 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20mb/intel/adlrvp_m: Enable touchpadBernardo Perez Priego
These changes include ELAN touchpad to ACPI tables and configure GPIO's. BUG=None Test=Boot board, touchpad should be functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-20mb/intel/adlrvp: Remove EC regionBernardo Perez Priego
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ic76c29069beb510dd7620f340e0aab212668c3f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-20mb/intel/jasperlake_rvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_JASPERLAKE_RVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: Ic7552195ed5a3ae6ab8e456d7d38d5539a052009 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-19mb/intel/kblrvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_KBLRVP_COMMON`, which is used as base for each variant. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-19mb/intel/coffeelake_rvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
2021-10-19cpu/intel/speedstep: Constify `get_cst_entries()`Angel Pons
Make the `get_cst_entries()` function provide a read-only pointer. Also, constify the actual data where applicable. Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-18mb/intel/adlrvp_m: Enable retimer force power gpioBernardo Perez Priego
Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain to toggle during a switch from DP Alt to TBT Alt modes. Contrary to DS specifying it may be left unconfigured, hence floating, there are instances seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp). Hence configure it to LOW. Branch=none Bug=none Test=Boot to OS, connect TBT dock which enumerates in DP Alt, Login, TBT dock enumerates in TBT Alt Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-17soc/intel/skylake: switch to common GNVSMichael Niewöhner
Switch to common GNVS. No additional fields to those being present in common GNVS are used by any SKL/KBL device. Thus, they're dropped completely. Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-10-17Skylake boards: Drop setting useless `IRQ_SLOT_COUNT`Angel Pons
The `IRQ_SLOT_COUNT` value is only meaningful when generating a PIRQ table. None of these boards do it, so specifying this value achieves absolutely nothing. Drop it to prevent further useless copy-pasting. Change-Id: I2d63b850c03fc1471c0eef180e8b621311b2c336 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-15mainboard: Drop invalid `VGA_BIOS_FILE` defaultsAngel Pons
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-08mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-M RVPBora Guvendik
This patch enables eNEM flow for ADL-M TEST=Able to build and boot ADL-M RVP using eNEM mode. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04mb/intel/adlrvp{p,m}: Enable dynamic GPIO PMMeera Ravindranath
GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot adlrvp to OS, ensure no TPM timeout errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-01mb/intel/adlrvp: set PL4 value dynamically for thermalSumeet Pawnikar
Set PL4 value dynamically for adlrvp board based on CPU SKUs which is detectable at runtime. These values are based on platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board On 682: Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000) Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/intel/adlrvp: set power limits dynamically for thermalSumeet Pawnikar
Set power limit values dynamically based on CPU TDP and PCI ID of SKU. These values are as per platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30mb/intel/adlrvp_m: correct SSD power sequenceSelma Bensaid
This is to fix SSD detectiong failure in warm boot observed on ADL-M RVP. This patch implements the coreect power sequence: SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-30mb/intel/adlrvp: Update Rcomp target value for DDR4 RVP SKUSubrata Banik
Update to recommended Rcomp drive strength value for DDR4 as per MRC team's input. Additionally, add space around the `targets` array. Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurationsTracy Wu
Add ADLP 242 sku PLx related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-27mb/intel/kblrvp: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/intel/kunimitsu: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/intel/saddlebrook: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-24mb/intel/adlrvp: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by using alias for dptf_policy device. Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-25 16:21:53 +0000