diff options
| author | Usha P <usha.p@intel.com> | 2022-04-07 14:19:43 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-20 09:38:03 +0000 |
| commit | 63eec22a620877d72ac0ccbe6cacaab75b725757 (patch) | |
| tree | 01b50702f742f79d9b7c871afa1fae9660df7350 /src/mainboard/intel | |
| parent | 0f89a113134639cd1af653f08a005427655bce58 (diff) | |
mb/intel/adlrvp_n: Disable SATA controller
Disable SATA config from devicetree for ADL-N RVP, since we are not
planning to use it in chrome config.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_n.cb | 18 |
1 files changed, 2 insertions, 16 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 2b7eca6e5f..57a37016fe 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -54,21 +54,7 @@ chip soc/intel/alderlake .flags = PCIE_RP_CLK_REQ_DETECT, }" - register "sata_salp_support" = "1" - - register "sata_ports_enable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" - - register "sata_ports_dev_slp" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" + register "sata_salp_support" = "0" # Enable EDP in PortA register "ddi_portA_config" = "1" @@ -241,7 +227,7 @@ chip soc/intel/alderlake device ref i2c2 on end device ref i2c3 on end device ref heci1 on end - device ref sata on end + device ref sata off end device ref i2c5 on chip drivers/intel/mipi_camera register "acpi_hid" = ""OVTI5675"" |