diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-03-10 17:53:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-03-15 10:17:25 +0000 |
| commit | 2eb51aace5489b2f2d20e510f19a1e3b17bf1d60 (patch) | |
| tree | 9bf2dcdc8ca37ca5aa4c49a24c0c5e764928d7f1 /src/mainboard/intel | |
| parent | 5730d018d1395cf68c2fe0e795831f6780c734de (diff) | |
{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.
This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/shadowmountain/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/romstage_fsp_params.c | 4 |
3 files changed, 4 insertions, 7 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 5b5cc6b295..8a24529f49 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -73,7 +73,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) case ADL_P_DDR4_1: case ADL_P_DDR4_2: case ADL_P_DDR5_1: - memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated, + memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); break; case ADL_P_DDR5_2: @@ -84,7 +84,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) case ADL_M_LP4: case ADL_M_LP5: case ADL_N_LP5: - memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated, + memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated, &dimms_changed); break; default: diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c index 0951936bdc..eb08d18eed 100644 --- a/src/mainboard/intel/shadowmountain/romstage.c +++ b/src/mainboard/intel/shadowmountain/romstage.c @@ -9,7 +9,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); const bool half_populated = false; bool dimms_changed = false; @@ -19,5 +18,5 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) .cbfs_index = variant_memory_sku(), }; - memcfg_init(m_cfg, mem_config, &lp5_spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &lp5_spd_info, half_populated, &dimms_changed); } diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 33415684ed..22859f62e6 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -40,8 +40,6 @@ static uintptr_t mainboard_get_spd_index(void) void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct mb_cfg *mem_config = variant_memory_params(); const struct mem_spd spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, @@ -49,6 +47,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; bool half_populated = false; - memcfg_init(mem_cfg, mem_config, &spd_info, half_populated); + memcfg_init(mupd, mem_config, &spd_info, half_populated); } |