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2022-07-07mb/google/brya/var/kinox: Configure TDC currentDtrain Hsu
Configure TDC current for VR domains. +-----------+-------+-------+---------+-------------+----------+ | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | +-----------+-------+-------+---------+-------------+----------+ | IA | 2.8 | 2.8 | 80 | 43 | 28000 | +-----------+-------+-------+---------+-------------+----------+ | GT | 3.2 | 3.2 | 40 | 23 | 28000 | +-----------+-------+-------+---------+-------------+----------+ - IA TDC current from 20A to 43A. - GT TDC current from 20A to 23A. - Others comes from 'commit c6d716694272 ("soc/intel/alderlake: Configure the SKU specific parameters for VR domains")' BUG=b:237230877 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ie9cf8975309b57b4189e2b50f37bd61ac0105e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65659 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07mb/google/brya/var/kinox: Support DPTF oem_variablesDtrain Hsu
Enable DPTF oem_variables and override based on charger type. BUG=b:230803675 TEST=1. With 90W adapter, check ACPI object ODVX and oem_variable[0]=1 Name (ODVX, Package (0x06) { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }) 2. With 65W adapter, check ACPI object ODVX and oem_variable[0]=0 Name (ODVX, Package (0x06) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }) Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I78929ecbc9db56aa234b3f46c641d1f2f3b7cba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-07mb/google/brya: Disable SaGV support for agah variantAnil Kumar
agah proto boards with i7 silicon face boot issues due to high power consumption during MRC training. This patch is a temporary WA to run in SAGV disabled mode while the thermal issue is being investigated. BUG=b:234402102 BRANCH=firmware-brya-14505.B TEST=Build CB image and boot on agah board. Change-Id: I431d233b23fb4f5c68117ea380fdec5646b88346 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65300 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-06mb/google/nissa/var/joxer: Add lock gpio pinsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia087b62904fd515bf73960a188b225f1d49197dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65646 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06mb/google/nissa: Select Kconfig to perform CSE FW update in ramstageKrishna Prasad Bhat
Alder Lake-N based nissa boards use compressed ME_RW blobs for CSE FW Update. Choose SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE Kconfig to perform CSE FW sync in ramstage. BRANCH=firmware-brya-14505.B TEST=Perform CSE FW upgrade/downgrade on nivviks. Change-Id: I00630096c52434f44914f3ae82ff043ecf77b80d Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65368 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06mb/google/nissa/var/pujjo: Add lock gpio pinsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I9f0fcf52b6b7d622e4fd182e007de6401856c7fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65645 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-05mb/google/brask/variants/moli: set tcc_offset to 0℃Raihow Shi
Set tcc_offset value to 0 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8d4c631e07873923226683c8aa0cf36cb872e2d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-05mb/google/nissa: Lock gpio pins in fw config for nissa variantsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=check gpios are locked in pinctrl dump. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ieed2d40b0222d8c8c193e0590131f83a5d96add9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-05mb/google/nissa: Lock gpio pins for nissa variantsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=check gpios are locked in pinctrl dump. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I61931b0b2f1f936a672e72c98b83d66ba0059bf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-04mb/google/brya: Disable PCH USB2 phy power gating for crotaTerry Chen
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for primus board. Please refer Intel doc#723158 for more information. BUG=b:237725329 TEST=Verify the build for crota board Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I6dde74c098ba57b7cd66ce7b9ee941b8961ad20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04mb/google/brya/var/kinox: Change HDMI port form DDPC to DDP2ericky_cheng
Modify GPIOs according to SOC_GPIO_Table_0629.xlsx. - GPP_A21 from TCP_DP1_CTRLCLK to NC - GPP_A22 from TCP_DP1_CTRLDATA to NC - GPP_E20 from NC to TCP_DP1_CTRLCLK (Native Function 1) - GPP_E21 from NC to TCP_DP1_CTRLDATA (Native Function 1) BUG=b:237468533 TEST=emerge-brask coreboot Change-Id: I8e7d343731efbfc04304d52a3493ab30b8a739b0 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-07-04mb/google/nissa: Lock PLT_RST_L pinReka Norman
There is a requirement that the TPM RST signal cannot be asserted by software. On nissa this is PLT_RST_L, so lock this pin to prevent it being reconfigured as a GPIO. BUG=b:216671701 TEST=Try to change GPP_B13 from the kernel: $ echo 677 > /sys/class/gpio/export $ echo out > /sys/class/gpio/gpio677/direction $ echo 0 > /sys/class/gpio/gpio677/value $ echo 1 > /sys/class/gpio/gpio677/value GSC console doesn't show "PLT_RST_L ASSERTED" / "PLT_RST_L DEASSERTED" Change-Id: Id5d64b4b028e4f63c4acb05cd8632d0642866688 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65591 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-04mb/google/nissa/var/craask: Enable G2 touchscreenTyler Wang
Add G2 touchscreen support for craaskvin. BUG=b:235919755 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7ade3ac1d135b8b21b09ef335ab7b30ae7a5e2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-04mb/google/nissa/var/joxer: set up gpioMark Hsieh
Set the GPIO configuration of joxer BUG=b:237628218 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I1f7529342fc0800878f875d3641a2f93fbe6009a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-04mb/google/brask/var/kuldax: Add ACPI _PLD custom valuesDavid Wu
This patch uses ACPI _PLD macros to add custom values for USB ports. C0 A2 A3 +----------------+ | REAR | | | | | | | | FRONT | +----------------+ A1 A0 BUG=b:232419500 TEST=emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I5ada4e9b25102a9cfd3b02a2abcd956f6cbc5619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Won Chung <wonchung@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-04mb/google/brya/var/kano: Disable PCH USB2 phy power gatingDavid Wu
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for kano board. Please refer Intel doc#723158 for more information. BUG=None TEST=Verify the build for kano board Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19430a68e1e847e71382781563200a4c88f37a59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-07-04mb/google/brya/var/pujjo: Add GPIO tableleo.chou
Fill GPIO table for Pujjo. BUG=b:235774770 TEST=emerge-nissa coreboot Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I307b8460632f1feae9591200057c0e6471cbab24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65104 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-04mb/google/brya/var/ghost4adl: Update Type-C locationsCaveh Jalali
This updates the ACPI locations of Type-C ports. BUG=b:232806406 TEST=none Change-Id: Ia15e09a58c731a1364a994fadf8df39115fbe7c4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04mb/google/geralt: Add MediaTek MT8188 reference boardRex-BC Chen
Add mainboard folder and drivers for new reference board 'Geralt'. TEST=saw the coreboot uart log to bootblock BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I5e437d46097369bef535ff64e6a693b7cf67f2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65586 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org>
2022-07-01mb/google/rex: Redirect AP UART over LPSS UART 0Subrata Banik
This patch ensures AP UART messages are coming over LPSS UART 0 hence, select required kconfig and program both early and late UART RX/TX GPIOs accroding to the rex schematics dated 06/27. BUG=b:224325352 TEST=Able to see AP UART log over LPSS UART0. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Generate LP5 RAM IDSubrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) BUG=b:224325352 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibcd25ae80d625b623b9a78ff2cd4447e85831cc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65476 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add memory initEric Lai
Add memory init with placeholder to fill in required memory configuration parameters. DQ map and Rcomp can be auto probed by the FSP-M hence, kept it as default. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Able to boot till FSP-M/MRC using MTL simics. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add EC smihandlerEric Lai
Add SMI handler implementation to manage power cycle, power state transition and Chrome EC events. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I10aab8257fce92aaf913a53c0c9fb6c1a4f5dea6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64623 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64622 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable ACPI and add ACPI tableEric Lai
Enable ACPI configuration and add DSDT ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8374a9b528f8dff4e23b6bdb4d1368dfd2c79b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64620 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock, romstage and ramstage. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I51426f9557dafc357fc54a971b6f76fac5323e0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64593 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add entry stubs of each stageEric Lai
Add entry point stubs of each stage for Rex. More functionalities will be added later. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2310e58ab92bdb0ce86a9f7284cc0b3e04a2889f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64591 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add flashmap descriptorEric Lai
Add 32MB flashmap descriptor as below: Descriptor Region -> 0 - 0x3fff (~16KB) CSE Partition -> 0x4000 - 0x8fffff (~9MB) BIOS Region -> 0x900000 - 0x1ffffff (23MB) BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia5ced770bb02c11a9ab39837e66562d2ee22b6e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-01mb/google/rex: Add MTL reference platformSubrata Banik
This commit is a stub for rex, which is a an Intel Meteor Lake-P reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I46bd8d47b370cacbe0a09bbeaccacf7f1d51d8b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62969 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30mb/google/brya/var/gimble: Disable PCH USB2 phy power gatingMark Hsieh
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for primus board. Please refer Intel doc#723158 for more information. BUG=b:237421399 TEST=Verify the build for gimble board Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie66c9679c985215ad7f1a5ae76560b839ea95702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65474 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30mb/google/corsola: Decide EC-is-trusted logic by board revYu-Ping Wu
Kingler and Krabby's rev 0 boards both have Cr50 instead of Ti50. In order to support them with the new firmware where TPM_GOOGLE_TI50 is selected, use the board rev to determine the EC-is-trusted logic. BUG=b:237355198 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I7797eafaa7a35355d241c4ea425a4716a35a7817 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-06-30mb/google/nissa: Remove WLAN power sequencing workaroundReka Norman
CB:63368 added a workaround of driving EN_PP3300_WLAN_X low in bootblock to prevent a kernel crash on warm reboot. The crash has been fixed in the kernel, so remove the workaround. Kernel fix: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3463465/ BUG=b:225261075 TEST=Wifi works on nereid, warm reboot doesn't crash the kernel Change-Id: Idb5547e65ea934954326fcc740b14a83c939432e Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-30mb/google/nissa/var/xivu: Add gpio.c to ramstageIan Feng
Fixes a bug in Makefile.inc. BUG=b:236576117 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2664df961a1fc0cd904a5e742face20c3fc8c3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65450 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30mb/google/nissa: Add fmd for debug FSPKangheui Won
Debug FSP is ~850KiB larger than release FSP and we don't have sufficient space for nissa flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. Note: This fmd will only used for internal testing/debugging and not for the firmware in released devices. BUG=b:231395098 TEST=build with CONFIG_BUILDING_WITH_DEBUG_FSP Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Idb17f003285575e80feb86bb292b95daf0f5b3b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-29mb/google/brask/variants/moli: remove ASPM_DISABLE for I225VRaihow Shi
Disabling the ASPM for I225V will cause I225V suspend fail, so remove ASPM_DISABLE for I225v. BUG=b:235565637 TEST=emerge-brask coreboot and check LAN_I225V sku can boot into OS. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Id4505a713a3d92cb66c189cc2963111b6e90f092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-29mb/google/skyrim: Enable fingerprint sensor in SkyrimMoises Garcia
Add fingerprint device and select UART_ACPI driver. Disable FPMCU until the proper boot segment initializes it. BUG=b:228271993 BRANCH=NONE TEST=Can add fingerprints and unlock the device using them. Signed-off-by: Moises Garcia <moisesgarcia@google.com> Change-Id: I71e1c7d654395284cdec43bb6e5f581e546da36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65299 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-06-29mb/google/brya/variants/nivviks: Enable DDR RFIM Policy for NivviksVidya Gopalakrishnan
DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Nivviks variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=b:237238786 BRANCH=None TEST=Build and boot Nivviks. - Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Iea5c6e0c404efb8231321701ea9282347e01f75d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-06-29mb/google/dedede/var/shotzo: Update devicetree and GPIO tableTony Huang
Based on latest schematic: 1. Update devicetree for USB port description 2. Add touchscreen ILITEK, amplifier ALC1019, codec ALC5682 3. Configure GPIO table to reflect that 4. Remove APW8738BQBI IC so set "disable_external_bypass_vr to "1" BUG=b:235303242, b:236791101 BRANCH=dedede TEST=build Change-Id: I38c8c5b913013d818ac6a26284184c9decdd9f4e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65079 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29mb/google/nissa: Remove gpio lock for garage IRQ pinEric Lai
Kernel driver will en/disable the IRQ when suspend/resume. If lock the pin, driver can't change the status which causes the unexpected behavior. Device will wake when insert the pen. This is workaround until we figure out the correct setting for driver. BUG=b:233159811 TEST=Pen garage wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ifc7b1e52a24c0e7bd54664d59870cb09536ef868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65380 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29mb/google/nissa: Change fw config override to pad_number table basedEric Lai
BUG=b:231690996 TEST=gpios are the same in kernel pinctrl dump. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I67a466fac478b2a3a682451174fbdcdd67816769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-29mb/google/nissa/variant/pujjo: Update devicetree settingsStanley Wu
Based on schematic and gpio table of pujjo, generate overridetree.cb settings for pujjo. BUG=b:235182560 TEST=FW_NAME=pujjo emerge-nissa coreboot chromeos-bootimage Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I47b10d03798004d1f3e398070acb2cbad46900b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-28mb/google/brya/var/skolas4es: use i2c1 for TPM for skolas4esNick Vaccaro
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the skolas4es variant. BUG=b:230773725 TEST=None Change-Id: I12b05cdacdd26bfffff47b7a3fb127aa7778f15d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65493 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28mb/google/skyrim: Add SoC thermal zoneFred Reitberger
The temperature values were taken from guybrush as a starting point for skyrim. BUG=b:230428864 TEST=Boot skyrim to OS and verify thermal zones are populated and working in /sys/class/thermal/ Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I6669b32f5e3dd63c6523f74166089eb4eb2d7848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-28mb/google/nissa: Change pen garage wake to EV_ACT_DEASSERTEDEric Lai
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed. After confirmed with the owner, the expect behavior is only wake when eject the pen. BUG=b:233159811 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7a82e5e8935c9ea27e923661f66809e9169bc86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65379 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-28mb/google/nissa/var/xivu: Add MIPI WFC supportIan Feng
Add MIPI WFC based on schematics BUG=b:236576117, b:235446911 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I85bd2ba187729a55c00369b218ca0414e0162b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-28mb/google/nissa/var/xivu: Modify SPI flash to 16MIan Feng
Follow latest schematic to modify SPI flash to 16M. BUG=b:236576117 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I56be68b962c38d3f885dcf25a0251b8d9ab6ff3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65446 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-27mb/google/brya/var/kinox: Modify ddi_ports_configDtrain Hsu
Modify ddi_ports_config based on schematic Kinox_SCH_20220602.pdf. DDI_PORT_A = DP DDI_PORT_B = HDMI DDI_PORT_1 = Type-C DP DDI_PORT_2 = DP or HDMI BUG=b:233338341 TEST=Boot to Chrome OS and check all display port working Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib2dbb34af1f85585b77638710d3799520c3f016f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-27mb/google/corsola: Add new board TentacruelKane Chen
Add a new board 'Tentacruel', and enable SDCARD_INIT for it. BUG=b:234409654 BRANCH=corsola TEST=none Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ia10efeead575b4e193a73562275a78839415a706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65192 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-27mb/google/nissa: Apply gpio padbased table overrideEric Lai
In order to improve gpio merge mechanism. Change iteration override to padbased table override. And the following patch will change fw config override with ramstage gpio table override. BUG=b:231690996 TEST=check gpios in pinctrl are the same. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3d0beabc2c185405cb0af31e5506b6df94e9522c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-24sc7280: Enable RECOVERY_MRC_CACHEShelley Chen
Enable caching of memory training data for recovery as well as normal mode. We had HAS_RECOVERY_MRC_CACHE selected in the sc7280 Kconfig, but never allocated a RECOVERY_MRC_CACHE in the herobrine fmap so it never worked. Adding RECOVERY_MRC_CACHE and also removing RO_DDR_TRAINING, RO_LIMITS_CFG, RW_LIMITS_CFG entries which have been deprecated. BUG=b:236995289 BRANCH=None TEST=run dut-control power_state:rec twice and make sure that DDR training doesn't run on the second boot. Change-Id: I39ac7eca4ae94075874324b13c69eef59522e3c5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-24mb/google/brya/{var/agah,acpi}: Update GPU GCOFF sequence for power downTim Wawrzynczak
We have clarified the powerdown sequence with Nvidia, and the EEs have come up with this modified sequence which still meets the requirements from the hardware design guide. BUG=b:233959099 TEST=Verified by ODM and EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-24mb/google/brya/var/osiris: Disable PCH USB2 phy power gatingDavid Wu
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for osiris board. Please refer Intel doc#723158 for more information. BUG=None TEST=Verify the build for osiris board Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia30a7b915df14c91a2526dca3e374436da286b7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-24mb/google/nissa/var/xivu: Update overridetreeIan Feng
Update override devicetree based on schematics. BUG=b:236576117 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2986ae6fd1f51efc6b9bb18ff2b7186357e55fcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-24mb/google/nissa/var/xivu: Update gpio settingsIan Feng
Configure GPIOs according to schematics. BUG=b:236576117 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I8c4347fcc975ed994261c7738e5ef811a12e4b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-24mb/google/brya/var/crota: Modify some GPIO programmingTerry Chen
Base on bernadino 14 adl-p 20220531.pdf, configure GPIOs according to schematics. GPP_B2 => BYPASS_DET GPP_F19 => FP_USER_PRES_FP_L BUG=b:234384954 TEST= USE="project_crota" emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ic2e7ecc34912f07463e0025787fdf59c7602e40b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-24mb/google/brya: Add `ext_pm_support` for volmar eMMC SKUSubrata Banik
This patch ensures google/volmar eMMC SKU has advanced PM support enabled. BUG=b:235915257 TEST=Able to boot to eMMC SKU to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e2883d894d2ca7f810f4b72af1c12037c8fdabc Reviewed-on: https://review.coreboot.org/c/coreboot/+/65244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-24mb/google/brya/var/taniks: Modify DPTF setting for taniksJoey Peng
Adjust sensor trigger point and fan duty according to thermal team tuning results. BRANCH=brya BUG=b:215033682 TEST=Built and tested on taniks board Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I8135684d471fdcfdbbe2f1bc5455902d56bb71de Reviewed-on: https://review.coreboot.org/c/coreboot/+/65287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-24mb/google/brya/var/volmar: Disable PCH USB2 phy power gatingRen Kuo
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for kano board. Please refer Intel doc#723158 for more information. BUG=None TEST=Verify the build for volmar board Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I4d12f7214a306ded54b4536a27fe0fb7f3c33b8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-23mb/google/nissa: Skip locking for GPP_F14 GPIOMaulik V Vaghela
There is an existing issue for nissa boards where wake up from RTC wake is not working during suspend_stress_test. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Reference: https://review.coreboot.org/c/coreboot/+/64089 Later issue was found to be with GPP_F14 configuration for nissa boards. When coreboot skips setting GPE_EN bit for GPP_F14, RTC wake works properly. Another way to make it work is to skip locking GPP_F14 GPIO to allow kernel to configure it properly. This patch skips the locking for GPP_F14 to allow kernel to configure it later. This fixes the issue of RTC wake not working. Note: This patch provides workaround for the existing issue and BUG will be closed once actual reason is identified and proper fix is available. BUG=b:234097956 BRANCH=None TEST=RTC wake works on Nivviks board with the patch. Change-Id: Ie8091ab8acf2b3f064cb79bdf4700f6b4c1674a5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-23mb/google/nissa/var/xivu: Generate RAM ID and SPD fileIan Feng
Add the support RAM parts for Xivu. Here is the ram part number list: DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) K3LKBKB0BM-MGCP 2 (0010) BUG=b:236576117 BRANCH=None TEST=Use part_id_gen to generate related settings and emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I02866f7dcdc70d1051d187fdda30e04bb654ece3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65252 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23mb/google/brya: Create xivu variantIan Feng
Create the xivu variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:235025984 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_XIVU Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I12341a2414e58ebc1c22429d35a03afef27adace Reviewed-on: https://review.coreboot.org/c/coreboot/+/65235 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23mb/google/guybrush/var/dewatt: Update telemetry valueKenneth Chan
AMD SDLE testing had been done. Apply the following telemetry settings for dewatt DVT: vdd scale: 91573 vdd offset: 620 soc scale: 30829 soc offset: 235 BUG=b:234417498 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Change-Id: I46650ca12ccfec90f15ee562d30c62c389d14d39 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-06-23mb/google/brya/var/ghost4adl: Add more memory partsJack Rosenthal
Add support for MT62F512M32D2DR-031 WT:B and K3LKLKL0EM-MGCN. These will be used as backup parts if there is issues getting the Hynix parts. BUG=b:233822880,b:236423310 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I6ace8788ffb2ec40d01b91d0a4d751e0a95883f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-06-23mb/google/brya/var/ghost: Add auto-generated GPIO config from ArbitrageJack Rosenthal
Arbitrage is an internal tool at Google to work with schematics programatically. In particular, it features an "export-coreboot-gpio" command, which, does it's best to try and make a gpio.c from the schematics to avoid human errors when translating to C code. This commit adds a gpio.c generated by running: "arb export-coreboot-gpio ghost4adl:P0_2022_06_17" This GPIO config will require hand modification. This is done in a follow-up CL. (i.e., this CL intentionally leaves the config exactly how it was generated by Arbitrage so we get a good diff on the changes we needed to make) BUG=b:234626939,b:231719130 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I35a85202768a366357073d3ebc177d0e0da661f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65210 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23mb/google/brya/var/ghost4adl: Enable TCSS display detection by defaultJack Rosenthal
Initial boards will not have an internal panel. Enable TCSS display detection so we can boot on an external panel over Type-C. BUG=b:235294840 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I6f65ddc24701d6f6ad0250560cc05b5e1d32370f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-06-22mb/google/brya/var/kinox: Refactoring update_power_limits functionDtrain Hsu
Based on 'commit 0b917bde36a7 ("mb/google/brya/var/kinox: Set power limit based on charger type")' to refactoring update_power_limits function for kinox. BUG=b:231911918 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1fcb593090f95bf23808e577dd11b8a836f47494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-22security/vboot: Deprecate VBOOT_VBNV_ECYu-Ping Wu
Boards using VBOOT_VBNV_EC (nyan, daisy, veyron, peach_pit) are all ChromeOS devices and they've reached the end of life since Feb 2022. Therefore, remove VBOOT_VBNV_EC for them, each with different replacement. - nyan (nyan, nyan_big, nyan_blaze): Add RW_NVRAM to their FMAP (by reducing the size of RW_VPD), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. - veyron: Add RW_NVRAM to their FMAP (by reducing the size of SHARED_DATA), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. Also enlarge the OVERLAP_VERSTAGE_ROMSTAGE section for rk3288 (by reducing the size of PRERAM_CBMEM_CONSOLE), so that verstage won't exceed its allotted size. - daisy: Because BOOT_DEVICE_SPI_FLASH is not set, which is required for VBOOT_VBNV_FLASH, disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. - peach_pit: As VBOOT is not set, simply remove the unused VBOOT_VBNV_EC option. Remove the VBOOT_VBNV_EC Kconfig option as well as related code, leaving VBOOT_VBNV_FLASH and VBOOT_VBNV_CMOS as the only two backend options for vboot nvdata (VBNV). Also add a check in read_vbnv() and save_vbnv() for VBNV options. BUG=b:178689388 TEST=util/abuild/abuild -t GOOGLE_NYAN -x -a TEST=util/abuild/abuild -t GOOGLE_VEYRON_JAQ -x -a TEST=util/abuild/abuild -t GOOGLE_DAISY -a TEST=util/abuild/abuild -t GOOGLE_PEACH_PIT -a BRANCH=none Change-Id: Ic67d69e694cff3176dbee12d4c6311bc85295863 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-22mb/google/brya/var/taeko: Modify DPTF setting for tarloJoey Peng
Adjust sensor trigger point and fan duty according to thermal team tuning results. BRANCH=brya BUG=b:215033683 TEST=Built and tested on tarlo board Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib543cee82f6940ab35a1a40af1d41bb2b8bf8521 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22mb/google/skyrim/variants/baseboard: enable iommuJason Glenesk
With IOMMU disabled, kernel complains that 'IOMMUv2 functionality not available on this system'. Enable iommu in devicetree for skyrim proto board in order to allow kernel to load and initialize IOMMUv2. BUG=b:232750390 TEST=Boot to Chrome OS on skyrim board, and grep dmesg for "AMD IOMMUv2 loaded and initialized" Change-Id: I2f10f5eda8083335619a34c44df253b8e5a8572c Signed-off-by: Jason Glenesk <Jason.Glenesk@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-06-22mb/google/brya/var/kinox: Enable PCIe WLANIan Feng
Enable PCIe WLAN for Kinox 1. Enable PCI port 5 for PCIe WLAN 2. Enable CLKREQ, CLK SRC 2 for PCI port 5 BUG=b:236175551 TEST=Build and boot to OS in Kinox. Ensure that the WLAN module is enumerated in the output of lspci. localhost ~ # lspci 02:00.0 Network controller: Realtek Semiconductor Co., Ltd.Device c852 (rev 01) Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I3fbeadc85c9c88f5d178326dbbc83762083fe59a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65168 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-21mb/google/nissa/var/joxer: add generic LPDDR5 SPDs for JoxerMark Hsieh
Add Makefile.inc to include five generic LPDDR5 SPDs for the following parts for Joxer: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) BUG=b:236576115 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I90acb436bccd5dae8585436316246c50fc256842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-21security/vboot: Add support for GSCVD (Google "RO verification")Julius Werner
This patch adds a new CONFIG_VBOOT_GSCVD option that will be enabled by default for TPM_GOOGLE_TI50 devices. It makes the build system run the `futility gscvd` command to create a GSCVD (GSC verification data) which signs the CBFS trust anchor (bootblock and GBB). In order for this to work, boards will need to have an RO_GSCVD section in their FMAP, and production boards should override the CONFIG_VBOOT_GSC_BOARD_ID option with the correct ID for each variant. BUG=b:229015103 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1cf86e90b2687e81edadcefa5a8826b02fbc8b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-21mb/google/brya: Add `ext_pm_support` for taeko eMMC SKUSubrata Banik
This patch ensures google/taeko eMMC SKU has advanced PM support enabled. BUG=b:235915257 TEST=Able to boot to eMMC SKU to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b14130e47c3e3ec9b066456f3195841c83623a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65243 Reviewed-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21mb/google/brya: Add `ext_pm_support` for taniks eMMC SKUSubrata Banik
This patch ensures google/taniks eMMC SKU has advanced PM support enabled. BUG=b:235915257 TEST=Able to boot to eMMC SKU to ChromeOS. Change-Id: I20c98006b6a45e2c8286480c560c8dbc0752327c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65213 Reviewed-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21mb/google/nissa: Create pujjo variantStanley Wu
Create the pujjo variant of the nissa reference board by copying the template files to a new directory named for the variant. (Follow other ADLN variant to generate by manual) BUG=b:235182560 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJO Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I73ec985bc19320260d0c3132c1ca23a3648df9e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-20mb/google/brya/variants/nereid: enable CNVi bluetooth in overridetreeJesper Lin
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nereid overridetree to enable port 10. BUG=b:236162084 TEST=USE="project_nereid emerge-nissa coreboot" and verify it builds without error. Signed-off-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com> Change-Id: Ic45301b863383e447b2dd3e06811b469cc247229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65188 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/apollolake: Hook up UfsEnabled to devicetreeSean Rhodes
Hook up FSP S UfsEnabled UPD (1d.0) to devicetree. UFS only exist on GLK, and has been there since its initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/google/brya/var/skolas4es: Add new memory partsNick Vaccaro
Add support for the MT53E2G32D4NQ-046 WT:C and MT53E512M32D1NP-046 WT:B memory parts to skolas4es. BUG=b:236284219 BRANCH=firmware-brya-14505.B TEST=None Change-Id: I5e3534985e12535ccc4285a0d829bca04781cf1b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65179 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-18mb/google/dedede/var/shotzo: Add EC defines for ACPITony Huang
Update Shotzo own ec.h with the battery, lid and ps2 defines stripped. This is to ensure the correct ASL is generated so that we don't advertise PS2 keyboard support and battery/lid interrupts which don't exist. In MAINBOARD_EC_SCI_EVENTS drop following events. EC_HOST_EVENT_LID_OPEN EC_HOST_EVENT_LID_CLOSED EC_HOST_EVENT_BATTERY_LOW EC_HOST_EVENT_BATTERY_CRITICAL EC_HOST_EVENT_BATTERY EC_HOST_EVENT_BATTERY_STATUS set MAINBOARD_EC_SMI_EVENTS to 0 and drop EC_HOST_EVENT_LID_CLOSED smi event. In MAINBOARD_EC_S5_WAKE_EVENTS drop below event. EC_HOST_EVENT_LID_OPEN In MAINBOARD_EC_S3_WAKE_EVENTS drop following events. EC_HOST_EVENT_AC_CONNECTED EC_HOST_EVENT_AC_DISCONNECTED EC_HOST_EVENT_KEY_PRESSED EC_HOST_EVENT_KEY_PRESSED BUG=b:235303242 BRANCH=dedede TEST=Build Change-Id: I5717e2e8ca7549d160fe46ccde31c6d7cf9649d7 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65167 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-18mb/google/brya/var/agah: Remove variant_finalizeTim Wawrzynczak
The EEs and I misunderstood, and apparently the vfio-pci kernel driver will turn off the dGPU when it sees it is unused, so coreboot should leave the dGPU on so the kernel driver can save state before it shuts it down. TEST=Tested by ODM Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I30b5dead7a5302f3385ddcaecfbf134c3bb68779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65181 Reviewed-by: Robert Zieba <robertzieba@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-17mb/google/brya/var/banshee: Update thermal settings PL1 and PL2Frank Wu
Update PL1 and PL2 based on the suggestion of the thermal team. Then the settings are both updated in firmware log. BUG=b:233703656, b:233703655 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ibb81a1a8519b88ed4774385d9ccf895d64bbdc21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-17mb/google/nissa: Create joxer variantMark Hsieh
Create the joxer variant of the nissa reference board by copying the template files to a new directory named for the variant. BUG=b:236086879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_JOXER Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4cb74f90c4ec33818b551d5f51759930e3222677 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2022-06-17mb/google/nissa/var/pujjo: Generate SPD ID for supported memory partLeo Chou
Add pujjo supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3LKBKB0BM-MGCP, K3LKCKC0BM-MGCP 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6E 3. Micron MT62F512M32D2DR-031 WT:B BUG=b:235765890 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I929527a219452082e416803f7a74d470be5a188c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65100 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/brya/var/agah: Remove stop pin declaration for LANTony Huang
Currently, the system fails to enter S0ix as the stop pin declation for LAN device will prevent system from entering suspend. So remove the stop pin declaration. Also add device_index=0 for the first NIC to get correct MAC from VPD setting. BUG=b:210970640 TEST=Build and suspend_stress_test -c 20 pass Check LAN works fine after resume Change-Id: I513bf8b4bcb4d6db2eed2790fef7f6000a441274 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65123 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17mb/google/nissa/var/craask: Enable Elan touchscreenTyler Wang
Add Elan touchscreen support for craaskvin. BUG=b:235919755 TEST=Build and test on MB, touchscreen function works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I18e0be688705942647c42ee532fcd32e862fe78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-17mb/google/nissa/var/craask: Add ALC5682I-VS codec supportTyler Wang
Add ALC5682I-VS related settings. And add codec/amplifier space in fw_config. BUG=b:229048361, b:235436515 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I567d3567318c810e19ae9e9ba5e0dc8332517866 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-17mb/google/nissa/var/craask: Disable SD card based on fw_configTyler Wang
Use fw_config Bit 5 to control whether to disable SD card: Bit 5 = 0 --> enable SD card Bit 5 = 1 --> disable SD card BUG=b:229048361 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ib5e92600564e2138e32a0d2e60259b9767516a4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65129 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/brya/var/banshee: Update gpio configurationFrank Wu
Update gpio configuration based on GPIO_0610b.xlsx. BUG=b:226182106, b:226182090 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I2b447629645690e5e97a17fff25860838f4f3344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-06-16mb/google/peach_pit: Select BOOT_DEVICE_NOT_SPI_FLASHYu-Ping Wu
CPU_SAMSUNG_EXYNOS5420 has its own boot device implementation (src/soc/samsung/exynos5420/alternate_cbfs.c), so BOOT_DEVICE_NOT_SPI_FLASH should be selected. Change-Id: I0a9f96ad68b28773ede4e99510bd33867789e185 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65109 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-16mb/google/brya/vell: Implement variant_devtree_update() for audioeddylu@ami.corp-partner.google.com
Different board versions have different audio layouts, therefore support both layouts by enabling only the appropriate devices in the devicetree via board_id(). BUG=b:207333035 BRANCH=none TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: If053b8f85933f8fc75589ae175e225cc9c1e3991 Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65124 Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15mb/google/brya/var/crota: Enable VNN_1.05v_bypass railTerry Chen
Some SKUs of crota have VNN 1.05v bypass rails for additional power savings in S0ix states. This patch uses FW_CONFIG to enable that feature when run on the applicable SKUs. BUG=b:233175019 BRANCH=none TEST=emerge-brya coreboot and verified pass Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Iaade50f4fe821b7114b3e2d44bda0747816da11c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15mb/google/brya/var/brya4es: Enable CNVi ddr rfimVarshit B Pandya
enable_cnvi_ddr_rfim enables DDR RFI mitigation feature, this feature needs to be enabled for all brya variants. Currently, it's not enabled for brya4es. BUG=b:201724512 TEST=Build, boot brya4es and check function 3 in _DSM method under \_SB.PCI0.WFA3 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6cc9d3e4721188dcbc8584596c9f3f89a737206f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65110 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15mb/google/nissa: Increase I2C bus frequency to around 390 kHzReka Norman
- Set the speed to I2C_SPEED_FAST in each speed_config so that the speed_config is actually applied. Currently, the speed_config isn't applied, so the hcnt/lcnt calculation falls back to rise_time_ns and fall_time_ns, which are 0 since they're not set. This results in frequencies around 300 kHz. - Move the data hold time to the speed_config, ensuring that the resulting sda_hold value remains the same. - For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to give a frequency around 390 kHz. - In the baseboard, keep default scl_lcnt and scl_hcnt values. These work well for buses with a rise time around 100 ns, and can be used as a starting point before tuning them for a specific variant. BUG=b:229547183 TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks and nereid and check they meet the spec. nereid clock frequencies: I2C0 - 387.9 kHz I2C1 - 392.7 kHz I2C3 - 386.3 kHz I2C5 - 383.6 kHz nivviks clock frequencies: I2C0 - 387.67 kHz I2C1 - 380.47 kHz I2C2 - 388.51 kHz I2C3 - 384.03 kHz I2C5 - 389.09 kHz Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15mb/google/dedede/var/shotzo: Generate SPD ID for supported partsTony Huang
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: - MT53E512M32D2NP-046 WT:E - H9HCNNNBKMMLXR-NEE - K4U6E3S4AA-MGCR - MT53E512M32D1NP-046 WT:B - H54G46CYRBX267 - K4U6E3S4AB-MGCL - K4U6E3S4AA-MGCL BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: Ie0ffdfed47b1791b990affd9eee262faede4b0c8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65081 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com>
2022-06-14mb/google/brya/var/agah: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ A2 | | A0 C2 | | C0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I8cc7be20988ff3cc3be1fac3c9b143059ff9190c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65088 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14mb/google/brask/variants/moli: change clk_src and clk_req for LAN_I225VRaihow Shi
change clk_src and clk_req to 4 for LAN_I225V based on ADL_Moli_SC_MB_20220601.pdf. BUG=b:235768639 TEST=emerge-brask coreboot and check LAN_I225V can connect. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I323726df84d07703402da9da44b1882a0cdc1e33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-14mb/google/brask/variants/moli: Remove the cnvi_bt_audio_offloadRaihow Shi
Remove the cnvi_bt_audio_offload because it is already probed in variant.c for moli. BUG=b:235426221 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I15077ca161b6283e764105d1c2fbc59ead1fd761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-14mb/google/brask/variants/moli: enable use_custom_pldRaihow Shi
enable use_custom_pld to match the custom physical location define. BUG=b:235426221 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I62d133eed02faf4e5ad054a0901f73b1196c4c6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Won Chung <wonchung@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>