diff options
| author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | 2022-06-13 16:49:52 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-14 22:12:31 +0000 |
| commit | b73cb4b1d2ca7754fd61310befdd82b793d693f0 (patch) | |
| tree | 01c69a95696cbf0c44c75a97b9b3f83782c1cdc1 /src/mainboard/google | |
| parent | d79bb899c1791869f2efaf10a189cf8dbcd3feee (diff) | |
mb/google/brask/variants/moli: change clk_src and clk_req for LAN_I225V
change clk_src and clk_req to 4 for LAN_I225V based on
ADL_Moli_SC_MB_20220601.pdf.
BUG=b:235768639
TEST=emerge-brask coreboot and check LAN_I225V can connect.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I323726df84d07703402da9da44b1882a0cdc1e33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/moli/overridetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index c9dd411a41..2a8526a296 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -83,10 +83,10 @@ chip soc/intel/alderlake end end # Audio Nau8825 device ref pcie_rp6 on - # Enable PCIe-to-i225 bridge PCIe 6 using clk 5 + # Enable PCIe-to-i225 bridge PCIe 6 using clk 4 register "pch_pcie_rp[PCH_RP(6)]" = "{ - .clk_src = 5, - .clk_req = 5, + .clk_src = 4, + .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_DISABLE, }" |