diff options
| author | Caveh Jalali <caveh@chromium.org> | 2022-06-28 22:20:00 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-04 13:59:32 +0000 |
| commit | 8dcc65180681e947c72a52b7f7e31df7b33ef6e3 (patch) | |
| tree | 9683c39bd8c0c57b9aaf517f0660a0289cf6ce89 /src/mainboard/google | |
| parent | db8442b10a586b6a029e4c45a004e604484c6014 (diff) | |
mb/google/brya/var/ghost4adl: Update Type-C locations
This updates the ACPI locations of Type-C ports.
BUG=b:232806406
TEST=none
Change-Id: Ia15e09a58c731a1364a994fadf8df39115fbe7c4
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/ghost4adl/overridetree.cb | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/ghost4adl/overridetree.cb b/src/mainboard/google/brya/variants/ghost4adl/overridetree.cb index 491d793ba3..9a98768117 100644 --- a/src/mainboard/google/brya/variants/ghost4adl/overridetree.cb +++ b/src/mainboard/google/brya/variants/ghost4adl/overridetree.cb @@ -130,11 +130,13 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn + # C0: Left side (on DB) use usb2_port1 as usb2_port use tcss_usb3_port3 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn + # C1: Right side (on MLB) use usb2_port2 as usb2_port use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end @@ -149,15 +151,15 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C0 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - # USB C0 is on RIGHT panel, LEFT side (when user is facing front) - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + # USB C0 is on the LEFT panel, LEFT side (i.e. rear) + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port3 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - # USB C1 is on the RIGHT panel, RIGHT side (when user is facing front) + # USB C1 is on the RIGHT panel, RIGHT side (i.e. rear) register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end @@ -171,13 +173,15 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C0 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + # USB C0 is on the LEFT panel, LEFT side (i.e. rear) + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" + # USB C1 is on the RIGHT panel, RIGHT side (i.e. rear) register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end |