summaryrefslogtreecommitdiff
path: root/src/mainboard/google
diff options
context:
space:
mode:
authorEric Lai <eric_lai@quanta.corp-partner.google.com>2022-06-01 11:19:39 +0800
committerSubrata Banik <subratabanik@google.com>2022-07-01 07:24:16 +0000
commit67219f73316f7b9f2bb91d195a6f95aa4e1f9e5d (patch)
treea9efc310bd403ab086ead8408c3f1baa9edc0574 /src/mainboard/google
parent8481056a53f5a42bfece355595c6dad21f2fd8f4 (diff)
mb/google/rex: Add memory init
Add memory init with placeholder to fill in required memory configuration parameters. DQ map and Rcomp can be auto probed by the FSP-M hence, kept it as default. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Able to boot till FSP-M/MRC using MTL simics. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/rex/Kconfig9
-rw-r--r--src/mainboard/google/rex/Makefile.inc2
-rw-r--r--src/mainboard/google/rex/romstage.c9
-rw-r--r--src/mainboard/google/rex/spd/Makefile.inc6
-rw-r--r--src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h6
-rw-r--r--src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc1
-rw-r--r--src/mainboard/google/rex/variants/baseboard/rex/memory.c32
-rw-r--r--src/mainboard/google/rex/variants/rex0/memory/Makefile.inc5
-rw-r--r--src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt5
-rw-r--r--src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt1
10 files changed, 76 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 3ce79cb1e7..9e02dd82b9 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_REX
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select MAINBOARD_HAS_CHROMEOS
+ select MEMORY_SOLDERDOWN
select SOC_INTEL_METEORLAKE
select SYSTEM_TYPE_LAPTOP
@@ -44,4 +45,12 @@ config VARIANT_DIR
string
default "rex0" if BOARD_GOOGLE_REX0
+config DIMM_SPD_SIZE
+ default 512
+
+config MEMORY_SOLDERDOWN
+ def_bool n
+ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+ select HAVE_SPD_IN_CBFS
+
endif # BOARD_GOOGLE_REX_COMMON
diff --git a/src/mainboard/google/rex/Makefile.inc b/src/mainboard/google/rex/Makefile.inc
index fc26bd2731..3fb7729318 100644
--- a/src/mainboard/google/rex/Makefile.inc
+++ b/src/mainboard/google/rex/Makefile.inc
@@ -16,6 +16,8 @@ BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
subdirs-y += variants/$(VARIANT_DIR)
+subdirs-y += variants/$(VARIANT_DIR)/memory
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
diff --git a/src/mainboard/google/rex/romstage.c b/src/mainboard/google/rex/romstage.c
index a993d14689..9e41d4660e 100644
--- a/src/mainboard/google/rex/romstage.c
+++ b/src/mainboard/google/rex/romstage.c
@@ -3,12 +3,21 @@
#include <baseboard/variants.h>
#include <fsp/api.h>
#include <soc/romstage.h>
+#include <string.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct pad_config *pads;
size_t pads_num;
+ const struct mb_cfg *mem_config = variant_memory_params();
+ bool half_populated = variant_is_half_populated();
+ struct mem_spd spd_info;
pads = variant_romstage_gpio_table(&pads_num);
gpio_configure_pads(pads, pads_num);
+
+ memset(&spd_info, 0, sizeof(spd_info));
+ variant_get_spd_info(&spd_info);
+
+ memcfg_init(memupd, mem_config, &spd_info, half_populated);
}
diff --git a/src/mainboard/google/rex/spd/Makefile.inc b/src/mainboard/google/rex/spd/Makefile.inc
new file mode 100644
index 0000000000..be4d98bd1d
--- /dev/null
+++ b/src/mainboard/google/rex/spd/Makefile.inc
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+ifneq ($(SPD_SOURCES),)
+LIB_SPD_DEPS := $(SPD_SOURCES)
+endif
diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
index c2dbe5401d..6fd64c9246 100644
--- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
@@ -4,6 +4,7 @@
#define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h>
+#include <soc/meminit.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -15,4 +16,9 @@ const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);
const struct pad_config *variant_romstage_gpio_table(size_t *num);
+const struct mb_cfg *variant_memory_params(void);
+void variant_get_spd_info(struct mem_spd *spd_info);
+int variant_memory_sku(void);
+bool variant_is_half_populated(void);
+
#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc
index 6c29346470..7d1f88652d 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc
+++ b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc
@@ -1,5 +1,6 @@
bootblock-y += gpio.c
romstage-y += gpio.c
+romstage-y += memory.c
ramstage-y += gpio.c
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/memory.c b/src/mainboard/google/rex/variants/baseboard/rex/memory.c
new file mode 100644
index 0000000000..0fb80e94af
--- /dev/null
+++ b/src/mainboard/google/rex/variants/baseboard/rex/memory.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+ .type = MEM_TYPE_LP5X,
+ /* TODO: Add Memory configuration */
+ .ect = 1, /* Enable Early Command Training */
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+ return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+ return 0;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+ return 0;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+ spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+ spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/rex/variants/rex0/memory/Makefile.inc b/src/mainboard/google/rex/variants/rex0/memory/Makefile.inc
new file mode 100644
index 0000000000..001625655b
--- /dev/null
+++ b/src/mainboard/google/rex/variants/rex0/memory/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-empty.hex # ID = 0(0b0000)
diff --git a/src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..ec320376f0
--- /dev/null
+++ b/src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+
+DRAM Part Name ID to assign
+empty 0 (0000)
diff --git a/src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..c6cac69265
--- /dev/null
+++ b/src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt
@@ -0,0 +1 @@
+empty