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2023-10-24mb/google/brya: Set WWAN_PCIE_WAKE_ODL as interrupt on RedrixPaweł Anikiel
This signal gets deasserted by the WWAN modem to reactivate the PCIe link when in low power mode. In order to handle this efficiently, the kernel needs to set up an interrupt. BUG=b:301150499 TEST=Compiled and tested on google/redrix Signed-off-by: Paweł Anikiel <panikiel@google.com> Change-Id: I37f6836aefe4a374eaff3e4bc11358be274cf563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78416 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-23mb/google/brya/variants/anraggar: Generate 13 RAM IDswuweimin
Vendor DRAM Part Name Type MICRON MT62F512M32D2DR-031 WT:B LPD5 HYNIX H9JCNNNBK3MLYR-N6E LPD5 HYNIX H9JCNNNCP3MLYR-N6E LPD5 MICRON MT62F1G32D4DR-031 WT:B LPD5 HYNIX H9JCNNNFA5MLYR-N6E LPD5 MICRON MT62F2G32D8DR-031 WT:B LPD5 SAMSUNG K3KL6L60GM-MGCT LPD5x MICRON MT62F1G32D2DS-026 WT:B LPD5x SAMSUNG K3KL8L80CM-MGCT LPD5x HYNIX H58G56BK7BX068 LPD5x MICRON MT62F2G32D4DS-026 WT:B LPD5x SAMSUNG K3KL9L90CM-MGCT LPD5x HYNIX H58G66BK7BX067 LPD5x BUG=b:304920262 TEST=Run part_id_gen tool without any errors Change-Id: I2968c2f0b9cdd55235f9833a3d3cdb3c83b8601b Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-23mb/google/rex/var/karis: Modify TCC_offset to 10Tyler Wang
Follow thermal team request, modify tcc_offset from 20 to 10. BUG=b:306548525 TEST=Build and verified by thermal team Change-Id: I7537e103be4cd1196c934ca72dbd61e064aed371 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-10-23mb/google/dedede: Add HPD GPIOs on dexi variantKenneth Chan
Some Type-C monitors do not immediately assert HPD. If we enter FSP-S before HDP is asserted, display initialisation may fail. So wait for HPD. This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP output on cold boots") on puff, except we don't use google_chromeec_wait_for_displayport() since that EC command was removed for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if HDMI is connected, which is the same behaviour as puff and fizz. BUG=b:303533815 BRANCH=dedede TEST=On dexi, connect a display via a Type-C to HDMI dongle and check the dev and recovery screens are now displayed correctly. Also check the logs in the following cases: Cold reboot in dev mode, Type-C to HDMI dongle: HPD ready after 800 ms Warm reboot in dev mode, Type-C to HDMI dongle: HPD ready after 0 ms Cold/warm reboot in dev mode, direct Type-C: HPD ready after 0 ms Cold/warm reboot in dev mode, direct HDMI: HPD ready after 0 ms Cold/warm reboot in dev mode, no display: HPD not ready after 3000 ms. Abort. Change-Id: Ib4fc071cac98a542072ffbeb6943bff4c988554c Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78450 Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/brya/var/dochi: Update overridetree for FingerPrintMorris Hsu
Update overridetree to correct FP_MCU fw_config settings. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: If76dd8fa3567ed01b11a6d2ba796e8c39807816c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78454 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/brya/var/dochi: Update overridetree for TouchPadMorris Hsu
Update overridetree for TouchPad. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I4f88fa8a34b65aaeb64746e7f02e82d9913ce21b Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78455 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/nissa/var/gothrax: Supplement register settings for SX9324 P-sensorYunlong Jia
Set the following register value to make SX9324 work normally "ph0_pin" = "{1, 3, 3}" "ph1_pin" = "{3, 2, 1}" "ph2_pin" = "{3, 3, 1}" "ph3_pin" = "{1, 3, 3}" "ph01_resolution" = "512" "ph23_resolution" = "1024" "startup_sensor" = "1" "ph01_proxraw_strength" = "2" "ph23_proxraw_strength" = "2" "avg_pos_strength" = "256" "cs_idle_sleep" = ""gnd"" "int_comp_resistor" = ""lowest"" "input_precharge_resistor_ohms" = "4000" "input_analog_gain" = "3" BUG=b:295109511 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-23mb/google/rex: Use upstream driver properties for SX9324Ivy Jian
Use human readable properties as upstream driver support. BUG=b:297977526 TEST=Able to get sensor values changed w/wo a hand covering the device. before this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { Zero, Zero, Zero }, ... Package (0x02) { "semtech,ph23-resolution", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, .... after this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { One, 0x02, 0x02 }, ... Package (0x02) { " semtech,ph23-resolution", 0x0400 }, Package (0x02) { "semtech,startup-sensor", One }, Change-Id: Ie0d929228f4510f33b07d9c4cfdfcd2a9a437c27 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78174 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
2023-10-23mb/google/dedede/var/cret: Modify Goodix touchpad HIDDtrain Hsu
Update Goodix touchpad HID to GDIX0000 for GXTP7288 and GXTP7863. BUG=b:305118852 BRANCH=firmware-dedede-13606.B TEST=Build and touchpads are workable # evtest for GXTP7863 No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: Elan Touchscreen /dev/input/event5: GDIX0000:00 27C6:0D51 Mouse /dev/input/event6: GDIX0000:00 27C6:0D51 Touchpad # evtest for GXTP7288 No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event10: GDIX0000:00 27C6:01F5 Touchpad /dev/input/event11: sof-da7219max98360a Headset Jack /dev/input/event12: sof-da7219max98360a HDMI/DP,pcm=2 /dev/input/event13: sof-da7219max98360a HDMI/DP,pcm=3 /dev/input/event14: sof-da7219max98360a HDMI/DP,pcm=4 /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: ELAN900C:00 04F3:2E5D /dev/input/event5: ELAN900C:00 04F3:2E5D UNKNOWN /dev/input/event6: ELAN900C:00 04F3:2E5D UNKNOWN /dev/input/event7: ELAN900C:00 04F3:2E5D Stylus /dev/input/event8: ELAN900C:00 04F3:2E5D Stylus /dev/input/event9: GDIX0000:00 27C6:01F5 Mouse Change-Id: Id2a6223bdbb2f0693149136baa853ca2efb57815 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20mb/google/myst: Enable CBFS VerificationKarthikeyan Ramasubramanian
Enable RO verification by GSC and RO/RW CBFS verification. BUG=b:277087492 TEST=Build and boot to OS in Myst with CBFS verification enabled using PSP verstage. Change-Id: I2dd3ce59f331f89660185309ccf60c53d50e4fad Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78235 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20Revert "mb/google/rex: Enable sending EOP from payload"Matt DeVillier
This reverts commit 55b7dee2784e9fe80870c6c33ba91b98021df8b5. Reason for revert: accidentally submitted out of order / breaks tree Change-Id: Ic15d0e3688cd54f7d678998341263e7bd30e75f2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78525 Tested-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-20mb/google/rex: Enable sending EOP from payloadKapil Porwal
Enable sending EOP from payload BUG=b:279184514 TEST=Verify sending EOP from depthcharge on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5eda0a5c6d4c34cfcc2de898adde0b005d6edc1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74768 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/google/brya/var/dochi: Enable EC keyboard backlightMorris Hsu
Enable EC keyboard backlight for dochi. BUG=b:299284564 TEST=FW_NAME=dochi emerge-brya coreboot chromeos-bootimage Change-Id: I1b640c576fcdd368110b88cba6f969f10dfc15f1 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20mb/google/rex/var/karis: Remove I2C2 "on" settingsTyler Wang
GPP_H04/GPP_H05 doesn't use for I2C usage, remove I2C2 "on" settings. BUG=b:294155897 TEST=Check ap firmware log, i2c2 is disabled Change-Id: I0124fd108fbbd87507d252e9caab4dfc16aceddb Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78339 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/google/rex: Set frequency and gears for SaGv pointsBora Guvendik
Update SaGv gears and frequency values as per recommendation from power and performance team. This change doesn't cause negative impact on firmware boot time performance. BUG=b:274137879 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ie8a81c05f25b1cdab1008d09c606d1debea6e6e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-20mb/google/kahlee: Hide Linux machine audio devices from WindowsCoolStar
Windows does not use these devices for audio. Hide these so they don't clutter device manager. Change-Id: Ic85eff7f7ff68e25cc005bbb822bf99374c96532 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78418 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/google/rex/var/karis: Use 2 gpio for stylus detect/wakeTyler Wang
Use 2 gpio for stylus detect and wake function. GPP_E04 is the IRQ source, and GPP_E09 is the wake source. BUG=b:304680060 TEST=Build and test on karis, stylus detect function works Change-Id: I7a83326f76932c8e501e6369bb845fc7236291b4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78336 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/google/nissa/var/craaskov: Use runtime detection for touchscreensRex Chou
Use runtime detection for touchscreens. BUG=b:289962599 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ia43ada8b3b6dbee95dbadacc353106e0f8f37549 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20mb/google/nissa/var/craaskov: Remove TOF functionRex Chou
Based on schematics and confirm with EE to remove TOF function. BUG=b:290891557 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1ae6a6562d87f8da5f41691a7606a1aa10989443 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78147 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-18mb/google/rex: enable WIFI_SAR for all variantsYH Lin
Enabling support of WiFi SAR table for all rex variants by setting the option at baseboard level. BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I17709cb5d75b56c6c1f386ab527c5c8730011bed Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78308 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-10-18mb/google/rex/var/karis: sync CBI FW_CONFIG definitionsYH Lin
Sync'ing Karis' FW_CONFIG definitions stored in CBI, ``` _FW_MASKS = struct( DB_USB = 0x00000003, # bit1~bit0 STYLUS = 0x00000004, # bit2 AMP = 0x00000038, # bit5~bit3 FAN = 0x000000C0, # bit7~bit6 MIPI_CAM = 0x00000300, # bit9 ~ bit8 FP_MCU = 0x00000C00, # bit11 ~ bit10 KB_TYPE = 0x00001000, # bit12 WIFI_TYPE = 0x00002000, # bit13 ) _FW_CONFIGS = struct( DB_USB_UNKNOWN = hw_topo.make_fw_config(_FW_MASKS.DB_USB, 0), DB_USB4_ANX7452 = hw_topo.make_fw_config(_FW_MASKS.DB_USB, 1), STYLUS_ABSENT = hw_topo.make_fw_config(_FW_MASKS.STYLUS, 0), STYLUS_PRESENT = hw_topo.make_fw_config(_FW_MASKS.STYLUS, 1), AUDIO_ALC5650 = hw_topo.make_fw_config(_FW_MASKS.AMP, 0), FP_MCU_ABSENT = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 0), FP_MCU_NUVOTON = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 1), FP_MCU_ELAN = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 2), WIFI_TYPE_CNVI = hw_topo.make_fw_config(_FW_MASKS.WIFI_TYPE, 0), WIFI_TYPE_PCIE = hw_topo.make_fw_config(_FW_MASKS.WIFI_TYPE, 1), MIPI_UF_CAM_HI556 = hw_topo.make_fw_config(_FW_MASKS.MIPI_CAM, 0), ) ``` BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I1e4965c009edc595f24c04ac82d81aa0e723bbf3 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78261 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-18mb/google/rex/var/karis: add hook for WiFi SAR tableYH Lin
WiFi SAR table for karis will be place into the CBFS later on and as a result adding the hook in coreboot to make use of the SAR table once the table is available. BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: Ic989024ab9eb0fc439fc701c335a85986c4cfec5 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78260 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-18mb/google/rex/var/karis: Add FAN field in fw_configTyler Wang
Update default fan settings(FAN_SETTING_1) in FAN field. Bit 6-7, FAN, 0 --> FAN_SETTING_1 BUG=b:290689824, b:294155897 TEST=Dump ssdt table and check fan settings is existed Change-Id: Id69ec67202b5d769cd3a9a68344a6d8913ebd78b Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-18mb/google/brox/Kconfig: Don't redefine config optionFelix Singer
Commit 9b230ae2955 introduced a redefinition of the config option `BOARD_GOOGLE_BROX`, which is already defined in Kconfig.name accordingly and thus causing a Kconfig warning. Fix that by removing the type redefinition. Change-Id: Iea6219a686a23d8d48a0bfb6ac642efd482fded9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78394 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-18mb/google/brya/var/dochi: update gpio settingsMorris Hsu
Configure GPIOs according to schematics revision 20231013. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I1ccab46b9f622fb98920d316c31800f39dc8ff95 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78384 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-17mb/google/brya: Create anraggar variantwuweimin
Create the anraggar variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:304920262 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ANRAGGAR Change-Id: I95e72188679fc825c94c4043ed02b0aad310c6a3 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-16mb/google/nissa/var/quandiso: Update SD card GPIO settingsRobert Chen
Disable SD card GPIO with fw_config for quandiso units without SD card and pull GPP_H12 to high to match the spec. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2023-10-16mb/google/rex/var/rex: Configure cpu power limits by battery statusJamie Ryu
When battery level is below critical level or battery is not present, cpus need to run with a power optimized configuration to avoid platform instabilities. This will check the current battery status and configure cpu power limits properly. BUG=b:296952944 TEST=Build rex0 and check cpu power limits are configured with a performance efficient configuration and the platform boots to OS if battery level is above the critical level. And check cpu power limits are configured with a power optimized configuration and boots to OS without an issue if battery is not present or battery level is at or below critical level. Change-Id: I12fd40abda76c8e7522b06a5aee72665f32ddec8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78322 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-13mb/google/brox: Create new Brox baseboardShelley Chen
This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to DRAM ID 0. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-13mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZEran Mitrani
BUG=NONE TEST=Tested on Rex, touch over SPI works properly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: If339f7a010fa51bf73b8898a55643b5e921d93b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-13mb/google/brya/var/dochi: Update overridetreeMorris Hsu
Update overridetree base on schematics revision 20230923. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78212 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-13mb/google/brya/var/dochi: use RPL FSP headersMorris Hsu
To support an RPL SKU on dochi, it must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for dochi so that it will use the RPL FSP headers. BUG=b:299570339 TEST=emerge-brya intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: I51c28744bd9f21fae58bad38abb01d38965140a4 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-10-13mb/google/nissa/var/quandiso: Update touchscreen power sequenceRobert Chen
Pull GPP_C1 to high in ramstage to meet touchscreen power sequence. BUG=b:302236370 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage & test touchscreen function on quandiso DUT Change-Id: Ia9f600ec0cc4be2d77ff08c0ae8951c90aec944f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-13mb/google/rex/var/rex0: Update NVM configuration for WFCJamie Ryu
This updates NVM Configuration according to EEPROM BRCA016GWZ-W datasheet for rex World Facing Camera module - O9B13-NT01BA to enumerate Camera module properly. BUG=b:301226048 TEST=Build rex0 and check SSDT table is updated correctly. Check "cros-camera-tool modules list" lists up the modules properly. cros-camera-tool modules list: /sys/devices/pci0000:00/0000:00:15.0/i2c_designware.0/i2c-0/i2c-PRP0001:01/i2c-PRP0001:011/nvmem /sys/devices/pci0000:00/0000:00:19.1/i2c_designware.4/i2c-13/i2c-PRP0001:03/i2c-PRP0001:032/nvmem [ { "module_id": "KC6977", "sensor_id": "OV013b", "sysfs_name": "i2c-0/i2c-PRP0001:01" }, { "module_id": "CH3c6d", "sensor_id": "HN0556", "sysfs_name": "i2c-13/i2c-PRP0001:03" } ] Change-Id: I51bdf249549d3e03180e9d126a85e9dff91028db Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78211 Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-13Revert "mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang"Wentao Qin
This reverts commit 5c35d30ffc7382af46b62044a5cf5326b1e57708. Reason for revert: Here we need to confirm whether the issue in mtl-staging-MTL.3323.92 has been improved in the QS sample in the factory build. BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang. Change-Id: I4517bbbefe11d95623d7e16a5e4bba2dd6f408e1 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78320 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-12mb/google/rex/var/karis: Fix touchscreen HID to ELAN9004Tyler Wang
Confirmed with vendor, Elan touchscreen HID should set to "ELAN9004". Correct Elan touchscreen HID to "ELAN9004" for karis. BUG=b:294155897 TEST=Dump the SSDT on karis and check the HID had been modified. Change-Id: I6ebb02540c894460388b9b9fe03f5c4031f8186d Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78266 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-11Revert "mb/google/rex/var/screebo: Enable GL9750 invert WP function"Kun Liu
This reverts commit ee4191852abf9b24f822468250c24edb993497c6. Reason for revert: In schematic a sdcard write protection pull-down resistor was added, so need to disable GL9750 invert WP function Change-Id: I00a8f43094d8b3674a4bbaeed24b96aab64b9b75 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78295 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-11mb/google/rex/var/karis: Set touchscreen power/reset GPIOs correctlyTyler Wang
The tochscreen isn't powered on yet when the detection is done, it makes touchscren no function. Set touchscreen power and reset GPIOs correctly in romstage and ramstage to make the detect feature works. BUG=b:303130400 TEST=(1) emerge-rex coreboot (2) Test on karis, touchscreen function works Change-Id: I6c7815b81eb47fb41e58233fde512ac6b9c000a7 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78254 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-10mb/google/brya/var/dochi: update gpio settingsMorris Hsu
Configure GPIOs according to schematics revision 20230923. TEST=emerge-brya coreboot Change-Id: I10bd1b72c9b0299b8d29ab642fddb5f0c4727652 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2023-10-10mb/google/dedede: Wait for HPD on dibbi variantsReka Norman
Some Type-C monitors do not immediately assert HPD. If we enter FSP-S before HDP is asserted, display initialisation may fail. So wait for HPD. This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP output on cold boots") on puff, except we don't use google_chromeec_wait_for_displayport() since that EC command was removed for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if HDMI is connected, which is the same behaviour as puff and fizz. TEST=On dibbi, connect a display via a Type-C to HDMI dongle and check the dev and recovery screens are now displayed correctly. Also check the logs in the following cases: Cold reboot in dev mode, Type-C to HDMI dongle: HPD ready after 800 ms Warm reboot in dev mode, Type-C to HDMI dongle: HPD ready after 0 ms Cold/warm reboot in dev mode, direct Type-C: HPD ready after 0 ms Cold/warm reboot in dev mode, direct HDMI: HPD ready after 0 ms Cold/warm reboot in dev mode, no display: HPD not ready after 3000 ms. Abort. Change-Id: Id4657b5d5a95a68ecbd9efcf3585cf96ad1e13e1 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-10-10mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control, as follows: 1.Cancel TCPU trip point and fine tune other protection temperature on the Critical policy table 2.Fine tune EC/Bios protection temperature BUG=b:291217859 TEST=emerge-rex coreboot Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78290 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-10mb/google/rex/var/rex0: update thermal settings to start fan earlierSumeet Pawnikar
Internal testing showed that CPU heatsink gets hot and temperature goes over 75C. In this situation, the fan does not even start to lower down CPU temperature. This is because of existing temperature thresholds of TSR0 and TSR1 sensors are set at 45C to start fan. With updated new settings based on tuning from thermal team, the fan starts early at 43C for TSR0 and TSR1 so the CPU temperature stays below 75C. BUG=b:302673874 TEST=Built and tested on google/rex board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I6580652d6165946e98ecf1b46ace3352cd34dcdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-09mb/google/dedede: Create dexi variantKenneth Chan
Create the dexi variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:303533815 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DEXI Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I708a16cb864dca7309cb0201e7887af7456a4885 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78249 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-09mb/google/nissa/var/joxer: Configure Acoustic noise mitigationMark Hsieh
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:303533832 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I575da55b96bf4deacec5c0992eae9930eb0745d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-09mb/google/nissa/var/joxer: Config I2C frequencyMark Hsieh
Measured the I2C frequency meets spec - I2C0 (TPM): 949.7 Khz - I2C1 (TouchScreen): 395.8 Khz - I2C3 (Audio): 387.4 Khz - I2C5 (Touchpad): 384.8 Khz BUG=b:303356736 TEST=USE="project_joxer emerge-nissa coreboot" and check all I2C devices measurement result Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I17dd1cb7800d00669f86fc6e2b350757695da881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78218 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-07mb/google/{rex,ovis}: Disable package C-state auto demotionSukumar Ghorai
Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter below PC8 state and additional power savings ~30mW in Local-Video-Playback scenario. BUG=b:303546334 TEST=Local build successfully & Boot to OS successfully - Also check platform enter PC8 state in local video playback - before this change: # iotools rdmsr 0 0xE2 -> 0x0000000060008008 - After # iotools rdmsr 0 0xE2 -> 0x0000000000008008 Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78250 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-06mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timingCong Yang
Based on the power sequence of the panel [1], the power on T3 sequence VSN to RESET should be larger than 1ms. Because the Power IC descending slope takes 2ms, actual measurement needs 3ms to meet the timing of panel sequence. [1] HX83102-J02_Datasheet_v03.pdf BUG=b:302212730 BRANCH=corsola TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78185 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-05mb/google/nissa/var/quandiso: Change camera fw_config feildRobert Chen
Quandiso reserve bit 11 for mipi camera usage. BUG=b:300574047 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id4343083f0d69a49c642657d165ceac349cd7422 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78213 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05mb/google/nissa/var/quandiso: Add ALC1019 amp supportRobert Chen
BUG=b:300573763 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Iff8167695c302f7b58976516d651a81f1a429bee Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-05mb/google/nissa/var/uldren: Remove fw_config probe for TS and TPDtrain Hsu
When service center repair touchscreen or touchpad will change compatible device not specific one, the fw_config probe mechanism is not convenient for service center. Removing touchscreen and touchpad fw_config probe for the purpose. BUG=b:297840605 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I66f12ae478f74c019c53ee5e77f7e0f9c324e758 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77538 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05mb/google/nissa/var/pirrha: Turn off SD card power signal in s0ixSeunghwan Kim
Turn off GPP_H13 (EN_PP3300_SD_X) in s0ix for power saving. It reduces about 3mW of power consumption in s0ix on pirrha proto board. BUG=b:300845527 TEST=Built and verified GPP_H13 voltage was 0V in s0ix. Also verified SD card worked after s0ix for 20 times. Change-Id: I5ec53820276e50f5b8b01584595118cf2dc4c95c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04mb/google/rex: Configure ISH UART TX/RX as NCBernardo Perez Priego
This patch reverses ISH UART pin configuration to allow ISH to enter into suspend mode. This UART port is for debugging purposes. BUG=b:302612549 TEST=On Google/rex platform with ISH enabled, do suspend_stress_test This test must pass Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I8aba45420744a3990e1f9637c3b31ea2e0f78f87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78049 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plugJoey Peng
Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. BUG=b:302230434 TEST=Verify USB-A device could wake up Boxy Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/google/dedede/var/taranza: Enable wake on USB2/3 (un)plugSheng-Liang Pan
Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. The physical USB slot is 6, USB2 port5 for Bluetooth, total USB2 port num is 7, USB3 keep 6. BUG=b:300844110 TEST=Verify USB-A device could wake up Taranza Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ied92c4a70bc594bd189dcb942f1a445412509464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78068 Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-10-04mb/google/geralt: Remove SAMSUNG_ATANA33XC20 panel supportYidi Lin
This panel is never actually enabled on Geralt. The derived project won't use this panel either. Therefore, remove this panel support. BUG=none BRANCH=none TEST=emerge-geralt coreboot Change-Id: I97ed5b341724ed42098b2c17d0eb75eab881dbb1 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-04mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD IDYidi Lin
The tolerance of ADC voltage table is too small. Update the table values accordring to the suggestion from the hardware team. The patch is prepared for the derived projects. There is no actual issue now. BRANCH=none BUG=b:301908091 TEST=check firmware screen Change-Id: I3bde30b6bbe79c81e276f23f4110715c3278d42c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-04mb/google/brya/var/yavilla: Add VCM power control sequenceSerin Yeh
Add VCM power control to configure 2.8V and reset pin, and VCM can be powered on/off properly. BUG=b:292907385 TEST=Run ITS test Change-Id: I242025836fd50076a40ffcc4e5d4a5d5bc6fb4d0 Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78170 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/amd: rework SPL file override and SPL fusing handlingFelix Held
The SPL_TABLE_FILE and SPL_RW_AB_TABLE_FILE Kconfig options provide a way to override the default SPL file configured in the SoC's fw.cfg file by passing the '--spl-table' parameter to amdfwtool which will then use the override instead of the SPL file from the fw.cfg file. When SPL*_TABLE_FILE is an empty string, the corresponding add_opt_prefix call in the makefile will result in no '--spl-table' parameter being passed to amdfwtool, so it'll use the default SPL file from fw.cfg. In order to not pass an SPL override by default, remove the default from the SPL_TABLE_FILE in the SoC's Kconfig. The SoC default pointed to the same SPL file as in fw.cfg file anyway. Now only when a mainboard sets this option to point to a file, that file will be used as an override. This override is used to include a special SPL file needed for the verstage on PSP case on the Chromebooks. Since SPL_TABLE_FILE is an empty string by default, neither the SPL_TABLE_FILE Kconfig option nor it being evaluated in the Makefile need to be guarded by HAVE_SPL_FILE, so remove the dependency in the Kconfig and the ifeq in the Makefile. Before this patch, the HAVE_SPL_FILE option controlled two things that shouldn't be controlled by the same Kconfig option: Only when HAVE_SPL_FILE was set to y, the SPL_TABLE_FILE override was taken into account, and it also controls if spl_fuse.c got added to the build which when added will send the SPL fusing command to the PSP. So the case of needing an SPL file override, but not updating the SPL fuses wasn't supported before. The SPL file in the amdfw part will be used by the PSP bootloader for the anti-rollback feature which makes sure that the SPL file version isn't lower than what is in the SPL fuses. For this the SPL file needs to be present in the PSP directory table. The SPL version check happens way before we're running code on the x86 cores. The SPL fusing PSP command that can be sent by coreboot will tell the PSP to update the SPL fuses so that the fused minimal SPL version will be updated to the current SPL version. Since the former HAVE_SPL_FILE option now only controls if the SPL fusing command will be sent to the PSP mailbox, rename it to PERFORM_SPL_FUSING to clarify what this will do and update the help text correctly describe what this does. TEST=With INCLUDE_CONFIG_FILE set to n, timeless builds for both Birman with Phoenix APU and Skyrim result in identical binaries. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/78178 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/google/nissa/var/yaviks: Add probe in devicetree for USB C1/A0 portWisley Chen
Add probe fw_config to USB C1/A0 port on daught_board for DB_1A sku. BUG=b:294456574 TEST=emerge-nissa coreboot Change-Id: I2261b0e4d2b673b6186a435cce8dc6a4ccacb0a7 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-03mb/google/brya: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I1439f785cb9ceeefab9d24caa88e35bd43f68315 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/google/dedede: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I5527d5968be35f52b912d9d6e1d9f46f24569bbc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03mb/google/rex: Fix ISH I2C pad for suspendCliff Huang
During suspend, the ISH I2C transactions cannot go through because the GPIO pads remain the pervious value. The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus active and functional during suspend. BUG=b:302612549 TEST=on Google/rex platform with ISH enabled, do suspend_stress_test and check that no i2c failure. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/78179 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Li1 Feng <li1.feng@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02security/tpm: Enable Hibernate on setup failureJon Murphy
Set default to enabled for hibernate on setup failure for all devices using a Google EC. This will have no impact on devices that don't bring the GSC down on hibernate, but will provide a recovery path for all devices that do. BUG=b:296439237 TEST=Force error on Skyrim with custom build, boot normally with normal build Change-Id: I2d9e8f75b25fb6c530a333024c342bea871eb85d Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78098 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02mb/google/corsola: Move common selects to BOARD_GOOGLE_CORSOLA_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CORSOLA_COMMON. Thus, move all selects to the latter option. Change-Id: I498c6671b2dfc72820fc522744af7ce3b0a62930 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-09-29mb/google/guybrush: Disable WLAN ASPMTim Van Patten
ASPM on the WLAN PCIe bus introduces large latency spikes, which can be measured with cyclictest: $ cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000 Disabling ASPM for WLAN reduces the latency spikes from 2,500-3,000 usec down to 35-65 usec. These latency spikes can impact the user when real-time processes like Audio (cras) are starved of CPU time, leading to buffer underruns resulting in crackling/distorted audio. ASPM is already disabled for Nipperkin devices (CB:63537), so this CL disables it for both in the shared declaration of guybrush_czn_dxio_descriptors. Power impact for Dewatt: * ASPM enabled power_VideoCall.FDO_25min_webrtc w_energy_rate 7.425043688811071 power_Idle.default20min wh_energy_used 1.4164200000000022 * ASPM disabled power_VideoCall.FDO_25min_webrtc w_energy_rate 8.779998551703423 power_Idle.default20min wh_energy_used 1.4860800000000012 When using Google Meet over WiFi, power increases by ~1.5W. BUG=b:297970318 TEST=cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000 Change-Id: I16940987d598943bd5d6ace8b4008eba4d4a177c Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77963 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-29mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreenShon Wang
Implement support for elan i2c touchscreen and use fw_config to pick between i2c or HID-over-i2c touchscreen. Support G2 TS have different slave address by fw_config BUG=b:295272539 BRANCH=firmware-nissa-15217.B TEST=build and verified touchscreen work Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-09-28mb/google/skyrim: Enable hibernate on TPM errJon Murphy
Enable hibernate on TPM setup error for Skyrim devices. BUG=b:296439237 TEST=Force the error by hard coding the return code and observe the device entering hibernate. BRANCH=None Change-Id: Ibf96b830f07dac98035d3152c8ec220685a912bc Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77668 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28treewide: convert to tpm_result_tJon Murphy
Convert TPM functions to return TPM error codes(referred to as tpm_result_t) values to match the TCG standard. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28treewide: convert to %#x hex printsJon Murphy
Convert hex print values to use the %#x qualifier to print 0x{value}. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/rex/var/ovis: Add DPTF configurationJakub Czapiga
Configure PL1 and PL2 are configured for powerformance. Based on values from Intel Meteor Lake UH Power Map document ID:640982 BUG=b:286834207 TEST=Build and boot google/ovis and check ACPI SSDT for DPTF entries Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77623 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/nissa/var/craask: Correct the USB setting by fw_configRen Kuo
Modify the settings: 1)Add fw_config probe on USB type C for "DB_1C_LTE". 2)Add fw_config probe on USB type A for "DB_1A_HDMI". BUG=b:296791122 TEST=build and check USB functions on craask Change-Id: I2775098ab380995e62f264bc51a430762c256c4b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78169 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26soc/intel/alderlake: Move C State Demotion to mainboard configSean Rhodes
Rather than disabling C State demotions for every single Raptor Lake board due to an issue with S0ix, regardless of if they even use S0ix, configure it in the mainboard. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-26mb/google/brya/var/dochi: Add memory configMorris Hsu
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:298337185 BRANCH=firmware-brya-14505.B TEST=FW_NAME=dochi emerge-brya coreboot Change-Id: I182e287423e6f784712c5004a6fe2d12a5b36190 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-09-26mb/google/dedede/var/taranza: Add power limits for JSL N4500 and N5100Sheng-Liang Pan
Add PLx from JSL PDG (ID: 613095) in taranza devicetree. Add ramstage.c in Makefile.inc and update Taranza power limits in taranza ramstage.c. BUG=b:296004956 TEST=emerge-dedede coreboot and check psys and PLx value on taranza Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Id43bb91bc9efb91cb074b075122cce4f22e0716c Reviewed-on: https://review.coreboot.org/c/coreboot/+/77857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-09-26mb/google/rex/var/rex0: Configure I2C5 timingIvy Jian
Configure I2C5 timing in devicetree to ensure I2C devices meet timing requirement. BUG=b:300177424 TEST=Build and check I2C devices timing meet spec. | | I2C5-Before | I2C5-After | |-------------|-------------|------------| | FSMB(KHz) | 445.400 | 343.638 | | TLOW(us) | 1.543 | 2.068 | | THIGH(us) | 0.475 | 0.604 | | THD:STA(us) | 0.603 | 0.711 | | TSU:STA(us) | 0.612 | 0.611 | | TSU:STO(us) | 0.605 | 0.611 | | TBUF(us) | >1.914 | >2.044 | Change-Id: I3bb678b66d55c6bfaff76e3e5500a2a3bc3a2c61 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78111 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26mb/google/nissa/var/pirrha: Add 4th DTT sensorSeunghwan Kim
Add 4th sensor device for DTT tuning. BUG=b:292134655 TEST=Built and verified DTT tool could monitor the new sensor device Change-Id: I62f50711af81dfc1566d655f6dcfc66f68dbc794 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2023-09-25mb/google/oak: Move common selects to BOARD_GOOGLE_OAK_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_OAK_COMMON. Thus, move all selects to the latter option. Change-Id: Id80b8a9bcad9337c8aa76fa6e5d2c9752b8021b7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-25mb/google/guybrush: Use only one option for common selectsFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_BASEBOARD_GUYBRUSH. Thus, move all selects to the latter option. Change-Id: I570c3cfd3d100ad90e35ec5d89686cb6a4bd8e82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-25mb/google/brya: Add SOF driver entries for Nissa-based boardsMatt DeVillier
Facilitates correct profile selection by SOF Windows drivers. Profiles for nokris and quandiso will be added once correct board configs can be determined. TEST=build/boot Win11 on google/craask, verify correct audio profiles loaded, audio functional. Change-Id: Id4582b5dd74a4905ea509813ec99663577360095 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-09-25mb/google/brya/var/dochi: add generic LPDDR5 SPDs for DochiMorris Hsu
Add Makefile.inc to include five generic LPDDR5 SPDs for the following parts for Dochi: DRAM Part Name ID to assign MT62F1G32D2DS-023 WT:B 0 (0000) K3KL8L80CM-MGCT 1 (0001) H58G56BK8BX068 0 (0000) BUG=b:298337185 TEST=USE="project_dochi emerge-brya coreboot" Change-Id: If0fd4bc950cef484db53b7b21849cfdfdd7816a5 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-25mb/google/corsola: Move board-specific selects to board optionsFelix Singer
Instead of selecting board-specific options under the common option and making them conditional, move them to their related board option. Change-Id: If9bea61cb84590e7455add908fa7722c60444503 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-25mb/google/corsola: Fine tune LCM ADC voltagesRuihai Zhou
The tolerance of LCM voltage table is too small which leads to wrong panel ID detection. Fine tune LCM ADC voltages based on hardware calculations. BUG=b:300418909 TEST=FW screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Id8dec043584f4c552837f70adb491584bfda7acf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-09-23mb/google/cherry: Move common selects to BOARD_GOOGLE_CHERRY_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CHERRY_COMMON. Thus, move all selects to the latter option. Change-Id: I080201761d0a06d3b8a5a29de6085dde58960a60 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75085 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/asurada: Move common selects to BOARD_GOOGLE_ASURADA_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_ASURADA_COMMON. Thus, move all selects to the latter option. Change-Id: Id80523dce70f13f64a49b71656276c51e80ae5cd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75084 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/rex: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id69ea99b452e4214fcc81335a5c961b4da3ce48b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-23mb/google/veyron: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id85503a5ec970ea92c07b99ec7048c521d85c79b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/corsola: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id450a4b6e409a548ee4d79b8b2ebf30ef61a3e27 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78083 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/skyrim/frostflow: Hide fingerprint reader from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on frostflow, verify unknown device for the fingerprint reader no longer present. Change-Id: I666e92706f698608f2df92c8296cfb615d5ece67 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/guybrush: Hide I2S machine driver from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on dewatt, verify unknown device for the ACP machine driver no longer present. Change-Id: I44d25fd2ea75593383cbb14f2324d4376b399de7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/zork: Hide I2S machine driver from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on morphius, verify unknown device for the ACP machine driver no longer present. Change-Id: I14347ab6c840066db4ff700eff1aad4cf6faf66b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/nissa/var/quandiso: Update USB port configRobert Chen
1. Support world facing usb camera on usb2_port7. 2. Update MB/DB fw_config to distinguish LTE and non-LTE devices. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0c508475fdc86f0d7357f19684bdaae06e77fc27 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77398 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Add P-sensor supportRobert Chen
- GPIO changes: GPP_B5 ==> I2C_P_SENSOR_SDA GPP_B6 ==> I2C_P_SENSOR_SCL GPP_H19 ==> P_SENSOR_INT_L - I2C SX9324 support - Disable GPIOs when sub board LTE not used BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5ed82b125b6c594225efca418017ef42f4f63b9d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-22mb/google/nissa/var/quandiso: Add SD card supportRobert Chen
GPIO changes - GPP_D8 ==> SD_CLKREQ_ODL - GPP_D17 ==> SD_WAKE_N - GPP_H12 ==> SD_PERST_L - GPP_H13 ==> EN_PP3300_SD_X Genesys Logic GL9750 support BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib7c80f43680481c0d1a18662fa494012390a984d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77391 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Disable WCAM supportRobert Chen
Quandiso doesn't support mipi WCAM. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I8a166d0bb1c034f2e3a5af7456500abd078e93f9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77389 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Update initial files based on yavillaRobert Chen
Update files copied from yavilla - fw_config setting - GPIO setting - Kconfig setting - overridetree setting - SPD memory parts - variant setting BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage flash bin file in DUT Change-Id: Ibbef42a1f891d0cf0309aa76edd7ec5dd664588e Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77361 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/dedede: Fix SOF config for unprovisioned audio ampMatt DeVillier
Dedede boards which select AUDIO_AMP_UNPROVISIONED via fw_config use rt1015 for the speaker topology, not max98360a. TEST=build/boot Win11 on google/magpie, verify correct audio profile selected. Change-Id: I5b75bd8fd37d2837de3c5bd25a02411a6982103b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-22mb/google/puff: Add VBT for Genesis variantMatt DeVillier
Add data.vbt file and Kconfig to use it. Extracted from google firmware genesis_13324.283.0 TEST=build genesis with FSP GOP display init Change-Id: If836b214da1350111d7b7d1f24865199f814c521 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-09-22mb/google/puff: Add VBT for Ambassador variantMatt DeVillier
Add data.vbt file and Kconfig to use it. Extracted from google firmware ambassador_13324.283.0 TEST=build ambassador with FSP GOP display init. Change-Id: I5c47700c5abe7d96112702d48a2b749f1784a494 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78032 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-22mb/google/puff: Set early GPIOs to enable bootblock consoleMatt DeVillier
Without the PCH UART GPIOs set early, there is no serial console output until ramstage. Add them to the early GPIOs for all puff variants. TEST=build/boot google/puff (wyvern) with serial console enabled, verify console output starts in bootblock. Change-Id: Ica0506b2b80e4fac0d3ca11b4cfdd128ce424b36 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78029 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/brya: Init TPM in bootblock when not using vbootMatt DeVillier
Brya queries the TPM in early ramstage (pre-device init) to determine if the CR50 has support for long-pulse interrupts. If the TPM (and underlying I2C controller) hasn't already been setup in verstage, it will fail to do so in ramstage since the I2C controller has not yet been initialized. To work around this, initialize the TPM in bootblock for the non-vboot case, to ensure the I2C controller is set up when needed in early ramstage. TEST=build/boot google/brya (banshee), verify no I2C errors in cbmem console when initializing TPM in early ramstage. Change-Id: I26f0711a9cc4c2eb9837f258cadf391d337994c9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78028 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 00:48:29 +0000