mb/google/dedede/var/taranza: Add power limits for JSL N4500 and N5100

Add PLx from JSL PDG (ID: 613095) in taranza devicetree.
Add ramstage.c in Makefile.inc and update Taranza power limits in
taranza ramstage.c.

BUG=b:296004956
TEST=emerge-dedede coreboot and check psys and PLx value on taranza

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Id43bb91bc9efb91cb074b075122cce4f22e0716c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>

3 files changed, 49 insertions, 0 deletions

diff --git a/src/mainboard/google/dedede/variants/taranza/Makefile.inc b/src/mainboard/google/dedede/variants/taranza/Makefile.inc
index f6abb34693..c4bbd20ede 100644
--- a/src/mainboard/google/dedede/variants/taranza/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/taranza/Makefile.inc
@@ -3,3 +3,4 @@
 ramstage-y += gpio.c
 
 ramstage-y += variant.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
index b85d043356..3b2f69390e 100644
--- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
@@ -25,6 +25,19 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+		.tdp_pl4 = 60,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+		.tdp_pl4 = 60,
+	}"
+
 	# Enable Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
 	register "PcieRpEnable[2]" = "1"
diff --git a/src/mainboard/google/dedede/variants/taranza/ramstage.c b/src/mainboard/google/dedede/variants/taranza/ramstage.c
new file mode 100644
index 0000000000..afb3fc7e34
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/taranza/ramstage.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+
+/*
+ * Psys_pmax considerations
+ *
+ * Given the hardware design in taranza, the serial shunt resistor is 0.01ohm.
+ * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A
+ * instead of real system power. The equation is shown below:
+ * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x R631/(R631 + R638)
+ * R631/(R631 + R638) = 0.5325 = 36K / (36K + 31.6K)
+ *
+ * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input
+ * current and the actual system power. Since there is no voltage information
+ * from PSYS, different voltage input would map to different Psys_pmax settings:
+ * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W
+ * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W
+ * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W
+ *
+ * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
+ * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system
+ * power = 120W * 5A / 6.009A = 100W, which is the actual system power.
+ */
+const struct psys_config psys_config = {
+	.efficiency = 97,
+	.psys_imax_ma = 6009,
+	.bj_volts_mv = 19000,
+	.bj_power_w = 65,
+};
+
+void variant_devtree_update(void)
+{
+	variant_update_psys_power_limits(&psys_config);
+}