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The current subsystem ID used by the amps may end up getting used
again for future products, therefore this CL updates the subsystem
ID to 103C8C08, which was specifically generated for this amp.
BUG=b:202484541
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: I399d8d99ead4fb6fdfa24c2a7a3e3d5e63603b8b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:238937091
TEST=Dump the SSDT on nivviks and check that the wifi device has the
DmaProperty.
Change-Id: I910b7da7050f9aebfe0eb58552c82b1b29de3772
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add FW_CONFIG probe for new audio sku:
ALC5682I + MAX98357
BUG=b:243474931
TEST=Boot to OS and verify audio devices are set based on
fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I16af6cf4644c473034e184e95ff2038ca31b20de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67016
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.
BUG=b:239670216
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ibc7116e8dc5367fd94d29aba36b91778d0c21e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Follow the "619907 Alder Lake-S and Raptor Lake-S Platform" and "685472 Intel® Dynamic Tuning Technology (Intel® DTT)" to override tdp pl1 in 15w cpu MSR to 55w and in 28w cpu MSR to 64w.
BUG=b:236294162
TEST=emerge-brask coreboot and check MSR_Package Power Limit-1 in 15w and 28w CPU is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Icb3d7c72b672fbd3e2a9f7ad1f2d1cb2ffc798c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66910
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because the poweron state of some of the WWAN GPIOs is the
asserted state, this patch fixes the poweron sequence so that the
WWAN module is always correctly powered on, in both cold and warm
reboot scenarios.
BUG=b:233564770
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I4ec8312c30392b9ca0a3e0321cb4578e76ec5787
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates
can be enabled and appear functional.
BUG=b:240390998
TEST=lspci reports them as functional, MODS does not hang
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Converge as many of the GPU's GPIOs to use PLTRST# as the reset signal
explicitly, as the hardware engineers requested this.
BUG=none
TEST=boot and reboot agah, dGPU still visible on PCIe bus
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I78e58eb17cadc95083571affbecb4e1ce0adf16a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66809
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Support oem_variables and change based on EC notify event.
BUG=b:238921409
TEST=emerge-draco coreboot
1. check ACPI object ODVX has oem_variable[0]=0
Name (ODVX, Package (0x06)
{
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
}
2. check can get EC oem variable change notify in the kernel log
Change-Id: Ibd856563a43d73a3b1be09b3fbebca1b36b5eab1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66575
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new skolas variant, which is a variant of brya's skolas
baseboard.
BUG=b:242869976
BRANCH=firmware-brya-14505.B
TEST=none
Change-Id: I7f9f0389d8b1bf75d8652cbcc9d0c15d3a529802
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable DPTF oem_variables and override based on CPU match id.
BUG=b:236294162
TEST=emerge-brask coreboot and check the value in odvp0 is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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bypass power
Add FW_CONFIG probe to separate ext fivr settings for Pujjoteen
and others(Pujjo and Pujjoflex)
BUG=b:242663554
TEST=Boot to OS and verify that ext_fivr_settings are set based on
fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6bb6d1701c55459cf331dd2f3ffe07f91bca2fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Configure GPIOs according to schematics.
BUG=b:242277219
TEST=emerge-nissa coreboot
Change-Id: Id7412059ba98d58f7014ab7201ea8958ede5905e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Update Devicetree according to yaviks's design.
BUG=b:242277219
TEST=emerge-nissa coreboot
Change-Id: I5d91cccbb44787bcbe7258a817ff97b6dce86c2e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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DPTF Policy and temperature sensor values from thermal team.
BUG=b:242797681
TEST=build FW and boot to OS.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4365f87843a4408ae457e7ef27291fdaa0d5bde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66827
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40msec on ADL-N
variants.
Boot time data:
Before:
* 955:returning from FspSiliconInit 1,231,364 (117,051)
After:
* 955:returning from FspSiliconInit 1,198,221 (79,497)
BUG=b:241850107
TEST=Verified that boot time is reduced by ~40msec and also S0i3
is working.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iaeaa8bcdf8467fdd467a10a98dd7582e8e0b067c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The infrastructure for selecting an appropriate firmware image to use
the right descriptor is now ready so runtime descriptor updates are no
longer necessary. Since the different descriptor builds split along
HDMI/USB-C lines for nereid, a single VBT file can be used for each,
removing the need for runtime VBT selection as well.
BUG=b:229022567
TEST=Nereid type-C and HDMI outputs work as expected
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: Idf1fbd6c26203adbda002dec3f11e54a7b9f9b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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DPTF Policy and temperature sensor values update from thermal team.
BUG=b:237640264
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I45b4f80cbec0723c63ac7fc7176e13ae5a2b54c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66365
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For board revs 3 and later, the PG pin for the NVVDD VR moved from
GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that
this code will write the correct GPIO # to depending on the board rev,
and we'll use that instead.
BUG=b:239721380
TEST=still works on board rev 2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Modify GPP_D17 setting for SD_WAKE_N.
BUG=b:242647845
TEST=Build and boot on pujjo
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Iacd89d27174869e34c48d1f62793ddc45b43f3f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Currently, to enable/disable LTE based on fw_config on nissa, we have
two sets of GPIOs: lte_enable_pads and lte_disable_pads. This was to
prevent the SAR interrupt pin GPP_H19 from floating for the short period
of time between enabling it in gpio.c and disabling it in fw_config.c
(see CB:64270 for more details).
With the new pad-based GPIO overrides (CB:64712), this is no longer an
issue since the gpio.c and fw_config.c overrides are applied at the same
time. So simplify the LTE GPIO configuration by enabling all the LTE
pins in the variant gpio.c, then disabling them in fw_config.c if
needed.
BUG=b:231690996
TEST=LTE still works on nivviks
Change-Id: I5bf20a027414ea5e7c1f198d69e355c76f467244
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66776
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:242277219
BRANCH=None
TEST=run part_id_gen to generate SPD id
Change-Id: I46c168482113beb7cd28f387ed495847aba8602f
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Create the yaviks variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:242277219
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVIKS
Change-Id: Id60fe0e54a8e0196a302141f58c6695779ac251a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add GPIO configuration and device tree to enable the chip.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=Patch linux with NXP's pending drivers
UWB device is probed and can respond to a simple hello packet
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
- Set pre-wake randomization time (DPA) to 100
BUG=b:241349500
TEST=build FW and checked fsp log.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4a1540de8c3ee74695631acc8181dcc446fe137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66783
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add FW_CONFIG probe based on pujjoteen boxster of below devices:
LTE, SD card, stylus, WFC camera, AUDIO
BUG=b:236158122
TEST=Boot to OS and verify that above devices are set based on
fw_cofnig.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I49fc5461e7affba68a6b89bf166c84598fbfa088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66741
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ghost has two amps and address are 0x3c and 0x3d.
BUG=b:231581723
BRANCH=firmware-brya-14505.B
TEST=max98396 driver can get the DSD property correctly.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3b6a331ca42e97f984f3a585726c02452bb067f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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EN_PP3300_EMMC will change to GPP_A21 to meet DP++ function and it based on Moli GPIO Table_20220803.xlsx. But it will let current eMMC skus can't boot into OS, so use the board_ver to decide which gpio table return and set override_gpio_table_id2 and early_gpio_table_id2 based on Moli GPIO Table_20220803.xlsx
1. set GPP_A21 to EN_PP3300_EMMC
2. set GPP_A22 to NC
3. set GPP_E20 to DDIC_DP_CTRCLK
4. set GPP_E21 to DDIC_DP_CTRLDATA
BUG=b:241370405
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I0a2c8684d140738f43658cd6075ed083eee44e65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Since the VW GPIOs are not in the baseboard GPIO table, they do
not actually override anything, and hence do not actually get
programmed. This patch moves the programming from the ramstage
table to the bootblock table so they get programmed.
BUG=b:214581763
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I42db44d38df20dd2695921e2f252be163f6b17f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add OV 5675 MIPI camera to ghost, sensor eeprom, and IPU device to
device tree. Enable config for MIPI camera.
BUG=b:241343306
BRANCH=firmware-brya-14505.B
TEST=with ghost overlay changes, camera in camera app works
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: Ie079e43ae0f34efba396331922ea4a89eda72128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.
For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.
Similar results are observed on Raptor Lake.
BRANCH=firmware-brya-14505.B
BUG=b:240669428
TEST=verify that EPP is back to the by default 50% setting
`iotools rdmsr 0 0x774'
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I735ad9d88c7bf54def7a23b75abc4e89a213fb61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit 938f33e9f7756d730a1da278679087476a476bf2.
A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.
For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.
BRANCH=firmware-brya-14505.B
BUG=b:240669428
TEST=verify that EPP is back to the by default 50% setting
`iotools rdmsr 0 0x774'
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Icacc555e62533ced30db83e0a036db1c85c0bfa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for taniks board. Please refer Intel doc#723158 for
more information.
BUG=b:241965786
TEST=Verify on taniks boards.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib95430c7ba9d84f8bafcb1febcff9b4e4038cadc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Moli has 90W adapter for 15W SOC and 135W adapter for 28W SOC, so modify the Psys_PL2 for both 15W and 28W SOC.
-set 90W Psys_PL2 for 15W SOC
-set 135W Psys_PL2 for 28W SOC
BUG=b:242119726
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: If8f9006d797d74f6d5d802d445edc425a4700420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for taeko board. Please refer Intel doc#723158 for
more information.
BUG=b:241965786
TEST=Verify on taeko/tarlo boards.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I03042906d5bea9b9010016adb98fbe68e2dc92f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add new ram_id:0001 for memory part H9HCNNNCPMMLXR-NEE.
BUG=b:241494931
TEST=none
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iee9f881d8ab21396d208a6af9f0cec8414cb50a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
Enable RFIM Policy, request by RF team.
BUG=b:239657092
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Id0f425d75a1ac9486a9284d4e8320ba4c63b182f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
|
Add WiFi SAR table for joxer.
BUG=b:239788985
TEST=build FW and checked SAR table can load by WiFi driver.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ia8dddf454e441840233fa4405704ee1f0a8ed86c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66522
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Pujjo support WWAN device, enable USB3.0 port 3 for WWAN device
BUG=b:241322361
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Iafe2ea18663794138e0a27879fc108d23eb81456
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
This update follows suggestions from Martin Roth about the contents of
the comment.
Change-Id: Ic296bcd6a0fb250426f5d75aac69a3fa0f2aaf32
Signed-off-by: Kevin Chowski <chowski@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This gets the display working.
BUG=b:240884260
BRANCH=firmware-brya-14505.B
TEST=display works in both depthcharge and linux
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I03edac865d68ef48e86d47a04f27ed84894f2f7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66395
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
1. Add active policy
2. Set critical policy trigger point to 105C
3. Correct TSR location
BUG=b:240634844
TEST=emerge-draco coreboot
values provided and verified by thermal team
Change-Id: I0d91bad03cbdeea5c84b533580ac98072ce0110b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
When GPP_B2 output high, there is a leakage path. This patch fix it by
setting the pin NC.
BUG=b:233959105
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I3c833d5d62c715960dcb27494a0b9b93c91e8f2f
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Set tcc_offset value to 3 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:240600260
TEST=emerge-draco coreboot
verified by thermal team
Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Follow latest schematic, GPP_A17 is used to enable AMP power.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check I2C scan can see the AMP return ACK.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Configure eMMC DLL tuning values for Craask board.
BUG=b:238985924
TEST="Use the value to boot on Nivviks and Craask successfully."
Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Disabling the Package C-state demotion feature for brya baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
DPTF Policy and temperature sensor values from thermal team.
BUG=b:236294162
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Add CS42L42 support in device tree.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check cs42l42 driver can probe successfully in kernel.
cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Remove the parameter and set I2C bus speed to fast. Will fill the
tuning value after real tuning.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Create the gaelin variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:239514438
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GAELIN
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
set i2c address to 0x14 for Goodix touchscreen
BUG=b:239180430
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
The EEs noticed this pin was misbehaving; it was accidentally set to a
low output, but should be open-drain (NC). This patch fixes that.
BUG=b:237837108
TEST=verified by EEs
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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For some yet unknown reason, when this GPIO is locked, there is an
interrupt storm for IRQ #9 apparently caused by GPE 0x66. GPP_F14 is set
to GPE 0x64 on the ADL platform, so this doesn't quite make sense. This
patch removes the lock and fixes this IRQ storm, but the root cause is
not identified yet.
BUG=b:236997604
TEST=`grep ' 9:' /proc/interrupts` shows a reasonable value now
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3d1c66fac80a173798ae33e48b1776d9f4fb5eaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
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After staring at lots of scope shots, the EE has determined that a few
modifications to the GCOFF sequence can be made:
- Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion
- Remove delay after ramping down FBVDD
This patch implements these minor changes.
BUG=b:240199017
TEST=verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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After some debugging, it has been determined that the ASPM L0s substate
is functional, but there is still some problem with ASPM L1 substates,
so this patch updates ASPM status for the dGPU from disabled to L0s
only.
BUG=b:240390998
TEST=tested with nvidia tools
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Generate SPD id for hynix H54G68CYRBX248
BUG=b:239899929
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id
Change-Id: I96babe340678ca9b82b06d3193b93a7676f23fef
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Generate SPD id for Hynix H54G68CYRBX248
BUG=b:239888704
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id
Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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GPP_F0 to GPP_F4 is for CNVi and should be NF1.
GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=CNVi wifi can get probed in kernel.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
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ChromeOS connection manager (shill) already
has support for dock MAC address passthrough, therefore remove the
code to pass a dock's MAC address in ACPI.
BUG=b:235045188
TEST=build coreboot
Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: I78320a7c6b0fd5392e24b63bff234229a3f4b9bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66040
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow latest schematic 6/27 to update the DQ map.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8d0de04a001cab53a245185707ebc9da7a501ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66122
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Add critical, passive policy, and pl values from thermal team.
BUG=b:239495499
TEST=Build and test on MB, system can boot to OS.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I8beb3b57ff56c6fe413bb0e3dd43d693aee08e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66125
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Pujjo support WLAN device, enable PCIe port 4 for WLAN device
BUG=b:239899932
TEST=Build and boot on pujjo
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX
signal integrity issue.
2. Disable unused USB port.
BUG=b:238230292
TEST=build FW and check Type-A USB3 port0/port1 RX pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Joxer will have both eMMC and UFS SKUs, which require different
settings in the descriptor. So update the descriptor at run-time based
on fw_config.
By default, the descriptor is configured for UFS. This configuration
still boots fine on eMMC SKUs, it just might cause problems with S0ix.
This is a temporary workaround. It will be removed once we've
implemented a proper solution for configuring the descriptor differently
for different SKUs.
BUG=b:238234376
TEST=Make an identical change for nivviks. On both nivviks (eMMC) and
nirwen (UFS), check that it boots and that the logs show the descriptor
being configured as expected.
Change-Id: I14232eb773936f2ecd183687208d332136935601
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Add pujjo new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.
Micron MT62F1G32D4DR-031 WT:B
BUG=b:239776504
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I95eb194ecbd5d39f66eb566132e75af056899325
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66039
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C2 | | A0
C0 | MLB DB | C1
| |
+----------------+
BUG=b:216490477
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I96202b9ac9586975e960d6577d279c995c67f34e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66031
Reviewed-by: Won Chung <wonchung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Use fw_config Bit 0 and Bit 1 to control:
Bit 0 = 0 --> enable WFC
Bit 0 = 1 --> disable WFC
Bit 1 = 0 --> enable pen garage wake
Bit 1 = 1 --> disable pen garage wake
BUG=b:238045498
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I85bc4753bfd16fd460286aa2b3bb5f3341049f61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.
Possible values for field WFC bits include:
option WFC_ABSENT 0
option_WFC_MIPI_OVTI5675 1
option WFC_MIPI_OVTI8856 2
BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.
Change-Id: If797b79f0d094816eeb3df7bfded06e92e4e6a32
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This reverts commit 58f68fb0cb8e9824256a115d1ebdc840c281e987.
Reason for revert: ODM thermal team request that change IA/GT TDC
current back to 20A.
BUG=b:237230877
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6a5cfdc18afb6fe43a3d630e5fa3d77c19640fc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.corp-partner.google.com>
Reviewed-by: Vinay Kumar <vinay.kumar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
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We plan to make 3 firmwares which differ only by Kconfig options and
can share a common variant directory.
ghost4adl: Board with an ADL chip.
ghost4es: Board near identical but has RPL-ES chip.
ghost: Will have final RPL silicon.
Since they will only differ by Kconfig options and Intel binary blobs,
let's not duplicate the variant directory but instead share it in
common.
BUG=b:239456576
BRANCH=firmware-brya-14505.B
TEST="make menuconfig", verify layout of board selection
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Follow the LED modification request in ADL_Moli_SC_MB_2022_0601.pdf and
set the customized_leds to 0x0482 based on 7.4 Customizable LED Configuration in "REALTEK+RTL8111K-CG+SPEC+0116" for RTL8111K in moli.
BUG=b:218985167
TEST=emerge-brask coreboot and check RTL8111K LED behaviour
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia154d15ecf14b32a4d589abf27b9573693339a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65958
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.
Possible values for field WFC bits include:
option WFC_ABSENT 0
option_WFC_MIPI_OVTI5675 1
option WFC_MIPI_OVTI8856 2
BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.
Change-Id: I23bdaf7feaff2e6a4979c3da789ab877e6ac3af2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Adjust I2C speed for codec, TPM, touchpad.
BUG=b:237691531
TEST=Built and verified adjusted I2C speed < 400KHz
Change-Id: I203d137d61019235ddf38ef74607427db2a7e975
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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For brya/skolas, I2C1 is cr50, and I2C3 is Touchscreen
BUG=None
BRANCH=firmware-brya-14505.B
TEST=None
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4058e0f33b2bb6227a0af92941ed4e2eb56ba542
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for
IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX
failed.
BUG=b:236661824
TEST=emerge-brask coreboot and check USB3 port2 RX pass
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add wifi sar table for osiris
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
BUG=b:234951991
TEST=build FW and checked SAR table can load by WiFi driver.
Cq-Depend: chrome-internal:4871098
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I301dce3229a24dd72b12b84d9eb7606abe10cbba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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For brya, I2C1 is cr50, and I2C3 is Touchscreen
BUG=None
BRANCH=firmware-brya-14505.B
TEST=None
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id564d5ede43e745c607ddfd851ff03557d76ddec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Pujjo only support RTL1019 amp device, remove MX98360A device setting
BUG=b:238716919
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I92ba66e8656ea36511f88cf867f51ba95168592e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Since ASPM is not verified as fully functional yet, and the board is
still in development, this patch disables ASPM for the dGPU.
BUG=b:236676400
TEST=boot to OS in agah, lspci -vvv shows ASPM is disabled
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I525eeb18c57d45fd55335b63a59262066afc9567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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init overridetree.cb based on the latest schematic.
BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I22778cc2582abdc2e62d98c6b049a0fa4dd467e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Follow latest schematic to add EC_IN_RW_OD.
BUG=b:238786599
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I701a940992895b2058b8ddfc444a2e7b7b9531ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Add SSD power sequence and remove the redundant weak.
BUG=b:238786597
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0c1ce311d54fb92b27b17f50beda813fe66ad118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Add module MT62F1G32D2DS-026 WT:B and assign RAM code.
BUG=b:238674174
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I811e1bbb985efe4198928f30ff6396a5b4368856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65796
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the I2C bus timing for all enabled I2C buses.
BUG=b:237751906
TEST=Verify the build for volmar board and measure the freq
is under 400KHz
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Iffa128146f5d8bec6dd3d5c2d1e7efd96895dc6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65604
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the support for providing a MAC address
for a dock to use based on the VPD values set in the platform.
BUG=b:235045188
TEST=tested on Brya by setting VPD values and observing the string
returned by the AMAC() method:
> vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB"
> echo 1 > /sys/module/acpi/parameters/aml_debug_output
[acpi.aml_debug_output=1]
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: I61b2a5e18bc17abeea0846f17e9be343e852c2b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65603
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pujjo support FM101 WWAN, use wwan_power.asl to handle the
power off sequence
BUG=b:238281124
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I53cd45c8030855c267d870d68d009c454350621e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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Modify USB2.0 port[6] setting for WFC camera support
BUG=b:235182560
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I78dad102be2d915a251f6528eef07f2056001b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65777
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move audio codec item from fw_config to SSFC.
BUG=b:238353613
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I361ef54cd2ee3e0a423ed5086184936d6f09e099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Remove the pad configuration for GPP_B11
as this is not used in Nereid/Nivviks
BUG=b:227694137
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3a213ffece75b9a706b96dc142a7e35c8b5973f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Agah doesn't support TBT interface so disable it in devicetree, for
fitimage configuration is at chrome-internal:4846869.
BUG=b:224423318
TEST=Build and check DUT boots.
Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the VR domain settings based on the request of internal team.
- IA ac_loadline from 2.3mOhms to 2.4mOhms.
- IA dc_loadline from 2.3mOhms to 2.28mOhms.
- GT ac_loadline from 3.2mOhms to 3.13mOhms.
- GT dc_loadline from 3.2mOhms to 2.94mOhms.
BUG=b:237044562
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I665665ab8e3bcd6d4643f8b954b86fad3ef78ccd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Override tdp pl1 value to 30W in CPU MSR.
BUG=b:238268367
TEST=Boot to Chrome OS and check cpu log show "CPU PL1 = 30 Watts".
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibbd5ecc4b87ede5a62799020c741e5bff2952144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Based on comments on CL:65534, update the non-early GPIO table.
These are cases where Arbitrage wasn't able to find a useful
heuristic, or the memory straps, where Arbitrage sees them as NC in
the schematic.
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6e00892243cd6af99dc1921ee3fc712f6cbb58c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65710
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Customize brya baseboard early GPIO table to add mem straps for
ghost4adl, change I2C bus for TPM to pins H6/H7, and remove pins which
are not used on ghost4adl (E16, H13).
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I126a66fc5d24fbefec99abf87862c55b50c5e398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65534
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use USB4 fw_config to enable TBT PCIe RP0.
BUG=b:237619214, b:237623610
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ie3e51a0f30e0c9d20127c017436813d4ede95639
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65696
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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On nissa, WLAN should be a wake source, so don't put it into D3cold
during suspend.
BUG=b:233325709
TEST=Wake-on-WLAN works on nereid
Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.
BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iffbd08351d083d2b550f309994af931bceb257d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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Configure the unused virtual CNVi BT GPIOs to NC since we
are using BT over USB mode for Nissa.
BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Id84823b9ad921ebd7ff773d6cce581563613745f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65669
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Disabling the Package C-state demotion feature for nissa baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=b:235005582
TEST=Boot and verify that S0ix issue is resolved.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I4d586b962c27b86ee75651dcd655bc0868504646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65664
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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