diff options
| author | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-07-13 08:51:07 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-07-14 21:28:10 +0000 |
| commit | f7ba881f98db6561e8c4964663f8774e1a82f41b (patch) | |
| tree | f9ba20ab8e02d1d8c4fcb7a8c0acb80b6f3517ae /src/mainboard/google/brya/variants | |
| parent | f2c1d8f061036c51b93b4e8b93f72d1dfe1ba4f3 (diff) | |
mb/google/brya/var/ghost4adl: Add EC_IN_RW_OD
Follow latest schematic to add EC_IN_RW_OD.
BUG=b:238786599
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I701a940992895b2058b8ddfc444a2e7b7b9531ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/ghost4adl/gpio.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/ghost4adl/gpio.c b/src/mainboard/google/brya/variants/ghost4adl/gpio.c index 07f44d3a13..e6a80f0fb5 100644 --- a/src/mainboard/google/brya/variants/ghost4adl/gpio.c +++ b/src/mainboard/google/brya/variants/ghost4adl/gpio.c @@ -249,8 +249,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> EC_PCH_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PLTRST, LEVEL, INVERT), - /* GPP_F18 : No heuristic was found useful */ - PAD_NC(GPP_F18, NONE), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* GPP_F19 : [NF1: SRCCLKREQ6# NF6: USB_C_GPP_F19] ==> GPP_F19 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF6), /* GPP_F20 : [] ==> UCAM_RST_L */ @@ -364,6 +364,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D3, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ |