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2021-03-12soc/amd: GOP: add UPD for VBIOS bufferNikolai Vyssotski
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP driver. BUG=b:171234996 BRANCH=Zork Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/amd/common/amdblocks/chip.h,psp.h: add missing stdint.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6fb53d88a840a782af7502660ff85205f84523b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/cezanne: add XHCI SCI/GEVENT setupFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32fd9b7165306266613e8497b5d07473b5fea02d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/common/amdblocks/smi.h: include types.h instead of stdint.hFelix Held
gpe_configure_sci has a size_t type parameter, so we need to include types.h instead of stdint.h here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2879d5cf27c432871a2b9c5c90bdd539b97f9d3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12cpu/intel/microcode: Fix caching logic in intel_microcode_findFurquan Shaikh
CB:49896 added support in `intel_microcode_find()` to cache the found microcode for faster subsequent accesses. This works okay when the function succeeds in finding the microcode on BSP. However, if for any reason, `cpu_microcode_blob.bin` does not contain a valid microcode for the given processor, then the logic ends up attempting to find microcode again and again every time it is called (because `ucode_updates` is set to NULL on failed find, thus retriggering the whole find sequence every time). This leads to a weird race condition when multiple APs are running in parallel and executing this function. A snippet of the issues observed in the scenario described above: ``` ... microcode: Update skipped, already up-to-date ... Microcode header corrupted! ... ``` 1. AP reports that microcode update is being skipped since the current version matches the version in CBFS (even though there is no matching microcode update in CBFS). 2. AP reports microcode header is corrupted because it thinks that the data size reported in the microcode is larger than the file read from CBFS. Above issues occur because each time an AP calls `intel_microcode_find()`, it might end up seeing some intermittent state of `ucode_updates` and taking incorrect action. This change fixes this race condition by separating the logic for finding microcode into an internal function `find_cbfs_microcode()` and maintaining the caching logic in `intel_microcode_find()` using a boolean flag `microcode_checked`. BUG=b:182232187 TEST=Verified that `intel_microcode_find()` no longer makes repeated attempts to find microcode from CBFS if it failed the first time. Change-Id: I8600c830ba029e5cb9c0d7e0f1af18d87c61ad3a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51371 Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12mb/google/dedede/var/boten: Increase Goodix touchscreen reset delay to 180 msStanley Wu
1. Follow GT7375P Programming Guide_Rev.0.6 to increase reset delay to 180ms. 2. Add TOUCH_RPT_EN pin(GPP_A11) control to fix TOUCH_RPT_EN pin keep high after system suspend. BUG=b:181711141 TEST=Build and boot boten to OS. Confirm TOUCH_RPT_EN pin keep low after system suspend. Change-Id: I98efbe68dab538906802647582eba0e068d9c11f Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51254 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12mb/google/dedede/var/boten: Configure I2C5 p-sensor high and low timeStanley Wu
Configure I2C bus 5 high and low time for p-sensor device. BUG=b:181727056 TEST=Measured the I2C bus frequency reduce to 387 KHz. Change-Id: I4b6d78d84b8ea145093f52bbb13684e2c6aa979c Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-12soc/intel/braswell: Factor out common `acpi_fill_madt`Angel Pons
Function is identical for all mainboards, so factor it out. Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12arch/x86/smbios_defaults.c: Default to motherboard typeAngel Pons
Nearly every board that coreboot supports is a motherboard. Change-Id: I1419874a0ba3f2e21568fa4b07b88f2048d10203 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50180 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/intel/common/block/fast_spi: Clean up headerAngel Pons
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex values and rename BIOS_CONTROL macros, as the register is not in SPIBAR. Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-12soc/intel/*: drop UART pad configuration from common codeMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Since all boards do pad setup on their own now, finally drop the pad configuration from SoC common code. Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-03-12mb/intel/adlrvp: do UART pad config at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-12mb/intel/shadowmountain: Enable Type-C subsystemV Sowmya
This patch adds the changes to enable the TCSS. BUG=b:175808146 TEST= Boot shadowmountain board, Test the functionality of the Type-C ports on both the mainboard and daughterboard by plugging in the Type-C devices and verified the devices are detected via EC console and in the OS. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/amd/common/block/smu: rename mailbox register definesFelix Held
Since we have the SMN access block now, rename the SMU mailbox interface registers to clarify that those are in the SMN register space. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/common: factor out SMN access function from SMU codeFelix Held
The SMU mailbox interface gets accessed over the SMN register space, so factor out those access functions into a separate common code SMN access building block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12mb/google/dedede/var/boten: Adjust p-sensor detect distance to 20mmStanley Wu
P-sensor vendor fine-tune detect distance as 20mm for WWAN SAR table switch. BUG=b:179000150 BRANCH=dedede TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected. un-approach: => register address: 0x01 value: 0x00 approach: => register address: 0x01 value: 0x02 Confirm WWAN SAR table work as expected. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I659721e60aa0766ed4c277dae43ded222e18ad1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51343 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11Documentation/acpi: switch example from edge to level interruptsDmitry Torokhov
Configuring touch controllers to use edge-triggered interrupts is not recommended as it is very easy to lose an edge when kernel drivers disable the interrupt for one reason or another, and recovering from this condition requires workarounds in the kernel. Unfortunately the example setting up a touchpad used edge-triggered interrupts, and this set up has been propagating through the boards. Let's switch the example to use level interrupts instead. Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-11mb/system76/lemp9: Drop unneeded memcfg values and commentsAngel Pons
This mainboard uses a Comet Lake SoC and mixed-topology DDR4 memory. Drop LPDDR-specific DQ and DQS mappings and comment about Cannon Lake. Change-Id: Icb986d1c074e64b3cfad3897b69d35d108f64bff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-11driver/intel/fsp2_0: Allow function to run serially on all APsAamir Bohra
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS passes in a boolean flag singlethread which indicates whether the work should be scheduled in a serially on all APs or in parallel. Current implementation of this function mp_startup_all_aps always schedules work in parallel on all APs. This implementation ensures mp_startup_all_aps honors to run serialized request. BUG=b:169114674 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I4d85dd2ce9115f0186790c62c8dcc75f12412e92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51085 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11src/cpu/x86: Add helper mp_run_on_all_apsAamir Bohra
Add a helper function mp_run_on_all_aps, it allows running a given func on all APs excluding the BSP, with an added provision to run func in serial manner per AP. BUG=b:169114674 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I74ee8168eb6380e346590f2575350e0a6b73856e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51271 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11soc/amd: move warm reset flag function prototypes to common codeFelix Held
Even though the implementation is different on Stoneyridge compared to Picasso and Cezanne, the function prototypes are identical, so move them to the AMD SoC common reset header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-11mb/google/mancomb: Add eSPI configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie3a3bb7526d734ae1936b8c4db43543b1174829d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable mancomb variantEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I554e7193494a4bbf005aaf2fb4efd6ded383fe07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable console UARTEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia03169c524dd12b8e7803ea8039c0e98a2b069e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable ACPI tablesEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I623fd052404a08cf0adb471bb654622960f1aa62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable CONFIG_CHROMEOSEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I45dcaa8b430721f864d4e5d78ae60883175085c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Add stubs to configure GPIOsEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7de5e4a4d2273d0ea5a84210ea0ce28d312eaa95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik
Convert the lines starts with whitespace with tab as applicable. TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes. Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11soc/intel/common/block: Add PCI IDs for EmmitsBurg PCHJonathan Zhang
According to Intel EmmitsBurg EDS, doc# 606161: * Add PCI devid for SPI. * Add PCI devid for ESPI (LPC). EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids Scalable Processor (SPR-SP). Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-11mb/google/guybrush: Enable USB ports in devicetreeMathew King
BUG=b:180529005 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I94d97a38d992f46b32c2c6aca4c8da688d3b76fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51257 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/amd/majolica: Enable USB ACPI in devicetreeMathew King
BUG=b:180529005 TEST=boot majolica, all USB ports work Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I6d3506bb4d54c7f8ea1e53576ef68d2aface6c89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-11mb/google/guybrush: Enable Chrome EC SKUID and BOARDIDMathew King
BUG=b:181910592 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I7851d3b11ea3b026b999019d02df1144f8393753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-11mb/google/guybrush: Log mainboard events to elogMathew King
BUG=b:180653357 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ifd43d9cc1832d8ed8d90c68ba88b5667e3c04f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10mb/google/guybrush: Add chomeec device to lpc bridgeMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I7b8b2ab73d66e0aaa0e9b7570661c885f7f777ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/51296 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/amd/cezanne: Add USB ports to chipset.cbMathew King
BUG=b:180529005 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I16de0869abd1eff4e89cf1b8128775858702acb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10mb/google/zork/var/shuboz: support regular/numpad touchpadKane Chen
Define the 26th bit of the fw_config for the regular touchpad and numpad touchpad selection. REGULAR_TOUCHPAD: 1 NUMPAD_TOUCHPAD: 0 BUG=b:174964012 BRANCH=zork TEST=build pass Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10mb/{amd/padmelon,google/zork}: Do not select `VGA_BIOS`Angel Pons
The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`. Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled. Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10mainboard: Drop unnecessary `VGA_BIOS` defaultAngel Pons
This option defaults to n already. Change-Id: I9f6407152f7cf2e2ac6fd1fff874e400f89a27ae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-10soc/amd/picasso: Fix PSP_SHAREDMEM_BASERaul E Rangel
PSP_SHAREDMEM_BASE made the assumption that _psp_sharedmem_dram would only match once. With CB:49332 there are now two symbols, and it was grabbing the wrong one. This change makes it so we match the exact symbol. It also switches to using awk to simplify the code. The bootblock.elf target that is added to the list of prerequisites also creates the bootblock.map file that gets used to extract the base address of the _psp_sharedmem_dram symbol. BUG=b:181354692 TEST=Boot zork past bootblock Fixes: 82d16b150ce3 ("memlayout: Store region sizes as separate symbols") Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79675bd73f964282b54bca858830e26de64037c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-10mb/amd/majolica: Update to use proper APCBs built for MajolicaMatt Papageorge
Some of the previous binaries were incorrect and should not be used for Majolica because they are templates instead of APCBs specifically built for the board. This APCB update also places the UMA region under 4G and size 32 MB which is essential for video output. TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory region size, base and alignment. Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10mb/google/zork/var/shuboz: adjust I2C2 data hold time for TPKane Chen
Add ".data_hold_time_ns" to follow I2C specification. The adjusted result aobut 0.315us(more than 0.3us) BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Id92fadcb54b9722709e32ced1f0be001b8c97975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10soc/amd/common/block/graphics/graphics: GOP: implement vbt_get()Nikolai Vyssotski
Even though AMD does not need VBT we still need to implement the vbt_get() function to not break the build with GOP driver enabled (see fsps_return_value_handler() in fsp2_0/silicon_init.c BUG=b:171234996 BRANCH=Zork Change-Id: I80a5131a9852a05998b55b847243748d24cf535f Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10mb/google/zork: Use SOC defines instead of magic numbersMathew King
BUG=b:182269526 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I351fb4fc493bb92b31e2c8bc946dfb048045335c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10soc/amd/picasso: Allow GPIO defines to be used in ASLMathew King
BUG=b:182269526 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib33a46a6eead84eaff2c4ac320800b7993f5c3f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10mb/google/zork/var/vilboz: Add Mainboard Type for VCORE ICJohn Su
To define Mainboard Type config, use the fw_config bit[26]. Check MB Type to modify SDLE settings for different VCORE IC. BUG=b:177193131 BRANCH=zork Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10mb/google/zork: add UPDM updating function before runing FSP-MChris Wang
Add the UPD updating hook in early stage for customization. BUG=b:117719313 BRANCH=zork TEST=build,check the hook function been executed. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I4954a438a51b29b086015624127e651fd06f971b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/amd/cezanne: select common APOB NV cache codeFelix Held
BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I660f19d18810c35dafcd75bcd1993216b7b09644 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51268 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02Ronak Kanabar
The headers added are generated as per FSP v2081_02. Previous FSP version was v2037. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h BUG=b:180758116 BRANCH=None TEST=Build and boot ADLRVP Cq-Depend: chrome-internal:3669105 Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10tests/Makefile.inc: Enable support for multiple test groupsJakub Czapiga
Until now output of all test groups run in single unit test were saved in the same file which caused Jenkins to fail because of existence of multiple root XML elements. Now each test group is saved to its own file containing its name at the end of the filename. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I21ba512073bc8d8693daad8a9b86d5b076bea03f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-10drivers/i2c: sx9310: Replace register map with descriptive namesGwendal Grignou
The current driver is using chip registers map to configure the SAR sensor, which is opaque, especially when the datasheet is not published widely. Use more descriptive names, as defined in Linux kernel documentation at https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml BUG=b:173341604 BRANCH=volteer TEST=Dump all tables, check semtech property: for i in $(find /sys/firmware/acpi/tables/ -type f) ; do f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat done In SSDT.dsl, we have: Package (0x06) { Package (0x02) { "semtech,cs0-ground", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, Package (0x02) { "semtech,proxraw-strength", Zero }, Package (0x02) { "semtech,avg-pos-strength", 0x0200 }, Package (0x02) { "semtech,combined-sensors", Package (0x03) { Zero, One, 0x02 } }, Package (0x02) { "semtech,resolution", "finest" } } Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-10soc/amd/stoneyridge/smihandler: sort includes alphabeticallyFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib317493fe938fe961aed06557e655ed8498e2694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10soc/amd/stoneyridge/smihandler: remove unused device/pci_def.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I388cdb1fb9b3decaa6eb6e0e4e538c620d3048a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10nb/intel/haswell: Finalize northbridge in ramstageAngel Pons
There's no need to finalize the northbridge in SMM. This also makes unification with Broadwell easier. Tested on Asrock B85M Pro4, still boots and registers get locked. Change-Id: I8b2c0d14a79e4fcd2e8985ce58542791cef9b1fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-10nb/intel/haswell/pcie.c: Add missing pre-ASPM initAngel Pons
Add devicetree configuration parameters for mainboard-specific settings, and provide reasonable defaults, which should usually be good enough. This is based on Haswell SA Reference Code version 1.9.0 (Nov 2014). Tested on Asrock B85M Pro4, registers now have the expected values. Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47223 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI modeAngel Pons
When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0 events in the SMI# handler, as these events have triggered a SCI. Do not ignore any other SMI# types, since they cannot cause a SCI. Note that these bits are reserved on APL and GLK. However, SoC-specific code already accounts for it. Thus, no special handling is needed here. Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-10soc/mediatek/mt8192: mt6315: revise initial settingHsin-Hsiung Wang
Remove unused boot status settings. Reset the power-off sequence to zero to meet hardware requirement. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: Ie9d39be532ec378bd6df6bf1b93307dae4068fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51246 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/mediatek/mt8192: mt6315: update initial flowHsin-Hsiung Wang
We saw EXT_PMIC_EN1 and PPVAR_DVDD_PROC_BC power off sequence failure, and after checking MT6315 MT6315 PMIC protection key summary.xlsx and MT6315 Top and CLK programming guide.docx, we found there are something wrong about the sequence of magic key protection flow and clk setting. Update correct initial flow. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51245 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/mediatek/mt8192: mt6315: update correct slave idHsin-Hsiung Wang
The initial settings for MT6315 were not applied correctly because the setup process didn't specify correct slave id (incorrectly always sending 0), and may cause failure in power off sequence. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-10drivers/usb/pci_xhci: Add cezanne xhci pci devce idMathew King
BUG=b:180529005 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I836bb838cc97593451f869490ff3c9dd156245b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51349 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10mb/google/guybrush: Add smihandlerMathew King
BUG=b:180507707 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I25ce0ca869ca854ff33242d2c416319e9688cc6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51264 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10mb/google/guybrush: Enable Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/amd/picasso/smihandler: sort includes alphabeticallyFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I674cff3352cd9f5d20b3d8f7e77339d045cadbb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51357 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/amd/cezanne/smihandler: add ELOG and SMMSTORE supportFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6bad684bc6a36bb4a2b83d10ff9da1c136f8bbd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51356 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/amd/picasso/smihandler: remove unused device/pci_def.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If4f75eadca101593cf37faf2722f4ea8f509a1f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51355 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/amd/*/smihandler: factor out ELOG and SMMSTORE handlerFelix Held
This also replaces the southbridge_ prefix of the handler functions with a handle_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib6ea1f4e2700c508a8bf72c488043e276ba4a062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51354 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09soc/amd/cezanne/Makefile: pass APOB NV parameters to amdfwtoolFelix Held
BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99d5984da82cfc98a106fc5c27e32fdc3cc13b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-09soc/amd/picasso/Makefile: simplify APOB NV parameter extractionFelix Held
TEST=Timeless build of amd/mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Raul Rangel <rrangel@chromium.org> Change-Id: Ie0e69532b7d13df87e2d9333ed34dbb008d2cc84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-09mb/google/brya: Define ChromeOS GPIO support in ACPI tbalesTim Wawrzynczak
Define the ChromeOS GPIOs (physical write-protect and virtual recovery mode) in ACPI tables so the OS knows which physical pad is used for them. BUG=b:181887865 TEST=flashrom_tester is able to "see" the WP GPIO Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3feed366afd6507894a1d31304891cc785a4d314 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51347 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09mb/google/brya: Reorganize flashmapTim Wawrzynczak
Intel ADL-P supports an additional memory-mapped 16MiB window into the platform SPI flash. Support for this window already exists at the SoC level, so all that is needed is to properly organize the flash map to take advantage of this. FW_SECTION_A moves down to the bottom of the available space in the lower 16MiB half, and FW_SECTION_B moves to the bottom of the top 16MiB half. RW_LEGACY is squashed down to 2M. BUG=b:182088676 TEST=build and boot to OS from FW_MAIN_A Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I60483b7e638c0a7e41f1f7e2b5503ae02e9906bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/51345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-09soc/intel/xeon_sp: Set SMI lockMarc Jones
Prevent writes to Global SMI enable as recommended by the BWG. Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-09soc/intel/xeon_sp: Add PCH lockdownMarc Jones
Add SOC_INTEL_COMMON_PCH_LOCKDOWN and PMC_GLOBAL_RESET_ENABLE_LOCK to meet device security requirements. LOCKDOWN has dependencies on SOC_INTEL_COMMON_PCH_BASE and several other common block devices. Add COMMON_PCH_BASE and COMMON_PCH_SERVER to pick up LOCKDOWN and the dependencies. COMMON_PCH_SERVER adds the following common devices that were not previously included by XEON_SP: SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG SOC_INTEL_COMMON_BLOCK_CSE SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG SOC_INTEL_COMMON_BLOCK_ITSS SOC_INTEL_COMMON_PCH_LOCKDOWN SOC_INTEL_COMMON_BLOCK_SATA SOC_INTEL_COMMON_BLOCK_SMBUS SOC_INTEL_COMMON_BLOCK_XHCI Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-09soc/intel/common/pch: Add server PCH optionMarc Jones
Add a server Kconfig option to select a subset of common PCH devices. Client devices are included if server isn't selected. This maintains the current Kconfig behavior. Change-Id: If11d1a51192dd87ad770b8aa53ce02b6a28b8da8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-09mb/google/asurada: Enlarge CONSOLE_CBMEM_BUFFER_SIZEYu-Ping Wu
Enlarge CONSOLE_CBMEM_BUFFER_SIZE from 128K (default) to 512K, so that more DRAM calibration logs can be stored in CBMEM console. BUG=b:181933863 TEST=emerge-asurada coreboot TEST="cbmem -c" shows the whole full calibration log BRANCH=none Change-Id: If82cbee5d2d5e97d98cbdaecda739d91a7cca0f8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51275 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09mb/google/octopus/var/fleex: Only check LTE sku on fleexEric Lai
Fleex has other project share the same FW. Only fleex has LTE sku. So we need to make sure it is fleex then check if LTE sku. BUG=b:181946744 BRANCH=octopus TEST=Check no SAR table can be loaded with sku id 4 and 5. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9f3d5fed4315fc716acad1a07735221d154c377e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
2021-03-08soc/amd,mb/google/,mb/amd: Move sleepstates.aslRaul E Rangel
This file is common for all the AMD platforms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08cbfs: Add cbfs_alloc() primitive and combine cbfs_load() and cbfs_map()Julius Werner
This patchs adds a new CBFS primitive that allows callers to pass in an allocator function that will be called once the size of the file to load is known, to decide on its final location. This can be useful for loading a CBFS file straight into CBMEM, for example. The new primitive is combined with cbfs_map() and cbfs_load() into a single underlying function that can handle all operations, to reduce the amount of code that needs to be duplicated (especially later when file verification is added). Also add a new variation that allows restraining or querying the CBFS type of a file as it is being loaded, and reorganize the documentation/definition of all these accessors and variations in the header file a little. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I5fe0645387c0e9053ad5c15744437940fc904392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-08cbfs: Pull handling of the CBFS_CACHE mem_pool into CBFS coreJulius Werner
This patch pulls control of the memory pool serving allocations from the CBFS_CACHE memlayout area into cbfs.c and makes it a core part of the CBFS API. Previously, platforms would independently instantiate this as part of boot_device_ro() (mostly through cbfs_spi.c). The new cbfs_cache pool is exported as a global so these platforms can still use it to directly back rdev_mmap() on their boot device, but the cbfs_cache can now also use it to directly make allocations itself. This is used to allow transparent decompression support in cbfs_map(). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0d52b6a8f582a81a19fd0fd663bb89eab55a49d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-08cbfs: Move trivial wrappers to static inlinesJulius Werner
The new CBFS API contains a couple of trivial wrappers that all just call the same base functions with slightly different predetermined arguments, and I'm planning to add several more of them as well. This patch changes these functions to become static inlines, and reorganizes the cbfs.h header a bit for better readability while I'm at it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If0170401b2a70c158691b6eb56c7e312553afad1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-08cbfs: Reflow cbfs.c and cbfs.h to 96-character line lengthsJulius Werner
Doing this all in one go keeps the files consistent and should make future refactoring easier. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4a701d24fc9ccd68dce8789aab15fd21964a55f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49330 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08mb/google/guybrush: Enable internal graphicsMathew King
BUG=b:181809122 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I64475a475e9b72a6edd04ce0728591e0649d9f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-08soc/amd/cezanne: Include gpio.c in smmMathew King
Mainboards can configure gpios in their smihandler. BUG=b:180507707 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I6c2b28f981f580cfb6f982a2d7e4c309d6f82e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-08soc/amd/cezanne: Allow GPIO defines to be used in ASLMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic29fa569899e7b77819ce7f72c6a748621684c40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-08soc/amd/common: Move GEVENT definitions to gpio_defs.hMathew King
This change will allow for GEVENTs to be used in ASL code. BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I77abd134555c21a32a302ee92cd080284cd2e634 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-08soc/amd/common/block/graphics/graphics: report GOP frame bufferNikolai Vyssotski
GOP needs to register the new framebuffer. BUG=b:171234996 BRANCH=Zork Change-Id: I17b6533520b0628df9529d09f70d5fc28339d522 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-08soc/intel/xeon_sp/cpx: Set the MRC "cold boot required" status bitDeomid "rojer" Ryabkov
If bit 0 of byte 0x47 is set FSP will perform full memory training even if previously saved data is supplied. Up to and including FSP 2021 WW01 it was reset internally at the end of PostMemoryInit. Starting with WW03 this is no longer the case and Intel advised that this bit should be reset externally if valid MRC data is present. Change-Id: I9c4191d2fa2e0203b3464dcf40d845ede5f14c6b Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-08mb/google/brya: Add Board and SKU ID support from Chrome ECTim Wawrzynczak
BUG=b:180456030 TEST=`mosys` is able to detect the platform correctly Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifbaa4a380bdb546bb54d579b46fe5760b2f4b754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-08mb/google/brya: Finish support for ChromeOS GPIOsTim Wawrzynczak
BUG=b:181887865 TEST=`crossystem` shows correct state of WP signal when toggled Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If49ca1d70cc36ab74d70e858336679c0a9a3258e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-08soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selectedRonak Kanabar
The default value for the LidStatus is "LidClosed" mean 0 Because of this GOP skips graphics initialization assuming lid is closed even though lid is open. This Patch is to set LidStatus UPD to 1 whenever RUN_FSP_GOP config is selected. BUG=b:178461282 BRANCH=None TEST=Build and boot ADLRVP and verify eDP is coming up in depthcharge Change-Id: I1648ae0f06e414b2a686e325acf803deb702b7a5 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-08soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 400KYu-Ping Wu
Move PRERAM_CBMEM_CONSOLE to SRAM L2C and increase its size from 15K to 400K. With this change, most part of the DRAM full calibration log can be stored in CBMEM console. BUG=b:181933863 TEST=emerge-asurada coreboot TEST=Hayato boots BRANCH=none Change-Id: I896884d298e197149f75865e9d00579124a34404 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-08soc/mediatek/mt8173,mt8183: revise SOC DRAM implementationXi Chen
Many header files and helper macros have been moved to the common folder and we want to use them in mt8173/mt8183 DRAM calibration code. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ifa483dcfffe0e1383cb46811563c90f0ab484d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51224 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08mb/google/asurada: Add generic DRAM groupsXi Chen
To reduce qualification effort, we want to pre-populate DRAM by their size, package type and geometry so when a new DRAM is introduced we don't need to spin off a new firmware release. Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I42ee170c159e551e840ab4e748f18f5149506b4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08soc/mediatek/mt8192: initialize DRAM using vendor reference codeHuayang Duan
Mediatek has released the reference implementation for DRAM initialization in vendorcode/mediatek/mt8192/dramc (CB:50294) so we want to use it to replace the derived calibration code in soc folder. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-08soc/mediatek/common: Move DRAM implementation from mt8192 to commonXi Chen
To reduce duplicated dram sources on seperate SOCs, add dpm, dram_init, dramc_params, memory(fast-k or full-k) implementations, also add dramc log level macro header files. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-08vendor: mediatek: Add mediatek mt8192 dram initialization codeXi Chen
This is the DRAM initialization code from the reference implementation released by Mediatek for MT8192. The DRAM calibration code can be taken as a standalone library, used by different boot loaders for initializing DRAM and following a different coding style (coreboot was using Linux Kernel coding style), so we have to put it in vendor code folder. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-08mb/google/kukui: Add Micron 4GB discrete LPDDR4X DDR supportJessy Jiang
Support 4G+128G MT29VZZZAD9GQFSM-046 W.9S9 discrete DDR bootup. BUG=b:162292216 BRANCH=kukui TEST=Boots correctly on Kukui. Signed-off-by: Jessy Jiang <jiangchao5@huaqin.corp-partner.google.com> Change-Id: I5657a007154bc52c6f0f27e1de6e3294a5e74ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-07nb/intel/haswell: Indent PCI ops with tabsAngel Pons
Change-Id: Ia338ce1a36aa0a14017201c1fc16f84915f55c07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint/me.c: Reorder functionsAngel Pons
Rearrange the code to ease comparing against Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3143f07ed845e0c6b1444817029a437db3b959e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint: Finalize ME in ramstageAngel Pons
Performing ME finalization in SMM does not seem to be required. Tested on Asrock B85M Pro4, ME still gets finalized successfully. Change-Id: I9fde40a54f3fb8da2fba46c531443fdd2e067077 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint/me.c: Use res2mmio()Angel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I87fa1ffb353135cc361ac6be30a4fc69e7f8ed47 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-07sb/intel/lynxpoint: Retype `mei_base_address` pointerAngel Pons
Also introduce uintptr_t cast and use PCI_BASE_ADDRESS_MEM_ATTR_MASK. Change-Id: I32fdcc6b1ffde1b0701218a3bd0a61ab827081b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>