diff options
| author | Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> | 2021-02-11 20:08:22 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-03-12 21:26:03 +0000 |
| commit | 2d24146aef39ef5a6b1d061a81c8c9e333886b5c (patch) | |
| tree | 3506d313964b785e8379a05bea0031561ff23932 | |
| parent | 7d3df29ce759434928d69a534abc51c537f26f02 (diff) | |
soc/amd: GOP: add UPD for VBIOS buffer
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP
driver.
BUG=b:171234996
BRANCH=Zork
Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/cezanne/fsp_params.c | 8 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fsp_params.c | 5 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspsUpd.h | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/picasso/FspsUpd.h | 4 |
4 files changed, 18 insertions, 3 deletions
diff --git a/src/soc/amd/cezanne/fsp_params.c b/src/soc/amd/cezanne/fsp_params.c index d3f9fcf555..b875dc02cb 100644 --- a/src/soc/amd/cezanne/fsp_params.c +++ b/src/soc/amd/cezanne/fsp_params.c @@ -2,6 +2,14 @@ #include <fsp/api.h> +static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) +{ + scfg->vbios_buffer_addr = 0; +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { + FSP_S_CONFIG *scfg = &supd->FspsConfig; + + fsp_assign_vbios_upds(scfg); } diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 2688b21a75..067ce2f280 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -175,7 +175,11 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg, scfg->pwrdown_bloff_to_varybloff = cfg->pwrdown_bloff_to_varybloff; scfg->min_allowed_bl_level = cfg->min_allowed_bl_level; } +} +static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) +{ + scfg->vbios_buffer_addr = 0; } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) @@ -189,4 +193,5 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) fsp_assign_ioapic_upds(scfg); fsp_usb_oem_customization(scfg, cfg); fsp_edp_tuning_upds(scfg, cfg); + fsp_assign_vbios_upds(scfg); } diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h index d4f8aeaa82..7025485e0c 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -51,8 +51,8 @@ typedef struct __packed { /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4[16]; - /** Offset 0x0140**/ uint8_t UnusedUpdSpace1[16]; + /** Offset 0x0130**/ uint32_t vbios_buffer_addr; + /** Offset 0x0134**/ uint8_t UnusedUpdSpace1[28]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 5aebf11b9e..4b6db36878 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -65,7 +65,9 @@ typedef struct __packed { /** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x; /** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x; /** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x; - /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[179]; + /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3]; + /** Offset 0x0150**/ uint32_t vbios_buffer_addr; + /** Offset 0x0154**/ uint8_t UnusedUpdSpace1[172]; /** Offset 0x0200**/ uint16_t UpdTerminator; } FSP_S_CONFIG; |