diff options
| author | Xi Chen <xixi.chen@mediatek.com> | 2021-02-05 11:45:12 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-08 01:49:52 +0000 |
| commit | 022b1b992f24890a04851dccc2829284a0431d6a (patch) | |
| tree | 1179f795920c5591f13b837a57353e5740bfc91c | |
| parent | 69da75411218c705b6b7375664523be707cb5258 (diff) | |
vendor: mediatek: Add mediatek mt8192 dram initialization code
This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8192.
The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
53 files changed, 85570 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 2d8613a60d..0e283ca1a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -614,6 +614,12 @@ M: Hung-Te Lin <hungte@chromium.org> S: Supported F: src/soc/mediatek/ +MEDIATEK MT8192 +M: Xi Chen <xixi.chen@mediatek.com> +S: Maintained +F: src/soc/mediatek/mt8192/ +F: src/vendorcode/mediatek/mt8192/ + ORPHANED ARM SOCS S: Orphaned F: src/cpu/armltd/ diff --git a/src/vendorcode/mediatek/Makefile.inc b/src/vendorcode/mediatek/Makefile.inc new file mode 100644 index 0000000000..06561ef24a --- /dev/null +++ b/src/vendorcode/mediatek/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOC_MEDIATEK_MT8192) += mt8192 diff --git a/src/vendorcode/mediatek/mt8192/Makefile.inc b/src/vendorcode/mediatek/mt8192/Makefile.inc new file mode 100644 index 0000000000..207eee54e2 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/Makefile.inc @@ -0,0 +1,5 @@ +subdirs-y += dramc + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include +CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8192/dramc/include -Isrc/vendorcode/mediatek/mt8192/include diff --git a/src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c b/src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c new file mode 100644 index 0000000000..d8fd41f451 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c @@ -0,0 +1,1243 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include "dramc_dv_init.h" + +//========================== +//PLL config +//========================== +static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate) +{ + U32 XTAL_FREQ = 26; + U8 PREDIV = 1; //0/1/2 + U8 POSDIV = 0; //0/1/2 + U8 FBKSEL = 0; //over 3800 1 otherwise 0 + U32 PCW; + U8 DIV16_CK_SEL = 0; + +#if EMI_LPBK_USE_DDR_800 // For Pe_trus DDR1600, sedalpbk DDR800 thru io + if(p->frequency==800) + { + POSDIV = 1; + } +#endif + +#if (fcFOR_CHIP_ID == fcMargaux) + if(A_D->DQ_CA_OPEN == 1) + { + DIV16_CK_SEL = 1; // For open loop mode DDR250 = 4G/div16, confirm with WL Lee + } + else +#endif + FBKSEL = (PLL_FREQ > 3800)?1:0; + PCW = (PLL_FREQ/XTAL_FREQ) << (8+1-FBKSEL-PREDIV-POSDIV); + + + mcSHOW_DBG_MSG((">>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL\n")); + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("data_rate = %d,PCW = 0X%x\n",data_rate,PCW)); + mcSHOW_DBG_MSG(("=================================== \n")); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL1), P_Fld(0, PHYPLL1_RG_RPHYPLL_TST_EN) | P_Fld(0, PHYPLL1_RG_RPHYPLL_TSTOP_EN)); + // @Darren, Mp settings sync @WL + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0) , P_Fld(0 , SHU_PHYPLL0_RG_RPHYPLL_RESERVED ) \ + | P_Fld(0 , SHU_PHYPLL0_RG_RPHYPLL_ICHP )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL0) , P_Fld(0 , SHU_CLRPLL0_RG_RCLRPLL_RESERVED ) \ + | P_Fld(0 , SHU_CLRPLL0_RG_RCLRPLL_ICHP )); + + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL2) , P_Fld(PREDIV , SHU_PHYPLL2_RG_RPHYPLL_PREDIV ) \ + | P_Fld(POSDIV , SHU_PHYPLL2_RG_RPHYPLL_POSDIV )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL2) , P_Fld(PREDIV , SHU_CLRPLL2_RG_RCLRPLL_PREDIV ) \ + | P_Fld(POSDIV , SHU_CLRPLL2_RG_RCLRPLL_POSDIV )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL1) , P_Fld(PCW , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW ) \ + | P_Fld(1 , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG ) \ + | P_Fld(0 , SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN )); //for DV could set 1 to solve clock jitter issue. + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL1) , P_Fld(PCW , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW ) \ + | P_Fld(1 , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG ) \ + | P_Fld(0 , SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN )); //for DV could set 1 to solve clock jitter issue. + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL1) , P_Fld(1 , SHU_PLL1_RG_RPHYPLLGP_CK_SEL ) \ + | P_Fld(1 , SHU_PLL1_R_SHU_AUTO_PLL_MUX )); //notice here. TODO. should create another function to manage the SPM related + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3) , P_Fld(0 , SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN ) \ + | P_Fld(1 , SHU_PHYPLL3_RG_RPHYPLL_RST_DLY ) \ + | P_Fld(FBKSEL , SHU_PHYPLL3_RG_RPHYPLL_FBKSEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3) , P_Fld(0 , SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN ) \ + | P_Fld(1 , SHU_CLRPLL3_RG_RCLRPLL_RST_DLY ) \ + | P_Fld(FBKSEL , SHU_CLRPLL3_RG_RCLRPLL_FBKSEL )); + if(A_D->DQ_CA_OPEN == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_CLK_CTRL0), P_Fld( A_D->DQ_CA_OPEN , SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3) , P_Fld( 1 , SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN ) \ + | P_Fld( DIV16_CK_SEL , SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3) , P_Fld( 1 , SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN ) \ + | P_Fld( DIV16_CK_SEL , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee + } +// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld(1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); + mcSHOW_DBG_MSG(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL\n")); +} + + +static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg) +{ + U8 TX_ARDQ_SERMODE=0; //DQ_P2S_RATIO + U8 TX_ARCA_SERMODE=0; //CA_P2S_RATIO + U8 ARDLL_SERMODE_B=0; + U8 ARDLL_SERMODE_C=0; + + mcSHOW_DBG_MSG((">>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n")); + switch (tr->DQ_P2S_RATIO) + { + case 4 : { TX_ARDQ_SERMODE = 1; break; } + case 8 : { TX_ARDQ_SERMODE = 2; break; } + case 16: { TX_ARDQ_SERMODE = 3; break; } + default: mcSHOW_DBG_MSG(("ERROR: tr->DQ_P2S_RATIO= %2d, Not support!!",tr->DQ_P2S_RATIO)); + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ14), P_Fld( TX_ARDQ_SERMODE , SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14), P_Fld( TX_ARDQ_SERMODE , SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6) , P_Fld( TX_ARDQ_SERMODE , SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6) , P_Fld( TX_ARDQ_SERMODE , SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1)); + + //Justin confirm that DES_MODE -> Deserializer mode, while DQ_P2S_RATIO=16 setting 3 others 2. in fact ANA could support some other mode, Here is an propsal option + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1)); + + switch (tr->CA_P2S_RATIO) + { + case 2 : { TX_ARCA_SERMODE = (0 + tr->CA_FULL_RATE); break; } + case 4 : { TX_ARCA_SERMODE = (1 + tr->CA_FULL_RATE); break; } + case 8: { TX_ARCA_SERMODE = (2 + tr->CA_FULL_RATE); break; } + default: mcSHOW_DBG_MSG(("ERROR: tr->CA_P2S_RATIO= %2d, Not support!!",tr->CA_P2S_RATIO)); + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD14), P_Fld(TX_ARCA_SERMODE, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6), P_Fld(TX_ARCA_SERMODE, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE)); + + switch (tr->DQ_AAMCK_DIV) + { + case 2 : { ARDLL_SERMODE_B = 1; break; } + case 4 : { ARDLL_SERMODE_B = 2; break; } + case 8: { ARDLL_SERMODE_B = 3; break; } + default: mcSHOW_DBG_MSG(("WARN: tr->DQ_AAMCK_DIV= %2d, Because of DQ_SEMI_OPEN, It's don't care.",tr->DQ_AAMCK_DIV)); + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(ARDLL_SERMODE_B , SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1)); + + switch (tr->CA_ADMCK_DIV) + { + case 2 : { ARDLL_SERMODE_C = 1; break; } + case 4 : { ARDLL_SERMODE_C = 2; break; } + case 8: { ARDLL_SERMODE_C = 3; break; } + default: mcSHOW_DBG_MSG(("ERROR: tr->CA_ADMCK_DIV= %2d, Not support!!",tr->CA_ADMCK_DIV)); + } + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), P_Fld(ARDLL_SERMODE_C , SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA)); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + + //DQ SEMI-OPEN register control + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0 ) \ + | P_Fld( tr->DQ_CA_OPEN , SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1 ) \ + | P_Fld( tr->DQ_CA_OPEN , SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1) , P_Fld((!(tr->DQ_SEMI_OPEN))&&(!(tr->DQ_CKDIV4_EN)), SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0 ) \ + | P_Fld((!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0 ) \ + | P_Fld( tr->PH8_DLY , SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1) , P_Fld((!(tr->DQ_SEMI_OPEN))&&(!(tr->DQ_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1 ) \ + | P_Fld((!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1 ) \ + | P_Fld( tr->PH8_DLY , SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1 )); + + + //CA SEMI-OPEN register control + if(tr->CA_SEMI_OPEN == 0) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6) , P_Fld( 0 , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA ) \ + | P_Fld( 0 , SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA ) \ + | P_Fld( 0 , SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld( 1 , SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN ) \ + | P_Fld( 1 , SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); + } else { + // @Darren, for DDR800semi + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6 , P_Fld( 1 , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA ) \ + | P_Fld( 1 , SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA ) \ + | P_Fld( 16 , SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA )); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_DLL_ARPI3 , P_Fld( 1 , SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN )); + //CHA CA as master + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); + //CHB CA as slave + vSetPHY2ChannelMapping(p, CHANNEL_B); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); + vSetPHY2ChannelMapping(p, CHANNEL_A); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + +//--------TODO ---20190721 WAITING DPHY KaiHsin & Alucary confirm this RG setting. +// if(a_cfg->DLL_ASYNC_EN == 1) +// { +// //CA as all master +// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); +// } else { +// DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); +// //CHA CA as master +// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); +// //CHB CA as slave +// vSetPHY2ChannelMapping(p, CHANNEL_B); +// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); +// vSetPHY2ChannelMapping(p, CHANNEL_A); +// DramcBroadcastOnOff(DRAMC_BROADCAST_ON); +// } + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6) , P_Fld( tr->DQ_CA_OPEN , SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13) , P_Fld( tr->CA_FULL_RATE , SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , P_Fld( tr->PH8_DLY , SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , P_Fld( tr->CA_PREDIV_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA)); + if(tr->SEMI_OPEN_CA_PICK_MCK_RATIO == 4) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6) , P_Fld( 0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA)); + } + else if (tr->SEMI_OPEN_CA_PICK_MCK_RATIO == 8) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6) , P_Fld( 1, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA)); + } else {} + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld( tr->DQ_TRACK_CA_EN, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1) , P_Fld( tr->DQ_TRACK_CA_EN, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2) , P_Fld( 1 , SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN )); + mcSHOW_DBG_MSG(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n")); +} + +//========================== +//DLL config +//========================== +static void ANA_DLL_non_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) +{ + U8 u1PDZone = (p->frequency >= 2133) ? 0x2 : 0x3; + + if(a_cfg->DLL_IDLE_MODE == 1) + { + if(a_cfg->DLL_ASYNC_EN == 1) + { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5) , P_Fld(0 , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA ) \ + | P_Fld(u1PDZone , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5) , P_Fld(1 , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0 ) \ + | P_Fld(u1PDZone , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0 )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5) , P_Fld(1 , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1 ) \ + | P_Fld(u1PDZone , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1 )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } else { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5) , P_Fld(0 , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA ) \ + | P_Fld(u1PDZone , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5) , P_Fld(1 , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0 ) \ + | P_Fld(u1PDZone , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5) , P_Fld(1 , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1 ) \ + | P_Fld(u1PDZone , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1 )); + vSetPHY2ChannelMapping(p, CHANNEL_B); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5) , P_Fld(1 , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA ) \ + | P_Fld(u1PDZone , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5) , P_Fld(1 , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0 ) \ + | P_Fld(u1PDZone , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5) , P_Fld(1 , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1 ) \ + | P_Fld(u1PDZone , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1 )); + + #if (CHANNEL_NUM>2) + vSetPHY2ChannelMapping(p, CHANNEL_C); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5) , P_Fld(0 , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA ) + | P_Fld(u1PDZone , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5) , P_Fld(1 , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0 ) + | P_Fld(u1PDZone , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5) , P_Fld(1 , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1 ) + | P_Fld(u1PDZone , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1 )); + vSetPHY2ChannelMapping(p, CHANNEL_D); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5) , P_Fld(1 , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA ) + | P_Fld(u1PDZone , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5) , P_Fld(1 , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0 ) + | P_Fld(u1PDZone , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5) , P_Fld(1 , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1 ) + | P_Fld(u1PDZone , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1 )); + #endif + + vSetPHY2ChannelMapping(p, CHANNEL_A); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI1) , P_Fld(0 , CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN ) \ + | P_Fld(0 , CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN ) \ + | P_Fld(0 , CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN ) \ + | P_Fld(0 , CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN ) \ + | P_Fld(0 , CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA ) \ + | P_Fld(0 , CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA ) \ + | P_Fld(1 , CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA ) \ + | P_Fld(0 , CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI1) , P_Fld(0 , B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI1) , P_Fld(0 , B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT)); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5) , P_Fld(0 , CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA ) \ + | P_Fld(0 , CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA ) \ + | P_Fld(0 , CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA ) \ + | P_Fld(0 , CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5) , P_Fld(0 , B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0 ) \ + | P_Fld(0 , B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0 )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5) , P_Fld(0 , B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1 ) \ + | P_Fld(0 , B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1 )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); +} + + +static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg) +{ + U8 u1Gain = 0; + if(p->frequency<=1600) + { + u1Gain = 2; + mcSHOW_DBG_MSG((">>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = %d\n",u1Gain)); + } + + mcSHOW_DBG_MSG((">>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL\n")); + if(a_cfg->DLL_ASYNC_EN == 1) + { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0) , P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?6:7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA ) \ + | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA ) \ + | P_Fld(!(a_cfg->ALL_SLAVE_EN) , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA ) \ + | P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA ) \ + | P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA)); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) \ + | P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) \ + | P_Fld( 0 , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA ) \ + | P_Fld( !(a_cfg->ALL_SLAVE_EN) , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } else { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0) , P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?6+u1Gain:7+u1Gain, SHU_CA_DLL0_RG_ARDLL_GAIN_CA ) \ + | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA ) \ + | P_Fld(!(a_cfg->ALL_SLAVE_EN) , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA ) \ + | P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA ) \ + | P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) \ + | P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) \ + | P_Fld( 0 , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA ) \ + | P_Fld(!(a_cfg->ALL_SLAVE_EN) , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA )); + + vSetPHY2ChannelMapping(p, CHANNEL_B); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0) , P_Fld( 7+u1Gain , SHU_CA_DLL0_RG_ARDLL_GAIN_CA ) \ + | P_Fld( 7 , SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA ) \ + | P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA ) \ + | P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA ) \ + | P_Fld( 1 , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) \ + | P_Fld( 0 , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA ) \ + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA ) \ + | P_Fld( 0 , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA )); + + #if (CHANNEL_NUM>2) + vSetPHY2ChannelMapping(p, CHANNEL_C); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0) , P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?6+u1Gain:7+u1Gain, SHU_CA_DLL0_RG_ARDLL_GAIN_CA ) + | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA ) + | P_Fld(!(a_cfg->ALL_SLAVE_EN) , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA ) + | P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA ) + | P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) + | P_Fld( a_cfg->ALL_SLAVE_EN , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) + | P_Fld( 0 , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA ) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA ) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA ) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA ) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA ) + | P_Fld(!(a_cfg->ALL_SLAVE_EN) , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA )); + + vSetPHY2ChannelMapping(p, CHANNEL_D); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0) , P_Fld( 7+u1Gain , SHU_CA_DLL0_RG_ARDLL_GAIN_CA ) + | P_Fld( 7 , SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA ) + | P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA ) + | P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA ) + | P_Fld( 1 , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) + | P_Fld( 0 , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA ) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA ) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA ) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA ) + | P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA ) + | P_Fld( 0 , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA )); + #endif + + vSetPHY2ChannelMapping(p, CHANNEL_A); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL0) , P_Fld( 7+u1Gain , SHU_B0_DLL0_RG_ARDLL_GAIN_B0 ) \ + | P_Fld( 7 , SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0 ) \ + | P_Fld( 0 , SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 ) \ + | P_Fld( 0 , SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0 ) \ + | P_Fld( 1 , SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld( 1 , SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) \ + | P_Fld( 1 , SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) \ + | P_Fld( 0 , SHU_B0_DLL1_RG_ARDLL_PGAIN_B0 ) \ + | P_Fld( 1 , SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0 ) \ + | P_Fld( 1 , SHU_B0_DLL1_RG_ARDLL_PHDIV_B0 ) \ + | P_Fld( 1 , SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0 ) \ + | P_Fld( 1 , SHU_B0_DLL1_RG_ARDLL_PS_EN_B0 ) \ + | P_Fld( 0 , SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0) , P_Fld( 7+u1Gain , SHU_B1_DLL0_RG_ARDLL_GAIN_B1 ) \ + | P_Fld( 7 , SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1 ) \ + | P_Fld( 0 , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 ) \ + | P_Fld( 0 , SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1 ) \ + | P_Fld( 1 , SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1) , P_Fld( 1 , SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) \ + | P_Fld( 1 , SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) \ + | P_Fld( 0 , SHU_B1_DLL1_RG_ARDLL_PGAIN_B1 ) \ + | P_Fld( 1 , SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1 ) \ + | P_Fld( 1 , SHU_B1_DLL1_RG_ARDLL_PHDIV_B1 ) \ + | P_Fld( 1 , SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1 ) \ + | P_Fld( 1 , SHU_B1_DLL1_RG_ARDLL_PS_EN_B1 ) \ + | P_Fld( 0 , SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 )); + mcSHOW_DBG_MSG(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL\n")); +} + +static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_DVFS_CORE_T *tr) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld( 0 , SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI3) , P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0 ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0 ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0 ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0 ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI3) , P_Fld((!(tr->DQ_SEMI_OPEN)) && (a_cfg->NEW_RANK_MODE), SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3) , P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1 ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1 ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1 ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1 ) \ + | P_Fld( !(tr->DQ_SEMI_OPEN), SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3) , P_Fld((!(tr->DQ_SEMI_OPEN)) && (a_cfg->NEW_RANK_MODE), SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2) , P_Fld( 1 , SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU ) \ + | P_Fld( 1 , SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA ) \ + | P_Fld( 1 , SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA ) \ + | P_Fld( 1 , SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA ) \ + | P_Fld( 1 , SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA ) \ + | P_Fld( 0 , SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2) , P_Fld( 1 , SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU ) \ + | P_Fld( 1 , SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2) , P_Fld( 1 , SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU ) \ + | P_Fld( 1 , SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld( 0 , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 ) \ + | P_Fld( 0 , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 ) \ + | P_Fld( 0 , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld( 0 , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 ) \ + | P_Fld( 0 , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 ) \ + | P_Fld( 0 , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW ) \ + | P_Fld( 0 , SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW )); +} +//========================== +//ANA_TX_CONFIG +//========================== +static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6) , P_Fld(0 , CA_CMD6_RG_TX_ARCMD_DDR3_SEL ) \ + | P_Fld(0 , CA_CMD6_RG_TX_ARCMD_DDR4_SEL ) \ + | P_Fld(1 , CA_CMD6_RG_TX_ARCMD_LP4_SEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld(0 , B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0 ) \ + | P_Fld(!(a_cfg->LP45_APHY_COMB_EN) , B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0 ) \ + | P_Fld(a_cfg->LP45_APHY_COMB_EN , B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld(0 , B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1 ) \ + | P_Fld(!(a_cfg->LP45_APHY_COMB_EN) , B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1 ) \ + | P_Fld(a_cfg->LP45_APHY_COMB_EN , B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1 )); + mcSHOW_DBG_MSG(("<<<<<< [CONFIGURE PHASE]: ANA_TX\n")); + //enable TX OE + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2) , P_Fld(1 , CA_CMD2_RG_TX_ARCMD_OE_DIS_CA ) \ + | P_Fld(0 , CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA ) \ + | P_Fld(0 , CA_CMD2_RG_TX_ARCLK_OE_DIS_CA ) \ + | P_Fld(0 , CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA ) \ + | P_Fld(1 , CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA ) \ + | P_Fld(1 , CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA ) \ + | P_Fld(0 , CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA ) \ + | P_Fld(0xff , CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2) , P_Fld(0 , B0_DQ2_RG_TX_ARDQ_OE_DIS_B0 ) \ + | P_Fld(0 , B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0 ) \ + | P_Fld(0 , B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0 ) \ + | P_Fld(0 , B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0 ) + | P_Fld(0 , B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0 ) \ + | P_Fld(0 , B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2) , P_Fld(0 , B1_DQ2_RG_TX_ARDQ_OE_DIS_B1 ) \ + | P_Fld(0 , B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1 ) \ + | P_Fld(0 , B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1 ) \ + | P_Fld(0 , B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1 ) \ + | P_Fld(0 , B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1 ) \ + | P_Fld(0 , B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1 )); + //enable TX & reset + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3) , P_Fld(1 , CA_CMD3_RG_TX_ARCMD_EN ) \ + | P_Fld(1 , CA_CMD3_RG_ARCMD_RESETB )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3) , P_Fld(1 , B0_DQ3_RG_ARDQ_RESETB_B0 ) \ + | P_Fld(1 , B0_DQ3_RG_TX_ARDQ_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3) , P_Fld(1 , B1_DQ3_RG_ARDQ_RESETB_B1 ) \ + | P_Fld(1 , B1_DQ3_RG_TX_ARDQ_EN_B1 )); +} + +static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id) +{ + //ODTEN & DQS control + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD14) , P_Fld(0 , SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13) , P_Fld(0 , SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA ) \ + | P_Fld(0 , SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld(1 , SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0 ) + | P_Fld(1 , SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0 ) + | P_Fld(0 , SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 ) + | P_Fld(0 , SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 ) + | P_Fld(0 , SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0 ) + | P_Fld(0 , SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0 ) + | P_Fld(a_cfg->TX_ODT_DIS , SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld(1 , SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1 ) + | P_Fld(1 , SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1 ) + | P_Fld(0 , SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 ) + | P_Fld(0 , SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 ) + | P_Fld(0 , SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1 ) + | P_Fld(0 , SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1 ) + | P_Fld(a_cfg->TX_ODT_DIS , SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ14) , P_Fld(1 , SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14) , P_Fld(1 , SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1 )); + + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld((LPDDR5_EN_S) ? 2 : 0 , SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld((LPDDR5_EN_S) ? 2 : 0 , SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ14) , P_Fld( 0 , SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0 ) \ + | P_Fld( 0 , SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14) , P_Fld( 0 , SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1 ) \ + | P_Fld( 0 , SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1 )); + + #if SA_CONFIG_EN + // enable after runtime configs + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( 0 , SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld( 0 , SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1 )); + #else + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( a_cfg->NEW_RANK_MODE , SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld( a_cfg->NEW_RANK_MODE , SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1 )); + #endif + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13) , P_Fld( 0 , SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2) , P_Fld( 0 , SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA ) \ + | P_Fld( 0 , SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA )); +} + +static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id) +{ + + U8 RDQS_SE_EN ; + U8 DQSIEN_MODE ; + U8 NEW_RANK_MODE ; + +#if ENABLE_LP4Y_DFS + RDQS_SE_EN = DFS(group_id)->data_rate<=1600 ? 1 : 0; +#else + RDQS_SE_EN = 0; //TODO for LPDDR5 +#endif + DQSIEN_MODE = DFS(group_id)->DQSIEN_MODE; + NEW_RANK_MODE = A_T->NEW_RANK_MODE; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10) , P_Fld( RDQS_SE_EN , SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0 ) \ + | P_Fld(DQSIEN_MODE , SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0 ) \ + | P_Fld(1 , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0 ) \ + | P_Fld(NEW_RANK_MODE , SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0 ) \ + | P_Fld(NEW_RANK_MODE , SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , P_Fld(NEW_RANK_MODE , SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0 ) \ + | P_Fld(NEW_RANK_MODE , SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 ) ); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2) , P_Fld(NEW_RANK_MODE , SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0 )\ + | P_Fld(NEW_RANK_MODE , SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10) , P_Fld( RDQS_SE_EN , SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1 ) \ + | P_Fld(DQSIEN_MODE , SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1 ) \ + | P_Fld(1 , SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1 ) \ + | P_Fld(NEW_RANK_MODE , SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1 ) \ + | P_Fld(NEW_RANK_MODE , SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , P_Fld(NEW_RANK_MODE , SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1 ) \ + | P_Fld(NEW_RANK_MODE , SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2) , P_Fld(NEW_RANK_MODE , SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1 )\ + | P_Fld(NEW_RANK_MODE , SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1 )); + + #if SA_CONFIG_EN + // enable after runtime configs + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10) , P_Fld( 0 , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2) , P_Fld( 0 , SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10) , P_Fld( 0 , SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2) , P_Fld( 0 , SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10) , P_Fld(1, SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA )\ + | P_Fld(1, SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11) , P_Fld(1, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA )); + #endif +} + + +static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6) , P_Fld( 0 , CA_CMD6_RG_RX_ARCMD_DDR3_SEL ) \ + | P_Fld( 0 , CA_CMD6_RG_RX_ARCMD_DDR4_SEL ) \ + | P_Fld( 0 , CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL ) \ + | P_Fld( 0 , CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5) , P_Fld( 1 , B0_DQ5_RG_RX_ARDQ_VREF_EN_B0 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0 ) \ + | P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0 ) \ + | P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0 ) \ + | P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3) , P_Fld( 1 , B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0 ) \ + | P_Fld( 1 , B0_DQ3_RG_RX_ARDQ_SMT_EN_B0 )); + +// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5) , P_Fld( 1 , B1_DQ5_RG_RX_ARDQ_VREF_EN_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1 ) \ + | P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1 ) \ + | P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1 ) \ + | P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3) , P_Fld( 1 , B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1 ) \ + | P_Fld( 1 , B1_DQ3_RG_RX_ARDQ_SMT_EN_B1 )); + + //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1)); + + //RX reset + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( 1 , CA_CMD9_RG_RX_ARCMD_STBEN_RESETB ) \ + | P_Fld( 1 , CA_CMD9_RG_RX_ARCLK_STBEN_RESETB )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0 ) \ + | P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1 ) \ + | P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1 )); + + //Justin confirm that: All set 1 for improving internal timing option + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8) , P_Fld( 1 , CA_CMD8_RG_RX_ARCLK_SER_RST_MODE )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8) , P_Fld( 1 , B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8) , P_Fld( 1 , B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1 )); + +} + +//============================================ +// RESET +//============================================ +void RESETB_PULL_DN(DRAMC_CTX_T *p) +{ + mcSHOW_DBG_MSG(("============ PULL DRAM RESETB DOWN ============\n")); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11) , P_Fld( 1 , CA_CMD11_RG_RRESETB_DRVP ) \ + | P_Fld( 1 , CA_CMD11_RG_RRESETB_DRVN ) \ + | P_Fld( 1 , CA_CMD11_RG_TX_RRESETB_DDR3_SEL ) \ + | P_Fld( 1 , CA_CMD11_RG_TX_RRESETB_PULL_DN )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DMRRESETB_I_OPT )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DMDA_RRESETB_E )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11) , P_Fld( 0 , CA_CMD11_RG_TX_RRESETB_PULL_DN )); + mcSHOW_DBG_MSG(("========== PULL DRAM RESETB DOWN end =========\n")); +} +//============================================ +// SUSPEND_OFF_control +//============================================ +static void SUSPEND_ON(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_LP_CTRL0) , P_Fld( 0 , B0_LP_CTRL0_RG_ARDMSUS_10_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_LP_CTRL0) , P_Fld( 0 , B1_LP_CTRL0_RG_ARDMSUS_10_B1 )); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0) , P_Fld( 0 , CA_LP_CTRL0_RG_ARDMSUS_10_CA )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); +} +//============================================ +// SPM_control +//============================================ +static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_LP_CTRL), P_Fld( 1 , MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL ) \ + | P_Fld( 1 , MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL ) \ + | P_Fld( 1 , MISC_LP_CTRL_RG_RRESETB_LP_SEL ) \ + | P_Fld( 1 , MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL ) \ + | P_Fld( 1 , MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL ) \ + | P_Fld( 1 , MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL ) \ + | P_Fld( 1 , MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL ) \ + | P_Fld( 1 , MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL ) \ + | P_Fld( 1 , MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL ) \ + | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL ) \ + | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL ) \ + | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL ) \ + | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL ) \ + | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL) \ + | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL ) \ + | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_LP_CTRL0) , P_Fld( 1 , B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL ) \ + | P_Fld( 0 , B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL ) \ + | P_Fld( 0 , B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL ) \ + | P_Fld( 1 , B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_LP_CTRL0) , P_Fld( 1 , B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL ) \ + | P_Fld( 0 , B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL ) \ + | P_Fld( 0 , B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL ) \ + | P_Fld( 1 , B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL)); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0) , P_Fld( 1 , CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL ) \ + // | P_Fld( 1 , CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL) + | P_Fld( 1 , CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL ) \ + | P_Fld( 1 , CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL) \ + | P_Fld( 0 , CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL )); //use CA as DQ set 1 + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + + if(a_cfg->DLL_ASYNC_EN == 1) + { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0), P_Fld((a_cfg->ALL_SLAVE_EN==0), CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + else + { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0), P_Fld((a_cfg->ALL_SLAVE_EN==0), CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL )); + vSetPHY2ChannelMapping(p, CHANNEL_B); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0), P_Fld(0 , CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL )); + #if (CHANNEL_NUM>2) + vSetPHY2ChannelMapping(p, CHANNEL_C); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0), P_Fld((a_cfg->ALL_SLAVE_EN==0), CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL )); + vSetPHY2ChannelMapping(p, CHANNEL_D); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0), P_Fld(0 , CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL )); + #endif + vSetPHY2ChannelMapping(p, CHANNEL_A); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + + //FOR DDR400 OPEN-LOOP MODE + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL9), P_Fld( 1 , MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN ) \ + | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN ) \ + | P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF ) \ + | P_Fld( 0 , MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON ) \ + | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF ) \ + | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN ) \ + | P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF ) \ + | P_Fld( 0 , MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON ) \ + | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF )); +#if 0 // @Darren-, new APHY remove 45/135 phases + | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN ) \ + | P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF ) \ + | P_Fld( 0 , MISC_CG_CTRL9_RG_DDR400_MCK4X_O_FORCE_ON ) \ + | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF )); +#endif +} + +static void DIG_DCM_nonshuffle_config(DRAMC_CTX_T *p) +{ + //RX DCM + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL), P_Fld(3 , MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY )); +} + +static void DIG_PHY_SHU_MISC_CG_CTRL(DRAMC_CTX_T *p) +{ + //bit 0 : DPHY_NAO_GLUE_B0.mck_dq_cg_ctrl + //bit 1 : DPHY_NAO_GLUE_B1.mck_dq_cg_ctrl + //bit 2 : DPHY_NAO_GLUE_CA.mck_ca_cg_ctrl + //bit 4 : DPHY_NAO_GLUE_B0.rx_mck_dq_cg_ctrl + //bit 5 : DPHY_NAO_GLUE_B1.rx_mck_dq_cg_ctrl + //bit 6 : DPHY_NAO_GLUE_CA.rx_mck_ca_cg_ctrl + //bit [9 : 8] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle + //bit [11:10] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_dq + //bit [13:12] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_cmd + //bit [17:16] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b0 + //bit [19:18] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b1 + //bit [22:20] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_cmd + //bit [26:24] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b0 + //bit [30:28] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b1 + +// vIO32Write4B (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x333f3f00); +// //1. ignore NAO_GLUE cg ctrl, +// 2.00:ddrphy_idle/_ca/b0/b1 01: ddrphy_idle_shuopt 10: ddrphy_idle_shuopt_pinmux + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x33400000);//rx_cmd_idle tie 1 others DCM control depend on CA B0 B1 independtly -- could save more power +} + +static void ANA_IMP_configure(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1) , P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1) , P_Fld( !(LPDDR5_EN_S), MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1) , P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_BIAS_EN ) \ + | P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_ODT_EN ) \ + | P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_PRE_EN ) \ + | P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_VREF_EN )); +} + + +static void ANA_CLOCK_SWITCH(DRAMC_CTX_T *p) +{ + //OPENLOOP MODE. w_chg_mem_mck1x + if(A_D->DQ_CA_OPEN) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1)); + mcDELAY_XNS(100); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1)); + } + //mem_sel _____|------------------------------------ + //w_chg_mem ______________|------------|______________ + //BLCK __|---|___|---|____________|-|_|-|_|-|_|- + // |<- 26M ->|<- MUTE ->|<- MCK4X ->| + //before DLL enable switch feedback clock + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL) , P_Fld( 1 , MISC_CKMUX_SEL_R_PHYCTRLDCM ) \ + | P_Fld( 1 , MISC_CKMUX_SEL_R_PHYCTRLMUX )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_CLK_MEM_SEL ) \ + | P_Fld( 1 , MISC_CG_CTRL0_W_CHG_MEM )); + + mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_W_CHG_MEM )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RG_FREERUN_MCK_CG )); + + //after clock change, if OPEN LOOP MODE should change clock to 1x. bit7 is RG_dvfs_clk_mem_mck1x_sel + if(A_D->DQ_CA_OPEN) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7)); + } +} + +static void ANA_Config_nonshuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) +{ + #if !SA_CONFIG_EN + RESETB_PULL_DN(p); + #endif + SUSPEND_ON(p); + SPM_control(p,a_cfg); + ANA_TX_nonshuffle_config(p,a_cfg); + ANA_RX_nonshuffle_config(p); + DIG_DCM_nonshuffle_config(p); + ANA_IMP_configure(p); + ANA_DLL_non_shuffle_config(p,a_cfg); +} + +void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id) +{ + ANA_PLL_shuffle_Config(p,A_D->PLL_FREQ,DFS(group_id)->data_rate); + ANA_ARPI_shuffle_config(p,a_cfg,A_D); + ANA_TX_shuffle_config(p,a_cfg,group_id); + ANA_RX_shuffle_config(p,group_id); + DIG_PHY_SHU_MISC_CG_CTRL(p); + ANA_CLK_DIV_config_setting(p,A_D,a_cfg); + ANA_DLL_shuffle_Config(p,a_cfg); +// ANA_sequence_shuffle_colletion(p,&ana_core_p); +} + +static void ANA_PHY_Config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) +{ + //RESET MD32 + //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN), 32'h1000_0001 ); + +// SC_DPY_MODE_SW(PULL_UP); + ANA_Config_nonshuffle(p,a_cfg); + ANA_Config_shuffle(p,a_cfg,0); +} + + +static void ANA_PLL_sequence(DRAMC_CTX_T *p) +{ + mcSHOW_DBG_MSG(("[ANA_INIT] PLL >>>>>>>> \n")); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2) , P_Fld(1, PHYPLL2_RG_RPHYPLL_RESETB )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0) , P_Fld(1, PHYPLL0_RG_RPHYPLL_EN )); + mcDELAY_XUS(20); + mcSHOW_DBG_MSG(("[ANA_INIT] PLL <<<<<<<< \n")); +} + +static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) +{ + mcSHOW_DBG_MSG(("[ANA_INIT] MIDPI >>>>>>>> \n")); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1) , 1, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0 ); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1) , 1, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1 ); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , 1, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA ); + + //ASVA 2-6 + //step1: CG high. --disable 8 phase clk output + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2) , P_Fld( 1 , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 ) \ + | P_Fld( 1 , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2) , P_Fld( 1 , SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 ) \ + | P_Fld( 1 , SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2) , P_Fld( 1 , SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA ) \ + | P_Fld( 1 , SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA )); + + //CG + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA)); + + //step2:PLLGP_CK_SEL -- Initial no need it + //step3: PLLCK_EN disable + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 0 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2) , P_Fld( 0 , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN ) \ + | P_Fld( 0 , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN )); + //step4:MIDPI_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , P_Fld( !(tr->CA_CKDIV4_EN), SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA ) \ + | P_Fld( tr->CA_CKDIV4_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , P_Fld( tr->CA_PREDIV_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_SHU_MIDPI_CTRL) , P_Fld( (!(tr->DQ_SEMI_OPEN))&&(!(tr->DQ_CKDIV4_EN)), B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0 ) \ + | P_Fld( (!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_SHU_MIDPI_CTRL) , P_Fld( (!(tr->DQ_SEMI_OPEN))&&(!(tr->DQ_CKDIV4_EN)), B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1 ) \ + | P_Fld( (!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_SHU_MIDPI_CTRL) , P_Fld( !(tr->CA_CKDIV4_EN), CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA ) \ + | P_Fld( tr->CA_CKDIV4_EN , CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA )); + //step5:PI_RESETB + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0) , P_Fld( 0 , CA_DLL_ARPI0_RG_ARPI_RESETB_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0) , P_Fld( 0 , B0_DLL_ARPI0_RG_ARPI_RESETB_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0) , P_Fld( 0 , B1_DLL_ARPI0_RG_ARPI_RESETB_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0) , P_Fld( 1 , CA_DLL_ARPI0_RG_ARPI_RESETB_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0) , P_Fld( 1 , B0_DLL_ARPI0_RG_ARPI_RESETB_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0) , P_Fld( 1 , B1_DLL_ARPI0_RG_ARPI_RESETB_B1 )); + //step6: PLLCK_EN enable + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2) , P_Fld( 1 , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN ) \ + | P_Fld( 1 , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN )); + //step7: release CG 8 Phase clk enable + //CG + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0) + | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0) + | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0) + | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0) + | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0) + | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0) + | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0) + | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0) + | P_Fld(tr->DQ_SEMI_OPEN, SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1) + | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1) + | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1) + | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1) + | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1) + | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1) + | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1) + | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1) + | P_Fld(tr->DQ_SEMI_OPEN, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA) + | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA) + | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA) + | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA) + | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS) + | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK) + | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD) + | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN) + | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA)); + + mcSHOW_DBG_MSG(("[ANA_INIT] MIDPI <<<<<<<< \n")); +} + +static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg) +{ + U8 DLL_ASYNC_EN; + U8 ALL_SLAVE_EN; + + DLL_ASYNC_EN = a_cfg->DLL_ASYNC_EN; + ALL_SLAVE_EN = a_cfg->ALL_SLAVE_EN; + + mcSHOW_DBG_MSG(("[ANA_INIT] DLL >>>>>>>> \n")); + //step1: DLL_RESETB + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8) , P_Fld( 1 , CA_CMD8_RG_ARDLL_RESETB_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8) , P_Fld( 1 , B0_DQ8_RG_ARDLL_RESETB_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8) , P_Fld( 1 , B1_DQ8_RG_ARDLL_RESETB_B1 )); + //step2: master DLL_EN + if(ALL_SLAVE_EN == 1) + { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA)); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + mcDELAY_XNS(300); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1)); + mcDELAY_XNS(400); //2nd DLL > 77TMCK + } + else + { + if(DLL_ASYNC_EN == 1) + { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA)); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + mcDELAY_XNS(300); //1st DLL > 55 TMCK + } + else + { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA)); + mcDELAY_XNS(300); //1st DLL >55T MCK + vSetPHY2ChannelMapping(p, CHANNEL_B); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA)); + #if (CHANNEL_NUM>2) + vSetPHY2ChannelMapping(p, CHANNEL_C); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA)); + mcDELAY_XNS(300); //1st DLL >55T MCK + vSetPHY2ChannelMapping(p, CHANNEL_D); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA)); + #endif + mcDELAY_XNS(300); //1st DLL >55T MCK + vSetPHY2ChannelMapping(p, CHANNEL_A); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1 )); + mcDELAY_XNS(400); //2nd DLL > 77TMCK + mcSHOW_DBG_MSG(("[ANA_INIT] DLL <<<<<<<< \n")); + } +} + + +//shuffle register for ANA initial flow control +//It is not easy for initial sequence SA/DV coding --- same register for different group. need two different method to manage it +//1. for seqeunce +//2. for another shuffle group need to DMA to SRAM +void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) +{ + //PLL + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2 + + //MIDPI + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 ) \ + | P_Fld( 0 , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 ) \ + | P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 ) \ + | P_Fld( 0 , SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1 ) \ + | P_Fld( tr->DQ_SEMI_OPEN , SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2) , P_Fld( 0 , SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA ) \ + | P_Fld( 0 , SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA ) \ + | P_Fld( tr->DQ_CA_OPEN , SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , P_Fld( !(tr->CA_CKDIV4_EN), SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA ) \ + | P_Fld( tr->CA_CKDIV4_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , P_Fld( tr->CA_PREDIV_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_SHU_MIDPI_CTRL) , P_Fld( !(tr->DQ_CKDIV4_EN), B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0 ) \ + | P_Fld( (!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_SHU_MIDPI_CTRL) , P_Fld( !(tr->DQ_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1 ) \ + | P_Fld( (!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_SHU_MIDPI_CTRL) , P_Fld( !(tr->CA_CKDIV4_EN), CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA ) \ + | P_Fld( tr->CA_CKDIV4_EN , CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA )); + //DLL + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1) , P_Fld( 1 , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1 )); +} + +static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL) + | P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM)); + mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM); + + //DLL Off + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), 0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), 0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), 0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + + //CG + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0) + | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1) + | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN) + | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA)); + + //PLLCK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2), 0, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU); //refer to MISC_DVFSCTRL2 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), P_Fld(0, PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN) + | P_Fld(0, PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN)); + + //PLL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0), 0, PHYPLL0_RG_RPHYPLL_EN); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), 0, PHYPLL2_RG_RPHYPLL_RESETB); +} + + +static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg) +{ + mcSHOW_DBG_MSG(("[ANA_INIT] flow start \n")); + ANA_PLL_sequence(p); + ANA_MIDPI_sequence(p,tr); + ANA_CLOCK_SWITCH(p); //clock switch supply correct FB clk. have to do this before DLL + ANA_DLL_sequence(p,tr,a_cfg); + mcSHOW_DBG_MSG(("[ANA_INIT] flow end \n")); +} + +void ANA_init(DRAMC_CTX_T *p) +{ + DRAMC_SUBSYS_PRE_CONFIG(p, &DV_p); + mcSHOW_DBG_MSG(("[ANA_INIT] >>>>>>>>>>>>>> \n")); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(1, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + ANA_ClockOff_Sequence(p); + ANA_PHY_Config(p,A_T); + ANA_init_sequence(p,A_D,A_T); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(0, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(1, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + LP4_single_end_DRAMC_post_config(p, M_LP4->LP4Y_EN); + mcSHOW_DBG_MSG(("[ANA_INIT] <<<<<<<<<<<<< \n")); +} + +#if 0 +void DPI_ANA_init(void) +{ + mysetscope(); + ANA_init(DramcConfig); +} +#endif diff --git a/src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c b/src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c new file mode 100644 index 0000000000..05a0f05570 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c @@ -0,0 +1,983 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include "dramc_dv_init.h" + +Gating_confg_T Gat_p; + +//============================================ +// digital PHY config +//============================================ +static void DIG_PHY_config(DRAMC_CTX_T *p) +{ +#if ENABLE_PINMUX_FOR_RANK_SWAP + U8 RK_SWAP_EN = 1; +#else + U8 RK_SWAP_EN = 0; +#endif + + mcSHOW_DBG_MSG(("[Flow] Enable top DCM control >>>>> \n")); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 3 , MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 0 , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG ) \ + | P_Fld( 0x1f , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 1 , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG ) \ + | P_Fld( 0x1f , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 0 , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG ) \ + | P_Fld( 0x1f , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 0x17 , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL ) \ + | P_Fld( 1 , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0) , P_Fld( 0 , MISC_CTRL0_R_STBENCMP_DIV4CK_EN ) \ + | P_Fld( 1 , MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL ) \ + | P_Fld( 1 , MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL ) \ + | P_Fld( 0 , MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL ) \ + | P_Fld( 1 , MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RXDVS2) , P_Fld( 1 , MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG)); + mcSHOW_DBG_MSG(("[Flow] Enable top DCM control <<<<< \n")); + + mcSHOW_DBG_MSG(("Enable DLL master slave shuffle \n")); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFS_EMI_CLK) , P_Fld( 1 , MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld(RK_SWAP_EN, MISC_CTRL1_R_RK_PINMUXSWAP_EN )); + + mcDELAY_US(1); + + if(A_T->NEW_RANK_MODE==0) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 4 , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 ) \ + | P_Fld( 0 , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 4 , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 ) \ + | P_Fld( 0 , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 0 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 0 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 )); + } + else + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 ) \ + | P_Fld( 1 , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 ) \ + | P_Fld( 1 , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 1 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 1 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 )); + } + + if(A_T->NEW_8X_MODE==1) + { + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL) , P_Fld( 1 , MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE ) \ + | P_Fld( 3 , MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } +} + + + +static void GATING_MODE_CFG(Gating_confg_T *tr) +{ + tr->GAT_TRACK_EN = ((A_D->DQ_SEMI_OPEN == 1)||(A_D->DQ_CA_OPEN==1))?0:1; + tr->RX_GATING_MODE = 2; //fix 7UI mode under LPDDR4 + tr->RX_GATING_TRACK_MODE = 2; //fix FIFO mode under LPDDR4 + tr->PICG_EARLY_EN = 1; //fix under LPDDR4, if LPDDR5 have to set 1 + tr->SELPH_MODE = 1; //random inside {0,1} //for improve APHY XRTR2R. NEW_APHY MODE with 1. + tr->VALID_LAT_VALUE = 1; //random inside {0,1} + + mcSHOW_DBG_MSG(("============================================================== \n")); + mcSHOW_DBG_MSG(("Gating Mode config\n" )); + mcSHOW_DBG_MSG(("============================================================== \n")); + mcSHOW_DBG_MSG(("Config description: \n")); + mcSHOW_DBG_MSG(("RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode\n")); + mcSHOW_DBG_MSG(("RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode\n")); + mcSHOW_DBG_MSG(("SELPH_MODE 0: By rank 1: By Phase \n")); + mcSHOW_DBG_MSG(("============================================================== \n")); + mcSHOW_DBG_MSG(("GAT_TRACK_EN = %2d\n",tr->GAT_TRACK_EN )); + mcSHOW_DBG_MSG(("RX_GATING_MODE = %2d\n",tr->RX_GATING_MODE )); + mcSHOW_DBG_MSG(("RX_GATING_TRACK_MODE = %2d\n",tr->RX_GATING_TRACK_MODE)); + mcSHOW_DBG_MSG(("SELPH_MODE = %2d\n",tr->SELPH_MODE )); + mcSHOW_DBG_MSG(("PICG_EARLY_EN = %2d\n",tr->PICG_EARLY_EN )); + mcSHOW_DBG_MSG(("VALID_LAT_VALUE = %2d\n",tr->VALID_LAT_VALUE )); + mcSHOW_DBG_MSG(("============================================================== \n")); +} + +//====================================== +//gating widnow mode +//====================================== +static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) +{ + mcSHOW_DBG_MSG(("Enter into Gating configuration >>>> \n")); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld(!gat_c->GAT_TRACK_EN, MISC_STBCAL1_STBCNT_SW_RST )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld(gat_c->SELPH_MODE, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_STBCNT_SHU_RST_EN )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD )); + + if(gat_c->PICG_EARLY_EN == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld( 1 , MISC_STBCAL2_STB_PICG_EARLY_1T_EN )); + } + + //================================ + //gating Mode config + //================================ + switch (gat_c->RX_GATING_MODE) + { + //Pulse Mode + case 0: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( 0 , MISC_SHU_STBCAL_DQSIEN_BURST_MODE )); + break; + } + // Burst Mode (8UI) + case 1: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1)); + break; + } + // Burst Mode (7UI) + case 2: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 2 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 2 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_DQSIEN_7UI_EN )); + break; + } + // Oringinal Burst + case 3: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1)); + break; + } + default: + { + mcSHOW_DBG_MSG(("ERROR: Gating Mode choose unexpected Mode!!!!\n")); + break; + } + } + + //================================ + //Gating tracking Mode config + //================================ + switch (gat_c->RX_GATING_TRACK_MODE) + { + //Valid DLY Mode + case 0: + { + //TODO SHU1_DQSG if -like mode should set STB_UPDMASKCYC = 0 STB_UPDMASK_EN=0 others STB_UPDMASKCYC=9 STB_UPDMASK_EN=1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_STB_DQIEN_IG ) \ + | P_Fld( 1 , MISC_STBCAL_PICHGBLOCK_NORD ) \ + | P_Fld( 0 , MISC_STBCAL_REFUICHG ) \ + | P_Fld( 0 , MISC_STBCAL_PHYVALID_IG ) \ + | P_Fld( 0 , MISC_STBCAL_STBSTATE_OPT ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_FILTER ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_PULSE ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_OPT ) \ + | P_Fld( 1 , MISC_STBCAL_PIMASK_RKCHG_OPT )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_STBCAL_FILTER ) \ + | P_Fld( 1 , MISC_STBCAL1_STB_FLAGCLR_OPT ) \ + | P_Fld( 1 , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG ) \ + | P_Fld( 1 , MISC_STBCAL1_STBCNT_MODESEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0) , P_Fld( 0 , MISC_CTRL0_R_DMDQSIEN_FIFO_EN ) \ + | P_Fld( 2 , MISC_CTRL0_R_DMVALID_DLY ) \ + | P_Fld( 1 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); //TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \ + | P_Fld( 0 , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 ) \ + | P_Fld( 0 , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 )); + break; + } + //-like Mode + case 1: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 0 , MISC_STBCAL_STB_DQIEN_IG ) \ + | P_Fld( 0 , MISC_STBCAL_PICHGBLOCK_NORD ) \ + | P_Fld( 1 , MISC_STBCAL_REFUICHG ) \ + | P_Fld( 0 , MISC_STBCAL_PHYVALID_IG ) \ + | P_Fld( 1 , MISC_STBCAL_STBSTATE_OPT ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_FILTER ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_PULSE ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_OPT ) \ + | P_Fld( 0 , MISC_STBCAL_PIMASK_RKCHG_OPT )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 0 , MISC_STBCAL1_STBCAL_FILTER ) \ + | P_Fld( 1 , MISC_STBCAL1_STB_FLAGCLR_OPT ) \ + | P_Fld( 0 , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG ) \ + | P_Fld( 1 , MISC_STBCAL1_STBCNT_MODESEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0) , P_Fld( 0 , MISC_CTRL0_R_DMDQSIEN_FIFO_EN ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \ + | P_Fld( 1 , MISC_CTRL0_R_DMVALID_NARROW_IG )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \ + | P_Fld( 0 , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 ) \ + | P_Fld( 0 , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 )); + break; + } + //FIFO Mode + case 2: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_STB_DQIEN_IG ) \ + | P_Fld( 1 , MISC_STBCAL_PICHGBLOCK_NORD ) \ + | P_Fld( 0 , MISC_STBCAL_REFUICHG ) \ + | P_Fld( 0 , MISC_STBCAL_PHYVALID_IG ) \ + | P_Fld( 0 , MISC_STBCAL_STBSTATE_OPT ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_FILTER ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_PULSE ) \ + | P_Fld( 0 , MISC_STBCAL_STBDLELAST_OPT ) \ + | P_Fld( 1 , MISC_STBCAL_PIMASK_RKCHG_OPT )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_STBCAL_FILTER ) \ + | P_Fld( 1 , MISC_STBCAL1_STB_FLAGCLR_OPT ) \ + | P_Fld( 1 , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG ) \ + | P_Fld( 1 , MISC_STBCAL1_STBCNT_MODESEL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0) , P_Fld( 1 , MISC_CTRL0_R_DMDQSIEN_FIFO_EN ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \ + | P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); // @Darren, func no use sync MP settings from HJ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1+gat_c->VALID_LAT_VALUE , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \ + | P_Fld( 0+gat_c->VALID_LAT_VALUE , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1+gat_c->VALID_LAT_VALUE , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 ) \ + | P_Fld( 0+gat_c->VALID_LAT_VALUE , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 )); + break; + } + default: + { + mcSHOW_DBG_MSG(("ERROR: Gating tracking Mode choose unexpected Mode!!!!")); + break; + } + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2) , P_Fld( 1 , B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2) , P_Fld( 1 , B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_DQSIENMODE ) \ + | P_Fld( 1 , MISC_STBCAL_SREF_DQSGUPD ) \ + | P_Fld( 1 , MISC_STBCAL_DQSIENCG_CHG_EN ) \ + | P_Fld( 1 , MISC_STBCAL_PICGEN ) \ + | P_Fld( 0 , MISC_STBCAL_RKCHGMASKDIS ) \ + | P_Fld( 0 , MISC_STBCAL_STBCAL2R )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DMDQSIENCG_EN )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld( 0 , MISC_STBCAL2_STB_GERRSTOP ) \ + | P_Fld( 0 , MISC_STBCAL2_STB_GERR_RST ) \ + | P_Fld( 1 , MISC_STBCAL2_STB_GERR_B01 ) \ + | P_Fld( 0 , MISC_STBCAL2_STB_GERR_B23 )); + //PICG_MODE only support new mode so here fix 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), P_Fld(1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), P_Fld(1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT )); + + if(A_T->NEW_RANK_MODE == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld( 1 , MISC_STBCAL2_STB_IG_XRANK_CG_RST ) \ + | P_Fld( 1 , MISC_STBCAL2_STB_RST_BY_RANK ) \ + | P_Fld( 1 , MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN )); + } + mcSHOW_DBG_MSG(("Exit from Gating configuration <<<< \n")); +} + +static void RX_INTPUT_Config(DRAMC_CTX_T *p) +{ + U8 VALID_LAT = 1;// TODO inside {0,1} + U8 RDSEL_LAT = 2;// TODO alywas VALID_LAT+1; + U8 dq_min = 0; + U8 dq_max = 0xff; + U8 scale = 3; + U8 threadhold = 0; + U32 dqs_min = 0; + U32 dqs_max = 0x1ff; + U8 RX_force_upd = 0; //TODO + U8 F_LEADLAG = 0; //TODO + U8 RG_MODE_EN = 0; //TODO + U8 irank = 0; + U8 backup_rank = 0; + + backup_rank = p->rank; + + mcSHOW_DBG_MSG(("[RX_INPUT] configuration >>>>> \n")); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0) , P_Fld( 1 , B0_RXDVS0_R_HWSAVE_MODE_ENA_B0 ) \ + | P_Fld( 0 , B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0 ) \ + | P_Fld( 1 , B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0 ) \ + | P_Fld( 1 , B0_RXDVS0_R_HWRESTORE_ENA_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0) , P_Fld( 1 , B1_RXDVS0_R_HWSAVE_MODE_ENA_B1 ) \ + | P_Fld( 0 , B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1 ) \ + | P_Fld( 1 , B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1 ) \ + | P_Fld( 1 , B1_RXDVS0_R_HWRESTORE_ENA_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9 ) , P_Fld( VALID_LAT , B0_DQ9_R_DMRXDVS_VALID_LAT_B0 ) \ + | P_Fld( RDSEL_LAT , B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9 ) , P_Fld( VALID_LAT , B1_DQ9_R_DMRXDVS_VALID_LAT_B1 ) \ + | P_Fld( RDSEL_LAT , B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RXDVS2 ) , P_Fld( 1 , MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN ) \ + | P_Fld( 0 , MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR ) \ + | P_Fld( 0 , MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN ) \ + | P_Fld( 1 , MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF )); + + for(irank = RANK_0; irank < p->support_rank_num; irank++) + { + vSetRank(p, irank); + //RK0--B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS3 ) , P_Fld( dq_min , RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0 ) \ + | P_Fld( dq_max , RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS4 ) , P_Fld( dqs_min , RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0 ) \ + | P_Fld( dqs_max , RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2 ) , P_Fld( scale , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0 ) \ + | P_Fld( scale , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0 ) \ + | P_Fld( 0 , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0 ) \ + | P_Fld( scale , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0 ) \ + | P_Fld( scale , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0 ) \ + | P_Fld( 0 , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0 ) \ + | P_Fld( 1 , RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0 ) \ + | P_Fld( 0 , RK_B0_RXDVS2_R_RK0_DVS_MODE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS1 ) , P_Fld( threadhold , RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG ) \ + | P_Fld( threadhold , RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD )); + + + //RK0--B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS3 ) , P_Fld( dq_min , RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1 ) \ + | P_Fld( dq_max , RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS4 ) , P_Fld( dqs_min , RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1 ) \ + | P_Fld( dqs_max , RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2 ) , P_Fld( scale , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1 ) \ + | P_Fld( scale , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1 ) \ + | P_Fld( 0 , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1 ) \ + | P_Fld( scale , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1 ) \ + | P_Fld( scale , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1 ) \ + | P_Fld( 0 , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1 ) \ + | P_Fld( 1 , RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1 ) \ + | P_Fld( 0 , RK_B1_RXDVS2_R_RK0_DVS_MODE_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS1 ) , P_Fld( threadhold , RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG ) \ + | P_Fld( threadhold , RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD )); + } + vSetRank(p, backup_rank); + + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL1 ) , 0xffffffff , MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL ); //TODO + + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS1 ) , P_Fld( F_LEADLAG , B0_RXDVS1_F_LEADLAG_TRACK_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS1 ) , P_Fld( F_LEADLAG , B1_RXDVS1_F_LEADLAG_TRACK_B1 )); + + if(RX_force_upd == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL ) , P_Fld( 1 , DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT ) \ + | P_Fld( 1 , DLLFRZ_CTRL_DLLFRZ_BLOCKLONG ) \ + | P_Fld( 1 , DLLFRZ_CTRL_INPUTRXTRACK_BLOCK )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS1 ) , P_Fld( 1 , B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS1 ) , P_Fld( 1 , B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1 )); + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5 ) , P_Fld( 1 , B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5 ) , P_Fld( 1 , B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0 ) , P_Fld( 1 , B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0 )\ + | P_Fld( 1 , B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 )\ + | P_Fld( 1 , B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0 )\ + | P_Fld( 0 , B0_RXDVS0_R_RX_RANKINCTL_B0 )\ + | P_Fld( 1 , B0_RXDVS0_R_RX_RANKINSEL_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0 ) , P_Fld( 1 , B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1 )\ + | P_Fld( 1 , B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 )\ + | P_Fld( 1 , B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1 )\ + | P_Fld( 0 , B1_RXDVS0_R_RX_RANKINCTL_B1 )\ + | P_Fld( 1 , B1_RXDVS0_R_RX_RANKINSEL_B1 )); + + for(irank = RANK_0; irank < RANK_MAX; irank++) + { + vSetRank(p, irank); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2 ) , P_Fld( 1 , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0 ) \ + | P_Fld( 1 , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0 ) \ + | P_Fld( 2 , RK_B0_RXDVS2_R_RK0_DVS_MODE_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2 ) , P_Fld( 1 , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1 ) \ + | P_Fld( 1 , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1 ) \ + | P_Fld( 2 , RK_B1_RXDVS2_R_RK0_DVS_MODE_B1 )); + } + vSetRank(p, backup_rank); + + //Enable RX input delay tracking.. + //TODO notice here if SA should not enbale it before RX perbit calibration + if (RG_MODE_EN == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 1 , MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN )); + } else { +// `TBA_TOP.dvfs_spm_vif.sc_dphy_reserved[1:0] = 2'b11; //TODO + } + + mcSHOW_DBG_MSG(("[RX_INPUT] configuration <<<<< \n")); +} + +static void DDRPHY_PICG_Config(DRAMC_CTX_T *p) +{ + U8 PICG_MODE = 1; // only support new Mode under + U8 MISC_CG_EN = 1; + U8 MISC_CG_REVERSE_DEFAULT_ON = 0; //for default CG enable. + + mcSHOW_DBG_MSG(("Enter into PICG configuration >>>> \n")); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4) , P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_MPDIV_CG ) \ + | P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_MCK ) \ + | P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_DQM ) \ + | P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_DQS ) \ + | P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_DQ ) \ + | P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_DQSIEN )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3) , P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT ) \ + | P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_MCK_DQ_OPT ) \ + | P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_DQS_OPT ) \ + | P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_DQ_OPT )); + + //Notice here: MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE = 1 will leading other_shuffle_group before register settle down latch ->error. can not set to 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE )); + + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( !MISC_CG_EN , MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE ) \ + | P_Fld( !MISC_CG_EN , MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL5) , P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN ) \ + | P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN ) \ + | P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_CA_DLY_DCM_EN ) \ + | P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ1_PI_DCM_EN ) \ + | P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ0_PI_DCM_EN ) \ + | P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_CA_PI_DCM_EN )); + + //defualt DCM enable, if we wanner to test CG enable, modified default CG condition. + //disable DCM.--- I think just for debug + if(MISC_CG_REVERSE_DEFAULT_ON == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_CG_SET0) , P_Fld( 1 , RX_CG_SET0_RDATCKAR ) \ + | P_Fld( 1 , RX_CG_SET0_RDYCKAR )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SREF_DPD_CTRL) , P_Fld( 1 , SREF_DPD_CTRL_CMDCKAR )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DCM_CTRL0) , P_Fld( 1 , DCM_CTRL0_BCLKAR )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0) , P_Fld( 1 , TX_CG_SET0_PSELAR ) \ + | P_Fld( 1 , TX_CG_SET0_DWCLKRUN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCSMCTRL_CG) , P_Fld( 1 , SCSMCTRL_CG_SCSM_CGAR ) \ + | P_Fld( 1 , SCSMCTRL_CG_SCARB_SM_CGAR )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0) , P_Fld( 1 , TX_TRACKING_SET0_RDDQSOSC_CGAR ) \ + | P_Fld( 1 , TX_TRACKING_SET0_HMRRSEL_CGAR ) \ + | P_Fld( 1 , TX_TRACKING_SET0_TXUIPI_CAL_CGAR )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0) , P_Fld( 1 , ZQ_SET0_ZQCS_MASK_SEL_CGAR )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ACTIMING_CTRL) , P_Fld( 1 , ACTIMING_CTRL_CLKWITRFC ) \ + | P_Fld( 1 , ACTIMING_CTRL_SEQCLKRUN3 ) \ + | P_Fld( 1 , ACTIMING_CTRL_SEQCLKRUN2 ) \ + | P_Fld( 1 , ACTIMING_CTRL_SEQCLKRUN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CLKAR) , P_Fld( 1 , CLKAR_REQQUECLKRUN ) \ + | P_Fld( 1 , CLKAR_REQQUE_PACG_DIS )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL) , P_Fld( 1 , DRAMC_PD_CTRL_PHYGLUECLKRUN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3) , P_Fld( 1 , TEST2_A3_TESTCLKRUN )); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 1 , DVFS_CTRL0_DVFS_CG_OPT )); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1) , P_Fld( 1 , MISC_DUTYSCAN1_EYESCAN_DQS_OPT )); + + //TODO -- for DPHY shuffle RG have to set to different Group into SRAM or not.--here just conf0 but not all frequency group + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8) , P_Fld( 1 , SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8) , P_Fld( 1 , SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 )); + } + + mcSHOW_DBG_MSG(("Exit from PICG configuration <<<< \n")); +} + +static void DRAMC_COMMON_Config(DRAMC_CTX_T *p) +{ + U8 RD2MRR_EXTEND_EN = 1; // for fix Samsung RD2MRR seamless error, If the samsung fix that bug, this could set 0 + U8 EBG_EN ; + U8 TMRRI_MODE = 1; // !!!Notice here: 0: Old Mode, 1: New Mode --- FIX NEW MODE. Pertrus not support old mode anymore + U8 NOBLOCKALE_EN = 1; + U8 RUNTIME_MRR = 1; +#if (fcFOR_CHIP_ID == fcMargaux) + U8 dram_mux = p->DRAMPinmux; // 0: DSC, 1: LPBK, 2: MCP +#endif + + //pre configuration calculate + if(TMRRI_MODE == 1) + { + NOBLOCKALE_EN = 1; + RUNTIME_MRR = 1; + } else { + //TODO + mcSHOW_DBG_MSG(("NONBLOCKALE RUNTIMEMRR could be random.--for MP should setting 1. just record it.")); + } + + +#if ENABLE_EARLY_BG_CMD==1 + if((LPDDR5_EN_S == 1) && (DFS(0)->data_rate < 3200)) EBG_EN = 0; else EBG_EN = 1; +#else + EBG_EN = 0; +#endif + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0) , P_Fld( 1 , DDRCOMMON0_BK8EN ) \ + | P_Fld( LPDDR5_EN_S , DDRCOMMON0_LPDDR5EN ) \ + | P_Fld( LPDDR4_EN_S , DDRCOMMON0_LPDDR4EN ) \ + | P_Fld( 0 , DDRCOMMON0_TRCDEARLY )); //if LPDDR5 set1 HEFF mode ACT -> R/W delay-1 + +#if (fcFOR_CHIP_ID == fcMargaux) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( dram_mux , MISC_CTRL1_R_DMPINMUX )); +#else + if(LPDDR5_EN_S == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 2 , MISC_CTRL1_R_DMPINMUX )); + } +#endif + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0) , P_Fld( 0 , RX_SET0_DM4TO1MODE )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0) , P_Fld( 5 , REFCTRL0_REF_PREGATE_CNT ) \ + | P_Fld( 0 , REFCTRL0_DMPGVLD_IG ) \ + | P_Fld( 4 , REFCTRL0_DISBYREFNUM ) \ + | P_Fld( 0 , REFCTRL0_PBREF_DISBYRATE ) \ + | P_Fld( 1 , REFCTRL0_PBREF_DISBYREFNUM ) \ + | P_Fld( 1 , REFCTRL0_PBREF_BK_REFA_ENA ) \ + | P_Fld( 1 , REFCTRL0_PBREF_BK_REFA_NUM )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1) , P_Fld( 1 , REFCTRL1_PB2AB_OPT ) \ + | P_Fld( 1 , REFCTRL1_REF_QUE_AUTOSAVE_EN ) \ + | P_Fld( 0 , REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA ) \ + | P_Fld( 1 , REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA ) \ + | P_Fld( 0 , REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA ) \ + | P_Fld( 0 , REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA ) \ + | P_Fld( 0 , REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA ) \ + | P_Fld( 0 , REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL2) , P_Fld( 0 , REFCTRL2_REF_OVERHEAD_RATE )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL) , P_Fld( 0 , DLLFRZ_CTRL_UPDBYWR ) \ + | P_Fld( 1 , DLLFRZ_CTRL_DLLFRZ )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMCTRL) , P_Fld( 0 , DRAMCTRL_ADRDECEN ) \ + | P_Fld( 1 , DRAMCTRL_PREALL_OPTION ) \ + | P_Fld( 1 , DRAMCTRL_REQQUE_THD_EN ) \ + | P_Fld( 1 , DRAMCTRL_DYNMWREN ) \ + | P_Fld( 0 , DRAMCTRL_AG0MWR ) \ + | P_Fld( 0 , DRAMCTRL_ADRBIT3DEC ) \ + | P_Fld( 0 , DRAMCTRL_CTOREQ_HPRI_OPT )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ACTIMING_CTRL) , P_Fld( 0 , ACTIMING_CTRL_CLKWITRFC ) \ + | P_Fld( 1 , ACTIMING_CTRL_SEQCLKRUN3 ) \ + | P_Fld( 0 , ACTIMING_CTRL_FASTW2R ) \ + | P_Fld( 0 , ACTIMING_CTRL_REFBW_FREN ) \ + | P_Fld( 1 , ACTIMING_CTRL_TMRRICHKDIS ) \ + | P_Fld( 0 , ACTIMING_CTRL_REFNA_OPT ) \ + | P_Fld(!TMRRI_MODE , ACTIMING_CTRL_MRRIOPT ) \ + | P_Fld(!TMRRI_MODE , ACTIMING_CTRL_TMRRIBYRK_DIS ) \ + | P_Fld( TMRRI_MODE , ACTIMING_CTRL_TMRRICHKDIS )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL) , P_Fld( 0x80 , ARBCTL_MAXPENDCNT ) \ + | P_Fld( 0 , ARBCTL_WDATACNTDIS ) ); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAM_CLK_CTRL) , P_Fld( 1 , DRAM_CLK_CTRL_CLK_EN ) ); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CLKAR) , P_Fld( 1 , CLKAR_DCMREF_OPT ) ); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL) , P_Fld( 1 , DRAMC_PD_CTRL_COMBCLKCTRL ) \ + | P_Fld( 0 , DRAMC_PD_CTRL_MIOCKCTRLOFF ) \ + | P_Fld( 1 , DRAMC_PD_CTRL_PHYCLKDYNGEN ) \ + | P_Fld( 1 , DRAMC_PD_CTRL_DCMEN ) \ + | P_Fld( 1 , DRAMC_PD_CTRL_DCMEN2 ) \ +// | P_Fld( 0x3 , DRAMC_PD_CTRL_APHYPI_CKCGH_CNT ) + | P_Fld( 0 , DRAMC_PD_CTRL_PG_DCM_OPT )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RKCFG) , P_Fld( 0 , RKCFG_CKE2RANK ) \ + | P_Fld( 0 , RKCFG_MRS2RK )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL) , P_Fld( 1 , CKECTRL_CKE2RANK_OPT2 ) \ + | P_Fld( 1 , CKECTRL_CKEON ) \ + | P_Fld( 0 , CKECTRL_CKETIMER_SEL ) \ + | P_Fld( 1 , CKECTRL_CKE2RANK_OPT8 ) \ + | P_Fld(!RUNTIME_MRR , CKECTRL_RUNTIMEMRRMIODIS ) \ + | P_Fld( 1 , CKECTRL_FASTWAKE_SEL ) \ + | P_Fld( 1 , CKECTRL_CKEPBDIS ) \ + | P_Fld( !TMRRI_MODE , CKECTRL_RUNTIMEMRRCKEFIX ) \ + | P_Fld( 0 , CKECTRL_CKELCKFIX )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SREF_DPD_CTRL) , P_Fld( 1 , SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN) \ + | P_Fld( 0 , SREF_DPD_CTRL_GT_SYNC_MASK ) \ + | P_Fld( 0 , SREF_DPD_CTRL_DAT_SYNC_MASK ) \ + | P_Fld( 0 , SREF_DPD_CTRL_PHY_SYNC_MASK ) \ + | P_Fld( 1 , SREF_DPD_CTRL_LPSM_BYPASS_B ) \ + | P_Fld( 0 , SREF_DPD_CTRL_SREF_PRD_OPT ) \ + | P_Fld( 1 , SREF_DPD_CTRL_CLR_EN ) \ + | P_Fld( 0 , SREF_DPD_CTRL_SRFPD_DIS ) \ + | P_Fld( 8 , SREF_DPD_CTRL_SREFDLY ) \ + | P_Fld( 1 , SREF_DPD_CTRL_SREF_HW_EN )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCHEDULER_COM) , P_Fld( 1 , SCHEDULER_COM_DISRDPHASE1 ) \ + | P_Fld( 1 , SCHEDULER_COM_MWHPRIEN ) \ + | P_Fld( 0 , SCHEDULER_COM_RWHPRICTL ) \ + | P_Fld( 1 , SCHEDULER_COM_RWOFOEN ) \ + | P_Fld( 1 , SCHEDULER_COM_RWSPLIT )); +// | P_Fld( 1 , SCHEDULER_COM_BGPIPEEN )); //diff with IPMV2 compile error + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_PERFCTL0) , P_Fld( 1 , PERFCTL0_EMILLATEN ) \ + | P_Fld( 1 , PERFCTL0_RWHPRIEN ) \ + | P_Fld( EBG_EN , PERFCTL0_EBG_EN ) \ + | P_Fld( 1 , PERFCTL0_RWLLATEN ) \ + | P_Fld( 1 , PERFCTL0_RWAGEEN ) \ + | P_Fld( 1 , PERFCTL0_WFLUSHEN ) \ + | P_Fld( 0 , PERFCTL0_REORDEREN ) \ + | P_Fld( 0 , PERFCTL0_REORDER_MODE )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_HW_MRR_FUN) , P_Fld(RUNTIME_MRR , HW_MRR_FUN_TMRR_ENA ) \ + | P_Fld( 0 , HW_MRR_FUN_TRPMRR_EN ) \ + | P_Fld( 0 , HW_MRR_FUN_TRCDMRR_EN ) \ + | P_Fld( 1 , HW_MRR_FUN_MRR_HW_HIPRI ) \ + | P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_TR2MRR_ENA ) \ + | P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_R2MRRHPRICTL ) \ + | P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_MANTMRR_EN )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0) , P_Fld( 0x0A , ZQ_SET0_ZQCSAD ) \ + | P_Fld( 0x56 , ZQ_SET0_ZQCSOP )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION) , P_Fld( 1 , MPC_OPTION_MPCRKEN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL) , P_Fld(!RUNTIME_MRR , MPC_CTRL_REFR_BLOCKEN ) \ + | P_Fld( NOBLOCKALE_EN , MPC_CTRL_ZQ_BLOCKALE_OPT ) \ + | P_Fld( NOBLOCKALE_EN , MPC_CTRL_MPC_BLOCKALE_OPT ) \ + | P_Fld( NOBLOCKALE_EN , MPC_CTRL_MPC_BLOCKALE_OPT1 ) \ + | P_Fld( NOBLOCKALE_EN , MPC_CTRL_MPC_BLOCKALE_OPT2 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_HMR4) , P_Fld( 1 , HMR4_SPDR_MR4_OPT )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1) , P_Fld( 0x010000 , RK_TEST2_A1_TEST2_BASE )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2) , P_Fld( 0x000020 , TEST2_A2_TEST2_OFF )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3) , P_Fld( 1 , TEST2_A3_TESTAUDPAT ) \ + | P_Fld( 1 , TEST2_A3_TEST2WREN2_HW_EN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4) , P_Fld( 0x11 , TEST2_A4_TESTAUDINIT ) \ + | P_Fld( 0x0d , TEST2_A4_TESTAUDINC ) \ + | P_Fld( 0x04 , TEST2_A4_TESTAGENTRKSEL )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CMD_DEC_CTRL0) , P_Fld( 1 , CMD_DEC_CTRL0_RKMODE )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MISCTL0) , P_Fld( 0 , MISCTL0_PAGDIS ) \ + | P_Fld( 0 , MISCTL0_PBC_ARB_E1T ) \ + | P_Fld( 1 , MISCTL0_REFA_ARB_EN2 ) \ + | P_Fld( 1 , MISCTL0_PBC_ARB_EN ) \ + | P_Fld( 1 , MISCTL0_REFP_ARB_EN2 ) \ + | P_Fld( 0 , MISCTL0_EMIPREEN ) \ + | P_Fld( 1 , MISCTL0_PG_WAKEUP_OPT )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCSMCTRL) , P_Fld( 1 , SCSMCTRL_SC_PG_MAN_DIS ) \ + | P_Fld( TMRRI_MODE , SCSMCTRL_SC_PG_UPD_OPT )); + + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHUCTRL1) , P_Fld( 0x1a , SHUCTRL1_FC_PRDCNT )); //TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1) , P_Fld( 1 , DVFS_TIMING_CTRL1_DMSHU_CNT )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFPEND1) , P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH0 ) \ + | P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH1 ) \ + | P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH2 ) \ + | P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH3 ) \ + | P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH4 ) \ + | P_Fld( 0x3 , REFPEND1_MPENDREFCNT_TH5 ) \ + | P_Fld( 0x3 , REFPEND1_MPENDREFCNT_TH6 ) \ + | P_Fld( 0x3 , REFPEND1_MPENDREFCNT_TH7 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1) , P_Fld( 0x10 , CBT_WLEV_CTRL1_CATRAIN_INTV ) \ + | P_Fld( 0x3 , CBT_WLEV_CTRL1_CATRAINLAT )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_DRSCLR_EN ) \ + | P_Fld( !TMRRI_MODE , TX_SET0_RK_SCINPUT_OPT )); + + if(A_T->LP45_APHY_COMB_EN == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_OE_DOWNGRADE )); + } + //@Jouling, UI reloade path is updated. (DQSOSCR_SREF_TXUI_RELOAD_OPT) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR) , P_Fld( 0 , DQSOSCR_SREF_TXUI_RELOAD_OPT ) \ + | P_Fld( 1 , DQSOSCR_SREF_TXPI_RELOAD_OPT )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD) , P_Fld( 1 , DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS ) \ + | P_Fld( 2 , DUMMY_RD_RANK_NUM ) \ + | P_Fld( 1 , DUMMY_RD_DUMMY_RD_SW ) \ + | P_Fld( 1 , DUMMY_RD_DQSG_DMYRD_EN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD_INTV) , P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT7 ) \ + | P_Fld( 1 , DUMMY_RD_INTV_DUMMY_RD_CNT6 ) \ + | P_Fld( 1 , DUMMY_RD_INTV_DUMMY_RD_CNT5 ) \ + | P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT4 ) \ + | P_Fld( 1 , DUMMY_RD_INTV_DUMMY_RD_CNT3 ) \ + | P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT2 ) \ + | P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT1 ) \ + | P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT0 )); + //Byte Mode choose + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC) , P_Fld( p->dram_cbt_mode[RANK_0] , RK_DQSOSC_RK0_BYTE_MODE )); + vSetRank(p, RANK_1); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC) , P_Fld( p->dram_cbt_mode[RANK_1] , RK_DQSOSC_RK0_BYTE_MODE )); + vSetRank(p, RANK_0); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0) , P_Fld( 0 , TX_TRACKING_SET0_TX_TRACKING_OPT )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0) , P_Fld( 1 , TX_CG_SET0_SELPH_4LCG_DIS )); + + //DVFS support SRAM_EN only + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), P_Fld(DV_p.SRAM_EN, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1) , P_Fld( 1 , SWCMD_CTRL1_WRFIFO_MODE2 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DBG_CMDDEC_CMDSEL0) , P_Fld( M_LP4->EX_ROW_EN[0], DBG_CMDDEC_CMDSEL0_RANK0_10GBEN ) \ + | P_Fld( M_LP4->EX_ROW_EN[1], DBG_CMDDEC_CMDSEL0_RANK1_10GBEN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DBIWR_PROTECT) , P_Fld( 1 , DBIWR_PROTECT_DBIWR_IMP_EN ) \ + | P_Fld( 0 , DBIWR_PROTECT_DBIWR_PINMUX_EN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0) , P_Fld( 1 , RX_SET0_PRE_DLE_VLD_OPT ) \ + | P_Fld( 7 , RX_SET0_DATLAT_PDLE_TH )); + + //TODO SRAM MD32 control + // @Darren, sync MP settings from Joe (APB will be available when SRAM DMA access) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0) , P_Fld( 1 , MISC_SRAM_DMA0_PENABLE_LAT_WR ) \ + | P_Fld( 1 , MISC_SRAM_DMA0_KEEP_APB_ARB_ENA ) \ + | P_Fld( 1 , MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_MCLK_DIV), P_Fld( 1 , SSPM_MCLK_DIV_MCLK_DCM_EN )); + + //Indivial random sync + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL1), 0xFFFFFFFF); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL4), 0xFFFFFFFF); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL7), 0xFFFFFFFF); +} + +static void IO_Release(DRAMC_CTX_T *p) +{ + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DM_TX_ARCLK_OE ) \ + | P_Fld( 1 , MISC_CTRL1_R_DM_TX_ARCMD_OE )); + if(LPDDR5_EN_S == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2) , P_Fld( 1 , B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0) ); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2) , P_Fld( 1 , B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1) ); + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_DN ) \ + | P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_UP ) \ + | P_Fld( 0 , CA_CMD7_RG_TX_ARCLK_PULL_DN ) \ + | P_Fld( 0 , CA_CMD7_RG_TX_ARCLK_PULL_UP ) \ + | P_Fld( 0 , CA_CMD7_RG_TX_ARCS0_PULL_DN ) \ + | P_Fld( 0 , CA_CMD7_RG_TX_ARCS0_PULL_UP ) \ + | P_Fld( 0 , CA_CMD7_RG_TX_ARCMD_PULL_DN ) \ + | P_Fld( 0 , CA_CMD7_RG_TX_ARCMD_PULL_UP )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0 ) \ + | P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0 ) \ + | P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0 ) \ + | P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0 ) \ + | P_Fld( 0 , B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0 ) \ + | P_Fld( 0 , B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0 ) \ + | P_Fld( 0 , B0_DQ7_RG_TX_ARDQ_PULL_DN_B0 ) \ + | P_Fld( 0 , B0_DQ7_RG_TX_ARDQ_PULL_UP_B0 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1 ) \ + | P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1 ) \ + | P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1 ) \ + | P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1 ) \ + | P_Fld( 0 , B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1 ) \ + | P_Fld( 0 , B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 ) \ + | P_Fld( 0 , B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 ) \ + | P_Fld( 0 , B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 )); + //for dram spec CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA will help to fix CKE=0 before for meet 10ns tINIT2 + //Assert DRAM reset PIN + #if !SA_CONFIG_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DMDA_RRESETB_I )); + #endif +} + +static void DVFS_PRE_config(DRAMC_CTX_T *p) +{ +#if (fcFOR_CHIP_ID == fcMargaux) + U32 MCP_EN = 0; //remove for MCP timing issue +#else + U32 MCP_EN = 1; //for MCP should adjust some setting between CHs (A-B/C-D) +#endif + U32 REF_104M_EN = 1; + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + mcSHOW_DBG_MSG(("Enter into DVFS_PRE_config >>>>> \n")); + +#if ENABLE_ECO_SRAM_DMA_MISS_REG + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ11 ) , P_Fld( 1 , B0_DQ11_DMY_DQ11_B0 )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ11 ) , P_Fld( 1 , B1_DQ11_DMY_DQ11_B1 )); +#endif + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 1 , DVFS_CTRL0_VRCG_EN ) \ + | P_Fld( 0 , DVFS_CTRL0_DVFS_SYNC_MASK ) \ + | P_Fld( 1 , DVFS_CTRL0_MR13_SHU_EN ) \ + | P_Fld( 1 , DVFS_CTRL0_HWSET_WLRL ) \ + | P_Fld( 0 , DVFS_CTRL0_MRWWOPRA )); //Have to fix 0, 1 with bug (some bank without precharge) + //for DVFS sync + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 0 , MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL ));//SPM mode TODO should random 0 for SPM mode default + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0 ) , P_Fld( 0 , MISC_SRAM_DMA0_DMA_TIMER_EN )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA1 ) , P_Fld( 0x1ffff , MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL7 ) , P_Fld( 1 , MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld( 1 , MISC_DVFSCTL_R_DVFS_PICG_POSTPONE ) \ + | P_Fld( 1 , MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT )); + //for channel balance + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2) , P_Fld( 0 , MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION ) \ + | P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL )); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2) , P_Fld( 1 , MISC_DVFSCTL2_R_DVFS_CDC_OPTION )); + //Could be randomed + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0 ) , P_Fld( 0 , DVFS_CTRL0_DVFS_CKE_OPT ) \ + | P_Fld( 1 , DVFS_CTRL0_SCARB_PRI_OPT )); + //here is a flow??--TODO + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 1 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK ) \ + | P_Fld( 0 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK ) \ + | P_Fld( 0 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK ) \ + | P_Fld( 1 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK ) \ + | P_Fld( 3 , MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI ) \ + | P_Fld( 1 , MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE ) \ + | P_Fld( 7 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK) \ + | P_Fld( 1 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK) \ + | P_Fld( 0x3f , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK) ); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CLK_CTRL ) , P_Fld( 1 , MISC_CLK_CTRL_DVFS_CLK_MEM_SEL ) \ + | P_Fld( 1 , MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN )); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 0x10 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK)); + //flow end?? + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1) , P_Fld( 1 , DVFS_TIMING_CTRL1_DMSHU_CNT )\ + | P_Fld( 1 , DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT )); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2 ) , P_Fld( 1 , MISC_DVFSCTL2_R_DVFS_CDC_OPTION )\ + | P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_DLL_CHA )\ + | P_Fld( 1 , MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS )\ + | P_Fld( 1 , MISC_DVFSCTL2_R_DVFS_PARK_N )\ + | P_Fld( 1 , MISC_DVFSCTL2_R_DVFS_OPTION )); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( REF_104M_EN , MISC_CKMUX_SEL_RG_52M_104M_SEL )); + + //notice here: + //*SHU_PHDET_SPM_EN = 1 means during DFS period as master. 2 means slave. + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT ) , P_Fld( 1 , MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN )\ + | P_Fld( 2 , MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN )\ + | P_Fld( 1 , MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN )\ + | P_Fld( 2 , MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN )\ + | P_Fld( 1 , MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN )\ + | P_Fld( 1 , MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN )); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW ) \ + | P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW ) \ + | P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW ) ); + if(A_T->DLL_ASYNC_EN == 0) + { + mcSHOW_DBG_MSG(("Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. \n")); + //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vSetPHY2ChannelMapping(p, CHANNEL_B); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2 ) , P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_DLL_CHA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT ) , P_Fld( 2 , MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN )); + #if (CHANNEL_NUM>2) + vSetPHY2ChannelMapping(p, CHANNEL_D); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2 ) , P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_DLL_CHA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT ) , P_Fld( 2 , MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN )); + #endif + vSetPHY2ChannelMapping(p, CHANNEL_A); + //DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + + + if(MCP_EN == 1) + { + //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vSetPHY2ChannelMapping(p, CHANNEL_B); + mcSHOW_DBG_MSG(("MCP Enable leading 2ch's sync singles should adjust delay margin.")); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld((REF_104M_EN==1)?6:4, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 9 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK )); + #if (CHANNEL_NUM>2) + vSetPHY2ChannelMapping(p, CHANNEL_D); + mcSHOW_DBG_MSG(("MCP Enable leading 2ch's sync singles should adjust delay margin.")); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld((REF_104M_EN==1)?6:4, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 9 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK )); + #endif + vSetPHY2ChannelMapping(p, CHANNEL_A); + //DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + + + //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( 1 , MISC_CKMUX_SEL_FMEM_CK_MUX )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 0 , DVFS_CTRL0_R_DRAMC_CHA )\ + | P_Fld( 0 , DVFS_CTRL0_SHU_PHYRST_SEL )); + vSetPHY2ChannelMapping(p, CHANNEL_B); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( 3 , MISC_CKMUX_SEL_FMEM_CK_MUX )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 0 , DVFS_CTRL0_R_DRAMC_CHA )\ + | P_Fld( 1 , DVFS_CTRL0_SHU_PHYRST_SEL )); + #if (CHANNEL_NUM>2) + vSetPHY2ChannelMapping(p, CHANNEL_C); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( 1 , MISC_CKMUX_SEL_FMEM_CK_MUX )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 0 , DVFS_CTRL0_R_DRAMC_CHA )\ + | P_Fld( 0 , DVFS_CTRL0_SHU_PHYRST_SEL )); + vSetPHY2ChannelMapping(p, CHANNEL_D); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( 3 , MISC_CKMUX_SEL_FMEM_CK_MUX )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 0 , DVFS_CTRL0_R_DRAMC_CHA )\ + | P_Fld( 1 , DVFS_CTRL0_SHU_PHYRST_SEL )); + #endif + vSetPHY2ChannelMapping(p, CHANNEL_A); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + mcSHOW_DBG_MSG(("Exit from DVFS_PRE_config <<<<< \n")); +} + +void DIG_STATIC_SETTING(DRAMC_CTX_T *p) +{ + DIG_PHY_config(p); + GATING_MODE_CFG(&Gat_p); + DPHY_GAT_TRACK_Config(p,&Gat_p); + DRAMC_COMMON_Config(p); + #if 1//!SA_CONFIG_EN + DVFS_PRE_config(p);//for DVFS initial config.-- bring-up no need this code. but DVFS will need this + #endif + DDRPHY_PICG_Config(p); + IO_Release(p); + RX_INTPUT_Config(p);//TODO dummy write trigger +} + +#if 0 +void DPI_DIG_init(void) +{ + mysetscope(); + DIG_STATIC_SETTING(DramcConfig); +} +#endif diff --git a/src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c b/src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c new file mode 100644 index 0000000000..b5dfe2f2aa --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c @@ -0,0 +1,621 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include "dramc_dv_init.h" + +//==================================== +//TX CA delay configuration +//------------------------------------ +//Notice: +//TX config with shuffle register with all data_rate the same +//if under real IC , need to banlance the PI/Dline calibrated result +//==================================== +static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id) +{ + mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id)); + + U8 backup_ch_id = p->channel; + u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + u8 TX_UI; + + TX_UI = (DFS(group_id)->data_rate<=800) ? 1: 0 ; //TODO -- LPDDR5 need confirm + + vSetPHY2ChannelMapping(p, ch_id); + + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CS )\ + | P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CKE )\ + | P_Fld( 0 , SHU_SELPH_CA1_TXDLY_ODT )\ + | P_Fld( 0 , SHU_SELPH_CA1_TXDLY_RESET)\ + | P_Fld( 0 , SHU_SELPH_CA1_TXDLY_WE )\ + | P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CAS )\ + | P_Fld( 0 , SHU_SELPH_CA1_TXDLY_RAS )\ + | P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CS1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA2), P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA0 )\ + | P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA1 )\ + | P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA2 )\ + | P_Fld( 0 , SHU_SELPH_CA2_TXDLY_CKE1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA0 )\ + | P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA1 )\ + | P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA2 )\ + | P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA3 )\ + | P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA4 )\ + | P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA5 )\ + | P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA6 )\ + | P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA7 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA4), P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA8 )\ + | P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA9 )\ + | P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA10 )\ + | P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA11 )\ + | P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA12 )\ + | P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA13 )\ + | P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA14 )\ + | P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA15 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld( TX_UI , SHU_SELPH_CA5_DLY_CS )\ + | P_Fld( 1 , SHU_SELPH_CA5_DLY_CKE )\ + | P_Fld( 0 , SHU_SELPH_CA5_DLY_ODT )\ + | P_Fld( 1 , SHU_SELPH_CA5_DLY_RESET )\ + | P_Fld( 1 , SHU_SELPH_CA5_DLY_WE )\ + | P_Fld( 1 , SHU_SELPH_CA5_DLY_CAS )\ + | P_Fld( 1 , SHU_SELPH_CA5_DLY_RAS )\ + | P_Fld( TX_UI , SHU_SELPH_CA5_DLY_CS1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), P_Fld( 1 , SHU_SELPH_CA6_DLY_BA0 )\ + | P_Fld( 1 , SHU_SELPH_CA6_DLY_BA1 )\ + | P_Fld( 1 , SHU_SELPH_CA6_DLY_BA2 )\ + | P_Fld( 1 , SHU_SELPH_CA6_DLY_CKE1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA0 )\ + | P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA1 )\ + | P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA2 )\ + | P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA3 )\ + | P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA4 )\ + | P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA5 )\ + | P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA6 )\ + | P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA7 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA8), P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA8 )\ + | P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA9 )\ + | P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA10 )\ + | P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA11 )\ + | P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA12 )\ + | P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA13 )\ + | P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA14 )\ + | P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA15 )); + + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = backup_ShuRGAccessIdx; + + mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id)); +} + +//==================================== +//Impdance configuration +//------------------------------------ +//Notice: +//ANA result depend on calibration +//==================================== +static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id) +{ + mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id)); + U8 IPM_ODT_EN; + U8 CHKCYCLE = 7; //200ns algrith --TODO, @Darren, fix hw imp tracking + U8 TXDLY_CMD = 8; //Need algrithm support .. RL . TODO + U8 backup_ch_id = p->channel; + u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + vSetPHY2ChannelMapping(p, ch_id); + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; + + IPM_ODT_EN = (DFS(group_id)->data_rate>=2667) ? 1 : 0; + if (DFS(group_id)->data_rate>=4266) + TXDLY_CMD = 0xc; + else if (DFS(group_id)->data_rate>=3733) + TXDLY_CMD = 0xb; + else if (DFS(group_id)->data_rate>=3200) + TXDLY_CMD = 0xa; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING2) , P_Fld(!IPM_ODT_EN , SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1) , P_Fld(CHKCYCLE , SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE )\ + | P_Fld(8 , SHU_MISC_IMPCAL1_IMPCAL_CALICNT )\ + | P_Fld(4 , SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE )\ + | P_Fld(0x40 , SHU_MISC_IMPCAL1_IMPCALCNT )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12) , P_Fld(IPM_ODT_EN?0x1b:0x0f , SHU_CA_CMD12_RG_RIMP_REV )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1), P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS )\ + | P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS )\ + | P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING6) , P_Fld(TXDLY_CMD , SHU_MISC_DRVING6_IMP_TXDLY_CMD )); + + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = backup_ShuRGAccessIdx; + mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id)); +} + +//==================================== +//RX input delay configuration by mode choose +//------------------------------------ +//Notice: +// +//==================================== +static void DIG_CONFIG_SHUF_RXINPUT(DRAMC_CTX_T *p, int ch_id, int group_id) +{ + U8 PERBYTE_TRACK_EN = 1;//TODO + U8 DQM_TRACK_EN = 1;//TODO --following RD DBI + U8 DQM_FLOW_DQ_SEL = 3;//TODO + U8 RX_force_upd = 0;//TODO + + U8 backup_ch_id = p->channel; + u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + vSetPHY2ChannelMapping(p, ch_id); + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; + + mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id)); + if(RX_force_upd == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8), P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8), P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1)); + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld(PERBYTE_TRACK_EN , SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) \ + | P_Fld(DQM_FLOW_DQ_SEL , SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 ) \ + | P_Fld(DQM_TRACK_EN , SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 ) \ + | P_Fld(DQM_TRACK_EN , SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld(PERBYTE_TRACK_EN , SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) \ + | P_Fld(DQM_FLOW_DQ_SEL , SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 ) \ + | P_Fld(DQM_TRACK_EN , SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 ) \ + | P_Fld(DQM_TRACK_EN , SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 )); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , P_Fld(1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , P_Fld(1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1)); + + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = backup_ShuRGAccessIdx; + + mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id)); +} + +#if ENABLE_WDQS_MODE_2 +static void WDQSMode2TxDQOE_CNT(DRAMC_CTX_T *p, U8 *u1DQOE_CNT) +{ + switch (p->frequency) + { + case 1866: + *u1DQOE_CNT = 6; + break; + case 1600: + case 1200: + case 800: + case 600: + *u1DQOE_CNT = 5; + break; + case 933: + *u1DQOE_CNT = 4; + break; + case 400: + *u1DQOE_CNT = 9; + break; + default: + mcSHOW_ERR_MSG(("[WDQSMode2TxDQOE_CNT] frequency err!\n")); + #if __ETT__ + while (1); + #endif + } +} +#endif + +//==================================== +// MISC shuffle register fit +//------------------------------------ +//Notice: +// MISC shuffle reigster should be fixed +//==================================== +static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) +{ + U8 PICG_MODE = 1; + U8 LP5_HEFF = 0;//TODO + U8 LP5WRAPEN = 1;//Could random 1bit + U8 DQSIEN_DQSSTB_MODE=0; + U8 irank = 0; + U8 LP5_CASMODE = 1; //TODO Impact AC timing 1,2,3 three mode support 1:Low Power; 2:Low Freq; 3:High Eff; + U8 WCKDUAL = 0; + U8 NEW_RANK_MODE = 1; + U8 DUALSCHEN = 1; + U8 backup_rank = 0; + U8 DQOE_OPT = 0, DQOE_CNT = 0; + + #if ENABLE_WDQS_MODE_2 + DQOE_OPT = 1; + WDQSMode2TxDQOE_CNT(p, &DQOE_CNT); + #endif + + backup_rank = p->rank; + + mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] MISC >>>>>, group_id=%2d \n", group_id)); + if(LPDDR4_EN_S) + { + DUALSCHEN = (A_D->DQ_P2S_RATIO==4) ? 0 : 1; + } + else if (LPDDR5_EN_S) + { + DUALSCHEN = (A_D->CA_P2S_RATIO==2) ? 0 : 1; + } + + + switch(DFS(group_id)->DQSIEN_MODE) + { + case 1: {DQSIEN_DQSSTB_MODE = 1;break;} + case 2: {DQSIEN_DQSSTB_MODE = 2;break;} + case 3: {DQSIEN_DQSSTB_MODE = 3;break;} + case 6: {DQSIEN_DQSSTB_MODE = 2;break;} + case 7: {DQSIEN_DQSSTB_MODE = 3;break;} + default: mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] Unexpected DFS(group_id)->DQSIEN_MODE=%1d input, group_id=%2d, \n",DFS(group_id)->DQSIEN_MODE, group_id)); + } + + switch(LP5_CASMODE) + { + case 1: {WCKDUAL=0;LP5_HEFF=0;break;} + case 2: {WCKDUAL=1;LP5_HEFF=0;break;} + case 3: {WCKDUAL=0;LP5_HEFF=1;break;} + default: mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] Unexpected LP5_CASMODE(%d) input\n",LP5_CASMODE)); + } + + + U8 backup_ch_id = p->channel; + u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + + vSetPHY2ChannelMapping(p, ch_id); + + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0) , P_Fld( 1 , SHU_COMMON0_BL4 ) \ + | P_Fld( (A_D->DQ_P2S_RATIO==8) , SHU_COMMON0_FREQDIV4 ) \ + | P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_FDIV2 ) \ + | P_Fld( LPDDR4_EN_S , SHU_COMMON0_BC4OTF ) \ + | P_Fld( !(A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_DM64BITEN ));//TODO + if(LPDDR5_EN_S == 1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0) , P_Fld( (A_D->DQ_P2S_RATIO==16) , SHU_COMMON0_FREQDIV8 ) \ + | P_Fld( (DFS(group_id)->data_rate>=3733) , SHU_COMMON0_LP5BGEN ) \ + | P_Fld( (DFS(group_id)->data_rate<=3200) , SHU_COMMON0_LP5BGOTF ) \ + | P_Fld( LP5_HEFF , SHU_COMMON0_LP5WCKON ) \ + | P_Fld( (DFS(group_id)->data_rate>=4800) , SHU_COMMON0_DLE256EN ) \ + | P_Fld( LP5WRAPEN , SHU_COMMON0_LP5WRAPEN ) \ + | P_Fld( LP5_HEFF , SHU_COMMON0_LP5HEFF_MODE )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL) , P_Fld( WCKDUAL , SHU_WCKCTRL_WCKDUAL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL_1) , P_Fld( (A_D->CKR==2) , SHU_WCKCTRL_1_WCKSYNC_PRE_MODE));//TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD) , P_Fld( (A_D->CA_P2S_RATIO==2) , SHU_LP5_CMD_LP5_CMD1TO2EN ));//TODO + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIMING_CONF), P_Fld( 1 , SHU_ACTIMING_CONF_TREFBWIG ) \ + | P_Fld( 54 , SHU_ACTIMING_CONF_SCINTV )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_DCM_CTRL0) , P_Fld( 1 , SHU_DCM_CTRL0_FASTWAKE2 ) \ + | P_Fld( 1 , SHU_DCM_CTRL0_FASTWAKE )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0) , P_Fld( 1 , SHU_CONF0_ADVPREEN ) \ + | P_Fld( 63 , SHU_CONF0_DMPGTIM ) \ + | P_Fld( 0 , SHU_CONF0_REFTHD ) \ + | P_Fld( 1 , SHU_CONF0_PBREFEN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MATYPE) , P_Fld( 2 , SHU_MATYPE_MATYPE )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCHEDULER) , P_Fld( DUALSCHEN , SHU_SCHEDULER_DUALSCHEN )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_WPRE2T )); + //TODO SHU_TX_SET0_WPST1P5T OVER3200 DRAM spec need 1 but in TBA should random + //OE_EXT2UI strange rule.--TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0) , P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_TX_SET0_WDATRGO ) \ + | P_Fld( (DFS(group_id)->data_rate>=3200) , SHU_TX_SET0_WPST1P5T ) \ + | P_Fld( DQOE_OPT , SHU_TX_SET0_DQOE_OPT ) \ + | P_Fld( DQOE_CNT , SHU_TX_SET0_DQOE_CNT ) \ + | P_Fld( LPDDR5_EN_S , SHU_TX_SET0_OE_EXT2UI ) \ + | P_Fld( ((DFS(group_id)->data_rate==1600) && (A_D->DQ_P2S_RATIO==8))?5:2, SHU_TX_SET0_TXUPD_W2R_SEL )); //TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL1), P_Fld( 0x30 , MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO) \ + | P_Fld( 1 , MISC_SHU_STBCAL1_STB_UPDMASK_EN ) \ + | P_Fld( 9 , MISC_SHU_STBCAL1_STB_UPDMASKCYC ) \ + | P_Fld( (DFS(group_id)->data_rate > 1600) , MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); //TODO + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STBCALEN ) \ + | P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STB_SELPHCALEN ) \ + | P_Fld( DQSIEN_DQSSTB_MODE , MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE)); //TODO + + //@Darren, NOTE: Fix gating error or fifo mismatch => DMSTBLAT date_rate=1866 >= 3 : 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( (((Gat_p.GAT_TRACK_EN)&&(DFS(group_id)->data_rate>=1866))?(2+Gat_p.VALID_LAT_VALUE):(0+Gat_p.VALID_LAT_VALUE)) , MISC_SHU_STBCAL_DMSTBLAT ) \ + | P_Fld( 1 , MISC_SHU_STBCAL_PICGLAT ) \ + | P_Fld( 1 , MISC_SHU_STBCAL_DQSG_MODE ) \ + | P_Fld( PICG_MODE , MISC_SHU_STBCAL_DQSIEN_PICG_MODE)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), P_Fld( PICG_MODE , MISC_SHU_RANKCTL_RANK_RXDLY_OPT )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MISC ), P_Fld( 1 , SHU_MISC_REQQUE_MAXCNT )); + for(irank = RANK_0; irank < p->support_rank_num; irank++) + { + vSetRank(p, irank); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), P_Fld( 0 , MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) \ + | P_Fld( (A_D->DQ_P2S_RATIO == 4) , MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT)); + } + vSetRank(p, backup_rank); + + //RODT offset TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), P_Fld( 1 , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN ) \ + | P_Fld( 0 , MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE ) \ + | P_Fld( (NEW_RANK_MODE)?1:PICG_MODE , MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE ) \ + | P_Fld( 1 , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) \ + | P_Fld( ((A_D->DQ_P2S_RATIO == 4)?2:0) , MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET ) \ + | P_Fld( ((A_D->DQ_P2S_RATIO == 4)?1:4) , MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET ) \ + | P_Fld( ((A_D->DQ_P2S_RATIO == 16)?19:((A_D->DQ_P2S_RATIO == 8)?13:10)) , MISC_SHU_RODTENSTB_RODTENSTB_EXT )); + + //[SV] //SHL, fix RODT rd_period low 1T issue + // @Darren, confirm MP settings w/ Chau-Wei Wang (Jason) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?1:0) , MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?2:1) , MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD )); + + switch (A_D->DQ_P2S_RATIO) + { + case 4: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 0 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \ + | P_Fld( 0 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 1 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \ + | P_Fld( 1 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \ + | P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT )); + break; + } + case 8: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \ + | P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \ + | P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \ + | P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT )); + break; + } + case 16: + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 3 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \ + | P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \ + | P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \ + | P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT )); + break; + } + default:mcSHOW_DBG_MSG(("ERROR:Unexcepted A_D.DQ_P2S_RATIO = %2d \n", A_D->DQ_P2S_RATIO)); + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_CKE_CTRL) , P_Fld( 0 , SHURK_CKE_CTRL_CKE_DBE_CNT )); + + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = backup_ShuRGAccessIdx; + + mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] MISC <<<<<<, group_id=%2d \n", group_id)); +} + +static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id) +{ + U8 backup_ch_id = p->channel; + u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + + vSetPHY2ChannelMapping(p, ch_id); + mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id=%2d \n", group_id)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DQSG_RETRY1), P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_EN ) \ + | P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ONCE ) \ + | P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_3TIMES ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_1RANK ) \ + | P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN ) \ + | P_Fld( 0 /*@Darren, sync MP settings by YT (DFS(group_id)->data_rate>=3733)*/ , MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK ) \ + | P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE ) \ + | P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND ) \ + | P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING ) \ + | P_Fld( 1 , MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK ) \ + | P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE )); + + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = backup_ShuRGAccessIdx; + mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id=%2d \n", group_id)); +} + +static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id) +{ + U8 RD_DBI_EN = 1;//TODO + U8 WR_DBI_EN = 1;//TODO + + LP4_DRAM_CONFIG_T LP4_temp; + LP5_DRAM_CONFIG_T LP5_temp; + + U8 backup_ch_id = p->channel; + u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + + mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DBI >>>>>>, group_id=%2d \n", group_id)); + if(LPDDR4_EN_S) + { + LP4_DRAM_config(DFS(group_id)->data_rate,&LP4_temp); + RD_DBI_EN = LP4_temp.DBI_RD; + WR_DBI_EN = LP4_temp.DBI_WR; + } + else + {//TODO LPDDR5 and other dram type not ready + LP5_DRAM_config(DFS(group_id),&LP5_temp); + RD_DBI_EN = LP5_temp.DBI_RD; + WR_DBI_EN = LP5_temp.DBI_WR; + } + + + vSetPHY2ChannelMapping(p, ch_id); + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), P_Fld(RD_DBI_EN, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0 ) \ + | P_Fld(RD_DBI_EN, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), P_Fld(RD_DBI_EN, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1 ) \ + | P_Fld(RD_DBI_EN, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(WR_DBI_EN, SHU_TX_SET0_DBIWR )); + + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = backup_ShuRGAccessIdx; + mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DBI <<<<<<, group_id=%2d \n", group_id)); +} + +//TODO LPDDR5 +static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id) +{ + U8 backup_ch_id = p->channel; + u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + + LP4_DRAM_CONFIG_T LP4_temp; + + U8 HWSET_MR13_OP_Value =0; + U8 HWSET_VRCG_OP_Value =0; + U8 HWSET_MR2_OP_Value =0; + + mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id=%2d \n", group_id)); + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; + + if(LPDDR4_EN_S) + { + LP4_DRAM_config (DFS(group_id)->data_rate,&LP4_temp); + + HWSET_MR13_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6) | (( 0 << 5) | 8); //DMI default enable + HWSET_VRCG_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6); + HWSET_MR2_OP_Value = ((LP4_temp.MR_WL & 7) << 3) | (LP4_temp.MR_WL & 7); + } else { + mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] LPDDR5 have to use Run-time MRW to support DVFS! Do not Use HWSET_MR serial Registers.")); + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(HWSET_MR13_OP_Value, SHU_HWSET_MR13_HWSET_MR13_OP )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(HWSET_VRCG_OP_Value, SHU_HWSET_VRCG_HWSET_VRCG_OP )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(0xb , SHU_HWSET_VRCG_VRCGDIS_PRDCNT)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2 ), P_Fld(HWSET_MR2_OP_Value , SHU_HWSET_MR2_HWSET_MR2_OP )); + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = backup_ShuRGAccessIdx; + + mcSHOW_DBG_MSG(("[test_sa.c]====>ch_id:%2d, group_id:%2d, DPI_TBA_DVFS_WLRL_setting Exit\n", ch_id, group_id)); +} + +//================================================= +//Jump ratio calculate and setting +//------------------------------------------------ +//notice: 400 800 not support tracking TODO +// should confirm it with DQ_SEMI_OPEN =1 or not but not data_rate as condition +// +//================================================ +#if 0 +void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id) +{ + int tar; + int ratio = 32; + int result[DFS_GROUP_NUM]; + + U8 backup_ch_id = p->channel; + u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + + vSetPHY2ChannelMapping(p, ch_id); + mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]>>>>>>>> group_id = %1d",group_id)); + for(tar = 0; tar<DFS_GROUP_NUM;tar++) + { + if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400))) //TODO wihtout tracking + { + result[tar] = 0; + } + else + { + result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5); //+0.5 for roundup + } + mcSHOW_DBG_MSG(("\n[TXRX_jumpratio]current_group data_rate=%1d,tar_data_rate=%1d,jumpratio=%1d;\n",DFS(group_id)->data_rate,DFS(tar)->data_rate,result[tar])); + } + //============================= + //setting + //============================= + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET0), P_Fld( result[0] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0) \ + | P_Fld( result[1] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) \ + | P_Fld( result[2] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) \ + | P_Fld( result[3] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET1), P_Fld( result[4] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4) \ + | P_Fld( result[5] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5) \ + | P_Fld( result[6] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6) \ + | P_Fld( result[7] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET2), P_Fld( result[8] , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8) \ + | P_Fld( result[9] , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9)); + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]<<<<<<< group_id = %1d",group_id)); +} +#endif + +static void DIG_CONFIG_DVFS_DEPENDENCE(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) +{ + DIG_CONFIG_SHUF_DVFSWLRL(p,ch_id,group_id); + //TX_RX_jumpratio_calculate(p,ch_id,group_id); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DVFSDLL ) , P_Fld((LPDDR4_EN_S==1)?0x37:0x37 , MISC_SHU_DVFSDLL_R_DLL_IDLE )\ + | P_Fld((LPDDR4_EN_S==1)?0x4d:0x37 , MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE )\ + | P_Fld( ana_top_p.ALL_SLAVE_EN , MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL )\ + | P_Fld( 0 , MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL )); +} + +//==================================== +// Digital shuffle configuration entry +//------------------------------------ +//Notice: +// +//==================================== +void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) +{ + DIG_CONFIG_SHUF_ALG_TXCA(p,ch_id,group_id); + DIG_CONFIG_SHUF_IMP(p,ch_id,group_id); + DIG_CONFIG_SHUF_RXINPUT(p,ch_id,group_id); + DIG_CONFIG_SHUF_MISC_FIX(p,ch_id,group_id); + DIG_CONFIG_SHUF_DQSGRETRY(p,ch_id,group_id); + DIG_CONFIG_SHUF_DBI(p,ch_id,group_id); + DIG_CONFIG_DVFS_DEPENDENCE(p,ch_id,group_id); +} + +#if 0 +void DIG_CONFIG_SHUF_init(void) +{ + mysetscope(); + DIG_CONFIG_SHUF(DramcConfig,0,0); //temp ch0 group 0 +} + +void OTHER_GP_INIT(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) +{ + U8 backup_ch_id = p->channel; + U8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; + + //notice here. Replace the A_D A_T with new frequency auto-generation + ANA_TOP_FUNCTION_CFG(A_T,DFS(group_id)->data_rate); + ANA_CLK_DIV_config(A_D,DFS(group_id)); + + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; + ANA_sequence_shuffle_colletion(p,A_D);//these RG will be set during flow,but for DV another GP should be set directly + ANA_Config_shuffle(p,A_T,group_id); + DIG_CONFIG_SHUF(p,ch_id,group_id); + vSetPHY2ChannelMapping(p, backup_ch_id); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; +} + +void DPI_OTHER_GP_INIT(U32 ch_id, U32 group_id) +{ + mysetscope(); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + OTHER_GP_INIT(DramcConfig,ch_id,group_id); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + conf_to_sram_sudo(0,group_id,1); + conf_to_sram_sudo(1,group_id,1); + //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + //vSetPHY2ChannelMapping(DramcConfig, CHANNEL_A); + //DRAMC_DMA_CONF_to_SRAM(DramcConfig,group_id,1); + //vSetPHY2ChannelMapping(DramcConfig, CHANNEL_B); + //DRAMC_DMA_CONF_to_SRAM(DramcConfig,group_id,1); + //vSetPHY2ChannelMapping(DramcConfig, CHANNEL_A); + //DramcBroadcastOnOff(DRAMC_BROADCAST_ON); +} +#endif diff --git a/src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c b/src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c new file mode 100644 index 0000000000..8e1e332335 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include "dramc_dv_init.h" + +DRAM_TYPE_T MEM_TYPE = LPDDR4; +LP4_DRAM_CONFIG_T LP4_INIT; +LP5_DRAM_CONFIG_T LP5_INIT; +ANA_top_config_T ana_top_p; +ANA_DVFS_CORE_T ANA_option; +DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM]; +DRAMC_SUBSYS_CONFIG_T DV_p; + + +void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate) +{ + // tr-> DLL_ASYNC_EN = 0 ; //from DV random + // tr-> NEW_RANK_MODE = 1 ; //from DV random + // tr-> DLL_IDLE_MODE = 1 ; //from DV random + // tr-> LP45_APHY_COMB_EN= 1 ; //from DV define + // tr-> NEW_8X_MODE = 1 ; + + + tr->ALL_SLAVE_EN = (data_rate <= 1866)?1:0; + + if(LPDDR5_EN_S == 1) + { + tr->TX_ODT_DIS = (data_rate <=3200) ? 1 : 0 ; + } else { + tr->TX_ODT_DIS = (data_rate <=2400) ? 1 : 0 ; + } + + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("ANA top config\n" )); + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("DLL_ASYNC_EN = %2d\n",tr->DLL_ASYNC_EN )); + mcSHOW_DBG_MSG(("ALL_SLAVE_EN = %2d\n",tr->ALL_SLAVE_EN )); + mcSHOW_DBG_MSG(("NEW_RANK_MODE = %2d\n",tr->NEW_RANK_MODE )); + mcSHOW_DBG_MSG(("DLL_IDLE_MODE = %2d\n",tr->DLL_IDLE_MODE )); + mcSHOW_DBG_MSG(("LP45_APHY_COMB_EN = %2d\n",tr->LP45_APHY_COMB_EN)); + mcSHOW_DBG_MSG(("TX_ODT_DIS = %2d\n",tr->TX_ODT_DIS )); + mcSHOW_DBG_MSG(("NEW_8X_MODE = %2d\n",tr->NEW_8X_MODE )); + mcSHOW_DBG_MSG(("=================================== \n")); +} + + +void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs) +{ + U32 SEMI_OPEN_FMIN = 300; + U32 SEMI_OPEN_FMAX = 500;//lp4 600 + U32 PI_FMIN = 600; + U32 DQ_PICK; + U32 CA_PICK; //U + U32 CA_MCKIO; //S + U32 MCKIO_SEMI; //Q + U16 data_rate; + + data_rate = dfs->data_rate; + tr->DQ_P2S_RATIO = dfs->DQ_P2S_RATIO; + tr->CKR = dfs->CKR; + + //tr->CA_P2S_RATIO + tr->CA_P2S_RATIO = tr->DQ_P2S_RATIO/tr->CKR; + + //tr->DQ_CA_OPEN + tr->DQ_CA_OPEN = ( data_rate < (SEMI_OPEN_FMIN * 2) ) ? 1 : 0; + tr->DQ_SEMI_OPEN = ( data_rate/2 < PI_FMIN ) ? (1-tr->DQ_CA_OPEN) : ((data_rate <= SEMI_OPEN_FMAX*2) ? (1-tr->DQ_CA_OPEN) : 0); + tr->CA_SEMI_OPEN = (( data_rate/(tr->CKR*2) < PI_FMIN ) ? ((data_rate/(tr->CKR*2) > SEMI_OPEN_FMAX) ? 0 : (((tr->CA_P2S_RATIO>2)||(tr->DQ_SEMI_OPEN))*(1-tr->DQ_CA_OPEN))) : tr->DQ_SEMI_OPEN); + tr->CA_FULL_RATE = (tr->DQ_CA_OPEN == 1) ? ((tr->CKR>1)?1:0) : ((tr->DQ_SEMI_OPEN*tr->CA_SEMI_OPEN*(tr->CKR>>1)) + (( data_rate/(tr->CKR*2) < PI_FMIN) ? (1-tr->CA_SEMI_OPEN) : 0 )); + tr->DQ_CKDIV4_EN = ( tr->DQ_SEMI_OPEN == 1) ? DONT_CARE_VALUE : ((( (data_rate/2) < 1200 ) ? 1 : 0 ) * (1-tr->DQ_CA_OPEN)) ; + + CA_MCKIO = (data_rate/(tr->CKR*2))*(1+tr->CA_FULL_RATE); + DQ_PICK = (tr->DQ_SEMI_OPEN == 1) ? 0 : (data_rate/2) ; + CA_PICK = (tr->CA_SEMI_OPEN == 1) ? CA_MCKIO*2 : ((CA_MCKIO>=PI_FMIN) ? CA_MCKIO : (( CA_MCKIO >= (PI_FMIN/2) ) ? CA_MCKIO*2 : CA_MCKIO *4 )); + + tr->CA_CKDIV4_EN = ((CA_PICK < 1200 ) ? 1 : 0 ) * ( 1- tr->DQ_CA_OPEN) ; + + tr->CA_PREDIV_EN = (data_rate >= 4800) ? 1 : 0 ; + + #if SA_CONFIG_EN + if(LPDDR4_EN_S) + { + // @Darren, for LP4 8PH Delay + if (data_rate <= 1866) + tr->PH8_DLY = 0; + else if (data_rate <= 2400) + tr->PH8_DLY = 0x11; + else if (data_rate <= 3200) + tr->PH8_DLY = 0xc; + else if (data_rate <= 3733) + tr->PH8_DLY = 0x9; + else + tr->PH8_DLY = 0x7; + } + else + #endif + { + tr->PH8_DLY = ((tr->DQ_CA_OPEN == 0) && (tr->DQ_SEMI_OPEN == 0) && (tr->DQ_CKDIV4_EN == 0)) ? ( (1000000>>4)/data_rate -4) : DONT_CARE_VALUE; + } + + MCKIO_SEMI = (tr->DQ_SEMI_OPEN * tr->CA_SEMI_OPEN * (data_rate/2)) + (1-tr->DQ_SEMI_OPEN) * tr->CA_SEMI_OPEN * CA_MCKIO; + + tr->SEMI_OPEN_CA_PICK_MCK_RATIO = ( MCKIO_SEMI == 0) ? DONT_CARE_VALUE : (CA_PICK*tr->DQ_P2S_RATIO)/data_rate ; //need to be improved + + tr->DQ_AAMCK_DIV = (tr->DQ_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/2)*(1-tr->DQ_SEMI_OPEN)) : DONT_CARE_VALUE; + tr->CA_AAMCK_DIV = (tr->CA_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/(2*tr->CKR))*(1+tr->CA_FULL_RATE)) : DONT_CARE_VALUE; + tr->CA_ADMCK_DIV = CA_PICK/(data_rate/tr->DQ_P2S_RATIO); //need to be improved + //tr->DQ_TRACK_CA_EN = ((data_rate/2) >= 2133) ? 1 : 0 ; //for Alucary confirm that 'interface timing' sign NOT OK. + tr->DQ_TRACK_CA_EN = 0 ; + tr->PLL_FREQ = ((DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) > (CA_PICK*2*(tr->CA_CKDIV4_EN+1))) ? (DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) : (CA_PICK*2*(tr->CA_CKDIV4_EN+1)); + #if SA_CONFIG_EN + //de-sense + if(data_rate==2400) + tr->PLL_FREQ = 2366; //DDR2366 + else if(data_rate==1200) + tr->PLL_FREQ = 2288; //DDR1144 + else if(data_rate==3200 || data_rate==1600) + tr->PLL_FREQ = 3068; //DDR3068 DDR1534 + else if(data_rate==800) + tr->PLL_FREQ = 3016; //DDR754 + else if(data_rate==400) + tr->PLL_FREQ = 4000; //DDR250 Op + #endif + tr->DQ_UI_PI_RATIO = 32; //TODO:notice here. infact if DQ_SEMI_OPEM == 1 UI_PI_RATIO will only 4 lower 2bit wihtout use + tr->CA_UI_PI_RATIO = (tr->CA_SEMI_OPEN == 0) ? ((tr->CA_FULL_RATE == 1)? 64 : DONT_CARE_VALUE) : 32; + + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("data_rate = %4d\n" ,data_rate )); + mcSHOW_DBG_MSG(("CKR = %1d\n" ,tr->CKR )); + mcSHOW_DBG_MSG(("DQ_P2S_RATIO = %1d\n" ,tr->DQ_P2S_RATIO )); + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("CA_P2S_RATIO = %1d\n" ,tr->CA_P2S_RATIO )); + mcSHOW_DBG_MSG(("DQ_CA_OPEN = %1d\n" ,tr->DQ_CA_OPEN )); + mcSHOW_DBG_MSG(("DQ_SEMI_OPEN = %1d\n" ,tr->DQ_SEMI_OPEN )); + mcSHOW_DBG_MSG(("CA_SEMI_OPEN = %1d\n" ,tr->CA_SEMI_OPEN )); + mcSHOW_DBG_MSG(("CA_FULL_RATE = %1d\n" ,tr->CA_FULL_RATE )); + mcSHOW_DBG_MSG(("DQ_CKDIV4_EN = %1d\n" ,tr->DQ_CKDIV4_EN )); + mcSHOW_DBG_MSG(("CA_CKDIV4_EN = %1d\n" ,tr->CA_CKDIV4_EN )); + mcSHOW_DBG_MSG(("CA_PREDIV_EN = %1d\n" ,tr->CA_PREDIV_EN )); + mcSHOW_DBG_MSG(("PH8_DLY = %1d\n" ,tr->PH8_DLY )); + mcSHOW_DBG_MSG(("SEMI_OPEN_CA_PICK_MCK_RATIO= %1d\n" ,tr->SEMI_OPEN_CA_PICK_MCK_RATIO)); + mcSHOW_DBG_MSG(("DQ_AAMCK_DIV = %1d\n" ,tr->DQ_AAMCK_DIV )); + mcSHOW_DBG_MSG(("CA_AAMCK_DIV = %1d\n" ,tr->CA_AAMCK_DIV )); + mcSHOW_DBG_MSG(("CA_ADMCK_DIV = %1d\n" ,tr->CA_ADMCK_DIV )); + mcSHOW_DBG_MSG(("DQ_TRACK_CA_EN = %1d\n" ,tr->DQ_TRACK_CA_EN )); + mcSHOW_DBG_MSG(("CA_PICK = %2d\n" ,CA_PICK )); + mcSHOW_DBG_MSG(("CA_MCKIO = %1d\n" ,CA_MCKIO )); + mcSHOW_DBG_MSG(("MCKIO_SEMI = %1d\n" ,MCKIO_SEMI )); + mcSHOW_DBG_MSG(("PLL_FREQ = %1d\n" ,tr->PLL_FREQ )); + mcSHOW_DBG_MSG(("DQ_UI_PI_RATIO = %1d\n" ,tr->DQ_UI_PI_RATIO )); + mcSHOW_DBG_MSG(("CA_UI_PI_RATIO = %1d\n" ,tr->CA_UI_PI_RATIO )); + mcSHOW_DBG_MSG(("=================================== \n")); +} + +void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr) +{ + U8 gp_id; + tr->SRAM_EN = 1; + tr->MD32_EN = 1; + tr->a_cfg = &ana_top_p; + tr->a_opt = &ANA_option; + tr->lp4_init = &LP4_INIT; + tr->lp5_init = &LP5_INIT; + + for(gp_id = 0; gp_id < DFS_GROUP_NUM; gp_id++) + { + tr->DFS_GP[gp_id] = &DFS_TOP[gp_id]; + } + + if(LPDDR4_EN_S) + { + (tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8; + (tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8; + (tr->DFS_GP[2])->data_rate = 2400; (tr->DFS_GP[2])->DQ_P2S_RATIO = 8; + (tr->DFS_GP[3])->data_rate = 1866; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8; + (tr->DFS_GP[4])->data_rate = 1600; (tr->DFS_GP[4])->DQ_P2S_RATIO = 4; + (tr->DFS_GP[5])->data_rate = 1200; (tr->DFS_GP[5])->DQ_P2S_RATIO = 4; + (tr->DFS_GP[6])->data_rate = 800 ; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4; + (tr->DFS_GP[7])->data_rate = 400 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4; + (tr->DFS_GP[8])->data_rate = 4266; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4; + (tr->DFS_GP[9])->data_rate = 1600; (tr->DFS_GP[9])->DQ_P2S_RATIO = 4; + + for(gp_id = 0; gp_id < DFS_GROUP_NUM; gp_id++) + { + (tr->DFS_GP[gp_id])->CKR = 1; + (tr->DFS_GP[gp_id])->DQSIEN_MODE = 1; + } +#if 0//DV_CONFIG_EN==1 + tr->lp4_init->LP4Y_EN = DUT_p.LP4Y_EN ; + tr->lp4_init->WR_PST = DUT_p.LP4_WR_PST ; + tr->lp4_init->OTF = DUT_p.LP4_OTF ; + tr->a_cfg->NEW_8X_MODE = DUT_p.NEW_8X_MODE ; + tr->a_cfg->LP45_APHY_COMB_EN = 1 ; + tr->a_cfg->DLL_IDLE_MODE = DUT_p.DLL_IDLE_MODE ; + tr->a_cfg->NEW_RANK_MODE = DUT_p.NEW_RANK_MODE ; + tr->a_cfg->DLL_ASYNC_EN = DUT_p.DLL_ASYNC_EN ; + tr->MD32_EN = DUT_p.MD32_EN ; + tr->SRAM_EN = DUT_p.SRAM_EN ; + tr->GP_NUM = DUT_p.GP_NUM ; + + + for(gp_id = 0; gp_id < DV_p.GP_NUM; gp_id++) + { + tr->DFS_GP[gp_id]->data_rate = DUT_shu_p[gp_id].data_rate ; + tr->DFS_GP[gp_id]->DQSIEN_MODE = DUT_shu_p[gp_id].DQSIEN_MODE ; + tr->DFS_GP[gp_id]->DQ_P2S_RATIO = DUT_shu_p[gp_id].DQ_P2S_RATIO; + tr->DFS_GP[gp_id]->CKR = DUT_shu_p[gp_id].CKR ; + } +#endif + #if SA_CONFIG_EN + tr->lp4_init->EX_ROW_EN[0] = p->u110GBEn[RANK_0] ; + tr->lp4_init->EX_ROW_EN[1] = p->u110GBEn[RANK_1] ; + tr->lp4_init->BYTE_MODE[0] = 0 ; + tr->lp4_init->BYTE_MODE[1] = 0 ; + tr->lp4_init->LP4Y_EN = 0;//DUT_p.LP4Y_EN ; + tr->lp4_init->WR_PST = 1;//DUT_p.LP4_WR_PST ; + tr->lp4_init->OTF = 1;//DUT_p.LP4_OTF ; + tr->a_cfg->NEW_8X_MODE = 1;//DUT_p.NEW_8X_MODE ; + tr->a_cfg->LP45_APHY_COMB_EN = 1 ; + tr->a_cfg->DLL_IDLE_MODE = 1;//DUT_p.DLL_IDLE_MODE ; + tr->a_cfg->NEW_RANK_MODE = 1;//DUT_p.NEW_RANK_MODE ; + tr->a_cfg->DLL_ASYNC_EN = 0;//DUT_p.DLL_ASYNC_EN ; + tr->MD32_EN = 0;//DUT_p.MD32_EN ; + tr->SRAM_EN = 1;//DUT_p.SRAM_EN ; + tr->GP_NUM = 10;//DUT_p.GP_NUM ; + + if(p->freq_sel==LP4_DDR4266) + { + (tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8; + } + else if(p->freq_sel==LP4_DDR3733) + { + (tr->DFS_GP[0])->data_rate = 3733; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8; + } + else if(p->freq_sel==LP4_DDR3200) + { + (tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8; + } + else if(p->freq_sel==LP4_DDR2400) + { + (tr->DFS_GP[0])->data_rate = 2400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8; + } + else if(p->freq_sel==LP4_DDR1866) + { + (tr->DFS_GP[0])->data_rate = 1866; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8; + } + else if(p->freq_sel==LP4_DDR1600) + { + (tr->DFS_GP[0])->data_rate = 1600; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8; + } + else if(p->freq_sel==LP4_DDR1200) + { + (tr->DFS_GP[0])->data_rate = 1200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8; + } + else if(p->freq_sel==LP4_DDR800) + { + (tr->DFS_GP[0])->data_rate = 800; (tr->DFS_GP[0])->DQ_P2S_RATIO = 4; + } + else if(p->freq_sel==LP4_DDR400) + { + (tr->DFS_GP[0])->data_rate = 400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 4; + } + #endif + +//============================================== +//Oterwise, SA should rebuild Top configuration. +//============================================== + + LP4_DRAM_config(tr->DFS_GP[0]->data_rate,tr->lp4_init); + } + + //TODO for LPDDR5 + //data_rate DQ_P2S_RATIO + //[4800:6400] 16 + //[1600:4800) 8 + //[400 :1600] 4 + //========================= + //data_rate CKR + //[3733:6400] 4 + //[400 :3733) 2 + else if (MEM_TYPE == LPDDR5) + { + #if SA_CONFIG_EN + if(p->freq_sel==LP5_DDR4266) + { + (tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2; + } + else if(p->freq_sel==LP5_DDR5500) + { + (tr->DFS_GP[0])->data_rate = 5500; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2; + } + else + { + (tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 2;tr->DFS_GP[0]->DQSIEN_MODE = 1; + } + #else + (tr->DFS_GP[0])->data_rate = 6400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 1; + #endif + (tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[1]->CKR = 2;tr->DFS_GP[1]->DQSIEN_MODE = 1; + (tr->DFS_GP[2])->data_rate = 1600; (tr->DFS_GP[2])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[2]->CKR = 2;tr->DFS_GP[2]->DQSIEN_MODE = 1; + (tr->DFS_GP[3])->data_rate = 4266; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[3]->CKR = 4;tr->DFS_GP[3]->DQSIEN_MODE = 1; + (tr->DFS_GP[4])->data_rate = 3733; (tr->DFS_GP[4])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[4]->CKR = 4;tr->DFS_GP[4]->DQSIEN_MODE = 1; + (tr->DFS_GP[5])->data_rate = 1600; (tr->DFS_GP[5])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[5]->CKR = 2;tr->DFS_GP[5]->DQSIEN_MODE = 1; + (tr->DFS_GP[6])->data_rate = 1200; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[6]->CKR = 2;tr->DFS_GP[6]->DQSIEN_MODE = 1; + (tr->DFS_GP[7])->data_rate = 800 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[7]->CKR = 2;tr->DFS_GP[7]->DQSIEN_MODE = 1; + (tr->DFS_GP[8])->data_rate = 400 ; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[8]->CKR = 2;tr->DFS_GP[8]->DQSIEN_MODE = 1; + (tr->DFS_GP[9])->data_rate = 5500; (tr->DFS_GP[9])->DQ_P2S_RATIO = 16; tr->DFS_GP[9]->CKR = 4;tr->DFS_GP[9]->DQSIEN_MODE = 1; + LP5_DRAM_config(tr->DFS_GP[0],tr->lp5_init); + } + + + ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate); + ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]); + + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("memory_type:%s \n",LPDDR5_EN_S?"LPDDR5":"LPDDR4" )); + mcSHOW_DBG_MSG(("GP_NUM : %1d \n",tr->GP_NUM )); + mcSHOW_DBG_MSG(("SRAM_EN : %1d \n",tr->SRAM_EN )); + mcSHOW_DBG_MSG(("MD32_EN : %1d \n",tr->MD32_EN )); + mcSHOW_DBG_MSG(("=================================== \n")); +} diff --git a/src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c b/src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c new file mode 100644 index 0000000000..01a0569bb0 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include "dramc_dv_init.h" + +//DRAM LP4 initial configuration +void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr) +{ + tr->BYTE_MODE[0] = 0;//TODO + tr->BYTE_MODE[1] = 0;//TODO +#if 0 // @Darren, remove it + #if SA_CONFIG_EN + tr->EX_ROW_EN[0] = 0;//TODO + tr->EX_ROW_EN[1] = 0;//TODO + #else + tr->EX_ROW_EN[0] = 1;//TODO + tr->EX_ROW_EN[1] = 0;//TODO + #endif +#endif + tr->MR_WL = LP4_DRAM_INIT_RLWL_MRfield_config(data_rate); + tr->MR_RL = tr->MR_WL; + tr->BL = 2; + tr->RPST = 0; + tr->RD_PRE = 0; + tr->WR_PRE = 1; + tr->WR_PST = (data_rate>=2667)?1:0; //TODO + #if SA_CONFIG_EN + tr->DBI_WR = 0; + tr->DBI_RD = 0; + #else + tr->DBI_WR = (data_rate>=2667)?1:0; + tr->DBI_RD = (data_rate>=2667)?1:0; + #endif + // tr->DMI = 1; + tr->OTF = 1; + #if ENABLE_LP4Y_DFS + tr->LP4Y_EN = (data_rate>=1866)?0:1; //TODO, @Darren for LP4Y + #else + tr->LP4Y_EN = 0; + #endif + tr->WORK_FSP = (data_rate>=2667)?1:0; + + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("LPDDR4 DRAM CONFIGURATION\n" )); + mcSHOW_DBG_MSG(("=================================== \n")); +// mcSHOW_DBG_MSG(("BYTE_MODE = B%1b\n",tr->BYTE_MODE)); + mcSHOW_DBG_MSG(("EX_ROW_EN[0] = 0x%1x\n",tr->EX_ROW_EN[0])); + mcSHOW_DBG_MSG(("EX_ROW_EN[1] = 0x%1x\n",tr->EX_ROW_EN[1])); + mcSHOW_DBG_MSG(("LP4Y_EN = 0x%1x\n",tr->LP4Y_EN )); + mcSHOW_DBG_MSG(("WORK_FSP = 0x%1x\n",tr->WORK_FSP )); + mcSHOW_DBG_MSG(("WL = 0x%1x\n",tr->MR_WL )); + mcSHOW_DBG_MSG(("RL = 0x%1x\n",tr->MR_RL )); + mcSHOW_DBG_MSG(("BL = 0x%1x\n",tr->BL )); + mcSHOW_DBG_MSG(("RPST = 0x%1x\n",tr->RPST )); + mcSHOW_DBG_MSG(("RD_PRE = 0x%1x\n",tr->RD_PRE )); + mcSHOW_DBG_MSG(("WR_PRE = 0x%1x\n",tr->WR_PRE )); + mcSHOW_DBG_MSG(("WR_PST = 0x%1x\n",tr->WR_PST )); + mcSHOW_DBG_MSG(("DBI_WR = 0x%1x\n",tr->DBI_WR )); + mcSHOW_DBG_MSG(("DBI_RD = 0x%1x\n",tr->DBI_RD )); +// mcSHOW_DBG_MSG(("DMI = 0x%1x\n",tr->DMI )); + mcSHOW_DBG_MSG(("OTF = 0x%1x\n",tr->OTF )); + mcSHOW_DBG_MSG(("=================================== \n")); +} +//LP4 dram initial ModeRegister setting +U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate) +{ + U8 MR2_RLWL; + + if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;} + else if ((data_rate<=3733) && (data_rate > 3200)) {MR2_RLWL = 6 ;} + else if ((data_rate<=3200) && (data_rate > 2667)) {MR2_RLWL = 5 ;} + else if ((data_rate<=2667) && (data_rate > 2400)) {MR2_RLWL = 4 ;} + else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;} + else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;} + else if ((data_rate<=1600) && (data_rate > 1200)) {MR2_RLWL = 2 ;} + else if ((data_rate<=1200) && (data_rate > 800 )) {MR2_RLWL = 2 ;} + else if ((data_rate<=800 ) && (data_rate > 400 )) {MR2_RLWL = 2 ;} + else if (data_rate<=400 ) {MR2_RLWL = 0 ;} + else {mcSHOW_DBG_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR4 \n",data_rate));return -1;} + + mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL)); + + return MR2_RLWL; +} + +U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value) +{ + U32 RL=0; + + switch(MR_RL_field_value) + { + case 0: {RL = 6; break;} + case 1: {RL = (BYTE_MODE_EN == 1) ? ( 12 ) : ((DBI_EN == 1) ? 12 : 10); break;} + case 2: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 18 : 16 ) : ((DBI_EN == 1) ? 16 : 14); break;} + case 3: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 24 : 22 ) : ((DBI_EN == 1) ? 22 : 20); break;} + case 4: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 30 : 28 ) : ((DBI_EN == 1) ? 28 : 24); break;} + case 5: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 36 : 32 ) : ((DBI_EN == 1) ? 32 : 28); break;} + case 6: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 40 : 36 ) : ((DBI_EN == 1) ? 36 : 32); break;} + case 7: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 44 : 40 ) : ((DBI_EN == 1) ? 40 : 36); break;} + default:{mcSHOW_DBG_MSG(("ERROR: Unexpected MR_RL_field_value:%1x under LPDDR4 \n",MR_RL_field_value));} + } + + mcSHOW_DBG_MSG(("[ReadLatency GET] BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,RL)); + + return RL; +} + +U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value) +{ + U32 WL=0; + + switch(MR_WL_field_value) + { + case 0: {WL = 4; break;} + case 1: {WL = ((Version == 0) ? 6 : 8 ); break;} + case 2: {WL = ((Version == 0) ? 8 : 12 ); break;} + case 3: {WL = ((Version == 0) ? 10 : 18 ); break;} + case 4: {WL = ((Version == 0) ? 12 : 22 ); break;} + case 5: {WL = ((Version == 0) ? 14 : 26 ); break;} + case 6: {WL = ((Version == 0) ? 16 : 30 ); break;} + case 7: {WL = ((Version == 0) ? 18 : 34 ); break;} + default:{mcSHOW_DBG_MSG(("ERROR: Unexpected MR_WL_field_value:%1x under LPDDR4 \n",MR_WL_field_value));} + } + + mcSHOW_DBG_MSG(("[WriteLatency GET] Version:%1d-MR_RL_field_value:%1x-WL:%2d\n",Version,MR_WL_field_value,WL)); + + return WL; +} + +//LP5 dram initial ModeRegister setting +static U8 LP5_DRAM_INIT_RLWL_MRfield_config(U32 data_rate) +{ + U8 MR2_RLWL=0; + + if ((data_rate<=6400) && (data_rate > 6000)) {MR2_RLWL = 11 ;} + else if ((data_rate<=6400) && (data_rate > 5500)) {MR2_RLWL = 10 ;} + else if ((data_rate<=5500) && (data_rate > 4800)) {MR2_RLWL = 9 ;} + else if ((data_rate<=4800) && (data_rate > 4266)) {MR2_RLWL = 8 ;} + else if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;} + else if ((data_rate<=3700) && (data_rate > 3200)) {MR2_RLWL = 6 ;} + else if ((data_rate<=3200) && (data_rate > 2400)) {MR2_RLWL = 5 ;} + else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;} + else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;} + else if ((data_rate<=1600) && (data_rate >= 800)) {MR2_RLWL = 2 ;} + else {mcSHOW_DBG_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR5 \n",data_rate));return -1;} + + mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL)); + + return MR2_RLWL; +} + +void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr) +{ + tr->BYTE_MODE[0] = 0 ; + tr->BYTE_MODE[1] = 0 ; + tr->EX_ROW_EN[0] = 0 ; + tr->EX_ROW_EN[1] = 0 ; + tr->MR_WL = LP5_DRAM_INIT_RLWL_MRfield_config(dfs_tr->data_rate); + tr->MR_RL = tr->MR_WL; + tr->BL = 2; + tr->CK_Mode = (dfs_tr->data_rate>=2133)?0:1; //0:diff 1:SE + tr->RPST = 0; + tr->RD_PRE = 0; + tr->WR_PRE = 1; + tr->WR_PST = (dfs_tr->data_rate>=3200)?1:0 ; + #if SA_CONFIG_EN + tr->DBI_WR = 0; + #if LP5_DDR4266_RDBI_WORKAROUND + tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ; + #else + tr->DBI_RD = 0; + #endif + #else + tr->DBI_WR = (dfs_tr->data_rate>=3733)?1:0 ; + tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ; + #endif + tr->DMI = 1; + tr->OTF = 1; + tr->WCK_PST = (dfs_tr->data_rate>=3733)?1:0 ; + tr->RDQS_PST = 0; + tr->CA_ODT = 0; + tr->DQ_ODT = (dfs_tr->data_rate>=3733)?3:0 ; + tr->CKR = (dfs_tr->CKR==4)?0:1; + tr->WCK_ON = 0; //TODO + #if SA_CONFIG_EN + #if WCK_LEVELING_FM_WORKAROUND + tr->WCK_FM = 0; + #else + tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0; + #endif + #else + tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0; + #endif + tr->WCK_ODT = (dfs_tr->CKR==4)?3:0; + tr->DVFSQ = (dfs_tr->data_rate>=3733)?0:1; + tr->DVFSC = (dfs_tr->data_rate>=2133)?0:1; + tr->RDQSmode[0] = EN_both;//TODO --RK0 have to EN_t if SE enable + tr->RDQSmode[1] = EN_both;//TODO --RK1 have to EN_c if SE enable + tr->WCKmode[0] = (dfs_tr->data_rate>=1600)?0:1; + tr->WCKmode[1] = (dfs_tr->data_rate>=1600)?0:2; + tr->RECC = 0;//TODO + tr->WECC = 0;//TODO + tr->BankMode = (dfs_tr->data_rate>=3733)?BG4BK4:BK16; + tr->WORK_FSP = 0;//TODO + + switch (dfs_tr->DQSIEN_MODE) + { + case 1: {tr->RDQS_PRE = 0;break;} + case 2: {tr->RDQS_PRE = 1;break;} + case 3: {tr->RDQS_PRE = 3;break;} + case 6: {tr->RDQS_PRE = 1;break;} + case 7: {tr->RDQS_PRE = 3;break;} + default : {mcSHOW_DBG_MSG(("ERROR: Unexpected DQSIEN_MODE :%d \n",dfs_tr->DQSIEN_MODE)); while(1);}; + } + + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("LPDDR5 DRAM CONFIGURATION\n" )); + mcSHOW_DBG_MSG(("=================================== \n")); + mcSHOW_DBG_MSG(("MR_WL = 0x%1x\n",tr->MR_WL )); + mcSHOW_DBG_MSG(("MR_RL = 0x%1x\n",tr->MR_RL )); + mcSHOW_DBG_MSG(("BL = 0x%1x\n",tr->BL )); + mcSHOW_DBG_MSG(("CK_Mode = 0x%1x\n",tr->CK_Mode )); + mcSHOW_DBG_MSG(("RPST = 0x%1x\n",tr->RPST )); + mcSHOW_DBG_MSG(("RD_PRE = 0x%1x\n",tr->RD_PRE )); + mcSHOW_DBG_MSG(("RDQS_PRE = 0x%1x\n",tr->RDQS_PRE )); + mcSHOW_DBG_MSG(("WR_PRE = 0x%1x\n",tr->WR_PRE )); + mcSHOW_DBG_MSG(("WR_PST = 0x%1x\n",tr->WR_PST )); + mcSHOW_DBG_MSG(("DBI_WR = 0x%1x\n",tr->DBI_WR )); + mcSHOW_DBG_MSG(("DBI_RD = 0x%1x\n",tr->DBI_RD )); + mcSHOW_DBG_MSG(("DMI = 0x%1x\n",tr->DMI )); + mcSHOW_DBG_MSG(("OTF = 0x%1x\n",tr->OTF )); + mcSHOW_DBG_MSG(("WCK_PST = 0x%1x\n",tr->WCK_PST )); + mcSHOW_DBG_MSG(("RDQS_PST = 0x%1x\n",tr->RDQS_PST )); + mcSHOW_DBG_MSG(("CA_ODT = 0x%1x\n",tr->CA_ODT )); + mcSHOW_DBG_MSG(("DQ_ODT = 0x%1x\n",tr->DQ_ODT )); + mcSHOW_DBG_MSG(("CKR = 0x%1x\n",tr->CKR )); + mcSHOW_DBG_MSG(("WCK_ON = 0x%1x\n",tr->WCK_ON )); + mcSHOW_DBG_MSG(("WCK_FM = 0x%1x\n",tr->WCK_FM )); + mcSHOW_DBG_MSG(("WCK_ODT = 0x%1x\n",tr->WCK_ODT )); + mcSHOW_DBG_MSG(("DVFSQ = 0x%1x\n",tr->DVFSQ )); + mcSHOW_DBG_MSG(("DVFSC = 0x%1x\n",tr->DVFSC )); + mcSHOW_DBG_MSG(("RDQSmode[0] = 0x%1x\n",tr->RDQSmode[0] )); + mcSHOW_DBG_MSG(("RDQSmode[1] = 0x%1x\n",tr->RDQSmode[1] )); + mcSHOW_DBG_MSG(("WCKmode[0] = 0x%1x\n",tr->WCKmode[0] )); + mcSHOW_DBG_MSG(("WCKmode[1] = 0x%1x\n",tr->WCKmode[1] )); + mcSHOW_DBG_MSG(("RECC = 0x%1x\n",tr->RECC )); + mcSHOW_DBG_MSG(("WECC = 0x%1x\n",tr->WECC )); + mcSHOW_DBG_MSG(("BankMode = 0x%1x\n",tr->BankMode )); + mcSHOW_DBG_MSG(("WORK_FSP = 0x%1x\n",tr->WORK_FSP )); + mcSHOW_DBG_MSG(("=================================== \n")); +} diff --git a/src/vendorcode/mediatek/mt8192/dramc/Hal_io.c b/src/vendorcode/mediatek/mt8192/dramc/Hal_io.c new file mode 100644 index 0000000000..d0f7c769a4 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/Hal_io.c @@ -0,0 +1,394 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include "x_hal_io.h" +#include "dramc_common.h" +#include "dramc_int_global.h" + +#if __ETT__ +#include <barriers.h> +#endif + +#ifdef DUMP_INIT_RG_LOG_TO_DE + U8 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0; +#endif + +static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_addr) +{ + U32 u4Offset = u4reg_addr & 0xffff; + U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf; + U32 u4BaseAddr = 0; + + if (u4reg_addr < Channel_A_DRAMC_NAO_BASE_VIRTUAL || + u4reg_addr >= MAX_BASE_VIRTUAL) + { + return u4reg_addr; + } + + if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register + { + if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR) + eShu = 0; + } + else if (u4RegType >= 6 && u4RegType <= 7)// ChA/B Dramc AO Register + { + if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR) + eShu = 0; + } + + if (eRank == RANK_1) + { + if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register + { + if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR && + u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR) + { + u4Offset += DRAMC_REG_AO_RANK_OFFSET; + } + else if (u4Offset >= DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR && + u4Offset <= DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR) + { + u4Offset += DRAMC_REG_AO_RANK_OFFSET; + } + } + else if (u4RegType >= 6 && u4RegType <= 7)// PhyA/B AO Register + { + // 0x60~0xE0 + if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR && + u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR) + { + u4Offset += DDRPHY_AO_RANK_OFFSET; + } + // 0x1E0~0x260 + else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR && + u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR) + { + u4Offset += DDRPHY_AO_RANK_OFFSET; + } + // 0x360~0x3E0 + else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR && + u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR) + { + u4Offset += DDRPHY_AO_RANK_OFFSET; + } + // 0x760~0x7E0 + else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR && + u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR) + { + u4Offset += DDRPHY_AO_RANK_OFFSET; + } + // 0x8E0~0x960 + else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR && + u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR) + { + u4Offset += DDRPHY_AO_RANK_OFFSET; + } + // 0xA60~0xAE0 + else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR && + u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR) + { + u4Offset += DDRPHY_AO_RANK_OFFSET; + } + // 0xBE0~0xC60 + else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR && + u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR) + { + u4Offset += DDRPHY_AO_RANK_OFFSET; + } + } + else if (u4RegType <= 1)// ChA/B Dramc NAO Register + { + if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) && + u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS)) + { + u4Offset += 0x100; + } + else if (u4Offset >= DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR && + u4Offset <= DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR) + { + u4Offset += DRAMC_REG_NAO_RANK_OFFSET; + } + } + else if (u4RegType >= 4 && u4RegType <= 5) // PhyA/B NAO Register + { + // PhyA/B NAO Register + if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START && + u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END) + { + u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET; + } + else if (u4Offset >= DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START && + u4Offset < DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END) + { + u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET; + } + else if (u4Offset >= DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START && + u4Offset < DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END) + { + u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET; + } + else if (u4Offset >= DDRPHY_NAO_RANK0_GATING_STATUS_START && + u4Offset < DDRPHY_NAO_RANK0_GATING_STATUS_END) + { + u4Offset += DDRPHY_NAO_GATING_STATUS_RK_OFFSET; + } + } + } + + switch (u4RegType) + { + case 0: + u4BaseAddr = Channel_A_DRAMC_NAO_BASE_ADDRESS; + break; + case 1: + u4BaseAddr = Channel_B_DRAMC_NAO_BASE_ADDRESS; + break; + case 2: + u4BaseAddr = Channel_A_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET); + break; + case 3: + u4BaseAddr = Channel_B_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET); + break; + case 4: + u4BaseAddr = Channel_A_DDRPHY_NAO_BASE_ADDRESS; + break; + case 5: + u4BaseAddr = Channel_B_DDRPHY_NAO_BASE_ADDRESS; + break; + case 6: + u4BaseAddr = Channel_A_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET); + break; + case 7: + u4BaseAddr = Channel_B_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET); + break; + case 8: + u4BaseAddr = Channel_A_DDRPHY_DPM_BASE_ADDRESS; + break; + } + + return (u4BaseAddr + u4Offset); +} + +inline U32 _u4Dram_Register_Read(U64 u4reg_addr) +{ + U32 u4reg_value; +#if (!__ETT__) && (FOR_DV_SIMULATION_USED == 0) + dsb(); +#endif + +#if QT_GUI_Tool + ucDramRegRead_1(u4reg_addr, &u4reg_value); +#elif (FOR_DV_SIMULATION_USED == 1) //DV + u4reg_value = register_read_c(u4reg_addr); +#else // real chip + u4reg_value = *((volatile unsigned int *)u4reg_addr); +#endif + + return u4reg_value; +} + +//------------------------------------------------------------------------- +/** ucDram_Register_Read + * DRAM register read (32-bit). + * @param u4reg_addr register address in 32-bit. + * @param pu4reg_value Pointer of register read value. + * @retval 0: OK, 1: FAIL + */ +//------------------------------------------------------------------------- +// This function need to be porting by BU requirement +U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr) +{ + u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr); + + return _u4Dram_Register_Read(u4reg_addr); +} + + +//------------------------------------------------------------------------- +/** ucDram_Register_Write + * DRAM register write (32-bit). + * @param u4reg_addr register address in 32-bit. + * @param u4reg_value register write value. + * @retval 0: OK, 1: FAIL + */ +//------------------------------------------------------------------------- + +#if REG_ACCESS_NAO_DGB +#if (fcFOR_CHIP_ID == fcCervino) +U8 Check_RG_Not_AO(U32 u4reg_addr) +{ + U8 RegNotAO = 0; + if ((u4reg_addr >= DRAMC_AO_BASE_ADDRESS) && (u4reg_addr <= DRAMC_REG_SHU4_DQSG_RETRY)) + { + } + else if ((u4reg_addr >= DRAMC_AO_BASE_ADDRESS + SHIFT_TO_CHB_ADDR) && (u4reg_addr <= DRAMC_REG_SHU4_DQSG_RETRY + SHIFT_TO_CHB_ADDR)) + { + } + else if ((u4reg_addr >= DDRPHY_AO_BASE_ADDR) && (u4reg_addr <= DDRPHY_RFU_0X1FCC)) + { + } + else if ((u4reg_addr >= DDRPHY_AO_BASE_ADDR + SHIFT_TO_CHB_ADDR) && (u4reg_addr <= DDRPHY_RFU_0X1FCC + SHIFT_TO_CHB_ADDR)) + { + } + else + { + RegNotAO = 1; + } + return RegNotAO; +} +#endif +#endif + +inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value) +{ +#if QT_GUI_Tool + ucDramRegWrite_1(u4reg_addr, u4reg_value); +#elif (FOR_DV_SIMULATION_USED == 1) //DV + register_write_c(u4reg_addr, u4reg_value); +#else // real chip + (*(volatile unsigned int *)u4reg_addr) = u4reg_value;//real chip + #if !defined(__MD32__) + dsb(); + #endif +#endif + +#ifdef DUMP_INIT_RG_LOG_TO_DE + if (gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag == 1) + { + mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",u4reg_addr,u4reg_value)); + gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0; + mcDELAY_MS(1); // to receive log for log + gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1; + } +#endif + +#if REG_ACCESS_PORTING_DGB + if (RegLogEnable) + { + mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG] ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value)); + } +#endif +} + +//This function need to be porting by BU requirement +void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value) +{ +#if __ETT__ + //CheckDramcWBR(u4reg_addr); +#endif + + //mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG] ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value)); + u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr); + + _ucDram_Register_Write(u4reg_addr, u4reg_value); +} + +void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32) +{ + U32 u4Val; + + reg32 = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, reg32); + + val32 &= msk32; + + u4Val = _u4Dram_Register_Read(reg32); + u4Val = ((u4Val & ~msk32) | val32); + _ucDram_Register_Write(reg32, u4Val); +} + + +void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32) +{ +U8 ii, u1AllCount; +U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM)); + +#if __ETT__ + if (GetDramcBroadcast()==DRAMC_BROADCAST_ON) + { + mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32)); + while (1); + } +#endif + + reg32 &= 0xffff; // remove channel information + + u1AllCount = CHANNEL_NUM; // for all dramC and PHY + + if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM + { + reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL; + if (u1AllCount > 1) + u1AllCount >>= 1; + } + else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO + { + reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL; + } + else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO + { + reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL; + } + else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO + { + reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL; + } + else // DramC NAO + { + reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL; + } + + for (ii = 0; ii < u1AllCount; ii++) + { + vIO32Write4B(reg32 + ((U32)ii << POS_BANK_NUM), val32); + } +} + +void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32) +{ + U32 u4Val, u4RegTmp; + U8 ii, u1AllCount; + U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM)); + +#if __ETT__ + if (GetDramcBroadcast()==DRAMC_BROADCAST_ON) + { + mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32)); + while (1); + } +#endif + + reg32 &= 0xffff; // remove channel information + + u1AllCount = CHANNEL_NUM; // for all dramC and PHY + + if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM + { + reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL; + if (u1AllCount > 1) + u1AllCount >>= 1; + } + else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO + { + reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL; + } + else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO + { + reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL; + } + else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO + { + reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL; + } + else // DramC NAO + { + reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL; + } + + for (ii = 0; ii < u1AllCount; ii++) + { + u4RegTmp = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, reg32 + ((U32)ii << POS_BANK_NUM)); + + u4Val = _u4Dram_Register_Read(u4RegTmp); + u4Val = ((u4Val & ~msk32) | val32); + _ucDram_Register_Write(u4RegTmp, u4Val); + } +} diff --git a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c new file mode 100644 index 0000000000..bb7f0acea5 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include "dramc_dv_init.h" + +void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank) +{ + switch(rank) + { + case 0 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKEFIXON)); break; + case 1 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKE1FIXON)); break; + default: mcSHOW_DBG_MSG(("ERROR: CKE FIX ON error. Unexpected Rank \n")); + } +} +//[SV] task LP4_MRS(bit [7:0] reg_addr, bit[7:0] reg_op, bit[1:0] rank); +static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank) +{ + U8 temp_MRS_RESPONSE ; + + mcSHOW_DBG_MSG(("[LP4_DRAM_INIT_MRS] RK:%1d-MA:%2d-OP:0x%2x @Channle:%1d\n",rank,reg_addr,reg_op,vGetPHY2ChannelMapping(p))); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), P_Fld(rank , SWCMD_CTRL0_MRSRK ) \ + | P_Fld(reg_addr, SWCMD_CTRL0_MRSMA ) \ + | P_Fld(reg_op , SWCMD_CTRL0_MRSOP )); + + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), P_Fld(1, SWCMD_EN_MRWEN)); + + temp_MRS_RESPONSE = 0 ; + do + { + temp_MRS_RESPONSE = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) ; + } while ( temp_MRS_RESPONSE != 1 ); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), P_Fld(0, SWCMD_EN_MRWEN)); +} + + +static void LP4_FSP_WR_or_OP (DRAMC_CTX_T *p, U8 FSP_WR, U8 FSP_OP, U8 rank) +{ + U8 MR13 = 0; + MR13 = ((FSP_OP & 1) << 7) | ((FSP_WR & 1) << 6) /*| ((LP4_DMI & 1) << 5)*/ | (1 << 4)/*[RRO] for MR4 refresh rate*/; + LP4_MRS(p, 13, MR13, rank); +} + +//================================== +//uesage(constraint): DBI = 1 for FSPOP=1 if DBI=0 then FSP_OP =0 +//================================== +static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 rank) +{ + U8 MR1; + U8 MR2; + U8 MR3; + U8 MR51; + U8 MR11; + U8 MR12; + U8 MR14; + + //default value for LP4 DRAM CONFIG + U8 nWR =5; + U8 WR_LEV =0; + U8 PDDS =5; + U8 PPRP =0; + U8 PU_CAL =0; + U8 WLS =0; + + //Notice: DBI default = 0 + + //field & configuration adaption + MR1 = ((tr->RPST & 1)<<7) | ((nWR & 7)<<4) | ((tr->RD_PRE & 1)<<3) | ((tr->WR_PRE & 1)<<2) | ((tr->BL & 3)<<0); + MR2 = ((WR_LEV & 1)<<7) | ((WLS & 1)<<6) | ((tr->MR_WL & 7)<<3) | ((tr->MR_RL & 7)<<0); + MR3 = ((tr->DBI_WR & 1)<<7) | ((tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); + MR51= ((tr->LP4Y_EN & 1)<<3) | ((tr->LP4Y_EN & 1)<<2) | ((tr->LP4Y_EN & 1)<<1); + if(tr->WORK_FSP == 0) + { + MR11 = 0x0; + MR14 = 0x5d; + } + else + { + MR11 = 0x04; + MR14 = 0x18; + } + MR12= 0x5d; + #if FSP1_CLKCA_TERM + if(p->dram_fsp == FSP_1) + MR12 = 0x20; + #endif + //temp workaround for global variable of MR + u1MR02Value[tr->WORK_FSP] = MR2; + u1MR03Value[tr->WORK_FSP] = MR3; + #if ENABLE_LP4_ZQ_CAL + DramcZQCalibration(p, rank); //ZQ calobration should be done before CBT calibration by switching to low frequency + #endif + + mcSHOW_DBG_MSG(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d >>>>>>\n",vGetPHY2ChannelMapping(p),rank)); + + //first FSP + if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 0, 1, rank);} + else {LP4_FSP_WR_or_OP(p, 1, 0, rank);} + + mcDELAY_XNS(15); //TCKFSPE + + LP4_MRS(p, 1, MR1 , rank); + LP4_MRS(p, 2, MR2 , rank); + LP4_MRS(p, 3, MR3 , rank); + LP4_MRS(p, 11, MR11 , rank); + LP4_MRS(p, 12, MR12 , rank); + LP4_MRS(p, 14, MR14 , rank); + if(tr->LP4Y_EN == 1) { LP4_MRS(p, 51, MR51, rank); } + + mcDELAY_XNS(15); //TCKFSPX + + //2nd FSP + if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 1, 0, rank);} + else {LP4_FSP_WR_or_OP(p, 0, 1, rank);} + + mcDELAY_XNS(15); //TCKFSPE + + LP4_MRS(p, 1, MR1 , rank); + LP4_MRS(p, 2, MR2 , rank); + //reverse the DBI + MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); + LP4_MRS(p, 3, MR3 , rank); + LP4_MRS(p, 11, MR11 , rank); + LP4_MRS(p, 12, MR12 , rank); + LP4_MRS(p, 14, MR14 , rank); + + LP4_FSP_WR_or_OP(p, tr->WORK_FSP, tr->WORK_FSP, rank); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y )); + + mcSHOW_DBG_MSG(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d <<<<<<\n",vGetPHY2ChannelMapping(p),rank)); +} + +void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN) +{ + mcSHOW_DBG_MSG(("============ LP4 DIFF to SE enter ============\n")); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( LP4Y_EN , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \ + | P_Fld( LP4Y_EN , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( LP4Y_EN , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0 ) \ + | P_Fld( LP4Y_EN , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld( LP4Y_EN , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \ + | P_Fld( LP4Y_EN , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD0) , P_Fld( 0 , SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ0) , P_Fld( 0 , SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ0) , P_Fld( 0 , SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK )); //@Darren, debugging for DFS stress fail + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld( LP4Y_EN , SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld( LP4Y_EN , SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 )); + +#if 1//ENABLE_LP4Y_DFS // @Darren, need confirm + // for strong pull low and normal mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y )); +#else + // for weak pull low mode only + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y )); +#endif + mcSHOW_DBG_MSG(("============ LP4 DIFF to SE exit ============\n")); +} + +void LP4_DRAM_INIT(DRAMC_CTX_T *p) +{ + U8 RANK; + + +#if SA_CONFIG_EN && DV_SIMULATION_DFS// @Darren, temp workaround + DramcPowerOnSequence(p); +#endif + + + mcDELAY_XNS(200); //tINIT3 = 2ms for DV fastup to 200ns + + for(RANK=0;RANK<2;RANK++) + { + CKE_FIX_ON(p,1,RANK); + mcDELAY_XNS(400); //tINIT5 fastup to 400ns + + //step4 moderegister setting + lp4_dram_init_single_rank(p,DV_p.lp4_init,RANK); + CKE_FIX_ON(p,0,RANK); + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), P_Fld(0, REFCTRL0_REFDIS)); //TODO enable refresh +} diff --git a/src/vendorcode/mediatek/mt8192/dramc/Makefile.inc b/src/vendorcode/mediatek/mt8192/dramc/Makefile.inc new file mode 100644 index 0000000000..1c4870a860 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/Makefile.inc @@ -0,0 +1,21 @@ +romstage-y += emi.c + +romstage-y += ANA_init_config.c +romstage-y += DIG_NONSHUF_config.c +romstage-y += DIG_SHUF_config.c +romstage-y += dramc_actiming.c +romstage-y += dramc_dv_freq_related.c +romstage-y += dramc_dvfs.c +romstage-y += dramc_lowpower.c +romstage-y += DRAM_config_collctioin.c +romstage-y += dramc_pi_basic_api.c +romstage-y += dramc_pi_calibration_api.c +romstage-y += dramc_pi_main.c +romstage-y += DRAMC_SUBSYS_config.c +romstage-y += dramc_top.c +romstage-y += dramc_tracking.c +romstage-y += dramc_utility.c +romstage-y += Hal_io.c +romstage-y += LP4_dram_init.c + +ramstage-y += emi.c diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c new file mode 100644 index 0000000000..a4f1b2f285 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c @@ -0,0 +1,4730 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//----------------------------------------------------------------------------- +// Include files +//----------------------------------------------------------------------------- +#include "dramc_common.h" +#include "x_hal_io.h" +#include "dramc_actiming.h" +#include "dramc_int_global.h" + +//----------------------------------------------------------------------------- +// Global variables +//----------------------------------------------------------------------------- + +//------------------------------------------------------------------------- +/** u1GetACTimingIdx() + * Retrieve internal ACTimingTbl's index according to dram type, freqGroup, Read DBI status + * @param p Pointer of context created by DramcCtxCreate. + * @retval u1TimingIdx Return ACTimingTbl entry's index + */ +//------------------------------------------------------------------------- +static U8 u1GetACTimingIdx(DRAMC_CTX_T *p) +{ + U8 u1TimingIdx = 0xff, u1TmpIdx; + U8 u1TmpDramType = p->dram_type; + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + u1TmpDramType = TYPE_LPDDR5; + } + else +#endif + { + // LP4/LP4P/LP4X use same table + if (u1TmpDramType == TYPE_LPDDR4X || u1TmpDramType == TYPE_LPDDR4P) + u1TmpDramType = TYPE_LPDDR4; + } + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP5; u1TmpIdx++) + { + if ((ACTimingTbl_LP5[u1TmpIdx].dramType == u1TmpDramType) && + /* p->frequency may not be in ACTimingTable, use p->freqGroup */ + (ACTimingTbl_LP5[u1TmpIdx].freq == p->freqGroup) && + (ACTimingTbl_LP5[u1TmpIdx].readDBI == p->DBI_R_onoff[p->dram_fsp]) && + (ACTimingTbl_LP5[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && // Darren for LP4 1:4 and 1:8 mode + (ACTimingTbl_LP5[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) //LP4 byte/mixed mode dram both use byte mode ACTiming + ) + { + u1TimingIdx = u1TmpIdx; + mcSHOW_DBG_MSG(("match AC timing %d\n", u1TimingIdx)); + mcDUMP_REG_MSG(("match AC timing %d\n", u1TimingIdx)); + break; + } + } + } + else +#endif + { + for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP4; u1TmpIdx++) + { + if ((ACTimingTbl_LP4[u1TmpIdx].dramType == u1TmpDramType) && + /* p->frequency may not be in ACTimingTable, use p->freqGroup */ + (ACTimingTbl_LP4[u1TmpIdx].freq == p->freqGroup) && + (ACTimingTbl_LP4[u1TmpIdx].readDBI == p->DBI_R_onoff[p->dram_fsp]) && + (ACTimingTbl_LP4[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && // Darren for LP4 1:4 and 1:8 mode + (ACTimingTbl_LP4[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) //LP4 byte/mixed mode dram both use byte mode ACTiming + ) + { + u1TimingIdx = u1TmpIdx; + mcSHOW_DBG_MSG(("match AC timing %d\n", u1TimingIdx)); + mcDUMP_REG_MSG(("match AC timing %d\n", u1TimingIdx)); + mcSHOW_DBG_MSG(("dramType %d, freq %d, readDBI %d, DivMode %d, cbtMode %d\n", u1TmpDramType, p->freqGroup, p->DBI_R_onoff[p->dram_fsp], vGet_Div_Mode(p), vGet_Dram_CBT_Mode(p))); + break; + } + } + } + + return u1TimingIdx; +} + +//------------------------------------------------------------------------- +/** UpdateACTimingReg() + * ACTiming related register field update + * @param p Pointer of context created by DramcCtxCreate. + * @param ACTbl Pointer to correct ACTiming table struct + * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL + */ +//------------------------------------------------------------------------- +#if __LP5_COMBO__ +DRAM_STATUS_T DdrUpdateACTimingReg_LP5(DRAMC_CTX_T *p, const ACTime_T_LP5 *ACTbl) +{ + ACTime_T_LP5 ACTblFinal; + U8 backup_rank = p->rank; + DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; //Variable used in step 1 (decide to use odt on or off ACTiming) + // ACTiming regs that have ODT on/off values -> declare variables to save the wanted value + // -> Used to retrieve correct SHU_ACTIM2_TR2W value and write into final register field +#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + U8 u1RANKINCTL = 0; +#endif + U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; //Used to store tmp ACTiming values + +#if SAMSUNG_LP4_NWR_WORKAROUND + U8 u1TWTR = 0, u1TWTR_05T = 0, u1TWTR_TMP = 0; +#endif + // ACTiming regs that aren't currently in ACTime_T struct + U8 u1TREFBW = 0; //REFBW_FR (tREFBW) for LP3, REFBW_FR=0 & TREFBWIG=1 (by CF) + U8 u1TFAW_05T=0, u1TRRD_05T=0; + U16 u2XRTWTW = 0, u2XTRTRT = 0, u2XRTW2R = 0, u2XRTR2W = 0, u2TFAW = 0; + U16 u2TRTW=0, u2TRTW_05T=0, u2TMRR2W=0, u2TRRD=0; + +#if XRTRTR_NEW_CROSS_RK_MODE + U16 u2PHSINCTL = 0; +#endif + + U32 u4RankINCTL_ROOT; + + if(ACTbl == NULL) + return DRAM_FAIL; + ACTblFinal = *ACTbl; + + // ----Step 1: Perform ACTiming table adjustments according to different usage/scenarios-------------------------- +#if ENABLE_TX_WDQS + r2w_odt_onoff = ODT_ON; +#else + r2w_odt_onoff = p->odt_onoff; +#endif + + // ACTimings that have different values for odt on/off, retrieve the correct one and store in local variable + if (r2w_odt_onoff == ODT_ON) //odt_on + { + u2TRTW = ACTblFinal.tr2w_odt_on; + u2TRTW_05T = ACTblFinal.tr2w_odt_on_05T; + u2XRTW2R = ACTblFinal.xrtw2r_odt_on_otf_off; + u2XRTR2W = ACTblFinal.xrtr2w_odt_on; + } + else //odt_off + { + u2TRTW = ACTblFinal.tr2w_odt_off; + u2TRTW_05T = ACTblFinal.tr2w_odt_off_05T; + u2XRTW2R = ACTblFinal.xrtw2r_odt_off_otf_off; + u2XRTR2W = ACTblFinal.xrtr2w_odt_off; + } + + // Override the above tRTW & tRTW_05T selection for Hynix LPDDR4P dram (always use odt_on's value for tRTW) + if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) //!SUPPORT_HYNIX_RX_DQS_WEAK_PULL (temp solution, need to discuss with SY) + { + u2TRTW = ACTblFinal.tr2w_odt_on; + u2TRTW_05T = ACTblFinal.tr2w_odt_on_05T; + } + + if (r2w_odt_onoff == ODT_ON) + { + u2XTRTRT = ACTblFinal.xrtr2r_odt_on; + u2XRTWTW = ACTblFinal.xrtw2w_odt_on; + } + else + { + u2XTRTRT = ACTblFinal.xrtr2r_odt_off; + u2XRTWTW = ACTblFinal.xrtw2w_odt_off; + } + +#if ENABLE_RODT_TRACKING_SAVE_MCK + // for rodt tracking save 1 MCK and rodt tracking enable or not(RODTENSTB_TRACK_EN) + u1ODT_ON = p->odt_onoff; + u1RODT_TRACK = ENABLE_RODT_TRACKING; + u1ROEN = u1WDQS_ON | u1ODT_ON; + u1ModeSel = u1RODT_TRACK & u1ROEN; + + // when WDQS on and RODT Track define open and un-term, RODT_TRACKING_SAVEING_MCK = 1 for the future setting + // Maybe "Save 1 MCK" will be set after Vins_on project, but Bian_co & Vins_on can not.(different with performance team) + //if (u1RODT_TRACK && (u1ROEN==1)) + // RODT_TRACKING_SAVEING_MCK = 1; +#endif + +#if (ENABLE_RODT_TRACKING || defined(XRTR2W_PERFORM_ENHANCE_RODTEN)) + /* yr: same code + // set to 0, let TRTW & XRTR2W setting values are the smae with DV-sim's value that DE provided + if (r2w_odt_onoff == ODT_ON) RODT_TRACKING_SAVEING_MCK = 0; //RODT_TRACKING eanble can save r2w 1 MCK + else RODT_TRACKING_SAVEING_MCK = 0; + */ + RODT_TRACKING_SAVEING_MCK = 0; +#endif + + // Update values that are used by RODT_TRACKING_SAVEING_MCK + u2TRTW = u2TRTW - RODT_TRACKING_SAVEING_MCK; + u2XRTR2W = u2XRTR2W - RODT_TRACKING_SAVEING_MCK; + +#if SAMSUNG_LP4_NWR_WORKAROUND + // If nWR is fixed to 30 for all freqs, tWTR@800Mhz should add 2tCK gap, allowing sufficient Samsung DRAM internal IO precharge time + if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency == 800)) //LP4X, Samsung, DDR1600 + { + u1TWTR_TMP = (ACTblFinal.twtr * 4 - ACTblFinal.twtr_05T * 2) + 2; //Convert TWTR to tCK, and add 2tCK + if ((u1TWTR_TMP % 4) == 0) //TWTR can be transferred to TWTR directly + { + u1TWTR = u1TWTR_TMP >> 2; + u1TWTR_05T = 0; + } + else //Can't be transfered to TWTR directly + { + u1TWTR = (u1TWTR_TMP + 2) >> 2; //Add 2 tCK and set TWTR value (Then minus 2tCK using 05T) + u1TWTR_05T = 1; //05T means minus 2tCK + } + + ACTblFinal.twtr = u1TWTR; + ACTblFinal.twtr_05T = u1TWTR_05T; + } +#endif + +//DATLAT related +if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + u1DATLAT_DSEL = ACTblFinal.datlat; +else + u1DATLAT_DSEL = ACTblFinal.datlat - 1; + +#if TX_OE_EXTEND + u2XRTWTW += 1; + u2XRTW2R += 1; +#endif + +#if 0//(!CMD_CKE_WORKAROUND_FIX) + U8 u1Txp = 0, u1Txp0p5 = 0; + + if (((p->frequency <= 1866) && (p->frequency >= 1600)) || ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400))) + { + u1Txp = 1; + } + else if ((p->frequency == 2133) || ((vGet_Div_Mode(p) == DIV4_MODE) && ((p->frequency <= 800) || (p->frequency >= 600)))) + { + u1Txp = 2; + } + + if ((p->frequency == 1866) || ((p->frequency <= 1333) && (p->frequency >= 1200))) + { + u1Txp0p5 = 1; + } + + ACTblFinal.txp = u1Txp; + ACTblFinal.txp_05T = u1Txp0p5; + ACTblFinal.ckelckcnt = 4; + ACTblFinal.earlyckecnt = 0; + ACTblFinal.ckeprd -= 1; +#endif + + // ----Step 2: Perform register writes for entries in ACTblFinal struct & ACTiming excel file (all actiming adjustments should be done in Step 1)------- + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM1, P_Fld(ACTblFinal.tras, SHU_ACTIM1_TRAS) + | P_Fld(ACTblFinal.trp, SHU_ACTIM1_TRP) + | P_Fld(ACTblFinal.trpab, SHU_ACTIM1_TRPAB) + | P_Fld(ACTblFinal.tmrwckel, SHU_ACTIM1_TMRWCKEL) + | P_Fld(ACTblFinal.trc, SHU_ACTIM1_TRC)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM3, P_Fld(ACTblFinal.trfc, SHU_ACTIM3_TRFC) + | P_Fld(ACTblFinal.tr2mrr, SHU_ACTIM3_TR2MRR) + | P_Fld(ACTblFinal.trfcpb, SHU_ACTIM3_TRFCPB)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM2, P_Fld(ACTblFinal.txp, SHU_ACTIM2_TXP) + | P_Fld(ACTblFinal.tmrri, SHU_ACTIM2_TMRRI) + | P_Fld(ACTblFinal.tfaw, SHU_ACTIM2_TFAW) + | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) // Value has odt_on/off difference, use local variable u1TRTW + | P_Fld(ACTblFinal.trtp, SHU_ACTIM2_TRTP)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM0, P_Fld(ACTblFinal.trcd, SHU_ACTIM0_TRCD) + | P_Fld(ACTblFinal.twr, SHU_ACTIM0_TWR) + | P_Fld(ACTblFinal.trrd, SHU_ACTIM0_TRRD)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM5, P_Fld(ACTblFinal.tpbr2pbr, SHU_ACTIM5_TPBR2PBR) + | P_Fld(ACTblFinal.twtpd, SHU_ACTIM5_TWTPD) + | P_Fld(ACTblFinal.tpbr2act, SHU_ACTIM5_TPBR2ACT)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM6, P_Fld(ACTblFinal.tr2mrw, SHU_ACTIM6_TR2MRW) + | P_Fld(ACTblFinal.tw2mrw, SHU_ACTIM6_TW2MRW) + | P_Fld(ACTblFinal.tmrd, SHU_ACTIM6_TMRD) + | P_Fld(ACTblFinal.zqlat2, SHU_ACTIM6_TZQLAT2) + | P_Fld(ACTblFinal.tmrw, SHU_ACTIM6_TMRW)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM4, P_Fld(ACTblFinal.tmrr2mrw, SHU_ACTIM4_TMRR2MRW) + | P_Fld(ACTblFinal.tmrr2w, SHU_ACTIM4_TMRR2W) + | P_Fld(ACTblFinal.tzqcs, SHU_ACTIM4_TZQCS) + | P_Fld(ACTblFinal.txrefcnt, SHU_ACTIM4_TXREFCNT)); + + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CKECTRL, ACTblFinal.ckeprd, SHU_CKECTRL_TCKEPRD); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(u2XRTWTW, SHU_ACTIM_XRT_XRTW2W) + | P_Fld(u2XRTW2R, SHU_ACTIM_XRT_XRTW2R) + | P_Fld(u2XRTR2W, SHU_ACTIM_XRT_XRTR2W) + | P_Fld(u2XTRTRT, SHU_ACTIM_XRT_XRTR2R)); + + vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT); +// vIO32WriteFldMulti_All(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT) +// | P_Fld(ACTblFinal.hwset_vrcg_op, SHU_HWSET_VRCG_HWSET_VRCG_OP)); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR2, ACTblFinal.hwset_mr2_op, SHU_HWSET_MR2_HWSET_MR2_OP); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR13, ACTblFinal.hwset_mr13_op, SHU_HWSET_MR13_HWSET_MR13_OP); + + // AC timing 0.5T + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(ACTblFinal.twtr_05T, SHU_AC_TIME_05T_TWTR_M05T) + | P_Fld(ACTblFinal.twtr_l_05T, SHU_AC_TIME_05T_BGTWTR_M05T) + | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) // Value has odt_on/off difference, use local variable u1TRTW + | P_Fld(ACTblFinal.twtpd_05T, SHU_AC_TIME_05T_TWTPD_M05T) + | P_Fld(ACTblFinal.tfaw_05T, SHU_AC_TIME_05T_TFAW_05T) + | P_Fld(ACTblFinal.trrd_05T, SHU_AC_TIME_05T_TRRD_05T) + | P_Fld(ACTblFinal.twr_05T, SHU_AC_TIME_05T_TWR_M05T) + | P_Fld(ACTblFinal.tras_05T, SHU_AC_TIME_05T_TRAS_05T) + | P_Fld(ACTblFinal.trpab_05T, SHU_AC_TIME_05T_TRPAB_05T) + | P_Fld(ACTblFinal.trp_05T, SHU_AC_TIME_05T_TRP_05T) + | P_Fld(ACTblFinal.trcd_05T, SHU_AC_TIME_05T_TRCD_05T) + | P_Fld(ACTblFinal.trtp_05T, SHU_AC_TIME_05T_TRTP_05T) + | P_Fld(ACTblFinal.txp_05T, SHU_AC_TIME_05T_TXP_05T) + | P_Fld(ACTblFinal.trfc_05T, SHU_AC_TIME_05T_TRFC_05T) + | P_Fld(ACTblFinal.trfcpb_05T, SHU_AC_TIME_05T_TRFCPB_05T) + | P_Fld(ACTblFinal.tpbr2pbr_05T, SHU_AC_TIME_05T_TPBR2PBR_05T) + | P_Fld(ACTblFinal.tpbr2act_05T, SHU_AC_TIME_05T_TPBR2ACT_05T) + | P_Fld(ACTblFinal.tr2mrw_05T, SHU_AC_TIME_05T_TR2MRW_05T) + | P_Fld(ACTblFinal.tw2mrw_05T, SHU_AC_TIME_05T_TW2MRW_05T) + | P_Fld(ACTblFinal.tmrr2mrw_05T, SHU_AC_TIME_05T_TMRR2MRW_05T) + | P_Fld(ACTblFinal.tmrw_05T, SHU_AC_TIME_05T_TMRW_05T) + | P_Fld(ACTblFinal.tmrd_05T, SHU_AC_TIME_05T_TMRD_05T) + | P_Fld(ACTblFinal.tmrwckel_05T, SHU_AC_TIME_05T_TMRWCKEL_05T) + | P_Fld(ACTblFinal.tmrri_05T, SHU_AC_TIME_05T_TMRRI_05T) + | P_Fld(ACTblFinal.trc_05T, SHU_AC_TIME_05T_TRC_05T)); + + { + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr_l, SHU_ACTIM0_TWTR_L); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM7, P_Fld(ACTblFinal.tcsh_cscal, SHU_ACTIM7_TCSH_CSCAL) + | P_Fld(ACTblFinal.tcacsh, SHU_ACTIM7_TCACSH)); + } + { + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr, SHU_ACTIM0_TWTR); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_CKECTRL, P_Fld(ACTblFinal.tpde, SHU_CKECTRL_TPDE) + | P_Fld(ACTblFinal.tpdx, SHU_CKECTRL_TPDX) + | P_Fld(ACTblFinal.tpde_05T, SHU_CKECTRL_TPDE_05T) + | P_Fld(ACTblFinal.tpdx_05T, SHU_CKECTRL_TPDX_05T)); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_WCKCTRL, P_Fld(ACTblFinal.wckrdoff, SHU_WCKCTRL_WCKRDOFF) + | P_Fld(ACTblFinal.wckrdoff_05T, SHU_WCKCTRL_WCKRDOFF_05T) + | P_Fld(ACTblFinal.wckwroff, SHU_WCKCTRL_WCKWROFF) + | P_Fld(ACTblFinal.wckwroff_05T, SHU_WCKCTRL_WCKWROFF_05T)); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM5, ACTblFinal.trtpd, SHU_ACTIM5_TR2PD); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, ACTblFinal.trtpd_05T, SHU_AC_TIME_05T_TR2PD_05T); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_LP5_CMD, ACTblFinal.tcsh, SHU_LP5_CMD_TCSH); + } + +#if AC_TIMING_DERATE_ENABLE + if (u1IsLP4Family(p->dram_type)) + { + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING0, P_Fld(ACTblFinal.trcd_derate, SHU_AC_DERATING0_TRCD_DERATE) + | P_Fld(ACTblFinal.trrd_derate, SHU_AC_DERATING0_TRRD_DERATE)); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING1, P_Fld(ACTblFinal.trc_derate, SHU_AC_DERATING1_TRC_DERATE) + | P_Fld(ACTblFinal.tras_derate, SHU_AC_DERATING1_TRAS_DERATE) + | P_Fld(ACTblFinal.trp_derate, SHU_AC_DERATING1_TRP_DERATE) + | P_Fld(ACTblFinal.trpab_derate, SHU_AC_DERATING1_TRPAB_DERATE)); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(ACTblFinal.trrd_05T_derate, SHU_AC_DERATING_05T_TRRD_05T_DERATE) + | P_Fld(ACTblFinal.tras_05T_derate, SHU_AC_DERATING_05T_TRAS_05T_DERATE) + | P_Fld(ACTblFinal.trpab_05T_derate, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) + | P_Fld(ACTblFinal.trp_05T_derate, SHU_AC_DERATING_05T_TRP_05T_DERATE) + | P_Fld(ACTblFinal.trcd_05T_derate, SHU_AC_DERATING_05T_TRCD_05T_DERATE) + | P_Fld(ACTblFinal.trc_05T_derate, SHU_AC_DERATING_05T_TRC_05T_DERATE)); + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0xc0, REFCTRL3_REF_DERATING_EN); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); //enable derating for AC timing + } +#endif + + // DQSINCTL related + vSetRank(p, RANK_0); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 0 DQSINCTL + vSetRank(p, RANK_1); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 1 DQSINCTL + vSetRank(p, backup_rank); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL, ACTblFinal.dqsinctl, MISC_SHU_ODTCTRL_RODT_LAT); + + if (ACTblFinal.dqsinctl >= 2) + { + u4RankINCTL_ROOT = ACTblFinal.dqsinctl - 2; + } + else + { + mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n")); + u4RankINCTL_ROOT = 0; + } + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(ACTblFinal.dqsinctl, MISC_SHU_RANKCTL_RANKINCTL_PHY) + | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) + | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL)); + +#if XRTRTR_NEW_CROSS_RK_MODE + u2PHSINCTL = (ACTblFinal.dqsinctl == 0)? 0: (ACTblFinal.dqsinctl - 1); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL); +#endif + + // DATLAT related, tREFBW + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(ACTblFinal.datlat, MISC_SHU_RDAT_DATLAT) + | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL) + | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIMING_CONF, u1TREFBW, SHU_ACTIMING_CONF_REFBW_FR); + + // ----Step 3: Perform register writes/calculation for other regs (That aren't in ACTblFinal struct)------------------------------------------------ +#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + //Wei-Jen: Ininital setting values are the same, RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1 + //XRTR2R setting will be updated in RxdqsGatingPostProcess + u1RANKINCTL = u4IO32ReadFldAlign(DDRPHY_REG_MISC_SHU_RANKCTL, MISC_SHU_RANKCTL_RANKINCTL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RANKCTL, u1RANKINCTL, MISC_SHU_RANKCTL_RANKINCTL_RXDLY); +#endif + + //Update releated RG of XRTW2W + if (p->frequency <= 800) + { + if (vGet_Div_Mode(p) == DIV4_MODE) + { + u1ROOT = 0; u1TXRANKINCTL = 1; u1TXDLY = 2; + } + else + { + u1ROOT = 0; u1TXRANKINCTL = 0; u1TXDLY = 1; + } + } + else + { + u1ROOT = (p->frequency == 1866)? 1: 0; + u1TXRANKINCTL = 1; u1TXDLY = 2; + } + #if TX_OE_EXTEND + if (p->frequency >= 1333) + { + u1TXRANKINCTL += 1; + u1TXDLY += 1; + } + #endif + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(u1ROOT, SHU_TX_RANKCTL_TXRANKINCTL_ROOT) + | P_Fld(u1TXRANKINCTL, SHU_TX_RANKCTL_TXRANKINCTL) + | P_Fld(u1TXDLY, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY)); + + return DRAM_OK; +} +#endif + +#if ENABLE_WDQS_MODE_2 +static void WDQSMode2AcTimingEnlarge(DRAMC_CTX_T *p, U16 *u2_XRTW2W, U16 *u2_XRTR2W, U16 *u2_XRTW2R, U16 *u2_TRTW) +{ + U16 u2XRTW2W_enlarge = 0, u2XRTR2W_enlarge = 0; + U16 u2XRTW2R_enlarge = 0, u2TRTW_enlarge = 0; + + switch (p->frequency) + { + case 1866: + u2XRTW2W_enlarge = 3; + break; + case 1600: + u2XRTW2W_enlarge = 2; + u2XRTR2W_enlarge = 1; + break; + case 1200: + u2XRTW2W_enlarge = 2; + if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) + u2XRTR2W_enlarge = 1; + break; + case 933: + u2XRTW2W_enlarge = 1; + if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE) + u2XRTR2W_enlarge = 1; + break; + case 800: + u2XRTW2W_enlarge = 2; + u2TRTW_enlarge = 1; + if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE) + u2XRTW2R_enlarge = 1; + break; + case 600: + u2XRTW2W_enlarge = 2; + u2TRTW_enlarge = 1; + if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE) + u2XRTW2R_enlarge = 1; + break; + case 400: + u2XRTW2W_enlarge = 3; + u2TRTW_enlarge = 2; + u2XRTR2W_enlarge = 1; + break; + default: + mcSHOW_ERR_MSG(("[WDQSMode2AcTimingEnlarge] frequency err!\n")); + #if __ETT__ + while (1); + #endif + } + + *u2_XRTW2W += u2XRTW2W_enlarge; + *u2_XRTR2W += u2XRTR2W_enlarge; + *u2_XRTW2R += u2XRTW2R_enlarge; + *u2_TRTW += u2TRTW_enlarge; +} +#endif + +static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 *ACTbl) +{ + ACTime_T_LP4 ACTblFinal; + U8 backup_rank = p->rank; + DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; //Variable used in step 1 (decide to use odt on or off ACTiming) + // ACTiming regs that have ODT on/off values -> declare variables to save the wanted value + // -> Used to retrieve correct SHU_ACTIM2_TR2W value and write into final register field +#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + U8 u1RANKINCTL = 0; +#endif + U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; //Used to store tmp ACTiming values + +#if SAMSUNG_LP4_NWR_WORKAROUND + U8 u1TWTR = 0, u1TWTR_05T = 0, u1TWTR_TMP = 0; +#endif + // ACTiming regs that aren't currently in ACTime_T struct + U8 u1TREFBW = 0; //REFBW_FR (tREFBW) for LP3, REFBW_FR=0 & TREFBWIG=1 (by CF) + U8 u1TFAW_05T=0, u1TRRD_05T=0; + U16 u2XRTWTW = 0, u2XTRTRT = 0, u2XRTW2R = 0, u2XRTR2W = 0, u2TFAW = 0; + U16 u2TRTW=0, u2TRTW_05T=0, u2TMRR2W=0, u2TRRD=0; + +#if XRTRTR_NEW_CROSS_RK_MODE + U16 u2PHSINCTL = 0; +#endif + + U32 u4RankINCTL_ROOT; + + if(ACTbl == NULL) + return DRAM_FAIL; + ACTblFinal = *ACTbl; + + // ----Step 1: Perform ACTiming table adjustments according to different usage/scenarios-------------------------- +#if ENABLE_TX_WDQS + r2w_odt_onoff = ODT_ON; +#else + r2w_odt_onoff = p->odt_onoff; +#endif + // ACTimings that have different values for odt on/off, retrieve the correct one and store in local variable + if (r2w_odt_onoff == ODT_ON) //odt_on + { + u2TRTW = ACTblFinal.trtw_odt_on; + u2TRTW_05T = ACTblFinal.trtw_odt_on_05T; + u2XRTW2R = ACTblFinal.xrtw2r_odt_on; + u2XRTR2W = ACTblFinal.xrtr2w_odt_on; + } + else //odt_off + { + u2TRTW = ACTblFinal.trtw_odt_off; + u2TRTW_05T = ACTblFinal.trtw_odt_off_05T; + u2XRTW2R = ACTblFinal.xrtw2r_odt_off; + u2XRTR2W = ACTblFinal.xrtr2w_odt_off; + } + + // Override the above tRTW & tRTW_05T selection for Hynix LPDDR4P dram (always use odt_on's value for tRTW) + if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) //!SUPPORT_HYNIX_RX_DQS_WEAK_PULL (temp solution, need to discuss with SY) + { + u2TRTW = ACTblFinal.trtw_odt_on; + u2TRTW_05T = ACTblFinal.trtw_odt_on_05T; + } + + { + u2TFAW = ACTblFinal.tfaw_4266; + u1TFAW_05T = ACTblFinal.tfaw_4266_05T; + u2TRRD = ACTblFinal.trrd_4266; + u1TRRD_05T = ACTblFinal.trrd_4266_05T; + #if XRTRTR_NEW_CROSS_RK_MODE + u2XTRTRT = ACTblFinal.xrtr2r_new_mode; + #else + u2XTRTRT = ACTblFinal.xrtr2r_old_mode; + #endif + + #if XRTWTW_NEW_CROSS_RK_MODE + u2XRTWTW = ACTblFinal.xrtw2w_new_mode; + #else + u2XRTWTW = ACTblFinal.xrtw2w_old_mode; + #endif + + #if ENABLE_WDQS_MODE_2 + WDQSMode2AcTimingEnlarge(p, &u2XRTWTW, &u2XRTR2W, &u2XRTW2R, &u2TRTW); + #endif + + if (r2w_odt_onoff == ODT_ON) + u2TMRR2W = ACTblFinal.tmrr2w_odt_on; + else + u2TMRR2W = ACTblFinal.tmrr2w_odt_off; + } + +#if ENABLE_RODT_TRACKING_SAVE_MCK + // for rodt tracking save 1 MCK and rodt tracking enable or not(RODTENSTB_TRACK_EN) + u1ODT_ON = p->odt_onoff; + u1RODT_TRACK = ENABLE_RODT_TRACKING; + u1ROEN = u1WDQS_ON | u1ODT_ON; + u1ModeSel = u1RODT_TRACK & u1ROEN; + + // when WDQS on and RODT Track define open and un-term, RODT_TRACKING_SAVEING_MCK = 1 for the future setting + // Maybe "Save 1 MCK" will be set after Vins_on project, but Bian_co & Vins_on can not.(different with performance team) + //if (u1RODT_TRACK && (u1ROEN==1)) + // RODT_TRACKING_SAVEING_MCK = 1; +#endif + +#if (ENABLE_RODT_TRACKING || defined(XRTR2W_PERFORM_ENHANCE_RODTEN)) + /* yr: same code + // set to 0, let TRTW & XRTR2W setting values are the smae with DV-sim's value that DE provided + if (r2w_odt_onoff == ODT_ON) RODT_TRACKING_SAVEING_MCK = 0; //RODT_TRACKING eanble can save r2w 1 MCK + else RODT_TRACKING_SAVEING_MCK = 0; + */ + RODT_TRACKING_SAVEING_MCK = 0; +#endif + + // Update values that are used by RODT_TRACKING_SAVEING_MCK + u2TRTW = u2TRTW - RODT_TRACKING_SAVEING_MCK; + u2XRTR2W = u2XRTR2W - RODT_TRACKING_SAVEING_MCK; + +#if SAMSUNG_LP4_NWR_WORKAROUND + // If nWR is fixed to 30 for all freqs, tWTR@800Mhz should add 2tCK gap, allowing sufficient Samsung DRAM internal IO precharge time + if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency == 800)) //LP4X, Samsung, DDR1600 + { + u1TWTR_TMP = (ACTblFinal.twtr * 4 - ACTblFinal.twtr_05T * 2) + 2; //Convert TWTR to tCK, and add 2tCK + if ((u1TWTR_TMP % 4) == 0) //TWTR can be transferred to TWTR directly + { + u1TWTR = u1TWTR_TMP >> 2; + u1TWTR_05T = 0; + } + else //Can't be transfered to TWTR directly + { + u1TWTR = (u1TWTR_TMP + 2) >> 2; //Add 2 tCK and set TWTR value (Then minus 2tCK using 05T) + u1TWTR_05T = 1; //05T means minus 2tCK + } + + ACTblFinal.twtr = u1TWTR; + ACTblFinal.twtr_05T = u1TWTR_05T; + } +#endif + +//DATLAT related +if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + u1DATLAT_DSEL = ACTblFinal.datlat; +else + u1DATLAT_DSEL = ACTblFinal.datlat - 1; + +#if TX_OE_EXTEND + u2XRTWTW += 1; + u2XRTW2R += 1; +#endif + +#if 0//(!CMD_CKE_WORKAROUND_FIX) + U8 u1Txp = 0, u1Txp0p5 = 0; + + if (((p->frequency <= 1866) && (p->frequency >= 1600)) || ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400))) + { + u1Txp = 1; + } + else if ((p->frequency == 2133) || ((vGet_Div_Mode(p) == DIV4_MODE) && ((p->frequency <= 800) || (p->frequency >= 600)))) + { + u1Txp = 2; + } + + if ((p->frequency == 1866) || ((p->frequency <= 1333) && (p->frequency >= 1200))) + { + u1Txp0p5 = 1; + } + + ACTblFinal.txp = u1Txp; + ACTblFinal.txp_05T = u1Txp0p5; + ACTblFinal.ckelckcnt = 4; + ACTblFinal.earlyckecnt = 0; + ACTblFinal.ckeprd -= 1; +#endif + + // ----Step 2: Perform register writes for entries in ACTblFinal struct & ACTiming excel file (all actiming adjustments should be done in Step 1)------- + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM1, P_Fld(ACTblFinal.tras, SHU_ACTIM1_TRAS) + | P_Fld(ACTblFinal.trp, SHU_ACTIM1_TRP) + | P_Fld(ACTblFinal.trpab, SHU_ACTIM1_TRPAB) + | P_Fld(ACTblFinal.tmrwckel, SHU_ACTIM1_TMRWCKEL) + | P_Fld(ACTblFinal.trc, SHU_ACTIM1_TRC)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM3, P_Fld(ACTblFinal.trfc, SHU_ACTIM3_TRFC) + | P_Fld(ACTblFinal.tr2mrr, SHU_ACTIM3_TR2MRR) + | P_Fld(ACTblFinal.trfcpb, SHU_ACTIM3_TRFCPB)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM2, P_Fld(ACTblFinal.txp, SHU_ACTIM2_TXP) + | P_Fld(ACTblFinal.tmrri, SHU_ACTIM2_TMRRI) + | P_Fld(u2TFAW, SHU_ACTIM2_TFAW) + | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) // Value has odt_on/off difference, use local variable u1TRTW + | P_Fld(ACTblFinal.trtp, SHU_ACTIM2_TRTP)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM0, P_Fld(ACTblFinal.trcd, SHU_ACTIM0_TRCD) + | P_Fld(ACTblFinal.twr, SHU_ACTIM0_TWR) + | P_Fld(u2TRRD, SHU_ACTIM0_TRRD)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM5, P_Fld(ACTblFinal.tpbr2pbr, SHU_ACTIM5_TPBR2PBR) + | P_Fld(ACTblFinal.twtpd, SHU_ACTIM5_TWTPD) + | P_Fld(ACTblFinal.tpbr2act, SHU_ACTIM5_TPBR2ACT)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM6, P_Fld(ACTblFinal.tr2mrw, SHU_ACTIM6_TR2MRW) + | P_Fld(ACTblFinal.tw2mrw, SHU_ACTIM6_TW2MRW) + | P_Fld(ACTblFinal.tmrd, SHU_ACTIM6_TMRD) + | P_Fld(ACTblFinal.zqlat2, SHU_ACTIM6_TZQLAT2) + | P_Fld(ACTblFinal.tmrw, SHU_ACTIM6_TMRW)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM4, P_Fld(ACTblFinal.tmrr2mrw, SHU_ACTIM4_TMRR2MRW) + | P_Fld(u2TMRR2W, SHU_ACTIM4_TMRR2W) + | P_Fld(ACTblFinal.tzqcs, SHU_ACTIM4_TZQCS) + | P_Fld(ACTblFinal.txrefcnt, SHU_ACTIM4_TXREFCNT)); + + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CKECTRL, ACTblFinal.ckeprd, SHU_CKECTRL_TCKEPRD); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(u2XRTWTW, SHU_ACTIM_XRT_XRTW2W) + | P_Fld(u2XRTW2R, SHU_ACTIM_XRT_XRTW2R) + | P_Fld(u2XRTR2W, SHU_ACTIM_XRT_XRTR2W) + | P_Fld(u2XTRTRT, SHU_ACTIM_XRT_XRTR2R)); + + vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT); +// vIO32WriteFldMulti_All(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT) +// | P_Fld(ACTblFinal.hwset_vrcg_op, SHU_HWSET_VRCG_HWSET_VRCG_OP)); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR2, ACTblFinal.hwset_mr2_op, SHU_HWSET_MR2_HWSET_MR2_OP); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR13, ACTblFinal.hwset_mr13_op, SHU_HWSET_MR13_HWSET_MR13_OP); + + // AC timing 0.5T + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(ACTblFinal.twtr_05T, SHU_AC_TIME_05T_TWTR_M05T) + | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) // Value has odt_on/off difference, use local variable u1TRTW + | P_Fld(ACTblFinal.twtpd_05T, SHU_AC_TIME_05T_TWTPD_M05T) + | P_Fld(u1TFAW_05T, SHU_AC_TIME_05T_TFAW_05T) + | P_Fld(u1TRRD_05T, SHU_AC_TIME_05T_TRRD_05T) + | P_Fld(ACTblFinal.twr_05T, SHU_AC_TIME_05T_TWR_M05T) + | P_Fld(ACTblFinal.tras_05T, SHU_AC_TIME_05T_TRAS_05T) + | P_Fld(ACTblFinal.trpab_05T, SHU_AC_TIME_05T_TRPAB_05T) + | P_Fld(ACTblFinal.trp_05T, SHU_AC_TIME_05T_TRP_05T) + | P_Fld(ACTblFinal.trcd_05T, SHU_AC_TIME_05T_TRCD_05T) + | P_Fld(ACTblFinal.trtp_05T, SHU_AC_TIME_05T_TRTP_05T) + | P_Fld(ACTblFinal.txp_05T, SHU_AC_TIME_05T_TXP_05T) + | P_Fld(ACTblFinal.trfc_05T, SHU_AC_TIME_05T_TRFC_05T) + | P_Fld(ACTblFinal.trfcpb_05T, SHU_AC_TIME_05T_TRFCPB_05T) + | P_Fld(ACTblFinal.tpbr2pbr_05T, SHU_AC_TIME_05T_TPBR2PBR_05T) + | P_Fld(ACTblFinal.tpbr2act_05T, SHU_AC_TIME_05T_TPBR2ACT_05T) + | P_Fld(ACTblFinal.tr2mrw_05T, SHU_AC_TIME_05T_TR2MRW_05T) + | P_Fld(ACTblFinal.tw2mrw_05T, SHU_AC_TIME_05T_TW2MRW_05T) + | P_Fld(ACTblFinal.tmrr2mrw_05T, SHU_AC_TIME_05T_TMRR2MRW_05T) + | P_Fld(ACTblFinal.tmrw_05T, SHU_AC_TIME_05T_TMRW_05T) + | P_Fld(ACTblFinal.tmrd_05T, SHU_AC_TIME_05T_TMRD_05T) + | P_Fld(ACTblFinal.tmrwckel_05T, SHU_AC_TIME_05T_TMRWCKEL_05T) + | P_Fld(ACTblFinal.tmrri_05T, SHU_AC_TIME_05T_TMRRI_05T) + | P_Fld(ACTblFinal.trc_05T, SHU_AC_TIME_05T_TRC_05T)); + + { + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr, SHU_ACTIM0_TWTR); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_CKECTRL, P_Fld(ACTblFinal.tpde, SHU_CKECTRL_TPDE) + | P_Fld(ACTblFinal.tpdx, SHU_CKECTRL_TPDX) + | P_Fld(ACTblFinal.tpde_05T, SHU_CKECTRL_TPDE_05T) + | P_Fld(ACTblFinal.tpdx_05T, SHU_CKECTRL_TPDX_05T)); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM5, ACTblFinal.trtpd, SHU_ACTIM5_TR2PD); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, ACTblFinal.trtpd_05T, SHU_AC_TIME_05T_TR2PD_05T); + } + +#if AC_TIMING_DERATE_ENABLE + if (u1IsLP4Family(p->dram_type)) + { + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING0, P_Fld(ACTblFinal.trcd_derate, SHU_AC_DERATING0_TRCD_DERATE) + | P_Fld(ACTblFinal.trrd_derate, SHU_AC_DERATING0_TRRD_DERATE)); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING1, P_Fld(ACTblFinal.trc_derate, SHU_AC_DERATING1_TRC_DERATE) + | P_Fld(ACTblFinal.tras_derate, SHU_AC_DERATING1_TRAS_DERATE) + | P_Fld(ACTblFinal.trp_derate, SHU_AC_DERATING1_TRP_DERATE) + | P_Fld(ACTblFinal.trpab_derate, SHU_AC_DERATING1_TRPAB_DERATE)); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(ACTblFinal.trrd_derate_05T, SHU_AC_DERATING_05T_TRRD_05T_DERATE) + | P_Fld(ACTblFinal.tras_derate_05T, SHU_AC_DERATING_05T_TRAS_05T_DERATE) + | P_Fld(ACTblFinal.trpab_derate_05T, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) + | P_Fld(ACTblFinal.trp_derate_05T, SHU_AC_DERATING_05T_TRP_05T_DERATE) + | P_Fld(ACTblFinal.trcd_derate_05T, SHU_AC_DERATING_05T_TRCD_05T_DERATE) + | P_Fld(ACTblFinal.trc_derate_05T, SHU_AC_DERATING_05T_TRC_05T_DERATE)); + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0xc0, REFCTRL3_REF_DERATING_EN); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); //enable derating for AC timing + } +#endif + + // DQSINCTL related + vSetRank(p, RANK_0); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 0 DQSINCTL + vSetRank(p, RANK_1); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 1 DQSINCTL + vSetRank(p, backup_rank); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL, ACTblFinal.dqsinctl, MISC_SHU_ODTCTRL_RODT_LAT); + + if (ACTblFinal.dqsinctl >= 2) + { + u4RankINCTL_ROOT = ACTblFinal.dqsinctl - 2; + } + else + { + mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n")); + u4RankINCTL_ROOT = 0; + } + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(ACTblFinal.dqsinctl, MISC_SHU_RANKCTL_RANKINCTL_PHY) + | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) + | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL)); + +#if XRTRTR_NEW_CROSS_RK_MODE + u2PHSINCTL = (ACTblFinal.dqsinctl == 0)? 0: (ACTblFinal.dqsinctl - 1); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL); +#endif + + // DATLAT related, tREFBW + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(ACTblFinal.datlat, MISC_SHU_RDAT_DATLAT) + | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL) + | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIMING_CONF, u1TREFBW, SHU_ACTIMING_CONF_REFBW_FR); + + // ----Step 3: Perform register writes/calculation for other regs (That aren't in ACTblFinal struct)------------------------------------------------ +#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + //Wei-Jen: Ininital setting values are the same, RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1 + //XRTR2R setting will be updated in RxdqsGatingPostProcess + u1RANKINCTL = u4IO32ReadFldAlign(DDRPHY_REG_MISC_SHU_RANKCTL, MISC_SHU_RANKCTL_RANKINCTL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RANKCTL, u1RANKINCTL, MISC_SHU_RANKCTL_RANKINCTL_RXDLY); +#endif + + //Update releated RG of XRTW2W + if (p->frequency <= 800) + { + if (vGet_Div_Mode(p) == DIV4_MODE) + { + u1ROOT = 0; u1TXRANKINCTL = 1; u1TXDLY = 2; + } + else + { + u1ROOT = 0; u1TXRANKINCTL = 0; u1TXDLY = 1; + } + } + else + { + u1ROOT = (p->frequency == 1866)? 1: 0; + u1TXRANKINCTL = 1; u1TXDLY = 2; + } + #if TX_OE_EXTEND + if (p->frequency >= 1333) + { + u1TXRANKINCTL += 1; + u1TXDLY += 1; + } + #endif + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(u1ROOT, SHU_TX_RANKCTL_TXRANKINCTL_ROOT) + | P_Fld(u1TXRANKINCTL, SHU_TX_RANKCTL_TXRANKINCTL) + | P_Fld(u1TXDLY, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY)); + + return DRAM_OK; +} + + +DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p) +{ + U8 u1TimingIdx = 0; + + mcSHOW_DBG_MSG3(("[UpdateACTiming]\n")); + + //Retrieve ACTimingTable's corresponding index + u1TimingIdx = u1GetACTimingIdx(p); + + if (u1TimingIdx == 0xff) + { + #if 0 + if (u1TmpDramType = TYPE_LPDDR4) + u1TimingIdx = 0; + else // LPDDR3 + u1TimingIdx = 6; + mcSHOW_ERR_MSG(("Error, no match AC timing, use default timing %d\n", u1TimingIdx)); + #else + mcSHOW_ERR_MSG(("Error, no match AC timing, not apply table\n")); + return DRAM_FAIL; + #endif + } + + //Set ACTiming registers +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + DdrUpdateACTimingReg_LP5(p, &ACTimingTbl_LP5[u1TimingIdx]); + } + else +#endif + { + DdrUpdateACTimingReg_LP4(p, &ACTimingTbl_LP4[u1TimingIdx]); + } + + return DRAM_OK; +} +#if 0 +#if ((!SW_CHANGE_FOR_SIMULATION) && (!FOR_DV_SIMULATION_USED && SW_CHANGE_FOR_SIMULATION == 0) && (!__ETT__)) +DRAM_STATUS_T DdrUpdateACTiming_EMI(DRAMC_CTX_T *p, AC_TIMING_EXTERNAL_T *ACRegFromEmi) +{ + U8 u1TimingIdx = 0; + #if (__LP5_COMBO__ == TRUE) + ACTime_T_LP5 ACTime_LP5; + #endif + ACTime_T_LP4 ACTime_LP4; + mcSHOW_DBG_MSG3(("[DdrUpdateACTiming_EMI]\n")); + + if (ACRegFromEmi == NULL) + return DRAM_FAIL; + + //Retrieve ACTimingTable's corresponding index + u1TimingIdx = u1GetACTimingIdx(p); +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + ACTime_LP5 = ACTimingTbl_LP5[u1TimingIdx]; + } +#endif + ACTime_LP4 = ACTimingTbl_LP4[u1TimingIdx]; + + //Overwrite AC timing from emi settings + ACTime.dramType = p->dram_type; +#if 1 // Will use MDL ac timing, Others from internal ac timing + ACTime.trp = ACRegFromEmi->AC_TIME_EMI_TRP; + ACTime.trpab = ACRegFromEmi->AC_TIME_EMI_TRPAB; + ACTime.trc = ACRegFromEmi->AC_TIME_EMI_TRC; + ACTime.trcd = ACRegFromEmi->AC_TIME_EMI_TRCD; + + ACTime.trp_05T = ACRegFromEmi->AC_TIME_EMI_TRP_05T; + ACTime.trpab_05T = ACRegFromEmi->AC_TIME_EMI_TRPAB_05T; + ACTime.trc_05T = ACRegFromEmi->AC_TIME_EMI_TRC_05T; + ACTime.trcd_05T = ACRegFromEmi->AC_TIME_EMI_TRCD_05T; +#else + ACTime.freq = ACRegFromEmi->AC_TIME_EMI_FREQUENCY; + ACTime.tras = ACRegFromEmi->AC_TIME_EMI_TRAS; + ACTime.trp = ACRegFromEmi->AC_TIME_EMI_TRP; + + ACTime.trpab = ACRegFromEmi->AC_TIME_EMI_TRPAB; + ACTime.trc = ACRegFromEmi->AC_TIME_EMI_TRC; + ACTime.trfc = ACRegFromEmi->AC_TIME_EMI_TRFC; + ACTime.trfcpb = ACRegFromEmi->AC_TIME_EMI_TRFCPB; + + ACTime.txp = ACRegFromEmi->AC_TIME_EMI_TXP; + ACTime.trtp = ACRegFromEmi->AC_TIME_EMI_TRTP; + ACTime.trcd = ACRegFromEmi->AC_TIME_EMI_TRCD; + ACTime.twr = ACRegFromEmi->AC_TIME_EMI_TWR; + + ACTime.twtr = ACRegFromEmi->AC_TIME_EMI_TWTR; + ACTime.trrd = ACRegFromEmi->AC_TIME_EMI_TRRD; + ACTime.tfaw = ACRegFromEmi->AC_TIME_EMI_TFAW; + ACTime.trtw_ODT_off = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_OFF; + ACTime.trtw_ODT_on = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_ON; + + ACTime.refcnt = ACRegFromEmi->AC_TIME_EMI_REFCNT; //(REFFRERUN = 0) + ACTime.refcnt_fr_clk = ACRegFromEmi->AC_TIME_EMI_REFCNT_FR_CLK; //(REFFRERUN = 1) + ACTime.txrefcnt = ACRegFromEmi->AC_TIME_EMI_TXREFCNT; + ACTime.tzqcs = ACRegFromEmi->AC_TIME_EMI_TZQCS; + + ACTime.trtpd = ACRegFromEmi->AC_TIME_EMI_TRTPD; + ACTime.twtpd = ACRegFromEmi->AC_TIME_EMI_TWTPD; + ACTime.tmrr2w_ODT_off = ACRegFromEmi->AC_TIME_EMI_TMRR2W_ODT_OFF; + ACTime.tmrr2w_ODT_on = ACRegFromEmi->AC_TIME_EMI_TMRR2W_ODT_ON; + + ACTime.tras_05T = ACRegFromEmi->AC_TIME_EMI_TRAS_05T; + ACTime.trp_05T = ACRegFromEmi->AC_TIME_EMI_TRP_05T; + ACTime.trpab_05T = ACRegFromEmi->AC_TIME_EMI_TRPAB_05T; + ACTime.trc_05T = ACRegFromEmi->AC_TIME_EMI_TRC_05T; + ACTime.trfc_05T = ACRegFromEmi->AC_TIME_EMI_TRFC_05T; + ACTime.trfcpb_05T = ACRegFromEmi->AC_TIME_EMI_TRFCPB_05T; + ACTime.txp_05T = ACRegFromEmi->AC_TIME_EMI_TXP_05T; + ACTime.trtp_05T = ACRegFromEmi->AC_TIME_EMI_TRTP_05T; + ACTime.trcd_05T = ACRegFromEmi->AC_TIME_EMI_TRCD_05T; + ACTime.twr_05T = ACRegFromEmi->AC_TIME_EMI_TWR_05T; + ACTime.twtr_05T = ACRegFromEmi->AC_TIME_EMI_TWTR_05T; + ACTime.trrd_05T = ACRegFromEmi->AC_TIME_EMI_TRRD_05T; + ACTime.tfaw_05T = ACRegFromEmi->AC_TIME_EMI_TFAW_05T; + ACTime.trtw_ODT_off_05T = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_OFF_05T; + ACTime.trtw_ODT_on_05T = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_ON_05T; + ACTime.trtpd_05T = ACRegFromEmi->AC_TIME_EMI_TRTPD_05T; + ACTime.twtpd_05T = ACRegFromEmi->AC_TIME_EMI_TWTPD_05T; +#endif + + //Set ACTiming registers + DdrUpdateACTimingReg(p, &ACTime); + + return DRAM_OK; +} +#endif +#endif +///TODO: wait for porting +++ +#if __A60868_TO_BE_PORTING__ + +U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p) +{ + U8 u1TimingIdx = u1GetACTimingIdx(p); +#if (__LP5_COMBO__ == TRUE) + ACTime_T_LP5 ACTime = ACTimingTbl_LP5[u1TimingIdx]; +#else + ACTime_T_LP4 ACTime = ACTimingTbl_LP4[u1TimingIdx]; +#endif + + return ACTime.datlat; +} +#endif // __A60868_TO_BE_PORTING__ +///TODO: wait for porting +++ + +/* Optimize all-bank refresh parameters (by density) for LP4 */ +void vDramcACTimingOptimize(DRAMC_CTX_T *p) +{ + /* TRFC: tRFCab + * Refresh Cycle Time (All Banks) + * TXREFCNT: tXSR max((tRFCab + 7.5ns), 2nCK) + * Min self refresh time (Entry to Exit) + * u1ExecuteOptimize: Indicate if ACTimings are updated at the end of this function + */ + U8 u1RFCabGrpIdx = 0, u1FreqGrpIdx = 0, u1ExecuteOptimize = ENABLE; + U8 u1TRFC=101, u1TRFC_05T=0, u1TRFCpb=44, u1TRFCpb_05T=0,u1TXREFCNT=118; + typedef struct + { /* Bitfield sizes set to current project register field's size */ + U8 u1TRFC : 8; + U8 u1TRFRC_05T : 1; + U8 u1TRFCpb : 8; + U8 u1TRFRCpb_05T : 1; + U16 u2TXREFCNT : 10; + } optimizeACTime; + /* JESD209-4B: tRFCab has 4 settings for 7 density settings (130, 180, 280, 380) + * tRFCAB_NUM: Used to indicate tRFCab group (since some densities share the same tRFCab) + */ + enum tRFCABIdx{tRFCAB_130 = 0, tRFCAB_180, tRFCAB_280, tRFCAB_380, tRFCAB_NUM}; + enum ACTimeIdx{GRP_DDR1200_ACTIM, GRP_DDR1600_ACTIM, GRP_DDR1866_ACTIM, GRP_DDR2400_ACTIM, GRP_DDR2667_ACTIM, GRP_DDR3200_ACTIM, GRP_DDR3733_ACTIM, GRP_DDR4266_ACTIM, GRP_ACTIM_NUM}; + enum ACTimeIdxDiv4{GRP_DDR800_DIV4_ACTIM = 0, GRP_DDR1200_DIV4_ACTIM, GRP_DDR1600_DIV4_ACTIM, GRP_ACTIM_NUM_DIV4}; + /* Values retrieved from 1. Alaska ACTiming excel file 2. JESD209-4B Refresh requirement table */ + + optimizeACTime *ptRFCab_Opt; + + optimizeACTime tRFCab_Opt [GRP_ACTIM_NUM][tRFCAB_NUM] = + { + //For freqGroup DDR1200 + {{.u1TRFC = 8, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 21}, //tRFCab = 130, tRFCpb = 60, @Robert Not enough to Optimize + {.u1TRFC = 15, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 29}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 30, .u1TRFRC_05T = 1, .u1TRFCpb = 9, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 44}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 45, .u1TRFRC_05T = 1, .u1TRFCpb = 17, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 59}},//tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR1600 + {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}},//tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR1866 + {{.u1TRFC = 18, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 33}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 30, .u1TRFRC_05T = 0, .u1TRFCpb = 9, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 44}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 53, .u1TRFRC_05T = 1, .u1TRFCpb = 21, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 68}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 77, .u1TRFRC_05T = 0, .u1TRFCpb = 32, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 91}},//tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR2400 + {{.u1TRFC = 27, .u1TRFRC_05T = 1, .u1TRFCpb = 6, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 42}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 42, .u1TRFRC_05T = 1, .u1TRFCpb = 15, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 57}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 72, .u1TRFRC_05T = 1, .u1TRFCpb = 30, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 87}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 102, .u1TRFRC_05T = 1, .u1TRFCpb = 45, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 117}},//tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR2667 + {{.u1TRFC = 31, .u1TRFRC_05T = 1, .u1TRFCpb = 8, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 46}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 48, .u1TRFRC_05T = 1, .u1TRFCpb = 18, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 63}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 81, .u1TRFRC_05T = 1, .u1TRFCpb = 35, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 96}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 115, .u1TRFRC_05T = 0, .u1TRFCpb = 51, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 130}}, //tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR3200 + {{.u1TRFC = 40, .u1TRFRC_05T = 0, .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 60, .u1TRFRC_05T = 0, .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, //tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR3733 + {{.u1TRFC = 49, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 65}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 72, .u1TRFRC_05T = 0, .u1TRFCpb = 30, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 88}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 119, .u1TRFRC_05T = 0, .u1TRFCpb = 53, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 135}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 165, .u1TRFRC_05T = 1, .u1TRFCpb = 77, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 181}}, //tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR4266 + {{.u1TRFC = 57, .u1TRFRC_05T = 1, .u1TRFCpb = 20, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 74}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 84, .u1TRFRC_05T = 0, .u1TRFCpb = 36, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 100}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 137, .u1TRFRC_05T = 1, .u1TRFCpb = 63, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 154}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 191, .u1TRFRC_05T = 0, .u1TRFCpb = 89, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 207}} //tRFCab = 380, tRFCpb = 190 + }; + + optimizeACTime tRFCab_Opt_Div4 [GRP_ACTIM_NUM_DIV4][tRFCAB_NUM] = + { + //NOTE: @Darren, For freqGroup DDR816 + {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}},//tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR1200 + {{.u1TRFC = 28, .u1TRFRC_05T = 0, .u1TRFCpb = 7, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 42}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 43, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 57}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 73, .u1TRFRC_05T = 0, .u1TRFCpb = 31, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 87}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 103, .u1TRFRC_05T = 0, .u1TRFCpb = 46, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 117}},//tRFCab = 380, tRFCpb = 190 + //For freqGroup DDR1600 + {{.u1TRFC = 40, .u1TRFRC_05T = 0, .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55}, //tRFCab = 130, tRFCpb = 60 + {.u1TRFC = 60, .u1TRFRC_05T = 0, .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75}, //tRFCab = 180, tRFCpb = 90 + {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115}, //tRFCab = 280, tRFCpb = 140 + {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, //tRFCab = 380, tRFCpb = 190 + }; + + + mcSHOW_DBG_MSG(("[ACTimingOptimize]")); + +#if __ETT__ + if (p->density==0xff) + { + mcSHOW_ERR_MSG(("Error : No call MR8 to get density!!\n")); + while(1); + } +#endif + + /* Set tRFCab group idx p->density = MR8 OP[5:2]*/ + switch (p->density) + { + case 0x0: //4Gb per die (2Gb per channel), tRFCab=130 + u1RFCabGrpIdx = tRFCAB_130; + break; + case 0x1: //6Gb per die (3Gb per channel), tRFCab=180 + case 0x2: //8Gb per die (4Gb per channel), tRFCab=180 + u1RFCabGrpIdx = tRFCAB_180; + break; + case 0x3: //12Gb per die (6Gb per channel), tRFCab=280 + case 0x4: //16Gb per die (8Gb per channel), tRFCab=280 + u1RFCabGrpIdx = tRFCAB_280; + break; + case 0x5: //24Gb per die (12Gb per channel), tRFCab=380 + case 0x6: //32Gb per die (16Gb per channel), tRFCab=380 + u1RFCabGrpIdx = tRFCAB_380; + break; + default: + u1ExecuteOptimize = DISABLE; + mcSHOW_ERR_MSG(("MR8 density err!\n")); + } + /* Set freqGroup Idx */ + switch (p->freqGroup) + { + case 400: + if (vGet_Div_Mode(p) == DIV4_MODE) + u1FreqGrpIdx = GRP_DDR800_DIV4_ACTIM; + else + { + u1ExecuteOptimize = DISABLE; + mcSHOW_ERR_MSG(("freqGroup err!\n")); + #if __ETT__ + while(1); + #endif + } + break; + case 600: + if (vGet_Div_Mode(p) == DIV4_MODE) + u1FreqGrpIdx = GRP_DDR1200_DIV4_ACTIM; + else + u1FreqGrpIdx = GRP_DDR1200_ACTIM; + break; + case 800: + if (vGet_Div_Mode(p) == DIV4_MODE) + u1FreqGrpIdx = GRP_DDR1600_DIV4_ACTIM; + else + u1FreqGrpIdx = GRP_DDR1600_ACTIM; + break; + case 933: + u1FreqGrpIdx = GRP_DDR1866_ACTIM; + break; + case 1200: + u1FreqGrpIdx = GRP_DDR2400_ACTIM; + break; + case 1333: + u1FreqGrpIdx = GRP_DDR2667_ACTIM; + break; + case 1600: + u1FreqGrpIdx = GRP_DDR3200_ACTIM; + break; + case 1866: + u1FreqGrpIdx = GRP_DDR3733_ACTIM; + break; + case 2133: + u1FreqGrpIdx = GRP_DDR4266_ACTIM; + break; + default: + u1ExecuteOptimize = DISABLE; + mcSHOW_ERR_MSG(("freqGroup err!\n")); + #if __ETT__ + while(1); + #endif + } + + if (vGet_Div_Mode(p) == DIV4_MODE && u1FreqGrpIdx >= GRP_ACTIM_NUM_DIV4) + { + u1ExecuteOptimize = DISABLE; + mcSHOW_ERR_MSG(("freqGroup err!\n")); + #if __ETT__ + while(1); + #endif + } + if (vGet_Div_Mode(p) == DIV4_MODE && u1FreqGrpIdx < GRP_ACTIM_NUM_DIV4) + ptRFCab_Opt = &tRFCab_Opt_Div4[u1FreqGrpIdx][0]; + else + ptRFCab_Opt = &tRFCab_Opt[u1FreqGrpIdx][0]; + + u1TRFC = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFC; + u1TRFC_05T = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFRC_05T; + u1TRFCpb = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFCpb; + u1TRFCpb_05T = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFRCpb_05T; + u1TXREFCNT = ptRFCab_Opt[u1RFCabGrpIdx].u2TXREFCNT; + + /* Only execute ACTimingOptimize(write to regs) when corresponding values have been found */ + if (u1ExecuteOptimize == ENABLE) + { + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM3, u1TRFC, SHU_ACTIM3_TRFC); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, u1TRFC_05T, SHU_AC_TIME_05T_TRFC_05T); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM4, u1TXREFCNT, SHU_ACTIM4_TXREFCNT); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM3, u1TRFCpb, SHU_ACTIM3_TRFCPB); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, u1TRFCpb_05T, SHU_AC_TIME_05T_TRFCPB_05T); + + mcSHOW_DBG_MSG(("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, TRFCpb %u, TRFCpb_05T %u\n", p->density, u1TRFC, u1TRFC_05T, u1TXREFCNT, u1TRFCpb, u1TRFCpb_05T)); + } + + return; +} + +/* ACTimingTbl: All freq's ACTiming from ACTiming excel file + * (Some fields don't exist for LP3 -> set to 0) + * Note: !!All ACTiming adjustments should not be set in-table should be moved into UpdateACTimingReg()!! + * Or else preloader's highest freq ACTimings may be set to different values than expected. + */ +const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { + //----------LPDDR4--------------------------- +#if SUPPORT_LP4_DDR4266_ACTIM + //LP4_DDR4266 ACTiming--------------------------------- +#if (ENABLE_READ_DBI == 1) +//LPDDR4 4X_4266_Div 8_DBI1.csv Read 1 +{ + .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, + .readLat = 40, .writeLat = 18, .DivMode = DIV8_MODE, + + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 15, .twr_05T = 0, + .twtr = 10, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 8, + .xrtr2w_odt_off = 8, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 15, .trtpd_05T = 1, + .twtpd = 18, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 18 +}, +//LPDDR4 4X_4266_BT_Div 8_DBI1.csv Read 1 +{ + .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, + .readLat = 44, .writeLat = 18, .DivMode = DIV8_MODE, + + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 16, .twr_05T = 0, + .twtr = 11, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 19, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 16, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 8, .trtw_odt_off_05T = 0, + .trtw_odt_on = 10, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 9, + .xrtr2w_odt_off = 9, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 16, .trtpd_05T = 1, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w_odt_off = 12, + .tmrr2w_odt_on = 14, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 18 +}, +#else //ENABLE_READ_DBI == 0) +//LPDDR4 4X_4266_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 36, .writeLat = 18, .DivMode = DIV8_MODE, + + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 15, .twr_05T = 0, + .twtr = 10, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 7, + .xrtr2w_odt_off = 7, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 14, .trtpd_05T = 1, + .twtpd = 18, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 18 +}, +//LPDDR4 4X_4266_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 40, .writeLat = 18, .DivMode = DIV8_MODE, + + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 16, .twr_05T = 0, + .twtr = 11, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 8, + .xrtr2w_odt_off = 8, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 15, .trtpd_05T = 1, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 18 +}, +#endif +#endif +#if SUPPORT_LP4_DDR3733_ACTIM + //LP4_DDR3733 ACTiming--------------------------------- +#if (ENABLE_READ_DBI == 1) +//LPDDR4 4X_3733_Div 8_DBI1.csv Read 1 +{ + .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, + .readLat = 36, .writeLat = 16, .DivMode = DIV8_MODE, + + .tras = 11, .tras_05T = 1, + .trp = 7, .trp_05T = 0, + .trpab = 8, .trpab_05T = 1, + .trc = 19, .trc_05T = 0, + .trfc = 119, .trfc_05T = 0, + .trfcpb = 53, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 8, .trcd_05T = 1, + .twr = 13, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .tpbr2pbr = 35, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 16, .tr2mrw_05T = 1, + .tw2mrw = 10, .tw2mrw_05T = 0, + .tmrr2mrw = 13, .tmrr2mrw_05T = 1, + .tmrw = 5, .tmrw_05T = 1, + .tmrd = 7, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 1, + .tfaw = 11, .tfaw_05T = 0, + .tfaw_4266 = 6, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .txrefcnt = 135, + .tzqcs = 40, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 8, + .xrtr2w_odt_off = 8, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 47, + .hwset_mr2_op = 54, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 9, .trcd_derate_05T = 1, + .trc_derate = 21, .trc_derate_05T = 1, + .tras_derate = 12, .tras_derate_05T = 0, + .trpab_derate = 9, .trpab_derate_05T = 1, + .trp_derate = 8, .trp_derate_05T = 0, + .trrd_derate = 5, .trrd_derate_05T = 0, + .trtpd = 14, .trtpd_05T = 0, + .twtpd = 16, .twtpd_05T = 1, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 14, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 16 +}, +//LPDDR4 4X_3733_BT_Div 8_DBI1.csv Read 1 +{ + .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, + .readLat = 40, .writeLat = 16, .DivMode = DIV8_MODE, + + .tras = 11, .tras_05T = 1, + .trp = 7, .trp_05T = 0, + .trpab = 8, .trpab_05T = 1, + .trc = 19, .trc_05T = 0, + .trfc = 119, .trfc_05T = 0, + .trfcpb = 53, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 8, .trcd_05T = 1, + .twr = 14, .twr_05T = 1, + .twtr = 9, .twtr_05T = 0, + .tpbr2pbr = 35, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 1, + .tw2mrw = 10, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 1, + .tmrw = 5, .tmrw_05T = 1, + .tmrd = 7, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 1, + .tfaw = 11, .tfaw_05T = 0, + .tfaw_4266 = 6, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 10, .trtw_odt_on_05T = 0, + .txrefcnt = 135, + .tzqcs = 40, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 9, + .xrtr2w_odt_off = 9, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 47, + .hwset_mr2_op = 54, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 9, .trcd_derate_05T = 1, + .trc_derate = 21, .trc_derate_05T = 1, + .tras_derate = 12, .tras_derate_05T = 0, + .trpab_derate = 9, .trpab_derate_05T = 1, + .trp_derate = 8, .trp_derate_05T = 0, + .trrd_derate = 5, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 17, .twtpd_05T = 1, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 14, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 16 +}, +#else //ENABLE_READ_DBI == 0) +//LPDDR4 4X_3733_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 32, .writeLat = 16, .DivMode = DIV8_MODE, + + .tras = 11, .tras_05T = 1, + .trp = 7, .trp_05T = 0, + .trpab = 8, .trpab_05T = 1, + .trc = 19, .trc_05T = 0, + .trfc = 119, .trfc_05T = 0, + .trfcpb = 53, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 8, .trcd_05T = 1, + .twr = 13, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .tpbr2pbr = 35, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 15, .tr2mrw_05T = 1, + .tw2mrw = 10, .tw2mrw_05T = 0, + .tmrr2mrw = 12, .tmrr2mrw_05T = 1, + .tmrw = 5, .tmrw_05T = 1, + .tmrd = 7, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 1, + .tfaw = 11, .tfaw_05T = 0, + .tfaw_4266 = 6, .tfaw_4266_05T = 0, + .trtw_odt_off = 5, .trtw_odt_off_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .txrefcnt = 135, + .tzqcs = 40, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 7, + .xrtr2w_odt_off = 7, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 47, + .hwset_mr2_op = 54, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 9, .trcd_derate_05T = 1, + .trc_derate = 21, .trc_derate_05T = 1, + .tras_derate = 12, .tras_derate_05T = 0, + .trpab_derate = 9, .trpab_derate_05T = 1, + .trp_derate = 8, .trp_derate_05T = 0, + .trrd_derate = 5, .trrd_derate_05T = 0, + .trtpd = 13, .trtpd_05T = 0, + .twtpd = 16, .twtpd_05T = 1, + .tmrr2w_odt_off = 9, + .tmrr2w_odt_on = 11, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 14, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 16 +}, +//LPDDR4 4X_3733_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 36, .writeLat = 16, .DivMode = DIV8_MODE, + + .tras = 11, .tras_05T = 1, + .trp = 7, .trp_05T = 0, + .trpab = 8, .trpab_05T = 1, + .trc = 19, .trc_05T = 0, + .trfc = 119, .trfc_05T = 0, + .trfcpb = 53, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 8, .trcd_05T = 1, + .twr = 14, .twr_05T = 1, + .twtr = 9, .twtr_05T = 0, + .tpbr2pbr = 35, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 16, .tr2mrw_05T = 1, + .tw2mrw = 10, .tw2mrw_05T = 0, + .tmrr2mrw = 13, .tmrr2mrw_05T = 1, + .tmrw = 5, .tmrw_05T = 1, + .tmrd = 7, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 1, + .tfaw = 11, .tfaw_05T = 0, + .tfaw_4266 = 6, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .txrefcnt = 135, + .tzqcs = 40, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 8, + .xrtr2w_odt_off = 8, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 47, + .hwset_mr2_op = 54, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 9, .trcd_derate_05T = 1, + .trc_derate = 21, .trc_derate_05T = 1, + .tras_derate = 12, .tras_derate_05T = 0, + .trpab_derate = 9, .trpab_derate_05T = 1, + .trp_derate = 8, .trp_derate_05T = 0, + .trrd_derate = 5, .trrd_derate_05T = 0, + .trtpd = 14, .trtpd_05T = 0, + .twtpd = 17, .twtpd_05T = 1, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 14, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 16 +}, +#endif +#endif +#if SUPPORT_LP4_DDR3200_ACTIM + //LP4_DDR3200 ACTiming--------------------------------- +#if (ENABLE_READ_DBI == 1) +//LPDDR4 4X_3200_Div 8_DBI1.csv Read 1 +{ + .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, + .readLat = 32, .writeLat = 14, .DivMode = DIV8_MODE, + + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 7, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 12, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 5, .trtw_odt_off_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 6, + .xrtr2w_odt_off = 6, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 13, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 1, + .tmrr2w_odt_off = 9, + .tmrr2w_odt_on = 11, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 +}, +//LPDDR4 4X_3200_BT_Div 8_DBI1.csv Read 1 +{ + .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, + .readLat = 36, .writeLat = 14, .DivMode = DIV8_MODE, + + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 15, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 13, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 7, + .xrtr2w_odt_off = 7, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 14, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 1, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 +}, +#else //ENABLE_READ_DBI == 0) +//LPDDR4 4X_3200_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 28, .writeLat = 14, .DivMode = DIV8_MODE, + + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 7, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 11, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 1, + .tmrr2w_odt_off = 8, + .tmrr2w_odt_on = 10, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 +}, +//LPDDR4 4X_3200_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 32, .writeLat = 14, .DivMode = DIV8_MODE, + + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 12, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 5, .trtw_odt_off_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 6, + .xrtr2w_odt_off = 6, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 13, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 1, + .tmrr2w_odt_off = 9, + .tmrr2w_odt_on = 11, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 +}, +#endif +#endif +#if SUPPORT_LP4_DDR2667_ACTIM + //LP4_DDR2667 ACTiming--------------------------------- +//LPDDR4 4X_2667_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 1333, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 24, .writeLat = 12, .DivMode = DIV8_MODE, + + .tras = 6, .tras_05T = 0, + .trp = 5, .trp_05T = 0, + .trpab = 6, .trpab_05T = 0, + .trc = 11, .trc_05T = 1, + .trfc = 81, .trfc_05T = 1, + .trfcpb = 35, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 10, .twr_05T = 0, + .twtr = 6, .twtr_05T = 0, + .tpbr2pbr = 23, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 1, + .tmrwckel = 6, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 9, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 5, .tfaw_05T = 1, + .tfaw_4266 = 2, .tfaw_4266_05T = 1, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 96, + .tzqcs = 29, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 34, + .hwset_mr2_op = 36, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 7, .trcd_derate_05T = 0, + .trc_derate = 13, .trc_derate_05T = 0, + .tras_derate = 6, .tras_derate_05T = 1, + .trpab_derate = 6, .trpab_derate_05T = 1, + .trp_derate = 5, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 1, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 11, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD +}, +//LPDDR4 4X_2667_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 1333, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 26, .writeLat = 12, .DivMode = DIV8_MODE, + + .tras = 6, .tras_05T = 0, + .trp = 5, .trp_05T = 0, + .trpab = 6, .trpab_05T = 0, + .trc = 11, .trc_05T = 1, + .trfc = 81, .trfc_05T = 1, + .trfcpb = 35, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 11, .twr_05T = 1, + .twtr = 7, .twtr_05T = 1, + .tpbr2pbr = 23, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 1, + .tmrwckel = 6, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 9, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 5, .tfaw_05T = 1, + .tfaw_4266 = 2, .tfaw_4266_05T = 1, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 96, + .tzqcs = 29, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 34, + .hwset_mr2_op = 36, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 7, .trcd_derate_05T = 0, + .trc_derate = 13, .trc_derate_05T = 0, + .tras_derate = 6, .tras_derate_05T = 1, + .trpab_derate = 6, .trpab_derate_05T = 1, + .trp_derate = 5, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 13, .twtpd_05T = 1, + .tmrr2w_odt_off = 7, + .tmrr2w_odt_on = 9, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 11, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD +}, +#endif +#if SUPPORT_LP4_DDR2400_ACTIM + //LP4_DDR2400 ACTiming--------------------------------- +//LPDDR4 4X_2400_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 1200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 24, .writeLat = 12, .DivMode = DIV8_MODE, + + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 9, .twr_05T = 1, + .twtr = 6, .twtr_05T = 1, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 1, + .twtpd = 12, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 4, .datlat = 13 +}, +//LPDDR4 4X_2400_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 1200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 26, .writeLat = 12, .DivMode = DIV8_MODE, + + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 10, .twr_05T = 0, + .twtr = 6, .twtr_05T = 0, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w_odt_off = 7, + .tmrr2w_odt_on = 9, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 4, .datlat = 13 +}, +#endif +#if SUPPORT_LP4_DDR1866_ACTIM + //LP4_DDR1866 ACTiming--------------------------------- +//LPDDR4 4X_1866_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 933, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 20, .writeLat = 10, .DivMode = DIV8_MODE, + + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 1, + .twtr = 5, .twtr_05T = 1, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 0, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 9, .trtpd_05T = 1, + .twtpd = 10, .twtpd_05T = 1, + .tmrr2w_odt_off = 5, + .tmrr2w_odt_on = 7, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 3, .datlat = 13 +}, +//LPDDR4 4X_1866_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 933, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 22, .writeLat = 10, .DivMode = DIV8_MODE, + + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 0, + .twtr = 5, .twtr_05T = 0, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 1, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 4, + .xrtr2w_odt_off = 4, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 0, + .twtpd = 11, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 3, .datlat = 13 +}, +#endif +#if SUPPORT_LP4_DDR1600_ACTIM + //LP4_DDR1600 ACTiming--------------------------------- +//LPDDR4 4X_1600_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 9, .tras_05T = 0, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 8, .trcd_05T = 0, + .twr = 15, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 7, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 11, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 6, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 7, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 10, .tras_derate_05T = 0, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 0, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 10 +}, +//LPDDR4 4X_1600_BT_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 9, .tras_05T = 0, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 8, .trcd_05T = 0, + .twr = 16, .twr_05T = 0, + .twtr = 11, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 7, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 11, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 8, .trtw_odt_off_05T = 0, + .trtw_odt_on = 12, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 6, + .xrtw2r_odt_off = 5, + .xrtr2w_odt_on = 11, + .xrtr2w_odt_off = 11, + .xrtr2r_new_mode = 7, + .xrtr2r_old_mode = 10, + .tr2mrr = 8, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 10, .tras_derate_05T = 0, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 0, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 16, .trtpd_05T = 0, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 10 +}, +//LPDDR4 4X_1600_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 10 +}, +//LPDDR4 4X_1600_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 0, + .twtr = 4, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 10 +}, +#endif +#if SUPPORT_LP4_DDR1333_ACTIM + //LP4_DDR1333 ACTiming--------------------------------- +//LPDDR4 4X_1333_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 6, .tras_05T = 0, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 11, .trc_05T = 0, + .trfc = 82, .trfc_05T = 0, + .trfcpb = 35, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 6, .trcd_05T = 0, + .twr = 14, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 23, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 9, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 6, .tfaw_05T = 0, + .tfaw_4266 = 2, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 96, + .tzqcs = 28, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 6, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 7, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 34, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 7, .trcd_derate_05T = 0, + .trc_derate = 13, .trc_derate_05T = 0, + .tras_derate = 7, .tras_derate_05T = 0, + .trpab_derate = 6, .trpab_derate_05T = 0, + .trp_derate = 5, .trp_derate_05T = 0, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 17, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 10, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD +}, +//LPDDR4 4X_1333_BT_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 6, .tras_05T = 0, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 11, .trc_05T = 0, + .trfc = 82, .trfc_05T = 0, + .trfcpb = 35, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 6, .trcd_05T = 0, + .twr = 15, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 23, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 9, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 6, .tfaw_05T = 0, + .tfaw_4266 = 2, .tfaw_4266_05T = 0, + .trtw_odt_off = 8, .trtw_odt_off_05T = 0, + .trtw_odt_on = 12, .trtw_odt_on_05T = 0, + .txrefcnt = 96, + .tzqcs = 28, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 6, + .xrtw2r_odt_off = 5, + .xrtr2w_odt_on = 11, + .xrtr2w_odt_off = 11, + .xrtr2r_new_mode = 7, + .xrtr2r_old_mode = 10, + .tr2mrr = 8, + .vrcgdis_prdcnt = 34, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 7, .trcd_derate_05T = 0, + .trc_derate = 13, .trc_derate_05T = 0, + .tras_derate = 7, .tras_derate_05T = 0, + .trpab_derate = 6, .trpab_derate_05T = 0, + .trp_derate = 5, .trp_derate_05T = 0, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 16, .trtpd_05T = 0, + .twtpd = 18, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 10, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD +}, +//LPDDR4 4X_1333_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 1, .trc_05T = 0, + .trfc = 35, .trfc_05T = 0, + .trfcpb = 11, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 8, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 48, + .tzqcs = 13, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 17, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 1, + .trc_derate = 2, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 8, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD +}, +//LPDDR4 4X_1333_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 1, .trc_05T = 0, + .trfc = 35, .trfc_05T = 0, + .trfcpb = 11, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 8, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 48, + .tzqcs = 13, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 17, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 1, + .trc_derate = 2, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 0, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD +}, +#endif +#if SUPPORT_LP4_DDR1200_ACTIM + //LP4_DDR1200 ACTiming--------------------------------- +//LPDDR4 4X_1200_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 5, .tras_05T = 0, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 10, .trc_05T = 0, + .trfc = 73, .trfc_05T = 0, + .trfcpb = 31, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 6, .trcd_05T = 0, + .twr = 13, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 21, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 5, .tfaw_05T = 0, + .tfaw_4266 = 2, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 6, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 7, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 11, .trc_derate_05T = 0, + .tras_derate = 6, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 0, + .trp_derate = 4, .trp_derate_05T = 0, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 17, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 10, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 9 +}, +//LPDDR4 4X_1200_BT_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 5, .tras_05T = 0, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 10, .trc_05T = 0, + .trfc = 73, .trfc_05T = 0, + .trfcpb = 31, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 6, .trcd_05T = 0, + .twr = 14, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 21, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 5, .tfaw_05T = 0, + .tfaw_4266 = 2, .tfaw_4266_05T = 0, + .trtw_odt_off = 8, .trtw_odt_off_05T = 0, + .trtw_odt_on = 12, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 6, + .xrtw2r_odt_off = 5, + .xrtr2w_odt_on = 11, + .xrtr2w_odt_off = 11, + .xrtr2r_new_mode = 7, + .xrtr2r_old_mode = 10, + .tr2mrr = 8, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 11, .trc_derate_05T = 0, + .tras_derate = 6, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 0, + .trp_derate = 4, .trp_derate_05T = 0, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 16, .trtpd_05T = 0, + .twtpd = 18, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 10, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 9 +}, +//LPDDR4 4X_1200_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 8, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 9 +}, +//LPDDR4 4X_1200_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 0, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 9 +}, +#endif +#if SUPPORT_LP4_DDR800_ACTIM + //LP4_DDR800 ACTiming--------------------------------- +//LPDDR4 4X_800_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 16, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 5, + .xrtr2w_odt_on = 9, + .xrtr2w_odt_off = 9, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 8, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 +}, +//LPDDR4 4X_800_BT_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 12, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 6, + .xrtw2r_odt_off = 4, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 16, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 +}, +//LPDDR4 4X_800_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 0, .trp_05T = 1, + .trpab = 1, .trpab_05T = 0, + .trc = 0, .trc_05T = 0, + .trfc = 16, .trfc_05T = 0, + .trfcpb = 2, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 2, .trcd_05T = 0, + .twr = 5, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 2, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 3, .tmrri_05T = 1, + .trrd = 0, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 29, + .tzqcs = 7, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 2, + .xrtr2w_odt_off = 2, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 10, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 2, .trcd_derate_05T = 0, + .trc_derate = 0, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 1, .trpab_derate_05T = 0, + .trp_derate = 0, .trp_derate_05T = 1, + .trrd_derate = 0, .trrd_derate_05T = 1, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 7, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 3, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 +}, +//LPDDR4 4X_800_BT_Div 8_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 0, .trp_05T = 1, + .trpab = 1, .trpab_05T = 0, + .trc = 0, .trc_05T = 0, + .trfc = 16, .trfc_05T = 0, + .trfcpb = 2, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 2, .trcd_05T = 0, + .twr = 5, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 2, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 3, .tmrri_05T = 1, + .trrd = 0, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 29, + .tzqcs = 7, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 10, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 2, .trcd_derate_05T = 0, + .trc_derate = 0, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 1, .trpab_derate_05T = 0, + .trp_derate = 0, .trp_derate_05T = 1, + .trrd_derate = 0, .trrd_derate_05T = 1, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 7, .twtpd_05T = 1, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 3, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 +}, +#endif +#if SUPPORT_LP4_DDR400_ACTIM + //LP4_DDR400 ACTiming--------------------------------- +//LPDDR4 4X_400_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 0, .trp_05T = 0, + .trpab = 1, .trpab_05T = 0, + .trc = 0, .trc_05T = 0, + .trfc = 16, .trfc_05T = 0, + .trfcpb = 2, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 2, .trcd_05T = 0, + .twr = 11, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 2, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 16, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 13, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 10, .trtw_odt_on_05T = 0, + .txrefcnt = 29, + .tzqcs = 7, + .xrtw2w_new_mode = 10, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 8, + .xrtw2r_odt_off = 8, + .xrtr2w_odt_on = 9, + .xrtr2w_odt_off = 9, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 8, + .tr2mrr = 8, + .vrcgdis_prdcnt = 10, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 2, .trcd_derate_05T = 0, + .trc_derate = 0, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 1, .trpab_derate_05T = 0, + .trp_derate = 0, .trp_derate_05T = 0, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 14, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 0, + .tmrr2w_odt_off = 9, + .tmrr2w_odt_on = 11, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 4, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 15 +}, +//LPDDR4 4X_400_BT_Div 4_DBI0.csv Read 0 +{ + .dramType = TYPE_LPDDR4, .freq = 200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, + + .tras = 0, .tras_05T = 0, + .trp = 0, .trp_05T = 0, + .trpab = 1, .trpab_05T = 0, + .trc = 0, .trc_05T = 0, + .trfc = 16, .trfc_05T = 0, + .trfcpb = 2, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 2, .trcd_05T = 0, + .twr = 11, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 2, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 29, + .tzqcs = 7, + .xrtw2w_new_mode = 10, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 7, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 10, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 2, .trcd_derate_05T = 0, + .trc_derate = 0, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 1, .trpab_derate_05T = 0, + .trp_derate = 0, .trp_derate_05T = 0, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 4, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 15 +}, +#endif +}; + +#if (__LP5_COMBO__) + const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5] = { + //----------LPDDR5--------------------------- + #if SUPPORT_LP5_DDR6400_ACTIM + //LP5_DDR6400 ACTiming--------------------------------- + #if (ENABLE_READ_DBI == 1) + //LPDDR5_6400_Div 16_DBI1.csv Read 1 + { + .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, + + //BL (burst length) = 16, DRMC_Clock_Rate = 400.0 + .readLat = 20, .writeLat = 9, .DivMode = DIV16_MODE, + + .tras = 8, .tras_05T = 0, + .trp = 7, .trp_05T = 1, + .trpab = 8, .trpab_05T = 1, + .trc = 16, .trc_05T = 1, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 2, .txp_05T = 1, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 19, .twr_05T = 0, + .twtr = 6, .twtr_05T = 0, + .twtr_l = 10, .twtr_l_05T = 0, + .tpbr2pbr = 28, .tpbr2pbr_05T = 0, + .tpbr2act = 2, .tpbr2act_05T = 0, + .tr2mrw = 15, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 1, + .tmrr2mrw = 13, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 5, .tr2w_odt_off_05T = 1, + .tr2w_odt_on = 7, .tr2w_odt_on_05T = 0, + .txrefcnt = 115, + .wckrdoff = 13, .wckrdoff_05T = 0, + .wckwroff = 7, .wckwroff_05T = 1, + .tzqcs = 34, + .xrtw2w_odt_off = 2, + .xrtw2w_odt_on = 3, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 8, + .xrtr2w_odt_on = 9, + .xrtr2r_odt_off = 6, + .xrtr2r_odt_on = 6, + .xrtw2w_odt_off_wck = 6, + .xrtw2w_odt_on_wck = 8, + .xrtw2r_odt_off_wck = 3, + .xrtw2r_odt_on_wck = 4, + .xrtr2w_odt_off_wck = 11, + .xrtr2w_odt_on_wck = 11, + .xrtr2r_wck = 8, + .tr2mrr = 4, + .hwset_mr2_op = 187, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 176, + .vrcgdis_prdcnt = 40, + .lp5_cmd1to2en = 0, + .trtpd = 13, .trtpd_05T = 1, + .twtpd = 21, .twtpd_05T = 1, + .tmrr2w = 16, + .ckeprd = 2, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 10, .tras_derate_05T = 0, + .trpab_derate = 7, .trpab_derate_05T = 1, + .trp_derate = 6, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 10 + }, + //LPDDR5_6400_BT_Div 16_DBI1.csv Read 1 + { + .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, + //BL (burst length) = 16, DRMC_Clock_Rate = 400.0 + .readLat = 18, .writeLat = 9, .DivMode = DIV16_MODE, + + .tras = 8, .tras_05T = 0, + .trp = 7, .trp_05T = 1, + .trpab = 8, .trpab_05T = 1, + .trc = 16, .trc_05T = 1, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 2, .txp_05T = 1, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 18, .twr_05T = 1, + .twtr = 5, .twtr_05T = 0, + .twtr_l = 9, .twtr_l_05T = 0, + .tpbr2pbr = 28, .tpbr2pbr_05T = 0, + .tpbr2act = 2, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 1, + .tmrr2mrw = 12, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1, + .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0, + .txrefcnt = 115, + .wckrdoff = 12, .wckrdoff_05T = 0, + .wckwroff = 7, .wckwroff_05T = 1, + .tzqcs = 34, + .xrtw2w_odt_off = 2, + .xrtw2w_odt_on = 3, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 7, + .xrtr2w_odt_on = 8, + .xrtr2r_odt_off = 6, + .xrtr2r_odt_on = 6, + .xrtw2w_odt_off_wck = 6, + .xrtw2w_odt_on_wck = 8, + .xrtw2r_odt_off_wck = 4, + .xrtw2r_odt_on_wck = 5, + .xrtr2w_odt_off_wck = 10, + .xrtr2w_odt_on_wck = 10, + .xrtr2r_wck = 8, + .tr2mrr = 3, + .hwset_mr2_op = 187, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 176, + .vrcgdis_prdcnt = 40, + .lp5_cmd1to2en = 0, + .trtpd = 12, .trtpd_05T = 1, + .twtpd = 21, .twtpd_05T = 0, + .tmrr2w = 15, + .ckeprd = 2, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 10, .tras_derate_05T = 0, + .trpab_derate = 7, .trpab_derate_05T = 1, + .trp_derate = 6, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 10 + }, + #else //ENABLE_READ_DBI == 0) + //LPDDR5_6400_Div 16_DBI0.csv Read 0 + { + .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + //BL (burst length) = 16, DRMC_Clock_Rate = 400.0 + .readLat = 18, .writeLat = 9, .DivMode = DIV16_MODE, + + .tras = 8, .tras_05T = 0, + .trp = 7, .trp_05T = 1, + .trpab = 8, .trpab_05T = 1, + .trc = 16, .trc_05T = 1, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 2, .txp_05T = 1, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 19, .twr_05T = 0, + .twtr = 6, .twtr_05T = 0, + .twtr_l = 10, .twtr_l_05T = 0, + .tpbr2pbr = 28, .tpbr2pbr_05T = 0, + .tpbr2act = 2, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 1, + .tmrr2mrw = 12, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1, + .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0, + .txrefcnt = 115, + .wckrdoff = 12, .wckrdoff_05T = 0, + .wckwroff = 7, .wckwroff_05T = 1, + .tzqcs = 34, + .xrtw2w_odt_off = 2, + .xrtw2w_odt_on = 3, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 7, + .xrtr2w_odt_on = 8, + .xrtr2r_odt_off = 6, + .xrtr2r_odt_on = 6, + .xrtw2w_odt_off_wck = 6, + .xrtw2w_odt_on_wck = 8, + .xrtw2r_odt_off_wck = 4, + .xrtw2r_odt_on_wck = 5, + .xrtr2w_odt_off_wck = 10, + .xrtr2w_odt_on_wck = 10, + .xrtr2r_wck = 8, + .tr2mrr = 3, + .hwset_mr2_op = 187, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 176, + .vrcgdis_prdcnt = 40, + .lp5_cmd1to2en = 0, + .trtpd = 12, .trtpd_05T = 1, + .twtpd = 21, .twtpd_05T = 1, + .tmrr2w = 15, + .ckeprd = 2, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 10, .tras_derate_05T = 0, + .trpab_derate = 7, .trpab_derate_05T = 1, + .trp_derate = 6, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 10 + }, + //LPDDR5_6400_BT_Div 16_DBI0.csv Read 0 + { + .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + //BL (burst length) = 16, DRMC_Clock_Rate = 400.0 + .readLat = 17, .writeLat = 9, .DivMode = DIV16_MODE, + + .tras = 8, .tras_05T = 0, + .trp = 7, .trp_05T = 1, + .trpab = 8, .trpab_05T = 1, + .trc = 16, .trc_05T = 1, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 2, .txp_05T = 1, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 18, .twr_05T = 1, + .twtr = 5, .twtr_05T = 0, + .twtr_l = 9, .twtr_l_05T = 0, + .tpbr2pbr = 28, .tpbr2pbr_05T = 0, + .tpbr2act = 2, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 1, + .tmrr2mrw = 11, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1, + .txrefcnt = 115, + .wckrdoff = 11, .wckrdoff_05T = 1, + .wckwroff = 7, .wckwroff_05T = 1, + .tzqcs = 34, + .xrtw2w_odt_off = 2, + .xrtw2w_odt_on = 3, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 7, + .xrtr2w_odt_on = 7, + .xrtr2r_odt_off = 6, + .xrtr2r_odt_on = 6, + .xrtw2w_odt_off_wck = 6, + .xrtw2w_odt_on_wck = 8, + .xrtw2r_odt_off_wck = 4, + .xrtw2r_odt_on_wck = 5, + .xrtr2w_odt_off_wck = 10, + .xrtr2w_odt_on_wck = 10, + .xrtr2r_wck = 8, + .tr2mrr = 2, + .hwset_mr2_op = 187, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 176, + .vrcgdis_prdcnt = 40, + .lp5_cmd1to2en = 0, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 21, .twtpd_05T = 0, + .tmrr2w = 15, + .ckeprd = 2, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 10, .tras_derate_05T = 0, + .trpab_derate = 7, .trpab_derate_05T = 1, + .trp_derate = 6, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 10 + }, + #endif + #endif + #if SUPPORT_LP5_DDR5500_ACTIM + //LP5_DDR5500 ACTiming--------------------------------- + #if ((ENABLE_READ_DBI == 1) || (LP5_DDR4266_RDBI_WORKAROUND == 1)) + //F5500_Div16_DB1_NT0_RG0_EC0.csv Read 1 + { + .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, + + //BL (burst length) = 16, DRMC_Clock_Rate = 343.75 + .readLat = 17, .writeLat = 8, .DivMode = DIV16_MODE, + + .tras = 5, .tras_05T = 1, + .trp = 6, .trp_05T = 1, + .trpab = 7, .trpab_05T = 1, + .trc = 13, .trc_05T = 0, + .trfc = 84, .trfc_05T = 1, + .trfcpb = 36, .trfcpb_05T = 1, + .txp = 2, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 16, .twr_05T = 1, + .twtr = 5, .twtr_05T = 0, + .twtr_l = 8, .twtr_l_05T = 1, + .tpbr2pbr = 23, .tpbr2pbr_05T = 0, + .tpbr2act = 2, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 11, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 1, + .tmrd = 5, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1, + .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0, + .txrefcnt = 99, + .wckrdoff = 11, .wckrdoff_05T = 1, + .wckwroff = 7, .wckwroff_05T = 0, + .tzqcs = 29, + .xrtw2w_odt_off = 2, + .xrtw2w_odt_on = 3, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 7, + .xrtr2w_odt_on = 8, + .xrtr2r_odt_off = 6, + .xrtr2r_odt_on = 6, + .xrtw2w_odt_off_wck = 6, + .xrtw2w_odt_on_wck = 8, + .xrtw2r_odt_off_wck = 3, + .xrtw2r_odt_on_wck = 4, + .xrtr2w_odt_off_wck = 10, + .xrtr2w_odt_on_wck = 10, + .xrtr2r_wck = 8, + .tr2mrr = 2, + .hwset_mr2_op = 153, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 144, + .vrcgdis_prdcnt = 35, + .lp5_cmd1to2en = 0, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w = 15, + .ckeprd = 2, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 7, .trcd_derate_05T = 0, + .trc_derate = 13, .trc_derate_05T = 1, + .tras_derate = 7, .tras_derate_05T = 0, + .trpab_derate = 6, .trpab_derate_05T = 0, + .trp_derate = 5, .trp_derate_05T = 0, + .trrd_derate = 1, .trrd_derate_05T = 1, + .zqlat2 = 11, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 19 + }, + //LPDDR5_DDR5500_Div 16_RDBI_ON_CBT_NORMAL_MODE + { + .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, + //BL (burst length) = 16, DRMC_Clock_Rate = 343.75 + .readLat = 16, .writeLat = 8, .DivMode = DIV16_MODE, + + .tras = 5, .tras_05T = 1, + .trp = 6, .trp_05T = 1, + .trpab = 7, .trpab_05T = 1, + .trc = 13, .trc_05T = 0, + .trfc = 84, .trfc_05T = 1, + .trfcpb = 36, .trfcpb_05T = 1, + .txp = 2, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 16, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .twtr_l = 8, .twtr_l_05T = 0, + .tpbr2pbr = 23, .tpbr2pbr_05T = 0, + .tpbr2act = 2, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 11, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 1, + .tmrd = 5, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1, + .txrefcnt = 99, + .wckrdoff = 11, .wckrdoff_05T = 0, + .wckwroff = 7, .wckwroff_05T = 0, + .tzqcs = 29, + .xrtw2w_odt_off = 2, + .xrtw2w_odt_on = 3, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 7, + .xrtr2w_odt_on = 7, + .xrtr2r_odt_off = 6, + .xrtr2r_odt_on = 6, + .xrtw2w_odt_off_wck = 6, + .xrtw2w_odt_on_wck = 8, + .xrtw2r_odt_off_wck = 4, + .xrtw2r_odt_on_wck = 5, + .xrtr2w_odt_off_wck = 10, + .xrtr2w_odt_on_wck = 10, + .xrtr2r_wck = 8, + .tr2mrr = 2, + .hwset_mr2_op = 153, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 144, + .vrcgdis_prdcnt = 35, + .lp5_cmd1to2en = 0, + .trtpd = 11, .trtpd_05T = 1, + .twtpd = 18, .twtpd_05T = 1, + .tmrr2w = 14, + .ckeprd = 2, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 7, .trcd_derate_05T = 0, + .trc_derate = 13, .trc_derate_05T = 1, + .tras_derate = 7, .tras_derate_05T = 0, + .trpab_derate = 6, .trpab_derate_05T = 0, + .trp_derate = 5, .trp_derate_05T = 0, + .trrd_derate = 1, .trrd_derate_05T = 1, + .zqlat2 = 11, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 19 + }, + #else //ENABLE_READ_DBI == 0 + //LPDDR5_DDR5500_Div 16_RDBI_OFF_CBT_BYTE_MODE1 + { + .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + //BL (burst length) = 16, DRMC_Clock_Rate = 343.75 + .readLat = 16, .writeLat = 8, .DivMode = DIV16_MODE, + + .tras = 5, .tras_05T = 1, + .trp = 6, .trp_05T = 1, + .trpab = 7, .trpab_05T = 1, + .trc = 13, .trc_05T = 0, + .trfc = 84, .trfc_05T = 1, + .trfcpb = 36, .trfcpb_05T = 1, + .txp = 2, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 16, .twr_05T = 1, + .twtr = 5, .twtr_05T = 0, + .twtr_l = 8, .twtr_l_05T = 1, + .tpbr2pbr = 23, .tpbr2pbr_05T = 0, + .tpbr2act = 2, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 11, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 1, + .tmrd = 5, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1, + .txrefcnt = 99, + .wckrdoff = 11, .wckrdoff_05T = 0, + .wckwroff = 7, .wckwroff_05T = 0, + .tzqcs = 29, + .xrtw2w_odt_off = 2, + .xrtw2w_odt_on = 3, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 7, + .xrtr2w_odt_on = 7, + .xrtr2r_odt_off = 6, + .xrtr2r_odt_on = 6, + .xrtw2w_odt_off_wck = 6, + .xrtw2w_odt_on_wck = 8, + .xrtw2r_odt_off_wck = 4, + .xrtw2r_odt_on_wck = 5, + .xrtr2w_odt_off_wck = 10, + .xrtr2w_odt_on_wck = 10, + .xrtr2r_wck = 8, + .tr2mrr = 2, + .hwset_mr2_op = 153, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 144, + .vrcgdis_prdcnt = 35, + .lp5_cmd1to2en = 0, + .trtpd = 11, .trtpd_05T = 1, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w = 14, + .ckeprd = 2, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 7, .trcd_derate_05T = 0, + .trc_derate = 13, .trc_derate_05T = 1, + .tras_derate = 7, .tras_derate_05T = 0, + .trpab_derate = 6, .trpab_derate_05T = 0, + .trp_derate = 5, .trp_derate_05T = 0, + .trrd_derate = 1, .trrd_derate_05T = 1, + .zqlat2 = 11, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 19 + }, + { + .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + //BL (burst length) = 16, DRMC_Clock_Rate = 343.75 + .readLat = 15, .writeLat = 8, .DivMode = DIV16_MODE, + + .tras = 5, .tras_05T = 1, + .trp = 6, .trp_05T = 1, + .trpab = 7, .trpab_05T = 1, + .trc = 13, .trc_05T = 0, + .trfc = 84, .trfc_05T = 1, + .trfcpb = 36, .trfcpb_05T = 1, + .txp = 2, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 16, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .twtr_l = 8, .twtr_l_05T = 0, + .tpbr2pbr = 23, .tpbr2pbr_05T = 0, + .tpbr2act = 2, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 1, + .tmrd = 5, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 3, .tr2w_odt_off_05T = 1, + .tr2w_odt_on = 5, .tr2w_odt_on_05T = 0, + .txrefcnt = 99, + .wckrdoff = 10, .wckrdoff_05T = 1, + .wckwroff = 7, .wckwroff_05T = 0, + .tzqcs = 29, + .xrtw2w_odt_off = 2, + .xrtw2w_odt_on = 3, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 1, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 6, + .xrtr2w_odt_on = 7, + .xrtr2r_odt_off = 6, + .xrtr2r_odt_on = 6, + .xrtw2w_odt_off_wck = 6, + .xrtw2w_odt_on_wck = 8, + .xrtw2r_odt_off_wck = 4, + .xrtw2r_odt_on_wck = 5, + .xrtr2w_odt_off_wck = 9, + .xrtr2w_odt_on_wck = 9, + .xrtr2r_wck = 8, + .tr2mrr = 1, + .hwset_mr2_op = 153, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 144, + .vrcgdis_prdcnt = 35, + .lp5_cmd1to2en = 0, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 18, .twtpd_05T = 1, + .tmrr2w = 14, + .ckeprd = 2, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 7, .trcd_derate_05T = 0, + .trc_derate = 13, .trc_derate_05T = 1, + .tras_derate = 7, .tras_derate_05T = 0, + .trpab_derate = 6, .trpab_derate_05T = 0, + .trp_derate = 5, .trp_derate_05T = 0, + .trrd_derate = 1, .trrd_derate_05T = 1, + .zqlat2 = 11, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 19 + }, + #endif + #endif + #if SUPPORT_LP5_DDR4266_ACTIM + //LP5_DDR4266 ACTiming--------------------------------- + #if ((ENABLE_READ_DBI == 1) || (LP5_DDR4266_RDBI_WORKAROUND == 1)) + //LPDDR5_4266_Div 8_CKR4_DBI1.csv Read 1 + { + .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, + + //BL (burst length) = 16, DRMC_Clock_Rate = 533.25 + .readLat = 14, .writeLat = 6, .DivMode = DIV8_MODE, + + .tras = 14, .tras_05T = 0, + .trp = 10, .trp_05T = 0, + .trpab = 12, .trpab_05T = 0, + .trc = 25, .trc_05T = 0, + .trfc = 138, .trfc_05T = 0, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 5, .txp_05T = 0, + .trtp = 4, .trtp_05T = 0, + .trcd = 10, .trcd_05T = 0, + .twr = 27, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .twtr_l = 16, .twtr_l_05T = 0, + .tpbr2pbr = 40, .tpbr2pbr_05T = 0, + .tpbr2act = 3, .tpbr2act_05T = 0, + .tr2mrw = 23, .tr2mrw_05T = 0, + .tw2mrw = 14, .tw2mrw_05T = 0, + .tmrr2mrw = 21, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 9, .tmrd_05T = 0, + .tmrwckel = 13, .tmrwckel_05T = 0, + .tpde = 5, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 17, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .tfaw = 3, .tfaw_05T = 0, + .tr2w_odt_off = 11, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 15, .tr2w_odt_on_05T = 0, + .txrefcnt = 154, + .wckrdoff = 20, .wckrdoff_05T = 0, + .wckwroff = 12, .wckwroff_05T = 0, + .tzqcs = 46, + .xrtw2w_odt_off = 5, + .xrtw2w_odt_on = 7, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 12, + .xrtr2w_odt_on = 14, + .xrtr2r_odt_off = 9, + .xrtr2r_odt_on = 9, + .xrtw2w_odt_off_wck = 10, + .xrtw2w_odt_on_wck = 12, + .xrtw2r_odt_off_wck = 6, + .xrtw2r_odt_on_wck = 7, + .xrtr2w_odt_off_wck = 18, + .xrtr2w_odt_on_wck = 18, + .xrtr2r_wck = 14, + .tr2mrr = 13, + .hwset_mr2_op = 119, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 112, + .vrcgdis_prdcnt = 54, + .lp5_cmd1to2en = 1, + .trtpd = 19, .trtpd_05T = 0, + .twtpd = 31, .twtpd_05T = 0, + .tmrr2w = 23, + .ckeprd = 3, + .ckelckcnt = 5, + .tcsh_cscal = 5, + .tcacsh = 3, + .tcsh = 4, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 17, .tras_derate_05T = 0, + .trpab_derate = 10, .trpab_derate_05T = 0, + .trp_derate = 8, .trp_derate_05T = 0, + .trrd_derate = 3, .trrd_derate_05T = 0, + .zqlat2 = 16, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 10, .datlat = 19 + }, + //LPDDR5_4266_BT_Div 8_CKR4_DBI1.csv Read 1 + { + .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, + //BL (burst length) = 16, DRMC_Clock_Rate = 533.25 + .readLat = 13, .writeLat = 6, .DivMode = DIV8_MODE, + + .tras = 14, .tras_05T = 0, + .trp = 10, .trp_05T = 0, + .trpab = 12, .trpab_05T = 0, + .trc = 25, .trc_05T = 0, + .trfc = 138, .trfc_05T = 0, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 5, .txp_05T = 0, + .trtp = 4, .trtp_05T = 0, + .trcd = 10, .trcd_05T = 0, + .twr = 26, .twr_05T = 0, + .twtr = 9, .twtr_05T = 0, + .twtr_l = 15, .twtr_l_05T = 0, + .tpbr2pbr = 40, .tpbr2pbr_05T = 0, + .tpbr2act = 3, .tpbr2act_05T = 0, + .tr2mrw = 22, .tr2mrw_05T = 0, + .tw2mrw = 14, .tw2mrw_05T = 0, + .tmrr2mrw = 20, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 9, .tmrd_05T = 0, + .tmrwckel = 13, .tmrwckel_05T = 0, + .tpde = 5, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 17, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .tfaw = 3, .tfaw_05T = 0, + .tr2w_odt_off = 10, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 14, .tr2w_odt_on_05T = 0, + .txrefcnt = 154, + .wckrdoff = 19, .wckrdoff_05T = 0, + .wckwroff = 12, .wckwroff_05T = 0, + .tzqcs = 46, + .xrtw2w_odt_off = 5, + .xrtw2w_odt_on = 7, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 11, + .xrtr2w_odt_on = 13, + .xrtr2r_odt_off = 9, + .xrtr2r_odt_on = 9, + .xrtw2w_odt_off_wck = 10, + .xrtw2w_odt_on_wck = 12, + .xrtw2r_odt_off_wck = 7, + .xrtw2r_odt_on_wck = 8, + .xrtr2w_odt_off_wck = 17, + .xrtr2w_odt_on_wck = 17, + .xrtr2r_wck = 14, + .tr2mrr = 12, + .hwset_mr2_op = 119, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 112, + .vrcgdis_prdcnt = 54, + .lp5_cmd1to2en = 1, + .trtpd = 18, .trtpd_05T = 0, + .twtpd = 30, .twtpd_05T = 0, + .tmrr2w = 22, + .ckeprd = 3, + .ckelckcnt = 5, + .tcsh_cscal = 5, + .tcacsh = 3, + .tcsh = 4, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 17, .tras_derate_05T = 0, + .trpab_derate = 10, .trpab_derate_05T = 0, + .trp_derate = 8, .trp_derate_05T = 0, + .trrd_derate = 3, .trrd_derate_05T = 0, + .zqlat2 = 16, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 10, .datlat = 19 + }, + #else //ENABLE_READ_DBI == 0) + //LPDDR5_4266_Div 8_CKR4_DBI0.csv Read 0 + { + .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + //BL (burst length) = 16, DRMC_Clock_Rate = 533.25 + .readLat = 13, .writeLat = 6, .DivMode = DIV8_MODE, + + .tras = 14, .tras_05T = 0, + .trp = 10, .trp_05T = 0, + .trpab = 12, .trpab_05T = 0, + .trc = 25, .trc_05T = 0, + .trfc = 138, .trfc_05T = 0, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 5, .txp_05T = 0, + .trtp = 4, .trtp_05T = 0, + .trcd = 10, .trcd_05T = 0, + .twr = 27, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .twtr_l = 16, .twtr_l_05T = 0, + .tpbr2pbr = 40, .tpbr2pbr_05T = 0, + .tpbr2act = 3, .tpbr2act_05T = 0, + .tr2mrw = 22, .tr2mrw_05T = 0, + .tw2mrw = 14, .tw2mrw_05T = 0, + .tmrr2mrw = 20, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 9, .tmrd_05T = 0, + .tmrwckel = 13, .tmrwckel_05T = 0, + .tpde = 5, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 17, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .tfaw = 3, .tfaw_05T = 0, + .tr2w_odt_off = 10, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 14, .tr2w_odt_on_05T = 0, + .txrefcnt = 154, + .wckrdoff = 19, .wckrdoff_05T = 0, + .wckwroff = 12, .wckwroff_05T = 0, + .tzqcs = 46, + .xrtw2w_odt_off = 5, + .xrtw2w_odt_on = 7, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 0, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 11, + .xrtr2w_odt_on = 13, + .xrtr2r_odt_off = 9, + .xrtr2r_odt_on = 9, + .xrtw2w_odt_off_wck = 10, + .xrtw2w_odt_on_wck = 12, + .xrtw2r_odt_off_wck = 7, + .xrtw2r_odt_on_wck = 8, + .xrtr2w_odt_off_wck = 17, + .xrtr2w_odt_on_wck = 17, + .xrtr2r_wck = 14, + .tr2mrr = 12, + .hwset_mr2_op = 119, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 112, + .vrcgdis_prdcnt = 54, + .lp5_cmd1to2en = 1, + .trtpd = 18, .trtpd_05T = 0, + .twtpd = 31, .twtpd_05T = 0, + .tmrr2w = 22, + .ckeprd = 3, + .ckelckcnt = 5, + .tcsh_cscal = 5, + .tcacsh = 3, + .tcsh = 4, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 17, .tras_derate_05T = 0, + .trpab_derate = 10, .trpab_derate_05T = 0, + .trp_derate = 8, .trp_derate_05T = 0, + .trrd_derate = 3, .trrd_derate_05T = 0, + .zqlat2 = 16, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 10, .datlat = 19 + }, + //LPDDR5_4266_BT_Div 8_CKR4_DBI0.csv Read 0 + { + .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + //BL (burst length) = 16, DRMC_Clock_Rate = 533.25 + .readLat = 12, .writeLat = 6, .DivMode = DIV8_MODE, + + .tras = 14, .tras_05T = 0, + .trp = 10, .trp_05T = 0, + .trpab = 12, .trpab_05T = 0, + .trc = 25, .trc_05T = 0, + .trfc = 138, .trfc_05T = 0, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 5, .txp_05T = 0, + .trtp = 4, .trtp_05T = 0, + .trcd = 10, .trcd_05T = 0, + .twr = 26, .twr_05T = 0, + .twtr = 9, .twtr_05T = 0, + .twtr_l = 15, .twtr_l_05T = 0, + .tpbr2pbr = 40, .tpbr2pbr_05T = 0, + .tpbr2act = 3, .tpbr2act_05T = 0, + .tr2mrw = 21, .tr2mrw_05T = 0, + .tw2mrw = 14, .tw2mrw_05T = 0, + .tmrr2mrw = 19, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 9, .tmrd_05T = 0, + .tmrwckel = 13, .tmrwckel_05T = 0, + .tpde = 5, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 17, .tmrri_05T = 0, + .trrd = 3, .trrd_05T = 0, + .tfaw = 3, .tfaw_05T = 0, + .tr2w_odt_off = 9, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 13, .tr2w_odt_on_05T = 0, + .txrefcnt = 154, + .wckrdoff = 18, .wckrdoff_05T = 0, + .wckwroff = 12, .wckwroff_05T = 0, + .tzqcs = 46, + .xrtw2w_odt_off = 5, + .xrtw2w_odt_on = 7, + .xrtw2r_odt_off_otf_off = 0, + .xrtw2r_odt_on_otf_off = 1, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 10, + .xrtr2w_odt_on = 12, + .xrtr2r_odt_off = 9, + .xrtr2r_odt_on = 9, + .xrtw2w_odt_off_wck = 10, + .xrtw2w_odt_on_wck = 12, + .xrtw2r_odt_off_wck = 8, + .xrtw2r_odt_on_wck = 9, + .xrtr2w_odt_off_wck = 16, + .xrtr2w_odt_on_wck = 16, + .xrtr2r_wck = 14, + .tr2mrr = 11, + .hwset_mr2_op = 119, + .hwset_mr13_op = 74, + .hwset_vrcg_op = 112, + .vrcgdis_prdcnt = 54, + .lp5_cmd1to2en = 1, + .trtpd = 17, .trtpd_05T = 0, + .twtpd = 30, .twtpd_05T = 0, + .tmrr2w = 21, + .ckeprd = 3, + .ckelckcnt = 5, + .tcsh_cscal = 5, + .tcacsh = 3, + .tcsh = 4, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 17, .tras_derate_05T = 0, + .trpab_derate = 10, .trpab_derate_05T = 0, + .trp_derate = 8, .trp_derate_05T = 0, + .trrd_derate = 3, .trrd_derate_05T = 0, + .zqlat2 = 16, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 10, .datlat = 19 + }, + #endif + #endif + #if SUPPORT_LP5_DDR3200_ACTIM + //LP5_DDR3200 ACTiming--------------------------------- + //LPDDR5_3200_Div 8_CKR2_DBI1.csv Read 0 + { + .dramType = TYPE_LPDDR5, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, + + //BL (burst length) = 16, DRMC_Clock_Rate = 400.0 + .readLat = 20, .writeLat = 10, .DivMode = DIV8_MODE, + + .tras = 8, .tras_05T = 0, + .trp = 7, .trp_05T = 1, + .trpab = 8, .trpab_05T = 1, + .trc = 16, .trc_05T = 1, + .trfc = 140, .trfc_05T = 0, + .trfcpb = 64, .trfcpb_05T = 0, + .txp = 2, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 7, .trcd_05T = 1, + .twr = 19, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .twtr_l = 10, .twtr_l_05T = 0, + .tpbr2pbr = 36, .tpbr2pbr_05T = 0, + .tpbr2act = 3, .tpbr2act_05T = 0, + .tr2mrw = 15, .tr2mrw_05T = 0, + .tw2mrw = 10, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0, + .txrefcnt = 115, + .wckrdoff = 13, .wckrdoff_05T = 0, + .wckwroff = 8, .wckwroff_05T = 0, + .tzqcs = 34, + .xrtw2w_odt_off = 6, + .xrtw2w_odt_on = 9, + .xrtw2r_odt_off_otf_off = 3, + .xrtw2r_odt_on_otf_off = 3, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 9, + .xrtr2w_odt_on = 10, + .xrtr2r_odt_off = 8, + .xrtr2r_odt_on = 8, + .xrtw2w_odt_off_wck = 7, + .xrtw2w_odt_on_wck = 9, + .xrtw2r_odt_off_wck = 5, + .xrtw2r_odt_on_wck = 6, + .xrtr2w_odt_off_wck = 12, + .xrtr2w_odt_on_wck = 12, + .xrtr2r_wck = 10, + .tr2mrr = 3, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .vrcgdis_prdcnt = 40, + .lp5_cmd1to2en = 0, + .trtpd = 13, .trtpd_05T = 1, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w = 16, + .ckeprd = 4, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 10, .tras_derate_05T = 0, + .trpab_derate = 7, .trpab_derate_05T = 1, + .trp_derate = 6, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 15 + }, + //LPDDR5_3200_BT_Div 8_CKR2_DBI1.csv Read 0 + { + .dramType = TYPE_LPDDR5, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, + //BL (burst length) = 16, DRMC_Clock_Rate = 400.0 + .readLat = 18, .writeLat = 10, .DivMode = DIV8_MODE, + + .tras = 8, .tras_05T = 0, + .trp = 7, .trp_05T = 1, + .trpab = 8, .trpab_05T = 1, + .trc = 16, .trc_05T = 1, + .trfc = 140, .trfc_05T = 0, + .trfcpb = 64, .trfcpb_05T = 0, + .txp = 2, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 7, .trcd_05T = 1, + .twr = 19, .twr_05T = -2, + .twtr = 9, .twtr_05T = 0, + .twtr_l = 9, .twtr_l_05T = 0, + .tpbr2pbr = 36, .tpbr2pbr_05T = 0, + .tpbr2act = 3, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 0, + .tw2mrw = 10, .tw2mrw_05T = 0, + .tmrr2mrw = 13, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 8, .tmrwckel_05T = 1, + .tpde = 2, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 1, + .tmrri = 12, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tr2w_odt_off = 3, .tr2w_odt_off_05T = 0, + .tr2w_odt_on = 5, .tr2w_odt_on_05T = 0, + .txrefcnt = 115, + .wckrdoff = 12, .wckrdoff_05T = 0, + .wckwroff = 8, .wckwroff_05T = 0, + .tzqcs = 34, + .xrtw2w_odt_off = 6, + .xrtw2w_odt_on = 9, + .xrtw2r_odt_off_otf_off = 3, + .xrtw2r_odt_on_otf_off = 3, + .xrtw2r_odt_off_otf_on = 3, + .xrtw2r_odt_on_otf_on = 3, + .xrtr2w_odt_off = 8, + .xrtr2w_odt_on = 9, + .xrtr2r_odt_off = 8, + .xrtr2r_odt_on = 8, + .xrtw2w_odt_off_wck = 7, + .xrtw2w_odt_on_wck = 9, + .xrtw2r_odt_off_wck = 6, + .xrtw2r_odt_on_wck = 7, + .xrtr2w_odt_off_wck = 11, + .xrtr2w_odt_on_wck = 11, + .xrtr2r_wck = 10, + .tr2mrr = 2, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .vrcgdis_prdcnt = 40, + .lp5_cmd1to2en = 0, + .trtpd = 12, .trtpd_05T = 1, + .twtpd = 12, .twtpd_05T = 0, + .tmrr2w = 15, + .ckeprd = 4, + .ckelckcnt = 3, + .tcsh_cscal = 3, + .tcacsh = 2, + .tcsh = 5, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 10, .tras_derate_05T = 0, + .trpab_derate = 7, .trpab_derate_05T = 1, + .trp_derate = 6, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .zqlat2 = 12, + + //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 15 + }, + #endif + }; +#endif diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c new file mode 100644 index 0000000000..f053ec4690 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c @@ -0,0 +1,23710 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//#include "svdpi.h" +//#include "vc_hdrs.h" +#include "dramc_common.h" +#include "dramc_int_global.h" +#include "x_hal_io.h" +//#include "./dramc_actiming.h" +#include "dramc_dv_init.h" + + +#if 0 + #include "./drivers/DRAMC_SUBSYS_config.c" + #include "./drivers/ANA_init_config.c" + #include "./drivers/DIG_NONSHUF_config.c" + #include "./drivers/DRAM_config_collctioin.c" + #include "./drivers/LP4_dram_init.c" + #include "./drivers/LP5_dram_init.c" + #include "./drivers/DIG_SHUF_config.c" +#endif + +#if 0 +void CInit_ConfigFromTBA(void) +{ + TbaConfig.dramc_dram_ratio = 4; + TbaConfig.channel = 0; + TbaConfig.dram_type = 4; + TbaConfig.shu_type = 0; + TbaConfig.dram_cbt_mode_RK0 = 1; + TbaConfig.dram_cbt_mode_RK1 = 1; + TbaConfig.DBI_R_onoff_FSP0 = 0; + TbaConfig.DBI_R_onoff_FSP1 = 0; + TbaConfig.frequency = 1600; + TbaConfig.voltage_state = 3; + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dramc_dram_ratio = %1d\n", TbaConfig.dramc_dram_ratio)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: channel = %1d\n", TbaConfig.channel)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_type = %1d\n", TbaConfig.dram_type)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: shu_type = %1d\n", TbaConfig.shu_type)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_cbt_mode_RK0 = %1d\n", TbaConfig.dram_cbt_mode_RK0)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_cbt_mode_RK1 = %1d\n", TbaConfig.dram_cbt_mode_RK1)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: DBI_R_onoff_FSP0 = %1d\n", TbaConfig.DBI_R_onoff_FSP0)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: DBI_R_onoff_FSP1 = %1d\n", TbaConfig.DBI_R_onoff_FSP1)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: frequency = %1d\n", TbaConfig.frequency)); + mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: voltage_state = %1d\n", TbaConfig.voltage_state)); + + + TbaEnvConfig.TMRRI_way = 1; + TbaEnvConfig.RUNTIMEMRR_way = 1; + TbaEnvConfig.PICG_MODE = 1; + TbaEnvConfig.LP_NEW8X_SEQ_MODE = 0; + TbaEnvConfig.DDR400_OPEN_LOOP_MODE = 0; + TbaEnvConfig.RXTRACK_PBYTE_OPT = 0; + TbaEnvConfig.RG_SPM_MODE = 0; + TbaEnvConfig.TX_OE_EXT_OPT = 0; + TbaEnvConfig.PLL_MODE_OPTION = 1; + TbaEnvConfig.TREFBWIG_IGNORE = 1; + TbaEnvConfig.SHUFFLE_LVL_MODE = 1; + TbaEnvConfig.SELPH_MODE = 1; + TbaEnvConfig.TRACK_UP_MODE = 1; + TbaEnvConfig.VALID_LAT_VALUE = 0; + TbaEnvConfig.NEW_RANK_MODE = 1; + TbaEnvConfig.WPST1P5T_OPT = 1; + TbaEnvConfig.TXP_WORKAROUND_OPT = 0; + TbaEnvConfig.DLL_IDLE_MODE = 1; + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TMRRI_way = %1d\n", TbaEnvConfig.TMRRI_way)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RUNTIMEMRR_way = %1d\n", TbaEnvConfig.RUNTIMEMRR_way)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: PICG_MODE = %1d\n", TbaEnvConfig.PICG_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: LP_NEW8X_SEQ_MODE = %1d\n", TbaEnvConfig.LP_NEW8X_SEQ_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: DDR400_OPEN_LOOP_MODE = %1d\n", TbaEnvConfig.DDR400_OPEN_LOOP_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RXTRACK_PBYTE_OPT = %1d\n", TbaEnvConfig.RXTRACK_PBYTE_OPT)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RG_SPM_MODE = %1d\n", TbaEnvConfig.RG_SPM_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TX_OE_EXT_OPT = %1d\n", TbaEnvConfig.TX_OE_EXT_OPT)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: PLL_MODE_OPTION = %1d\n", TbaEnvConfig.PLL_MODE_OPTION)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TREFBWIG_IGNORE = %1d\n", TbaEnvConfig.TREFBWIG_IGNORE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: SHUFFLE_LVL_MODE = %1d\n", TbaEnvConfig.SHUFFLE_LVL_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: SELPH_MODE = %1d\n", TbaEnvConfig.SELPH_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TRACK_UP_MODE = %1d\n", TbaEnvConfig.TRACK_UP_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: VALID_LAT_VALUE = %1d\n", TbaEnvConfig.VALID_LAT_VALUE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: NEW_RANK_MODE = %1d\n", TbaEnvConfig.NEW_RANK_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: WPST1P5T_OPT = %1d\n", TbaEnvConfig.WPST1P5T_OPT)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TXP_WORKAROUND_OPT = %1d\n", TbaEnvConfig.TXP_WORKAROUND_OPT)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: DLL_IDLE_MODE = %1d\n", TbaEnvConfig.DLL_IDLE_MODE)); + + TBA_Build_Def.DQSG_TRACK_on = 1; + mcSHOW_DBG_MSG(("[TBA_build_def_T] Global: DQSG_TRACK_on = %1d\n", TBA_Build_Def.DQSG_TRACK_on)); + + + TbaEnvDVFSCfg.group_num = 2; + TbaEnvDVFSCfg.LP5BGOTF = 0; + TbaEnvDVFSCfg.LP5BGEN = 0; + TbaEnvDVFSCfg.CAS_MODE = 3; + TbaEnvDVFSCfg.LP5_RDQS_SE_EN = 0; + TbaEnvDVFSCfg.DQSIEN_MODE = 1; + TbaEnvDVFSCfg.freq_group_map_0 = 2; + TbaEnvDVFSCfg.freq_group_map_1 = 6; + mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: group_num = %1d\n", TbaEnvDVFSCfg.group_num)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5BGOTF = %1d\n", TbaEnvDVFSCfg.LP5BGOTF)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5BGEN = %1d\n", TbaEnvDVFSCfg.LP5BGEN)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: CAS_MODE = %1d\n", TbaEnvDVFSCfg.CAS_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5_RDQS_SE_EN = %1d\n", TbaEnvDVFSCfg.LP5_RDQS_SE_EN)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: DQSIEN_MODE = %1d\n", TbaEnvDVFSCfg.DQSIEN_MODE)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: freq_group_map_0 = %1d\n", TbaEnvDVFSCfg.freq_group_map_0)); + mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: freq_group_map_1 = %1d\n", TbaEnvDVFSCfg.freq_group_map_1)); + + + TbaEnvHwFuncCfg.HW_MR4_OPTION_RANDOM = 1; + TbaEnvHwFuncCfg.HW_DMYRD_OPTION_RANDOM = 1; + TbaEnvHwFuncCfg.HW_DQSOSC_OPTION_RANDOM = 1; + TbaEnvHwFuncCfg.HW_ZQ_OPTION_RANDOM = 1; + TbaEnvHwFuncCfg.RX_INPUT_TRACK_OPTION_RANDOM = 1; + TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_OPTION_RANDOM = 1; + TbaEnvHwFuncCfg.HW_MR4_EN = 1; + TbaEnvHwFuncCfg.HW_DMYRD_EN = 1; + TbaEnvHwFuncCfg.HW_DQSOSC_EN = 1; + TbaEnvHwFuncCfg.HW_ZQ_EN = 1; + TbaEnvHwFuncCfg.DQSG_RETRY_EN = 0; + TbaEnvHwFuncCfg.RX_INPUT_TRACK_EN = 1; + TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_EN = 1; + TbaEnvHwFuncCfg.RDSEL_TRACK_EN = 0; + TbaEnvHwFuncCfg.DQSG_TRACK_EN = 0; + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_MR4_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.HW_MR4_OPTION_RANDOM)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DMYRD_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.HW_DMYRD_OPTION_RANDOM)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DQSOSC_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.HW_DQSOSC_OPTION_RANDOM)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_ZQ_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.HW_ZQ_OPTION_RANDOM)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RX_INPUT_TRACK_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.RX_INPUT_TRACK_OPTION_RANDOM)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RUNTIME_DEBUG_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_OPTION_RANDOM)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_MR4_EN = %1d\n", TbaEnvHwFuncCfg.HW_MR4_EN)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DMYRD_EN = %1d\n", TbaEnvHwFuncCfg.HW_DMYRD_EN)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DQSOSC_EN = %1d\n", TbaEnvHwFuncCfg.HW_DQSOSC_EN)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_ZQ_EN = %1d\n", TbaEnvHwFuncCfg.HW_ZQ_EN)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RETRY_EN = %1d\n", TbaEnvHwFuncCfg.DQSG_RETRY_EN)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RX_INPUT_TRACK_EN = %1d\n", TbaEnvHwFuncCfg.RX_INPUT_TRACK_EN)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RUNTIME_DEBUG_EN = %1d\n", TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_EN)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RDSEL_TRACK_EN = %1d\n", TbaEnvHwFuncCfg.RDSEL_TRACK_EN)); + mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_TRACK_EN = %1d\n", TbaEnvHwFuncCfg.DQSG_TRACK_EN)); + + + TbaTestListDef.RandDefaultData_on = 1; + TbaTestListDef.DQS2DQ_TRACK_on = 1; + TbaTestListDef.LPDDR4_EN = 1; + TbaTestListDef.ESL_LOG_GEN = 1; + TbaTestListDef.LP4_X8_on = 0; + TbaTestListDef.LP4_X8_mix_on = 0; //Jeremy + TbaTestListDef.INCLUDE_LP45_COMBO_APHY = 1; + TbaTestListDef.LP45_COMBO_APHY_EN = 1; + TbaTestListDef.LPDDR5_EN = 0; + TbaTestListDef.LP3_4_PINMUX_EN = 0; + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: RandDefaultData_on = %1d\n", TbaTestListDef.RandDefaultData_on)); + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: DQS2DQ_TRACK_on = %1d\n", TbaTestListDef.DQS2DQ_TRACK_on)); + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LPDDR4_EN = %1d\n", TbaTestListDef.LPDDR4_EN)); + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: ESL_LOG_GEN = %1d\n", TbaTestListDef.ESL_LOG_GEN)); + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP4_X8_on = %1d\n", TbaTestListDef.LP4_X8_on)); + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: INCLUDE_LP45_COMBO_APHY = %1d\n", TbaTestListDef.INCLUDE_LP45_COMBO_APHY)); + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP45_COMBO_APHY_EN = %1d\n", TbaTestListDef.LP45_COMBO_APHY_EN)); + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LPDDR5_EN = %1d\n", TbaTestListDef.LPDDR5_EN)); + mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP3_4_PINMUX_EN = %1d\n", TbaTestListDef.LP3_4_PINMUX_EN)); + + + + TbaDramcBenchConfig.rank_swap = 0; + TbaDramcBenchConfig.new_uP_spm_mode = 0; + TbaDramcBenchConfig.LP_MTCMOS_CONTROL_SEL = 0; + // CHA, BYTE 0 + TbaDramcBenchConfig.cha_pinmux_anti_order_0 = 0; + TbaDramcBenchConfig.cha_pinmux_anti_order_1 = 1; + TbaDramcBenchConfig.cha_pinmux_anti_order_2 = 2; + TbaDramcBenchConfig.cha_pinmux_anti_order_3 = 3; + TbaDramcBenchConfig.cha_pinmux_anti_order_4 = 4; + TbaDramcBenchConfig.cha_pinmux_anti_order_5 = 5; + TbaDramcBenchConfig.cha_pinmux_anti_order_6 = 6; + TbaDramcBenchConfig.cha_pinmux_anti_order_7 = 7; + // CHA, BYTE 1 + TbaDramcBenchConfig.cha_pinmux_anti_order_8 = 8; + TbaDramcBenchConfig.cha_pinmux_anti_order_9 = 9; + TbaDramcBenchConfig.cha_pinmux_anti_order_10 = 10; + TbaDramcBenchConfig.cha_pinmux_anti_order_11 = 11; + TbaDramcBenchConfig.cha_pinmux_anti_order_12 = 12; + TbaDramcBenchConfig.cha_pinmux_anti_order_13 = 13; + TbaDramcBenchConfig.cha_pinmux_anti_order_14 = 14; + TbaDramcBenchConfig.cha_pinmux_anti_order_15 = 15; + // CHB, BYTE 0 + TbaDramcBenchConfig.chb_pinmux_anti_order_0 = 0; + TbaDramcBenchConfig.chb_pinmux_anti_order_1 = 1; + TbaDramcBenchConfig.chb_pinmux_anti_order_2 = 2; + TbaDramcBenchConfig.chb_pinmux_anti_order_3 = 3; + TbaDramcBenchConfig.chb_pinmux_anti_order_4 = 4; + TbaDramcBenchConfig.chb_pinmux_anti_order_5 = 5; + TbaDramcBenchConfig.chb_pinmux_anti_order_6 = 6; + TbaDramcBenchConfig.chb_pinmux_anti_order_7 = 7; + // CHB, BYTE 1 + TbaDramcBenchConfig.chb_pinmux_anti_order_8 = 8; + TbaDramcBenchConfig.chb_pinmux_anti_order_9 = 9; + TbaDramcBenchConfig.chb_pinmux_anti_order_10 = 10; + TbaDramcBenchConfig.chb_pinmux_anti_order_11 = 11; + TbaDramcBenchConfig.chb_pinmux_anti_order_12 = 12; + TbaDramcBenchConfig.chb_pinmux_anti_order_13 = 13; + TbaDramcBenchConfig.chb_pinmux_anti_order_14 = 14; + TbaDramcBenchConfig.chb_pinmux_anti_order_15 = 15; + + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: rank_swap = %1d\n", TbaDramcBenchConfig.rank_swap)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: new_uP_spm_mode = %1d\n", TbaDramcBenchConfig.new_uP_spm_mode)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: LP_MTCMOS_CONTROL_SEL = %1d\n", TbaDramcBenchConfig.LP_MTCMOS_CONTROL_SEL)); + // CHA, BYTE 0 + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_0 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_0)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_1 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_1)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_2 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_2)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_3 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_3)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_4 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_4)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_5 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_5)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_6 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_6)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_7 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_7)); + // CHA BYTE 1 + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_8 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_8)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_9 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_9)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_10)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_11 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_11)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_12 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_12)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_13)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_14)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_15)); + // CHB, BYTE 0 + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_0 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_0)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_1 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_1)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_2 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_2)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_3 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_3)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_4 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_4)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_5 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_5)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_6 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_6)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_7 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_7)); + // CHB, BYTE 1 + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_8 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_8)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_9 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_9)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_10)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_11 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_11)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_12 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_12)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_13)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_14)); + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_15)); + +} +#endif + +#if BYPASS_CALIBRATION +#if (FOR_DV_SIMULATION_USED==0) +void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) +{ + U8 u1RankIdx=0; + U8 backup_rank=0; + + backup_rank = p->rank; + + ShiftDQUI_AllRK(p, -1, ALL_BYTES); + ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES); + ShiftDQSWCK_UI(p, -1, ALL_BYTES); + + for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + //CBT + DramcCmdUIDelaySetting(p, 0); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), + P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS); + + //WL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0x20, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0x20, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay + + //Gating + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + { + // normal mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(11, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(15, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(11, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(15, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + + #if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); + #endif + } + else + { + //mix mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(15, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(3, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(15, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(3, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + + #if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); + #endif + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), + 8, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), + 8, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + + DramPhyReset(p); + + // set dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), + P_Fld((U32)0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), + P_Fld((U32)0x46, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), + P_Fld((U32)0, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), + P_Fld((U32)0x46, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1)); + + // set dq delay + U8 u1BitIdx; + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), + P_Fld(((U32)0x46), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(((U32)0x46), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), + P_Fld((U32)0x46, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld((U32)0x46, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); + + //mcSHOW_DBG_MSG(("u1BitId %d Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2, + // FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly, FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly)); + } + + { + U8 u1TXMCK[4] = {2,2,2,2}; + U8 u1TXOENMCK[4] = {1,1,1,1}; + U8 u1TXUI[4] = {1,1,1,1}; + U8 u1TXOENUI[4] = {5,5,5,5}; + U8 u1TXPI[4] = {30,30,30,30}; + + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + { + u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =41; + } + else + { + u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =30; + } + + TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI); + TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI); + + //Tx Perbits delay + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1); + + + #if ENABLE_TX_TRACKING + TXUpdateTXTracking(p, TX_DQ_DQS_MOVE_DQ_ONLY, u1TXPI, u1TXPI); + #endif + } + + dle_factor_handler(p, 9); + } + + vSetRank(p, backup_rank); +} + +void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) +{ + U8 u1RankIdx=0; + // WL + U8 u1WLB0_Dly=0, u1WLB1_Dly=0; + // Gating + U8 u1GatingMCKB0_Dly=0, u1GatingMCKB1_Dly=0; + U8 u1GatingUIB0_Dly=0, u1GatingUIB1_Dly=0; + U8 u1GatingPIB0_Dly=0, u1GatingPIB1_Dly=0; + U8 u1B0RodtMCK=0, u1B1RodtMCK=0; + U8 u1B0RodtUI=0, u1B1RodtUI=0; + // Rx + U8 u1RxDQS0=0, u1RxDQS1=0; + U8 u1RxDQM0=0, u1RxDQM1=0; + U8 u1RxRK0B0DQ[8] = {153,147,155,133,149,147,147,143}; + U8 u1RxRK0B1DQ[8] = {163,157,149,143,147,159,151,155}; + U8 u1RxRK1B0DQ[8] = {151,147,149,131,151,147,143,139}; + U8 u1RxRK1B1DQ[8] = {167,159,149,143,151,157,149,157}; + U8 *pRxB0DQ, *pRxB1DQ; + U8 *pTxDQPi; + U8 backup_rank=0; + + backup_rank = p->rank; + + ShiftDQUI_AllRK(p, -1, ALL_BYTES); + ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES); + ShiftDQSWCK_UI(p, -1, ALL_BYTES); + + for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + +#if 0 + //CBT + DramcCmdUIDelaySetting(p, 0); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), + P_Fld(32, SHU_R0_CA_CMD0_RG_ARPI_CMD) | + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS); +#endif + + #if 1 + //WL + if (p->rank == RANK_0) + { + u1WLB0_Dly = 29; + u1WLB1_Dly = 28; + } + else + { + u1WLB0_Dly = 31; + u1WLB1_Dly = 24; + } + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u1WLB0_Dly, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u1WLB1_Dly, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay + + //Gating MCK/UI + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + { + //if (p->rank == RANK_0) + { + u1GatingMCKB0_Dly=0; u1GatingMCKB1_Dly=0; + u1GatingUIB0_Dly=14; u1GatingUIB1_Dly=14; + u1GatingPIB0_Dly=8; u1GatingPIB1_Dly=10; + u1B0RodtMCK=0; u1B1RodtMCK=0; + u1B0RodtUI=3; u1B1RodtUI=3; + } + //else + { + // u1GatingMCKB0_Dly=0; u1GatingMCKB1_Dly=0; + // u1GatingUIB0_Dly=14; u1GatingUIB1_Dly=14; + // u1GatingPIB0_Dly=4; u1GatingPIB1_Dly=10; + // u1B0RodtMCK=0; u1B1RodtMCK=0; + // u1B0RodtUI=3; u1B1RodtUI=3; + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(u1GatingMCKB0_Dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(u1GatingUIB0_Dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(u1GatingMCKB0_Dly+1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(u1GatingUIB0_Dly+4-16, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(u1GatingMCKB1_Dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(u1GatingUIB1_Dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(u1GatingMCKB1_Dly+1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(u1GatingUIB1_Dly+4-16, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + } + else + { + if (p->rank == RANK_0) + { + u1GatingMCKB0_Dly=1; u1GatingMCKB1_Dly=1; + u1GatingUIB0_Dly=6; u1GatingUIB1_Dly=6; + u1GatingPIB0_Dly=0; u1GatingPIB1_Dly=4; + u1B0RodtMCK=1; u1B1RodtMCK=1; + u1B0RodtUI=3; u1B1RodtUI=3; + } + else + { + u1GatingMCKB0_Dly=1; u1GatingMCKB1_Dly=1; + u1GatingUIB0_Dly=5; u1GatingUIB1_Dly=6; + u1GatingPIB0_Dly=28; u1GatingPIB1_Dly=0; + u1B0RodtMCK=1; u1B1RodtMCK=1; + u1B0RodtUI=2; u1B1RodtUI=3; + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(u1GatingMCKB0_Dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(u1GatingUIB0_Dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(u1GatingMCKB0_Dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(u1GatingUIB0_Dly+4, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(u1GatingMCKB1_Dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(u1GatingUIB1_Dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(u1GatingMCKB1_Dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(u1GatingUIB1_Dly+4, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + } + +#if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(u1B0RodtMCK, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(u1B0RodtUI, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(u1B0RodtMCK, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(u1B0RodtUI, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(u1B1RodtMCK, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(u1B1RodtUI, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(u1B1RodtMCK, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(u1B1RodtUI, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); +#endif + + //Gating PI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), + u1GatingPIB0_Dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), + u1GatingPIB1_Dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + + DramPhyReset(p); + + #if RDSEL_TRACKING_EN + //Byte 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), + (u1GatingMCKB0_Dly << 3) | (u1GatingUIB0_Dly), + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), u1GatingPIB0_Dly, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); //PI + //Byte 1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), + (u1GatingMCKB1_Dly << 3) | (u1GatingUIB1_Dly), + DDRPHY_REG_SHU_R0_B1_INI_UIPI);//UI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), + u1GatingPIB1_Dly, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); //PI + #endif + + if (p->rank == RANK_0) + { + u1RxDQS0=0; u1RxDQS1=0; + u1RxDQM0=146; u1RxDQM1=153; + pRxB0DQ = u1RxRK0B0DQ; + pRxB1DQ = u1RxRK0B1DQ; + } + else + { + u1RxDQS0=0; u1RxDQS1=0; + u1RxDQM0=144; u1RxDQM1=154; + pRxB0DQ = u1RxRK1B0DQ; + pRxB1DQ = u1RxRK1B1DQ; + } + + // set Rx dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), + P_Fld((U32)u1RxDQS0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), + P_Fld((U32)u1RxDQM0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld((U32)0, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), + P_Fld((U32)u1RxDQS1, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), + P_Fld((U32)u1RxDQM1, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld((U32)0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + + // set Rx dq delay + U8 u1BitIdx; + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), + P_Fld(((U32)pRxB0DQ[u1BitIdx]), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(((U32)pRxB0DQ[u1BitIdx+1]), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), + P_Fld((U32)pRxB1DQ[u1BitIdx], SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld((U32)pRxB1DQ[u1BitIdx+1], SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); + + //mcSHOW_DBG_MSG(("u1BitId %d Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2, + // FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly, FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly)); + } + + { + U8 u1TXMCK[4] = {4,4,4,4}; + U8 u1TXOENMCK[4] = {4,4,4,4}; + U8 u1TXUI[4] = {6,6,6,6}; + U8 u1TXOENUI[4] = {2,2,2,2}; + U8 u1TXRK0PI[4] = {31,34,31,34}; + U8 u1TXRK1PI[4] = {33,28,33,28}; + + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + { + u1TXRK0PI[0] = u1TXRK0PI[1]= u1TXRK0PI[2] = u1TXRK0PI[3] =53; + u1TXRK1PI[0] = 45; + u1TXRK1PI[1]= u1TXRK1PI[2] = u1TXRK1PI[3] =53; + } + + if (p->rank == RANK_0) + pTxDQPi = u1TXRK0PI; + else + pTxDQPi = u1TXRK1PI; + + TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi); + TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi); + + //Tx Perbits delay + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1); + + #if ENABLE_TX_TRACKING + TXUpdateTXTracking(p, TX_DQ_DQS_MOVE_DQ_ONLY, pTxDQPi, pTxDQPi); + #endif + } + + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + dle_factor_handler(p, 16); + else + dle_factor_handler(p, 17); + #endif + } + + vSetRank(p, backup_rank); +} +#else +void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation +{ + U8 u1RankIdx=0; + U8 backup_rank=0; + + backup_rank = p->rank; + + ShiftDQUI_AllRK(p, -1, ALL_BYTES); + ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES); + ShiftDQSWCK_UI(p, -1, ALL_BYTES); + + for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + //CBT + DramcCmdUIDelaySetting(p, 0); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), + P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS); + + //WL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0x20, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0x20, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay + + //Gating + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + { + if(p->rank==RANK_0) + { + // normal mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(9, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(13, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(9, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(13, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + + #if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); + #endif + } + else + { + // normal mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(12, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(12, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + + #if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); + #endif + } + } + else + { + //mix mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(15, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(3, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(15, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(3, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + + #if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); + #endif + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), + 16, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), + 16, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + + DramPhyReset(p); + + // set dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), + P_Fld((U32)0x45, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), + P_Fld((U32)0x0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), + P_Fld((U32)0x45, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), + P_Fld((U32)0x0, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1)); + + // set dq delay + U8 u1BitIdx; + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), + P_Fld(((U32)0x0), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(((U32)0x0), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), + P_Fld((U32)0x0, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld((U32)0x0, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); + + //mcSHOW_DBG_MSG(("u1BitId %d Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2, + // FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly, FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly)); + } + + { + U8 u1TXMCK[4] = {2,2,2,2}; + U8 u1TXOENMCK[4] = {1,1,1,1}; + U8 u1TXUI[4] = {1,1,1,1}; + U8 u1TXOENUI[4] = {5,5,5,5}; + U8 u1TXPI[4] = {30,30,30,30}; + + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + { + u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =30; + } + else + { + u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =30; + } + + if(p->rank==RANK_1) + { + u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =50; + } + + TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI); + TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI); + + //Tx Perbits delay + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1); + + + #if ENABLE_TX_TRACKING + TXUpdateTXTracking(p, TX_DQ_DQS_MOVE_DQ_ONLY, u1TXPI, u1TXPI); + #endif + } + + dle_factor_handler(p, 8); + } + + vSetRank(p, backup_rank); +} + +void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation +{ + U8 u1RankIdx=0; + // WL + U8 u1WLB0_Dly=0, u1WLB1_Dly=0; + // Gating + U8 u1GatingMCKB0_Dly=0, u1GatingMCKB1_Dly=0; + U8 u1GatingUIB0_Dly=0, u1GatingUIB1_Dly=0; + U8 u1GatingPIB0_Dly=0, u1GatingPIB1_Dly=0; + U8 u1B0RodtMCK=0, u1B1RodtMCK=0; + U8 u1B0RodtUI=0, u1B1RodtUI=0; + // Rx + U8 u1RxDQS0=0, u1RxDQS1=0; + U8 u1RxDQM0=0, u1RxDQM1=0; + U8 u1RxRK0B0DQ[8] = {70,70,70,70,70,70,70,70}; + U8 u1RxRK0B1DQ[8] = {70,70,70,70,70,70,70,70}; + U8 u1RxRK1B0DQ[8] = {70,70,70,70,70,70,70,70}; + U8 u1RxRK1B1DQ[8] = {70,70,70,70,70,70,70,70}; + U8 *pRxB0DQ, *pRxB1DQ; + U8 *pTxDQPi; + U8 backup_rank=0; + + backup_rank = p->rank; + + ShiftDQUI_AllRK(p, -1, ALL_BYTES); + ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES); + ShiftDQSWCK_UI(p, -1, ALL_BYTES); + + for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + +#if 1 + //CBT + //DramcCmdUIDelaySetting(p, 0); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), + P_Fld(40, SHU_R0_CA_CMD0_RG_ARPI_CMD) | + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS); +#endif + + #if 1 + //WL + if (p->rank == RANK_0) + { + u1WLB0_Dly = 34; + u1WLB1_Dly = 38; + } + else + { + u1WLB0_Dly = 37; + u1WLB1_Dly = 32; + } + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u1WLB0_Dly, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u1WLB1_Dly, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay + + //Gating MCK/UI + if (p->rank == RANK_0) + { + u1GatingMCKB0_Dly=0; u1GatingMCKB1_Dly=0; + u1GatingUIB0_Dly=9; u1GatingUIB1_Dly=9; + u1GatingPIB0_Dly=16; u1GatingPIB1_Dly=16; + u1B0RodtMCK=0; u1B1RodtMCK=0; + u1B0RodtUI=0; u1B1RodtUI=0; + } + else + { + u1GatingMCKB0_Dly=1; u1GatingMCKB1_Dly=1; + u1GatingUIB0_Dly=2; u1GatingUIB1_Dly=2; + u1GatingPIB0_Dly=0; u1GatingPIB1_Dly=0; + u1B0RodtMCK=1; u1B1RodtMCK=1; + u1B0RodtUI=3; u1B1RodtUI=3; + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(u1GatingMCKB0_Dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(u1GatingUIB0_Dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(((u1GatingMCKB0_Dly<<4)+u1GatingUIB0_Dly+4)>>4, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(((u1GatingMCKB0_Dly<<4)+u1GatingUIB0_Dly+4)%16, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(u1GatingMCKB1_Dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(u1GatingUIB1_Dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(((u1GatingMCKB1_Dly<<4)+u1GatingUIB1_Dly+4)>>4, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(((u1GatingMCKB1_Dly<<4)+u1GatingUIB1_Dly+4)%16, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + +#if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(u1B0RodtMCK, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(u1B0RodtUI, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(u1B0RodtMCK, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(u1B0RodtUI, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(u1B1RodtMCK, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(u1B1RodtUI, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(u1B1RodtMCK, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(u1B1RodtUI, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); +#endif + + //Gating PI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), + u1GatingPIB0_Dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), + u1GatingPIB1_Dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + + DramPhyReset(p); + + + if (p->rank == RANK_0) + { + u1RxDQS0=0; u1RxDQS1=0; + u1RxDQM0=70; u1RxDQM1=70; + pRxB0DQ = u1RxRK0B0DQ; + pRxB1DQ = u1RxRK0B1DQ; + } + else + { + u1RxDQS0=0; u1RxDQS1=0; + u1RxDQM0=70; u1RxDQM1=70; + pRxB0DQ = u1RxRK1B0DQ; + pRxB1DQ = u1RxRK1B1DQ; + } + + // set Rx dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), + P_Fld((U32)u1RxDQS0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), + P_Fld((U32)u1RxDQM0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld((U32)0, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), + P_Fld((U32)u1RxDQS1, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), + P_Fld((U32)u1RxDQM1, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld((U32)0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + + // set Rx dq delay + U8 u1BitIdx; + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), + P_Fld(((U32)pRxB0DQ[u1BitIdx]), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(((U32)pRxB0DQ[u1BitIdx+1]), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), + P_Fld((U32)pRxB1DQ[u1BitIdx], SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld((U32)pRxB1DQ[u1BitIdx+1], SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); + + //mcSHOW_DBG_MSG(("u1BitId %d Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2, + // FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly, FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly)); + } + + { + U8 u1TXMCK[4] = {4,4,4,4}; + U8 u1TXOENMCK[4] = {4,4,4,4}; + U8 u1TXUI[4] = {6,6,6,6 }; + U8 u1TXOENUI[4] = {2,2,2,2}; + U8 u1TXRK0PI[4] = {28,28,28,28}; + + + U8 u1TXMCK_RK1[4] = {4,4,4,4}; + U8 u1TXOENMCK_RK1[4] = {4,4,4,4}; + U8 u1TXUI_RK1[4] = {7,7,7,7}; + U8 u1TXOENUI_RK1[4] = {3,3,3,3}; + U8 u1TXRK1PI[4] = {46,46,46,46}; + + if (p->rank == RANK_0) + { + pTxDQPi = u1TXRK0PI; + + TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi); + TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi); + } + else + { + pTxDQPi = u1TXRK1PI; + TXSetDelayReg_DQ(p, 1, u1TXMCK_RK1, u1TXOENMCK_RK1, u1TXUI_RK1, u1TXOENUI_RK1, pTxDQPi); + TXSetDelayReg_DQM(p, 1, u1TXMCK_RK1, u1TXOENMCK_RK1, u1TXUI_RK1, u1TXOENUI_RK1, pTxDQPi); + } + + //Tx Perbits delay + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1); + } + + dle_factor_handler(p, 14); + #endif + } + + vSetRank(p, backup_rank); +} + +#endif +#endif + +void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p) +{ +// Enter body +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @13206 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h09 (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfeb (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h015 (Mirror: 12'h000) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x09, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xfeb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x015, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @13076 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h09 (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h09 (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h09 (Mirror: 5'h00) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x09, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @13012 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0 + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0 + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @13002 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h0 + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0) + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h1 (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h0 + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h0 + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h3 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_PHY)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @13229 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12823 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12827 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); +/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @8022 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); +/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @8036 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @8029 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @8040 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9429 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9443 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9436 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9447 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @13022 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h1 (Mirror: 4'h0) + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @8206 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9613 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @13176 + RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @8044 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @8051 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9451 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9458 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5628 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h0 + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h0 + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @13192 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0 + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h1 (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0 + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12841 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12848 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @8000 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x09, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9407 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x09, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @8005 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9412 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @8010 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9417 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @8016 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9423 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10832 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7980 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h19 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h19 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x19, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x19, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @9387 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h1f (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h1f (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10842 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7990 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h13 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h13 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @9397 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h12 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h12 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5331 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMD_CLKEN_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[10:8]=3'h3 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) + APHYPI_CKCGL_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h2 + APHYPI_CKCGH_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[23:20]=4'h4 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) | + P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5683 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h0 + DPHY_TX_DCM_EXTCNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2 + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @5221 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h1 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @5226 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h1 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h1 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5677 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h0 + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h0 + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5576 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h1 + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h1 + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5587 + dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h1 + dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h1 + dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 + dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 + dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 + dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) | + P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @5041 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h1 + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h1 + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @5063 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h1 + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h1 + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @5085 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1 + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1 + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @5107 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1 + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1 + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @5052 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h1 + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h1 + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @5074 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h1 + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h1 + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @5096 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h7 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @5118 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h7 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @5129 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h019 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h01f (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x019, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @5139 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h019 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h01f (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x019, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @5177 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h019 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h01f (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x019, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @5134 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h013 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h012 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x012, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @5144 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h013 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h012 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x012, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @5182 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h013 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h012 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x012, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @5187 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h1f (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h19 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h1f (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h19 (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x19, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x19, SHURK_PI_RK0_ARPI_DQM_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @5194 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h12 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h13 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h12 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h13 (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x12, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x12, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7826 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h3c (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h3c (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h3c (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h3c (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7840 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h3c (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h3c (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h3c (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h3c (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7868 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h3c (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x3c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @9240 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @9254 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @9281 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: +// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5538 + ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h0 + TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h1 (Mirror: 3'h0) + TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'h4 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) | + P_Fld(0x1, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x4, SHU_AC_DERATING0_TRCD_DERATE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5544 + TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'h3 (Mirror: 4'h0) + TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h2 (Mirror: 4'h0) + TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h00 + TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x3, SHU_AC_DERATING1_TRPAB_DERATE) | + P_Fld(0x2, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRAS_DERATE) | + P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_AC_DERATING_05T_0 ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0 - @5551 + TRC_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[0:0]=1'h0 + TRCD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[6:6]=1'h0 + TRP_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[7:7]=1'h1 (Mirror: 1'h0) + TRPAB_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[8:8]=1'h1 (Mirror: 1'h0) + TRAS_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[9:9]=1'h1 (Mirror: 1'h0) + TRRD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[12:12]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) | + P_Fld(0x0, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRP_05T_DERATE) | + P_Fld(0x1, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRAS_05T_DERATE) | + P_Fld(0x0, SHU_AC_DERATING_05T_TRRD_05T_DERATE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5322 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5341 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5504 + TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 + TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 + TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 + TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 + TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0 + TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0) + TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 + TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) + TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 + TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 + TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) + TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 + TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 + TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 + TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 + TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0) + TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0) + TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 + BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 + BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 + BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0 + TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 + TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) + XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 + TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0) + TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0) + TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0) + TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0) + TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 + TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0) + XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5497 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h03 (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h3 (Mirror: 4'h1) + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h04 (Mirror: 5'h01) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x3, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x04, SHU_ACTIM_XRT_XRTW2W)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5443 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h04 (Mirror: 6'h01) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h07 (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0) + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h2 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x04, SHU_ACTIM0_TWTR) | + P_Fld(0x07, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) | + P_Fld(0x4, SHU_ACTIM0_TRCD) | P_Fld(0x2, SHU_ACTIM0_CKELCKCNT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5451 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha) + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h4 (Mirror: 4'h8) + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h2 + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h00 (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) | + P_Fld(0x4, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) | + P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5459 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h05 (Mirror: 5'h0e) + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h0 + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h03 (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | + P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x0, SHU_ACTIM2_TRTP) | + P_Fld(0x03, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5467 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h1a (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h40 (Mirror: 8'h00) + TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x1a, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0x40, SHU_ACTIM3_TRFC) | P_Fld(0x00, SHU_ACTIM3_TWTR_L)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5475 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h04e (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h07 (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h05 (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x04e, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x07, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) | + P_Fld(0x10, SHU_ACTIM4_TZQCS)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5482 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h08 (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h09 (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h0b (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x08, SHU_ACTIM5_TR2PD) | + P_Fld(0x09, SHU_ACTIM5_TWTPD) | P_Fld(0x0b, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5489 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h3 (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h2 (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h06 (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h09 (Mirror: 6'h13) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x3, SHU_ACTIM6_TMRD) | P_Fld(0x2, SHU_ACTIM6_TMRW) | + P_Fld(0x06, SHU_ACTIM6_TW2MRW) | P_Fld(0x09, SHU_ACTIM6_TR2MRW)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5567 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h1 (Mirror: 3'h2) + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | + P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x1, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5671 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8226 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9633 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8126 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h5 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9533 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h5 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7888 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h64 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h64 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7902 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h64 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h64 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7916 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h64 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h64 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7930 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h64 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h64 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7944 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x64, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x64, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7954 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h0da (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h0da (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x0da, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x0da, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7895 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h63 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h63 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7909 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h63 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h63 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7923 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h63 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h63 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7937 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h63 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h63 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7949 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x63, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7959 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h0d9 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h0d9 (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0d9, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x0d9, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9295 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h64 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h64 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9309 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h64 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h64 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9323 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h64 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h64 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9337 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h64 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h64 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9351 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h64 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h64 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x64, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x64, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9361 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0da (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0da (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0da, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x0da, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9302 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h63 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h63 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9316 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h63 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h63 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9330 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h63 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h63 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9344 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h63 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h63 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9356 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h63 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h63 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x63, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9366 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0d9 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0d9 (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0d9, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x0d9, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7782 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9189 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7711 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h6e (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h6e (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h24 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h24 (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x6e, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x6e, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x24, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x24, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9118 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h6e (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h6e (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h24 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h24 (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x6e, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x6e, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x24, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x24, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7718 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9125 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT +// Exit body +} + + +void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) +{ + // Enter body + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @13206 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0e (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hff5 (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h00b (Mirror: 12'h000) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0e, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xff5, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x00b, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @13076 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0e (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0e (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0e (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0e, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @13012 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h1 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0 + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0 + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @13002 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h3 (Mirror: 4'h0) + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0) + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h4 (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h4 (Mirror: 4'h0) + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h4 (Mirror: 4'h0) + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h6 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @13229 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h4 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h4 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h4 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12823 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h6 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12827 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h6 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @8022 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h6 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h8 (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x8, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @8036 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @8029 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h9 (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @8040 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1f (Mirror: 7'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9429 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h6 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h8 (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x8, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9443 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9436 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h9 (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9447 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1f (Mirror: 7'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @13022 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h4 (Mirror: 4'h0) + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x4, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @8206 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9613 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @13176 + RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @8044 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h1 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @8051 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9451 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h1 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9458 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5628 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @13192 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0 + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h5 (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0 + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h1 (Mirror: 4'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x5, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12841 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12848 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @8000 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x06, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9407 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x06, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @8005 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x07, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9412 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x07, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @8010 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h08 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x06, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9417 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h08 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x06, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @8016 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h09 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x07, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9423 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h09 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x07, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7980 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @9387 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7990 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h18 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h18 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @9397 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h18 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h18 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5331 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMD_CLKEN_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[10:8]=3'h3 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h6 (Mirror: 4'h0) + APHYPI_CKCGL_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h2 + APHYPI_CKCGH_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[23:20]=4'h4 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x5, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) | + P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5683 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h0 + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0) + DPHY_TX_DCM_EXTCNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2 + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @5221 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h0 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @5226 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h0 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5677 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0) + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5576 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @5041 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @5063 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @5085 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1 + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1 + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h2 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h2 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @5107 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1 + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1 + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h2 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h2 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @5052 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @5074 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @5096 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h1 + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h1 + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h2 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h2 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @5118 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h1 + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h1 + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h2 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h2 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @5129 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h018 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h018 (Mirror: 11'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @5139 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h018 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h018 (Mirror: 11'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @5177 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h018 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h018 (Mirror: 11'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @5134 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h018 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h018 (Mirror: 11'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @5144 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h018 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h018 (Mirror: 11'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @5182 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h018 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h018 (Mirror: 11'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @5187 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h18 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h18 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h18 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h18 (Mirror: 6'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @5194 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h18 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h18 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h18 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h18 (Mirror: 6'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7826 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h30 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h30 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h30 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h30 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7840 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h30 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h30 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h30 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h30 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7868 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h30 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x30, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @9233 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h0c (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h0c (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h0c (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h0c (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @9247 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h0c (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h0c (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h0c (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h0c (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @9275 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h0c (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x0c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7833 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h10 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h10 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h10 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h10 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7847 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h10 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h10 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h10 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h10 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7874 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h10 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @9240 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h20 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h20 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h20 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h20 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @9254 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h20 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h20 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h20 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h20 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @9281 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h20 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5651 + TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0) + TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0) + TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5538 + ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h1 (Mirror: 1'h0) + TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h2 (Mirror: 3'h0) + TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'h4 (Mirror: 4'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x1, SHU_AC_DERATING0_ACDERATEEN) | + P_Fld(0x2, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x4, SHU_AC_DERATING0_TRCD_DERATE)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5544 + TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'h3 (Mirror: 4'h0) + TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h2 (Mirror: 4'h0) + TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h01 (Mirror: 6'h00) + TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x3, SHU_AC_DERATING1_TRPAB_DERATE) | + P_Fld(0x2, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x01, SHU_AC_DERATING1_TRAS_DERATE) | + P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5322 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5341 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5497 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h05 (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h0a (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h6 (Mirror: 4'h1) + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h09 (Mirror: 5'h01) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x05, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x0a, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x6, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x09, SHU_ACTIM_XRT_XRTW2W)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5443 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h0a (Mirror: 6'h01) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h0c (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0) + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x0a, SHU_ACTIM0_TWTR) | + P_Fld(0x0c, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) | + P_Fld(0x4, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5451 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha) + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h7 (Mirror: 4'h8) + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h2 + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h01 (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) | + P_Fld(0x7, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) | + P_Fld(0x01, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5459 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h07 (Mirror: 5'h0e) + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0) + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h0a (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | + P_Fld(0x07, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) | + P_Fld(0x0a, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5467 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h1a (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h8 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h8 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h40 (Mirror: 8'h00) + TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h25 (Mirror: 6'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x1a, SHU_ACTIM3_TRFCPB) | + P_Fld(0x8, SHU_ACTIM3_MANTMRR) | P_Fld(0x8, SHU_ACTIM3_TR2MRR) | + P_Fld(0x40, SHU_ACTIM3_TRFC) | P_Fld(0x25, SHU_ACTIM3_TWTR_L)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5475 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h04e (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x04e, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) | + P_Fld(0x10, SHU_ACTIM4_TZQCS)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5482 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h10 (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h0f (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h15 (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x10, SHU_ACTIM5_TR2PD) | + P_Fld(0x0f, SHU_ACTIM5_TWTPD) | P_Fld(0x15, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5489 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h6 (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0d (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h11 (Mirror: 6'h13) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x6, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | + P_Fld(0x0d, SHU_ACTIM6_TW2MRW) | P_Fld(0x11, SHU_ACTIM6_TR2MRW)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5567 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h0 + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h3 (Mirror: 3'h1) + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h3 (Mirror: 3'h1) + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h2 + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x0, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x3, SHU_CKECTRL_TPDE) | + P_Fld(0x3, SHU_CKECTRL_TPDX) | P_Fld(0x2, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5671 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8226 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0031 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0031, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9633 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0031 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0031, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8126 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h7 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x7, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9533 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h7 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x7, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7888 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7902 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7916 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7930 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7944 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7954 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h17e (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h17e (Mirror: 9'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x17e, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x17e, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7895 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h74 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h74 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7909 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h74 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h74 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7923 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h74 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h74 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7937 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h74 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h74 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7949 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x74, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7959 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h17d (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h17d (Mirror: 9'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17d, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x17d, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9295 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9309 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9323 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9337 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9351 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h75 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9361 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h17e (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h17e (Mirror: 9'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x17e, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x17e, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9302 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h74 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h74 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9316 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h74 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h74 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9330 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h74 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h74 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9344 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h74 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h74 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9356 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h74 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h74 (Mirror: 8'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x74, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9366 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h17d (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h17d (Mirror: 9'h000) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17d, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x17d, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7782 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9189 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7711 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h03 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h03 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h35 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h35 (Mirror: 6'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x03, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x03, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x35, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x35, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9118 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h03 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h03 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h35 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h35 (Mirror: 6'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x03, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x03, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x35, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x35, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7718 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9125 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT + // Exit body +} + + +void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) +{ + // Enter body + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @13206 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0f (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfd0 (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h030 (Mirror: 12'h000) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0f, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xfd0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x030, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @13076 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0f (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0f (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0f (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0f, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @13012 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0) + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @13002 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0) + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0) + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h6 (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0) + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0) + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @13229 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12823 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12827 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @8022 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h0 + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h4 (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x4, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @8036 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @8029 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hb (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xb, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @8040 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1c (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1c, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9429 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h0 + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h4 (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x4, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9443 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9436 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hb (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xb, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9447 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1c (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1c, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @13022 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h7 (Mirror: 4'h0) + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x7, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @8206 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9613 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @13176 + RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @8044 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h3 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h3 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @8051 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9451 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h3 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h3 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9458 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5628 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @13192 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0 + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h6 (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h2 (Mirror: 4'h0) + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x6, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12841 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12848 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @8000 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x10, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9407 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x10, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @8005 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x17, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9412 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x17, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @8010 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h14 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x14, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9417 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h14 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x14, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @8016 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1b (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x17, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9423 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1b (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x17, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10832 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7980 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h11 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h11 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x11, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x11, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @9387 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h12 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h12 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10842 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7990 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h16 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h16 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x16, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x16, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @9397 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h21 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h21 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5331 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMD_CLKEN_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[10:8]=3'h3 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) + APHYPI_CKCGL_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h2 + APHYPI_CKCGH_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[23:20]=4'h4 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) | + P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5683 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h2 (Mirror: 3'h0) + DPHY_TX_DCM_EXTCNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2 + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @5221 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @5226 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5677 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0) + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0) + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5576 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5587 + dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h1 + dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h1 + dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 + dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 + dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 + dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) | + P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @5041 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h3 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h3 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @5063 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h3 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h3 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @5085 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h2 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h2 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h7 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @5107 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h2 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h2 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h7 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @5052 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h3 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h3 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @5074 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h3 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h3 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @5096 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h3 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h3 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h0 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h0 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x0, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x0, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @5118 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h3 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h3 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h0 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h0 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x0, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x0, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @5129 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h011 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h012 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x011, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x012, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @5139 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h011 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h012 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x011, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x012, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @5177 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h011 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h012 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x011, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x012, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @5134 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h016 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h021 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @5144 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h016 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h021 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @5182 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h016 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h021 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @5187 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h12 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h11 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h12 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h11 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x12, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x11, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x12, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x11, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @5194 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h21 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h16 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h21 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h16 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x16, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x16, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7826 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7840 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7868 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @9233 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h04 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h04 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h04 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h04 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @9247 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h04 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h04 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h04 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h04 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @9275 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h04 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x04, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7833 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h34 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h34 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h34 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h34 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7847 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h34 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h34 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h34 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h34 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7874 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h34 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @9240 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @9254 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @9281 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5651 + TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0) + TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0) + TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5538 + ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h0 + TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h5 (Mirror: 3'h0) + TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'h9 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) | + P_Fld(0x5, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x9, SHU_AC_DERATING0_TRCD_DERATE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5544 + TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'h9 (Mirror: 4'h0) + TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h8 (Mirror: 4'h0) + TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h0c (Mirror: 6'h00) + TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x9, SHU_AC_DERATING1_TRPAB_DERATE) | + P_Fld(0x8, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x0c, SHU_AC_DERATING1_TRAS_DERATE) | + P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_DERATING_05T_0 ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0 - @5551 + TRC_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[0:0]=1'h0 + TRCD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[6:6]=1'h1 (Mirror: 1'h0) + TRP_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[7:7]=1'h0 + TRPAB_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[8:8]=1'h1 (Mirror: 1'h0) + TRAS_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[9:9]=1'h0 + TRRD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[12:12]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) | + P_Fld(0x1, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRP_05T_DERATE) | + P_Fld(0x1, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRAS_05T_DERATE) | + P_Fld(0x0, SHU_AC_DERATING_05T_TRRD_05T_DERATE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5322 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5341 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h75 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x75, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5504 + TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 + TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 + TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0) + TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 + TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0) + TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0 + TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0) + TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h0 + TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h1 (Mirror: 1'h0) + TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h1 (Mirror: 1'h0) + TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) + TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 + TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 + TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 + TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 + TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0) + TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0 + TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 + BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 + BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 + BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0 + TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 + TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h0 + XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 + TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0) + TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0 + TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0) + TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 + TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h1 (Mirror: 1'h0) + TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0) + XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5497 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h1 + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5443 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h08 (Mirror: 6'h01) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h0d (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h4 (Mirror: 3'h0) + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h8 (Mirror: 4'h2) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x08, SHU_ACTIM0_TWTR) | + P_Fld(0x0d, SHU_ACTIM0_TWR) | P_Fld(0x4, SHU_ACTIM0_TRRD) | + P_Fld(0x8, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5451 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h8 (Mirror: 4'ha) + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h8 + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h7 (Mirror: 4'h2) + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h0b (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x8, SHU_ACTIM1_TRPAB) | + P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x7, SHU_ACTIM1_TRP) | + P_Fld(0x0b, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5459 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0c (Mirror: 5'h0e) + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0) + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h0b (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | + P_Fld(0x0c, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) | + P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x0b, SHU_ACTIM2_TFAW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5467 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h4d (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'ha5 (Mirror: 8'h00) + TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x4d, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0xa5, SHU_ACTIM3_TRFC) | P_Fld(0x00, SHU_ACTIM3_TWTR_L)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5475 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h0b5 (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0d (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h28 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x0b5, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x0d, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) | + P_Fld(0x28, SHU_ACTIM4_TZQCS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5482 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h0e (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h10 (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h23 (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0e, SHU_ACTIM5_TR2PD) | + P_Fld(0x10, SHU_ACTIM5_TWTPD) | P_Fld(0x23, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5489 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h0e (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0a (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h10 (Mirror: 6'h13) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x0e, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | + P_Fld(0x0a, SHU_ACTIM6_TW2MRW) | P_Fld(0x10, SHU_ACTIM6_TR2MRW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5567 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h3 (Mirror: 3'h2) + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | + P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5671 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8226 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h00e7 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x00e7, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9633 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h00e7 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x00e7, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8126 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h4 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x4, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9533 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h4 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x4, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7888 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h6d (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h6d (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7902 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h6d (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h6d (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7916 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h6d (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h6d (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7930 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h6d (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h6d (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7944 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x6d, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x6d, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7954 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h061 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h061 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x061, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x061, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7895 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h6c (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h6c (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7909 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h6c (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h6c (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7923 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h6c (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h6c (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7937 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h6c (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h6c (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7949 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x6c, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7959 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h060 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h060 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x060, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x060, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9295 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h6d (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h6d (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9309 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h6d (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h6d (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9323 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h6d (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h6d (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9337 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h6d (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h6d (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9351 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h6d (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h6d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x6d, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x6d, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9361 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h061 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h061 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x061, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x061, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9302 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h6c (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h6c (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9316 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h6c (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h6c (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9330 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h6c (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h6c (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9344 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h6c (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h6c (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9356 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h6c (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h6c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x6c, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9366 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h060 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h060 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x060, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x060, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7782 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9189 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7711 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h75 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h75 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h2d (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h2d (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x2d, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x2d, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9118 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h75 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h75 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h2d (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h2d (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x2d, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x2d, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7718 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9125 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT + // Exit body +} + +void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) +{ + // Enter body + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @13241 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h10 (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @13111 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h10 (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0f (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0f (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x10, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @13047 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0) + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @13037 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0) + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0) + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h6 (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0) + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0) + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @13264 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12858 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12862 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @8012 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @8026 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x01, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @8019 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @8030 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9435 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9449 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x01, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9442 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9453 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @13057 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h7 (Mirror: 4'h0) + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x7, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @8204 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9627 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @8034 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @8041 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9457 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9464 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5361 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @13227 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0 + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h6 (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h2 (Mirror: 4'h0) + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x6, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12876 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12883 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7990 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x01, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9413 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x01, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7995 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x19, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9418 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x19, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @8000 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x15, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9423 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x15, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @8006 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x19, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9429 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x19, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7970 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h13 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h13 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @9393 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h16 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h16 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x16, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x16, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7980 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h2b (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h2b (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h01 (Mirror: 6'h00) + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x2b, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x2b, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x01, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @9403 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h2b (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h2b (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h01 (Mirror: 6'h00) + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x2b, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x2b, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x01, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5064 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMD_CLKEN_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[10:8]=3'h3 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) + APHYPI_CKCGL_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h2 + APHYPI_CKCGH_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[23:20]=4'h4 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) | + P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5416 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0) + DPHY_TX_DCM_EXTCNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2 + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4954 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h4 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4959 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h4 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5410 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0) + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5309 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5320 + dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h5 (Mirror: 4'h1) + dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h5 (Mirror: 4'h1) + dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 + dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 + dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h2 (Mirror: 4'h1) + dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h2 (Mirror: 4'h1) + dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 + dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0) | + P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0) | + P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4774 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4796 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4818 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h6 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h6 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h3 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h3 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4840 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h6 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h6 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h3 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h3 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4785 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4807 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4829 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h7 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h7 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h4 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h4 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4851 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h7 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h7 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h4 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h4 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4862 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h013 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h016 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x016, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4872 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h013 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h016 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x016, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4910 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h013 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h016 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x016, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4867 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h02b (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h02b (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x02b, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4877 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h02b (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h02b (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x02b, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4915 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h02b (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h02b (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x02b, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4920 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h16 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h13 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h16 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h13 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x16, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x16, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4927 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h2b (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h2b (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h2b (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h2b (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7816 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h10 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h10 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h10 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7830 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h10 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h10 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h10 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7858 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h10 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @9239 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h04 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h04 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h04 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h04 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @9253 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h04 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h04 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h04 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h04 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @9281 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h04 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x04, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7823 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7837 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7864 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @9246 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @9260 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @9287 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5384 + TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0) + TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0) + TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5271 + ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h0 + TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h5 (Mirror: 3'h0) + TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'hb (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) | + P_Fld(0x5, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0xb, SHU_AC_DERATING0_TRCD_DERATE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5277 + TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'hb (Mirror: 4'h0) + TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h9 (Mirror: 4'h0) + TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h0f (Mirror: 6'h00) + TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0xb, SHU_AC_DERATING1_TRPAB_DERATE) | + P_Fld(0x9, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x0f, SHU_AC_DERATING1_TRAS_DERATE) | + P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_DERATING_05T_0 ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0 - @5284 + TRC_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[0:0]=1'h0 + TRCD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[6:6]=1'h0 + TRP_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[7:7]=1'h1 (Mirror: 1'h0) + TRPAB_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[8:8]=1'h0 + TRAS_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[9:9]=1'h0 + TRRD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[12:12]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) | + P_Fld(0x0, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRP_05T_DERATE) | + P_Fld(0x0, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRAS_05T_DERATE) | + P_Fld(0x1, SHU_AC_DERATING_05T_TRRD_05T_DERATE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5055 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5074 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5237 + TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 + TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h1 (Mirror: 1'h0) + TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 + TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 + TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0 + TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0) + TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 + TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) + TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 + TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 + TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h0 + TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 + TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 + TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 + TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h1 (Mirror: 1'h0) + TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h0 + TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0 + TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0) + BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 + BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 + BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0 + TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 + TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) + XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 + TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0 + TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0) + TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0 + TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 + TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 + TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 + XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5230 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h1 + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5176 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h0a (Mirror: 6'h01) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h0f (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h3 (Mirror: 3'h0) + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x0a, SHU_ACTIM0_TWTR) | + P_Fld(0x0f, SHU_ACTIM0_TWR) | P_Fld(0x3, SHU_ACTIM0_TRRD) | + P_Fld(0xa, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5184 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'ha + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h8 + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h8 (Mirror: 4'h2) + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xa, SHU_ACTIM1_TRPAB) | + P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x8, SHU_ACTIM1_TRP) | + P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5192 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h1 (Mirror: 4'h0) + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0e + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0) + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h08 (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x1, SHU_ACTIM2_TXP) | + P_Fld(0x0e, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) | + P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x08, SHU_ACTIM2_TFAW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5200 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h59 (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'hbf (Mirror: 8'h00) + TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x59, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0xbf, SHU_ACTIM3_TRFC) | P_Fld(0x00, SHU_ACTIM3_TWTR_L)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5208 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h0cf (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0b (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x0cf, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0b, SHU_ACTIM4_TMRR2W) | + P_Fld(0x2e, SHU_ACTIM4_TZQCS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5215 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h0f (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h12 (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h29 (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0f, SHU_ACTIM5_TR2PD) | + P_Fld(0x12, SHU_ACTIM5_TWTPD) | P_Fld(0x29, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5222 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h8 (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0b (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h12 (Mirror: 6'h13) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x8, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | + P_Fld(0x0b, SHU_ACTIM6_TW2MRW) | P_Fld(0x12, SHU_ACTIM6_TR2MRW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5300 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h3 (Mirror: 3'h2) + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | + P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5404 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8224 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9647 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8124 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9547 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7878 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h54 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h54 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h54 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h54 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7892 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h54 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h54 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h54 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h54 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7906 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h54 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h54 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h54 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h54 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7920 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h54 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h54 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h54 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h54 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7934 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h54 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h54 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x54, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x54, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7944 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h04a (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h04a (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x04a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x04a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7885 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h46 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h46 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h46 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h46 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7899 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h46 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h46 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h46 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h46 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7913 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h46 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h46 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h46 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h46 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7927 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h46 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h46 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h46 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h46 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7939 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h46 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h46 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x46, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7949 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h038 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h038 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x038, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x038, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9301 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'hcd (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'hcd (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'hcd (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'hcd (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9315 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'hcd (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'hcd (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'hcd (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'hcd (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9329 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'hcd (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'hcd (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'hcd (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'hcd (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9343 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'hcd (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'hcd (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'hcd (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'hcd (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9357 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'hcd (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'hcd (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0xcd, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0xcd, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9367 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0bd (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0bd (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9308 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'hfe (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'hfe (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'hfe (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'hfe (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9322 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'hfe (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'hfe (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'hfe (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'hfe (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9336 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'hfe (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'hfe (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'hfe (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'hfe (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9350 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'hfe (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'hfe (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'hfe (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'hfe (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9362 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'hfe (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'hfe (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0xfe, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9372 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0f4 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0f4 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0f4, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x0f4, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7772 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9195 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7701 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h5a (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h5a (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h14 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h14 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x5a, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x5a, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x14, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x14, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9124 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h53 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h53 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h0d (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h0d (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x53, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x53, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x0d, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x0d, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7708 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9131 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT + // Exit body +} + +void TX_Path_Algorithm(DRAMC_CTX_T *p) +{ + U8 u1RandIdx = 0; + U8 WL = 0; + U8 u1DQS_TotalUI = 0; + U8 u1DQS_OE_TotalUI = 0; + U8 u1DQS_MCK, u1DQS_UI; + U8 u1DQS_OE_MCK, u1DQS_OE_UI; + U8 u1Small_ui_to_large; + U8 u1TxDQOEShift = 0; + + u1Small_ui_to_large = u1MCK2UI_DivShift(p); + WL = Get_WL_by_MR_LP4(0, (u1MR02Value[p->dram_fsp]&0x3F)>>3); + u1DQS_TotalUI = WL*DFS_TOP[0].CKR*2 + 1; + #if ENABLE_WDQS_MODE_2 + u1TxDQOEShift = WDQSMode2AcTxOEShift(p); + #else + u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4; + #endif + u1DQS_OE_TotalUI = u1DQS_TotalUI - u1TxDQOEShift; + + u1DQS_UI = u1DQS_TotalUI - ((u1DQS_TotalUI >> u1Small_ui_to_large) << u1Small_ui_to_large); + u1DQS_MCK = (u1DQS_TotalUI >> u1Small_ui_to_large); + + u1DQS_OE_UI = u1DQS_OE_TotalUI - ((u1DQS_OE_TotalUI >> u1Small_ui_to_large) << u1Small_ui_to_large); + u1DQS_OE_MCK = (u1DQS_OE_TotalUI >> u1Small_ui_to_large); + + //u1DQ_UI = WL*DFS_TOP[0].CKR*2 - u1WDBI_EN*(DFS_TOP[0].DQ_P2S_RATIO) + (tDQSS+tDQS2DQ)*1000000/DFS_TOP[0].data_rate; + + mcSHOW_DBG_MSG(("[TX_path_calculate] data rate=%d, WL=%d, DQS_TotalUI=%d\n", DFS_TOP[0].data_rate, WL, u1DQS_TotalUI)); + mcSHOW_DBG_MSG(("[TX_path_calculate] DQS = (%d,%d) DQS_OE = (%d,%d)\n", u1DQS_MCK, u1DQS_UI, u1DQS_OE_MCK, u1DQS_OE_UI)); + + for(u1RandIdx = 0; u1RandIdx < p->support_rank_num; u1RandIdx ++) + { + vIO32WriteFldMulti_All(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(u1DQS_MCK, SHU_SELPH_DQS0_TXDLY_DQS0) + | P_Fld(u1DQS_MCK, SHU_SELPH_DQS0_TXDLY_DQS1) + | P_Fld(u1DQS_OE_MCK, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) + | P_Fld(u1DQS_OE_MCK, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(u1DQS_UI, SHU_SELPH_DQS1_DLY_DQS0) + | P_Fld(u1DQS_UI, SHU_SELPH_DQS1_DLY_DQS1) + | P_Fld(u1DQS_OE_UI, SHU_SELPH_DQS1_DLY_OEN_DQS0) + | P_Fld(u1DQS_OE_UI, SHU_SELPH_DQS1_DLY_OEN_DQS1)); + } +} + + +void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) +{ + // Enter body + // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634 + DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h09 (Mirror: 5'h00) + DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h07 (Mirror: 5'h00) + DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h09 (Mirror: 5'h00) + DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h07 (Mirror: 5'h00) + DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h09 (Mirror: 5'h00) + DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h07 (Mirror: 5'h00) + DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0 + DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | + P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645 + CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h09 (Mirror: 5'h00) + CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h07 (Mirror: 5'h00) + CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h09 (Mirror: 5'h00) + CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h07 (Mirror: 5'h00) + DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h09 (Mirror: 5'h00) + DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h07 (Mirror: 5'h00) + DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h1 (Mirror: 1'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0xF, SHU_MISC_DRVING2_CMDDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0xF, SHU_MISC_DRVING2_CMDDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x09, SHU_MISC_DRVING2_DQDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x1, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655 + DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00) + DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00) + DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00) + DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00) + DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00) + DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664 + CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00) + CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00) + CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00) + CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00) + DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00) + DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682 + IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h07 (Mirror: 6'h01) + DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00 + DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x07, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | + P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625 + IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h3 (Mirror: 3'h4) + IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00 + IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00 + IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4 + IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00) + IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x3, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | + P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | + P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | + P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0a (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfeb (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h015 (Mirror: 12'h000) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0a, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xfeb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x015, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0a (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h09 (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h09 (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0a, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0 + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0 + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h0 + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0 + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h2 (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h0 + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h0 + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h3 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x2, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*0x80), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*0x80), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*0x80), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*0x80), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*0x80), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h1 (Mirror: 4'h0) + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*0x80), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*0x80), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h0 + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h0 + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0) + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h3 (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0) + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x3, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*0x80), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x09, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x09, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h1d (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h1d (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h1d (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h1d (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x1d, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h0d (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h0d (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*0x80), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x0d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h13 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h13 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*0x80), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x13, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x13, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if (fcFOR_CHIP_ID == fcA60868) + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + #elif(fcFOR_CHIP_ID == fcPetrus) + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h7 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h0 + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x7, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h1 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h1 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*0x200), P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h0 + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h0 + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h1 + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h1 + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282 + dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h1 + dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h1 + dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 + dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 + dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 + dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) | + P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h1 + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h1 + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h1 + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h1 + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1 + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1 + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1 + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1 + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h1 + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h1 + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h1 + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h1 + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h7 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h7 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h01d (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h01d (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h01d (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h01d (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h01d (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h01d (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h00d (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h013 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h00d (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h013 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h00d (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h013 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h1d (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h1d (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h1d (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h1d (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h13 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h0d (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h13 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h0d (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*0x200), P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x0d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x0d, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h10 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h10 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h10 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h10 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h10 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h10 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h10 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @8831 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h14 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h14 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h14 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h14 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @8845 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h14 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h14 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h14 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h14 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @8873 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h14 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x14, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h3c (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h3c (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h3c (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h3c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h3c (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h3c (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h3c (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h3c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h3c (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ9_0 ral_reg_DDRPHY_blk_SHU_B0_DQ9_0 - @7845 + RG_ARPI_RESERVE_B0 uvm_reg_field ... RW SHU_B0_DQ9_0[31:0]=32'hbf31f45b (Mirror: 32'hbf33f45b) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0xbf31f45b, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041 + TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052 + TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01 + TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | + P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | + P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060 + TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071 + TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082 + dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1 + dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1 + dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1) + dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1 + dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1 + dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1 + dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1 + dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199 + TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 + TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 + TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 + TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 + TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0 + TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0) + TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 + TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) + TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 + TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 + TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) + TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 + TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 + TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 + TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 + TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0) + TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0) + TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 + BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 + BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 + BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0) + TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 + TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) + XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 + TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0 + TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0) + TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0) + TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0) + TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 + TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 + XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h03 (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h3 (Mirror: 4'h1) + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h03 (Mirror: 5'h01) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x3, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x4, SHU_ACTIM_XRT_XRTW2W)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'h4 (Mirror: 4'h1) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h2 (Mirror: 3'h0) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h08 (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0) + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2) + TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h7 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if (fcFOR_CHIP_ID == fcA60868) + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x4, SHU_ACTIM0_TWTR) | + P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x08, SHU_ACTIM0_TWR) | + P_Fld(0x1, SHU_ACTIM0_TRRD) | P_Fld(0x4, SHU_ACTIM0_TRCD) | + P_Fld(0x7, SHU_ACTIM0_TWTR_L)); + #elif (fcFOR_CHIP_ID == fcPetrus) + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x4, SHU_ACTIM0_TWTR) | + P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x08, SHU_ACTIM0_TWR) | + P_Fld(0x1, SHU_ACTIM0_TRRD) | P_Fld(0x4, SHU_ACTIM0_TRCD)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha) + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h4 (Mirror: 4'h8) + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h2 + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h00 (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h04 (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) | + P_Fld(0x4, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) | + P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x04, SHU_ACTIM1_TRC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h05 (Mirror: 5'h0e) + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h1 (Mirror: 3'h0) + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h03 (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | + P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x1, SHU_ACTIM2_TRTP) | + P_Fld(0x03, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h10 (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h2c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x10, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0x2c, SHU_ACTIM3_TRFC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h03a (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h07 (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h05 (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x03a, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x07, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) | + P_Fld(0x10, SHU_ACTIM4_TZQCS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h08 (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h09 (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h12 (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x08, SHU_ACTIM5_TR2PD) | + P_Fld(0x09, SHU_ACTIM5_TWTPD) | P_Fld(0x12, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h3 (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h2 (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h06 (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h07 (Mirror: 6'h13) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x3, SHU_ACTIM6_TMRD) | P_Fld(0x2, SHU_ACTIM6_TMRW) | + P_Fld(0x06, SHU_ACTIM6_TW2MRW) | P_Fld(0x07, SHU_ACTIM6_TR2MRW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h1 (Mirror: 3'h2) + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | + P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x1, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h5 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x20, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); //RX_ARDQ_VREF_SEL_B0 is useless + + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h5 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x20, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); //RX_ARDQ_VREF_SEL_B0 is useless + + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h9f (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h9f (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h9f (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h9f (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h9f (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h9f (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h9f (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h9f (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x9f, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x9f, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h0e5 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h0e5 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x0e5, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x0e5, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h9e (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h9e (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h9e (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h9e (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h9e (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h9e (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h9e (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h9e (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x9e, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h0e4 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h0e4 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*0x80), P_Fld(0x0e4, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x0e4, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h9f (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h9f (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h9f (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h9f (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h9f (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h9f (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h9f (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h9f (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h9f (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h9f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x9f, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x9f, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0e5 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0e5 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h9e (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h9e (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h9e (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h9e (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h9e (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h9e (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h9e (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h9e (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h9e (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h9e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x9e, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0e4 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0e4 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*0x80), P_Fld(0x0e4, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x0e4, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h29 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h29 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h1f (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h1f (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x29, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x29, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x1f, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x1f, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h29 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h29 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h1f (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h1f (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x29, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x29, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x1f, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x1f, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001 + FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0) + FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0 + FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h0 + DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0) + DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h0 + LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h0 + LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h0 + CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0 + BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0 + BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0) + LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0 + BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1 + LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h0 + SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) | + P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) | + P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | + P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) | + P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) | + P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | + P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) | + P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255 + SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a) + TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0 + REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000 + TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | + P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | + P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0) + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if (fcFOR_CHIP_ID == fcA60868) + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + #elif (fcFOR_CHIP_ID == fcPetrus) + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356 + DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08) + ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0 + ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0) + PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0) + REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0) + REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) | + P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | + P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | + P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996 + MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0) + NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) | + P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SCHEDULER_0 ral_reg_DRAMC_blk_SHU_SCHEDULER_0 - @5023 + DUALSCHEN uvm_reg_field ... RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899 + TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0 + TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0 + DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0 + TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1 + DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0 + OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0 + DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0 + WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0) + DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0 + DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0 + ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0 + TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0 + DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0 + DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0 + RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0 + DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) | + P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) | + P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) | + P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) | + P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) | + P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) | + P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) | + P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) | + P_Fld(0x0, TX_SET0_DRAMOEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h5 (Mirror: 3'h0) + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h0 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0) + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if (fcFOR_CHIP_ID == fcA60868) + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x5, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + #elif (fcFOR_CHIP_ID == fcPetrus) + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x5, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514 + DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0 + DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0 + r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0 + STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0) + STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0) + DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | + P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | + P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | + P_Fld(0x0, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499 + DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h0 + PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0) + DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0) + DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0) + DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h1 + DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1 + DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0 + STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0) + STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0) + DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0 + DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0 + DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x0, MISC_SHU_STBCAL_DMSTBLAT) | + P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) | + P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562 + RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0) + RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0 + RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0 + RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1 + RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0 + RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0) + RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0 + RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | + P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751 + DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0) + RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0) + RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | + P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HWSET_MR13_0 ral_reg_DRAMC_blk_SHU_HWSET_MR13_0 - @5127 + HWSET_MR13_MRSMA uvm_reg_field ... RW SHU_HWSET_MR13_0[12:0]=13'h000d + HWSET_MR13_OP uvm_reg_field ... RW SHU_HWSET_MR13_0[23:16]=8'h08 (Mirror: 8'hc8) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13, P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) | + P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HWSET_VRCG_0 ral_reg_DRAMC_blk_SHU_HWSET_VRCG_0 - @5132 + HWSET_VRCG_MRSMA uvm_reg_field ... RW SHU_HWSET_VRCG_0[12:0]=13'h000d + HWSET_VRCG_OP uvm_reg_field ... RW SHU_HWSET_VRCG_0[23:16]=8'h00 (Mirror: 8'hc0) + VRCGDIS_PRDCNT uvm_reg_field ... RW SHU_HWSET_VRCG_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) | + P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384 + tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h2b (Mirror: 8'h00) + tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h18 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | + P_Fld(0x2b, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x18, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | + P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523 + r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h1 (Mirror: 1'h0) + r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0 + r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46) + r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | + P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | + P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); + + mcDELAY_US(1); + + /*TINFO=---===BROADCAST OFF!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter + mcDELAY_US(1); + + mcDELAY_US(1); + + /*TINFO=---===BROADCAST ON!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338 + DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h08 (Mirror: 8'h00) + DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0 + DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0 + DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x08, SHU_DQSOSCR_DQSOSCRCNT) | + P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | + P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332 + DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1 + DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h011 (Mirror: 10'h00f) + DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x011, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h0866 (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h0866 (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0866, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0866, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h0399 (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h0399 (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*0x200), P_Fld(0x0399, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0399, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h0ac (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h072 (Mirror: 12'h001) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x0ac, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x072, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h01f (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h015 (Mirror: 12'h001) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*0x200), P_Fld(0x01f, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x015, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h5 + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h0 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h08 (Mirror: 6'h0e) + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if (fcFOR_CHIP_ID == fcA60868) + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x5, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x08, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + #elif (fcFOR_CHIP_ID == fcPetrus) + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x5, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x08, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 + ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000) + TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1b + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0063 + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0063 + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'hd (Mirror: 4'h0) + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0xd, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'hd (Mirror: 4'h0) + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0xd, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ11_0 ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 - @7794 + RG_RX_ARDQ_RANK_SEL_SER_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[0:0]=1'h0 + RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[1:1]=1'h0 + RG_RX_ARDQ_OFFSETC_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[2:2]=1'h0 + RG_RX_ARDQ_OFFSETC_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[3:3]=1'h0 + RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[4:4]=1'h0 + RG_RX_ARDQ_FRATE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[5:5]=1'h0 + RG_RX_ARDQ_CDR_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[6:6]=1'h0 + RG_RX_ARDQ_DVS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQ_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[11:8]=4'h0 + RG_RX_ARDQ_DES_MODE_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[17:16]=2'h2 + RG_RX_ARDQ_BW_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[19:18]=2'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ11_0 ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 - @9197 + RG_RX_ARDQ_RANK_SEL_SER_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[0:0]=1'h0 + RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[1:1]=1'h0 + RG_RX_ARDQ_OFFSETC_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[2:2]=1'h0 + RG_RX_ARDQ_OFFSETC_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[3:3]=1'h0 + RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[4:4]=1'h0 + RG_RX_ARDQ_FRATE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[5:5]=1'h0 + RG_RX_ARDQ_CDR_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[6:6]=1'h0 + RG_RX_ARDQ_DVS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQ_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[11:8]=4'h0 + RG_RX_ARDQ_DES_MODE_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[17:16]=2'h2 + RG_RX_ARDQ_BW_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[19:18]=2'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); + // Exit body +} + +#if 0 +void CInit_golden_mini_freq_related_vseq_LP4_1600_SHU1(DRAMC_CTX_T *p) +{ +// Enter body +// ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Enter: +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | + P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x09, SHU_MISC_DRVING2_DQDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x1, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x07, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | + P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | + P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | + P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | + P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Exit: + mcDELAY_US(1); + + mcDELAY_US(1); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) | + P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) | + P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) | + P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) | + P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) | + P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) | + P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x1, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) | + P_Fld(0x15, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) | + P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) | + P_Fld(0x0e, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) | + P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x1, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) | + P_Fld(0x0a, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) | + P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) | + P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) | + P_Fld(0x50, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) | + P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) | + P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) | + P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x00, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) | + P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) | + P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) | + P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) | + P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x00, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) | + P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) | + P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) | + P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) | + P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) | + P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) | + P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x894a, SHU_PLL0_RG_RPHYPLL_TOP_REV) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) | + P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) | + P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) | + P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) | + P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) | + P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) | + P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) | + P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) | + P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) | + P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) | + P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET), 0x716c0638, SHU_CA_CMD9_RG_ARPI_RESERVE_CA); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) | + P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) | + P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) | + P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0xd4f91bb7, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); +vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0x53b8f566, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) | + P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) | + P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) | + P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x15ba2788, SHU_CA_DLL2_RG_ARCMD_REV); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) | + P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) | + P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x0cebb192, SHU_B0_DLL2_RG_ARDQ_REV_B0); +vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x4b99094e, SHU_B1_DLL2_RG_ARDQ_REV_B1); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) | + P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) | + P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) | + P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit +// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) | + P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) | + P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) | + P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) | + P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) | + P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) | + P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x1, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) | + P_Fld(0x03, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) | + P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) | + P_Fld(0x05, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) | + P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x1, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) | + P_Fld(0x07, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) | + P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) | + P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) | + P_Fld(0x50, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) | + P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) | + P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) | + P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x00, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) | + P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) | + P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) | + P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) | + P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x00, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) | + P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) | + P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) | + P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) | + P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) | + P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) | + P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0825, SHU_PLL0_RG_RPHYPLL_TOP_REV) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) | + P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) | + P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) | + P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) | + P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) | + P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) | + P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) | + P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) | + P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) | + P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) | + P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x4103911e, SHU_CA_CMD9_RG_ARPI_RESERVE_CA); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) | + P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) | + P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) | + P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xfa9fd5c2, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); +vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x6b9a7ebf, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) | + P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) | + P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) | + P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x1793f0fe, SHU_CA_DLL2_RG_ARCMD_REV); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) | + P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) | + P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xb357f9bf, SHU_B0_DLL2_RG_ARDQ_REV_B0); +vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x7e18d6d9, SHU_B1_DLL2_RG_ARDQ_REV_B1); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) | + P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) | + P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) | + P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit + mcDELAY_US(1); + + mcDELAY_US(1); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter +vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN) | + P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN) | + P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA) | + P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0) | + P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0) | + P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1) | + P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1) | + P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX_MODE_SET related setting Enter +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Enter: +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xff0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x010, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x10, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x2, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_PHY)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); +vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET), 0x5, MISC_SHU_RK_DQSCTL_DQSINCTL); +vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x5, MISC_SHU_RK_DQSCTL_DQSINCTL); +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xa, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x19, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xf, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x05, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xa, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x19, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xf, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x05, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x4, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); +vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x6, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x19, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x0a, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x19, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x0a, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x0d, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x0d, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x19, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x0a, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x19, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x0a, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Exit: +// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Enter: +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x17, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x17, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0a, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x0a, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x06, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x06, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xa, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); +vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x017, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x017, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x017, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00a, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x006, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00a, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x006, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00a, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x006, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x17, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x17, SHURK_PI_RK0_ARPI_DQM_B0)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x06, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x0a, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x06, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x0a, SHURK_PI_RK0_ARPI_DQM_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x38, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x38, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x38, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x38, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x38, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x38, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x38, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x38, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x38, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x2c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x2c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x2c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x2c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x2c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x2c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x2c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x2c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x2c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x3c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Exit: +// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Enter: +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | + P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | + P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Exit +// ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Enter: +vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); +vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4b, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x06, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x0a, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x6, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x07, SHU_ACTIM_XRT_XRTW2W)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xa, SHU_ACTIM0_TWTR) | + P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x0e, SHU_ACTIM0_TWR) | + P_Fld(0x3, SHU_ACTIM0_TRRD) | P_Fld(0x6, SHU_ACTIM0_TRCD) | + P_Fld(0x3, SHU_ACTIM0_TWTR_L)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x5, SHU_ACTIM1_TRPAB) | + P_Fld(0x7, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x4, SHU_ACTIM1_TRP) | + P_Fld(0x05, SHU_ACTIM1_TRAS) | P_Fld(0x0a, SHU_ACTIM1_TRC)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_ACTIM2_TXP) | + P_Fld(0x08, SHU_ACTIM2_TMRRI) | P_Fld(0x1, SHU_ACTIM2_TRTP) | + P_Fld(0x0a, SHU_ACTIM2_TR2W) | P_Fld(0x05, SHU_ACTIM2_TFAW)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1f, SHU_ACTIM3_TRFCPB) | + P_Fld(0x8, SHU_ACTIM3_MANTMRR) | P_Fld(0x8, SHU_ACTIM3_TR2MRR) | + P_Fld(0x49, SHU_ACTIM3_TRFC)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x057, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) | + P_Fld(0x1a, SHU_ACTIM4_TZQCS)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x10, SHU_ACTIM5_TR2PD) | + P_Fld(0x11, SHU_ACTIM5_TWTPD) | P_Fld(0x1c, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0a, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x5, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | + P_Fld(0x0d, SHU_ACTIM6_TW2MRW) | P_Fld(0x12, SHU_ACTIM6_TR2MRW)); +vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x3, SHU_CKECTRL_TPDE) | + P_Fld(0x2, SHU_CKECTRL_TPDX) | P_Fld(0x2, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); +vIO32WriteFldMulti(DRAMC_REG_SHU_MISC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) | + P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) | + P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Exit +// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Enter. +// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Exit. +// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x6, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x6, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0xe5, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0xe5, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0xe5, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0xe5, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0xe5, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x18a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x18a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0xe4, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0xe4, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0xe4, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0xe4, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0xe4, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x189, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x189, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0xe5, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xe5, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xe5, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xe5, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0xe5, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x18a, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x18a, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0xe4, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xe4, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xe4, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xe4, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0xe4, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x189, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x189, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set EXIT +// ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Enter +vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_COMMON0_FREQDIV4) | + P_Fld(0x1, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) | + P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | + P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) | + P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) | + P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | + P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) | + P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | + P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | + P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3f, SHU_CONF0_DMPGTIM) | + P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | + P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | + P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); +vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MATYPE_MATYPE) | + P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x1, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | + P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | + P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | + P_Fld(0x0, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL_DMSTBLAT) | + P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) | + P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) | + P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) | + P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | + P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | + P_Fld(0x2, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | + P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Exit +// ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Enter +// ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Exit +// ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Enter +vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) | + P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP)); +vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) | + P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Exit +// ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Enter +vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | + P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | + P_Fld(0x2b, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Exit +// ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Enter +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | + P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | + P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); + + mcDELAY_US(1); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Enter + mcDELAY_US(1); + + mcDELAY_US(1); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); +// ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Exit +vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0c, SHU_DQSOSCR_DQSOSCRCNT) | + P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | + P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); +vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0b06, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0b06, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x128, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x0c5, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x036, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x024, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x1, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x06, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0000, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT)); +vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT)); +vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4b, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0xb, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0xb, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); +// Exit body +} +#endif + +void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p) +{ +// Enter body +// ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter: +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634 + DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00) + DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00) + DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00) + DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00) + DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00) + DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00) + DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0 + DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | + P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645 + CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00) + CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00) + CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00) + CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00) + DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00) + DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00) + DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655 + DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00) + DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00) + DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00) + DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00) + DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00) + DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664 + CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00) + CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00) + CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00) + CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00) + DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00) + DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682 + IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h0a (Mirror: 6'h01) + DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00 + DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x0a, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | + P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625 + IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h7 (Mirror: 3'h4) + IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00 + IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00 + IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4 + IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00) + IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x7, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | + P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | + P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | + P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit: +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h10 (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h10 (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h10 (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h10 (Mirror: 5'h00) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x10, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x10, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x10, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0) + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h3 (Mirror: 3'h0) + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x3, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h5 (Mirror: 4'h0) + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0 + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h8 (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h6 (Mirror: 4'h0) + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h6 (Mirror: 4'h0) + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h9 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL_PHY)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h8 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x8, MISC_SHU_RK_DQSCTL_DQSINCTL); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h8 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x8, MISC_SHU_RK_DQSCTL_DQSINCTL); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x01, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x01, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h8 (Mirror: 4'h0) + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x8, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @12704 + RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0) + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h9 (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0) + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x9, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x01, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x01, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x19, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x19, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x15, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x15, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x19, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x19, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h15 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h15 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x15, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h15 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h15 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h24 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h24 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x24, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x24, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h22 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h22 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +#if (fcFOR_CHIP_ID == fcA60868) +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +#elif (fcFOR_CHIP_ID == fcPetrus) +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +#endif +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h7 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x7, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h4 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0) + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0) + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282 + dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h5 (Mirror: 4'h1) + dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h5 (Mirror: 4'h1) + dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 + dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 + dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h2 (Mirror: 4'h1) + dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h2 (Mirror: 4'h1) + dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 + dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0) | + P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0) | + P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h3 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h3 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h3 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h3 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h6 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h6 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h3 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h3 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h6 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h6 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h3 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h3 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h3 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h3 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h3 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h3 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h7 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h7 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h4 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h4 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h7 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h7 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h4 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h4 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h015 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h015 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h015 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h015 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h015 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h015 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h024 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h022 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x022, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h024 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h022 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x022, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h024 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h022 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x022, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h15 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h15 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h15 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h15 (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h22 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h24 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h22 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h24 (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x22, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x24, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x22, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x24, SHURK_PI_RK0_ARPI_DQM_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @8831 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @8845 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @8873 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h20 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h20 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h20 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h20 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h20 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h20 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h20 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h20 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h20 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @8838 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h28 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h28 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h28 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h28 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @8852 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h28 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h28 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h28 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h28 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @8879 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h28 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5345 + TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0) + TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0) + TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ9_0 ral_reg_DDRPHY_blk_SHU_B0_DQ9_0 - @7845 + RG_ARPI_RESERVE_B0 uvm_reg_field ... RW SHU_B0_DQ9_0[31:0]=32'h31105ab1 (Mirror: 32'h31165ab1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0x31105ab1, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ9_0 ral_reg_DDRPHY_blk_SHU_B1_DQ9_0 - @9248 + RG_ARPI_RESERVE_B1 uvm_reg_field ... RW SHU_B1_DQ9_0[31:0]=32'hd5713d50 (Mirror: 32'hd5733d50) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xd5713d50, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter: +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041 + TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052 + TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01 + TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | + P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | + P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060 + TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071 + TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082 + dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1 + dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1 + dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1) + dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1 + dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1 + dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1 + dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1 + dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199 + TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 + TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 + TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0) + TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 + TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0) + TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0) + TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 + TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) + TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 + TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 + TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h0 + TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h1 (Mirror: 1'h0) + TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h1 (Mirror: 1'h0) + TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 + TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h1 (Mirror: 1'h0) + TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h0 + TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0 + TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0) + BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 + BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 + BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0) + TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 + TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) + XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 + TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0) + TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0) + TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0 + TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 + TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 + TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 + XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h1 + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'ha (Mirror: 4'h1) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h10 (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h4 (Mirror: 3'h0) + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2) + TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'hc (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +#if (fcFOR_CHIP_ID == fcA60868) +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0xa, SHU_ACTIM0_TWTR) | + P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x10, SHU_ACTIM0_TWR) | + P_Fld(0x4, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) | + P_Fld(0xc, SHU_ACTIM0_TWTR_L)); +#elif (fcFOR_CHIP_ID == fcPetrus) +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0xa, SHU_ACTIM0_TWTR) | + P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x10, SHU_ACTIM0_TWR) | + P_Fld(0x4, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD)); +#endif +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'ha + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h8 + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h8 (Mirror: 4'h2) + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h19 (Mirror: 5'h05) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xa, SHU_ACTIM1_TRPAB) | + P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x8, SHU_ACTIM1_TRP) | + P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x19, SHU_ACTIM1_TRC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h2 (Mirror: 4'h0) + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0e + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0) + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h0d (Mirror: 5'h05) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x2, SHU_ACTIM2_TXP) | + P_Fld(0x0e, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) | + P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x0d, SHU_ACTIM2_TFAW)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h3f (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h89 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x3f, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0x89, SHU_ACTIM3_TRFC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h09a (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0b (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x09a, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0b, SHU_ACTIM4_TMRR2W) | + P_Fld(0x2e, SHU_ACTIM4_TZQCS)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h0f (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h12 (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h30 (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0f, SHU_ACTIM5_TR2PD) | + P_Fld(0x12, SHU_ACTIM5_TWTPD) | P_Fld(0x30, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0b (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h12 (Mirror: 6'h13) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | + P_Fld(0x0b, SHU_ACTIM6_TW2MRW) | P_Fld(0x12, SHU_ACTIM6_TR2MRW)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2) + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | + P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_TX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_TX_PIPE_CTRL_0 - @12708 + CMD_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) + CK_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[1:1]=1'h1 (Mirror: 1'h0) + TX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[2:2]=1'h0 + CS_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[3:3]=1'h1 (Mirror: 1'h0) + SKIP_TXPIPE_BYPASS uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[8:8]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL, P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) | + P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) | + P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h6f (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h6f (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h6f (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h6f (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h6f (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h6f (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h6f (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h6f (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x6f, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x6f, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h02f (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h02f (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x02f, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x02f, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h6e (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h6e (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h6e (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h6e (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h6e (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h6e (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h6e (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h6e (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x6e, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h02e (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h02e (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x02e, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x02e, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h6f (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h6f (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h6f (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h6f (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h6f (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h6f (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h6f (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h6f (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h6f (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h6f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x6f, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x6f, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h02f (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h02f (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x02f, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x02f, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h6e (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h6e (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h6e (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h6e (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h6e (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h6e (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h6e (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h6e (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h6e (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h6e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x6e, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h02e (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h02e (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x02e, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x02e, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h75 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h75 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h2f (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h2f (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x2f, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x2f, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h75 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h75 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h2f (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h2f (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x2f, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x2f, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001 + FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0) + FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0 + FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h0 + DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0) + DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h0 + LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h0 + LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h0 + CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0 + BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0 + BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0) + LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0 + BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1 + LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h0 + SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) | + P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) | + P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | + P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) | + P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) | + P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | + P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) | + P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255 + SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a) + TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0 + REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000 + TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | + P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | + P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0) + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +#if (fcFOR_CHIP_ID == fcA60868) +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +#elif (fcFOR_CHIP_ID == fcPetrus) +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +#endif +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356 + DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08) + ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0 + ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0) + PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0) + REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0) + REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) | + P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | + P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | + P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996 + MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0) + NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) | + P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SCHEDULER_0 ral_reg_DRAMC_blk_SHU_SCHEDULER_0 - @5023 + DUALSCHEN uvm_reg_field ... RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899 + TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0 + TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0 + DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0 + TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1 + DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0 + OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0 + DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0 + WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0) + DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0 + DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0 + ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0 + TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0 + DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0 + DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0 + RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0 + DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) | + P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) | + P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) | + P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) | + P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) | + P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) | + P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) | + P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) | + P_Fld(0x0, TX_SET0_DRAMOEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0) + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0) + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0) + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +#if (fcFOR_CHIP_ID == fcA60868) +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +#elif (fcFOR_CHIP_ID == fcPetrus) +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +#endif +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514 + DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0 + DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0 + r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0 + STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0) + STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0) + DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | + P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | + P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | + P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499 + DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0) + PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0) + DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0) + DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0) + DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h1 + DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1 + DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0 + STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0) + STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0) + DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0 + DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0 + DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) | + P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) | + P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562 + RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0) + RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0 + RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0 + RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1 + RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0 + RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0) + RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0 + RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | + P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751 + DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0) + RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0) + RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | + P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0) + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0) + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0) + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +#if (fcFOR_CHIP_ID == fcA60868) +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +#elif (fcFOR_CHIP_ID == fcPetrus) +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +#endif +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_HWSET_MR2_0 ral_reg_DRAMC_blk_SHU_HWSET_MR2_0 - @5122 + HWSET_MR2_MRSMA uvm_reg_field ... RW SHU_HWSET_MR2_0[12:0]=13'h0002 + HWSET_MR2_OP uvm_reg_field ... RW SHU_HWSET_MR2_0[23:16]=8'h3f (Mirror: 8'h12) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) | + P_Fld(0x3f, SHU_HWSET_MR2_HWSET_MR2_OP)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384 + tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h72 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h09 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | + P_Fld(0x72, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x09, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | + P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523 + r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h0 + r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0 + r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46) + r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | + P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | + P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); + + mcDELAY_US(1); + +/*TINFO=---===BROADCAST OFF!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter + mcDELAY_US(1); + + mcDELAY_US(1); + +/*TINFO=---===BROADCAST ON!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338 + DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h15 (Mirror: 8'h00) + DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0 + DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0 + DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x15, SHU_DQSOSCR_DQSOSCRCNT) | + P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | + P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332 + DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1 + DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h012 (Mirror: 10'h00f) + DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x012, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h0326 (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h0326 (Mirror: 16'h0000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0326, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0326, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h0159 (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h0159 (Mirror: 16'h0000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h018 (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h010 (Mirror: 12'h001) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x018, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x010, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h004 (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h002 (Mirror: 12'h001) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x004, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h17 (Mirror: 6'h0e) + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +#if (fcFOR_CHIP_ID == fcA60868) +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x17, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +#elif (fcFOR_CHIP_ID == fcPetrus) +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x17, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +#endif +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 + ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0000 + TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1d (Mirror: 5'h1b) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0000, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 + ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000) + TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1d +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'hb (Mirror: 4'h0) + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h1 (Mirror: 1'h0) + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h1 (Mirror: 1'h0) + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0xb, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'hb (Mirror: 4'h0) + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h1 (Mirror: 1'h0) + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h1 (Mirror: 1'h0) + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0xb, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ11_0 ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 - @7794 + RG_RX_ARDQ_RANK_SEL_SER_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[0:0]=1'h0 + RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[1:1]=1'h0 + RG_RX_ARDQ_OFFSETC_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[2:2]=1'h0 + RG_RX_ARDQ_OFFSETC_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[3:3]=1'h0 + RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[4:4]=1'h0 + RG_RX_ARDQ_FRATE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[5:5]=1'h0 + RG_RX_ARDQ_CDR_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[6:6]=1'h0 + RG_RX_ARDQ_DVS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQ_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[11:8]=4'h0 + RG_RX_ARDQ_DES_MODE_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[17:16]=2'h2 + RG_RX_ARDQ_BW_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[19:18]=2'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ11_0 ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 - @9197 + RG_RX_ARDQ_RANK_SEL_SER_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[0:0]=1'h0 + RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[1:1]=1'h0 + RG_RX_ARDQ_OFFSETC_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[2:2]=1'h0 + RG_RX_ARDQ_OFFSETC_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[3:3]=1'h0 + RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[4:4]=1'h0 + RG_RX_ARDQ_FRATE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[5:5]=1'h0 + RG_RX_ARDQ_CDR_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[6:6]=1'h0 + RG_RX_ARDQ_DVS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQ_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[11:8]=4'h0 + RG_RX_ARDQ_DES_MODE_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[17:16]=2'h2 + RG_RX_ARDQ_BW_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[19:18]=2'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); +// Exit body +} + + +#if __LP5_COMBO__ +void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p) +{ + // Enter body + // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634 + DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00) + DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00) + DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00) + DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00) + DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00) + DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00) + DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0 + DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | + P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645 + CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00) + CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00) + CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00) + CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00) + DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00) + DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00) + DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655 + DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00) + DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00) + DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00) + DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00) + DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00) + DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664 + CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00) + CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00) + CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00) + CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00) + DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00) + DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682 + IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h09 (Mirror: 6'h01) + DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00 + DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x09, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | + P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625 + IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h5 (Mirror: 3'h4) + IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00 + IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00 + IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4 + IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00) + IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x5, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | + P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | + P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | + P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0e (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfd7 (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h029 (Mirror: 12'h000) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0e, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xfd7, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x029, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0e (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0e (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0e (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0e, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0) + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0) + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0 + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h7 (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0) + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0) + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x7, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'ha (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'he (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xa, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xe, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00) + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'ha (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'he (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xa, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xe, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h6 (Mirror: 4'h0) + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x6, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @12704 + RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h5 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h5 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h5 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h5 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0) + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h8 (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0) + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x8, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x0a, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x0a, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x0a, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0e (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x0a, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10426 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h10 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h0f (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h0f (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0f, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x0f, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10436 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h10 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h0e (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h0e (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0e, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x0e, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h15 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h15 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0) + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0) + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282 + dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h6 (Mirror: 4'h1) + dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h7 (Mirror: 4'h1) + dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 + dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 + dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h3 (Mirror: 4'h1) + dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h4 (Mirror: 4'h1) + dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 + dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x6, SHU_SELPH_DQS1_DLY_DQS0) | + P_Fld(0x7, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS1_DLY_OEN_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h5 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h5 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h1 + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h1 + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x5, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x5, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h5 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h5 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h1 + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h1 + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x5, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x5, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h6 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h6 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h2 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h2 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h6 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h6 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h2 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h2 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h00f (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h018 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x00f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h00f (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h018 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x00f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h00f (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h018 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x00f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h00e (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h015 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h00e (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h015 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h00e (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h015 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h18 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h0f (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h18 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h0f (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x0f, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x0f, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h15 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h0e (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h15 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h0e (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x0e, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x0e, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h2c (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h2c (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h2c (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h2c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h2c (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h2c (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h2c (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h2c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h2c (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h2c (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h2c (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h2c (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h2c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h2c (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h2c (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h2c (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h2c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h2c (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @8838 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @8852 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @8879 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5345 + TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0) + TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0) + TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_WR_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0 - @4936 + WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h3 (Mirror: 4'h1) + WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h3 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) | + P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_WR_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1 - @4941 + WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h3 (Mirror: 4'h1) + WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h3 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) | + P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_RD_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0 - @4946 + WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h4 (Mirror: 4'h1) + WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h4 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_RD_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1 - @4951 + WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h4 (Mirror: 4'h1) + WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h4 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_FS_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0 - @4956 + WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h2 (Mirror: 4'h1) + WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h2 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) | + P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_FS_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1 - @4961 + WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h2 (Mirror: 4'h1) + WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h2 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) | + P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_FS_UI_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_0 - @4986 + WCK_FS_B0_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_0[3:0]=4'h5 (Mirror: 4'h1) + WCK_FS_B1_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_0[7:4]=4'h5 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI, P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B0_UI) | + P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B1_UI)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_FS_UI_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_1 - @4991 + WCK_FS_B0_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_1[3:0]=4'h5 (Mirror: 4'h1) + WCK_FS_B1_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_1[7:4]=4'h5 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B0_UI) | + P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B1_UI)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041 + TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052 + TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01 + TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | + P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | + P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060 + TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071 + TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082 + dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1 + dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1 + dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1) + dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1 + dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1 + dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1 + dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1 + dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h64 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x64, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199 + TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h1 (Mirror: 1'h0) + TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 + TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 + TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 + TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0) + TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0 + TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0) + TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) + TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h1 (Mirror: 1'h0) + TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 + TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) + TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 + TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 + TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 + TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 + TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0) + TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0) + TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 + BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 + BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 + BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0 + TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h1 (Mirror: 1'h0) + TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h0 + XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 + TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0 + TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0 + TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0 + TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 + TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 + TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 + XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h09 (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h0b (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h6 (Mirror: 4'h1) + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h06 (Mirror: 5'h01) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x09, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x0b, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x6, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x06, SHU_ACTIM_XRT_XRTW2W)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'h9 (Mirror: 4'h1) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h13 (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h2 (Mirror: 3'h0) + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h7 (Mirror: 4'h2) + TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h9 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x9, SHU_ACTIM0_TWTR) | + P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x13, SHU_ACTIM0_TWR) | + P_Fld(0x2, SHU_ACTIM0_TRRD) | P_Fld(0x7, SHU_ACTIM0_TRCD) | + P_Fld(0x9, SHU_ACTIM0_TWTR_L)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h8 (Mirror: 4'ha) + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h8 + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h7 (Mirror: 4'h2) + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h08 (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h10 (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x8, SHU_ACTIM1_TRPAB) | + P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x7, SHU_ACTIM1_TRP) | + P_Fld(0x08, SHU_ACTIM1_TRAS) | P_Fld(0x10, SHU_ACTIM1_TRC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h2 (Mirror: 4'h0) + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0b (Mirror: 5'h0e) + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0) + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h06 (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x2, SHU_ACTIM2_TXP) | + P_Fld(0x0b, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) | + P_Fld(0x06, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h2c (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h64 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x2c, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0x64, SHU_ACTIM3_TRFC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h073 (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h22 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x073, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) | + P_Fld(0x22, SHU_ACTIM4_TZQCS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h11 (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h16 (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h24 (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x11, SHU_ACTIM5_TR2PD) | + P_Fld(0x16, SHU_ACTIM5_TWTPD) | P_Fld(0x24, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x3, SHU_ACTIM5_TPBR2ACT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h0c (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h6 (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0a (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h0f (Mirror: 6'h13) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x0c, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x6, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | + P_Fld(0x0a, SHU_ACTIM6_TW2MRW) | P_Fld(0x0f, SHU_ACTIM6_TR2MRW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h1 (Mirror: 1'h0) + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h2 (Mirror: 3'h1) + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2) + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x1, SHU_CKECTRL_TPDX_05T) | P_Fld(0x2, SHU_CKECTRL_TPDE) | + P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_LP5_CMD_0 ral_reg_DRAMC_blk_SHU_LP5_CMD_0 - @5427 + LP5_CMD1TO2EN uvm_reg_field ... RW SHU_LP5_CMD_0[0:0]=1'h0 + TCSH uvm_reg_field ... RW SHU_LP5_CMD_0[7:4]=4'h5 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) | + P_Fld(0x5, SHU_LP5_CMD_TCSH)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM7_0 ral_reg_DRAMC_blk_SHU_ACTIM7_0 - @5436 + TCSH_CSCAL uvm_reg_field ... RW SHU_ACTIM7_0[3:0]=4'h3 (Mirror: 4'h0) + TCACSH uvm_reg_field ... RW SHU_ACTIM7_0[7:4]=4'h1 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0x3, SHU_ACTIM7_TCSH_CSCAL) | + P_Fld(0x1, SHU_ACTIM7_TCACSH)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_WCKCTRL_0 ral_reg_DRAMC_blk_SHU_WCKCTRL_0 - @5407 + WCKRDOFF uvm_reg_field ... RW SHU_WCKCTRL_0[5:0]=6'h0c (Mirror: 6'h00) + WCKRDOFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[7:7]=1'h0 + WCKWROFF uvm_reg_field ... RW SHU_WCKCTRL_0[13:8]=6'h08 (Mirror: 6'h00) + WCKWROFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[15:15]=1'h0 + WCKDUAL uvm_reg_field ... RW SHU_WCKCTRL_0[16:16]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x0c, SHU_WCKCTRL_WCKRDOFF) | + P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x08, SHU_WCKCTRL_WCKWROFF) | + P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h00c4 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x00c4, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h00c4 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x00c4, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h4 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x4, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h4 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x4, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h76 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h76 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h76 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h76 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h76 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h76 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h76 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h76 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x76, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x76, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h047 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h047 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x047, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x047, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h046 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h046 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x046, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x046, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h76 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h76 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h76 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h76 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h76 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h76 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h76 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h76 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h76 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h76 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x76, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x76, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h047 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h047 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x047, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x047, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h75 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h75 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h75 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h75 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h046 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h046 (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x046, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x046, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h7e (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h7e (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h36 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h36 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x7e, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x7e, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x36, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x36, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h7e (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h7e (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h36 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h36 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x7e, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x7e, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x36, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x36, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001 + FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0) + FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0 + FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h0 + DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0) + DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h0 + LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h0 + LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h0 + CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0 + BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0 + BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0) + LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0 + BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1 + LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h0 + SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) | + P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) | + P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | + P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) | + P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) | + P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | + P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) | + P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_WCKCTRL_1_0 ral_reg_DRAMC_blk_SHU_WCKCTRL_1_0 - @5415 + WCKSYNC_PRE_MODE uvm_reg_field ... RW SHU_WCKCTRL_1_0[0:0]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DRAMC_REG_SHU_WCKCTRL_1, 0x1, SHU_WCKCTRL_1_WCKSYNC_PRE_MODE); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255 + SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a) + TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0 + REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000 + TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | + P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | + P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0) + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356 + DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08) + ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0 + ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0) + PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0) + REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0) + REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) | + P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | + P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | + P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996 + MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0) + NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) | + P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SCHEDULER_0 ral_reg_DRAMC_blk_SHU_SCHEDULER_0 - @5023 + DUALSCHEN uvm_reg_field ... RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899 + TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0 + TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0 + DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0 + TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1 + DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0 + OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0 + DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0 + WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0) + DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0 + DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0 + ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0 + TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0 + DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0 + DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0 + RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0 + DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) | + P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) | + P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) | + P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) | + P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) | + P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) | + P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) | + P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) | + P_Fld(0x0, TX_SET0_DRAMOEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0) + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0) + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0) + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514 + DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0 + DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0 + r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0 + STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0) + STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0) + DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | + P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | + P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | + P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499 + DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0) + PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0) + DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0) + DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0) + DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h1 + DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1 + DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0 + STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0) + STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0) + DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0 + DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0 + DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) | + P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) | + P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562 + RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0) + RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0 + RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0 + RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1 + RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0 + RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0) + RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0 + RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | + P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751 + DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0) + RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0) + RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | + P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HWSET_MR13_0 ral_reg_DRAMC_blk_SHU_HWSET_MR13_0 - @5127 + HWSET_MR13_MRSMA uvm_reg_field ... RW SHU_HWSET_MR13_0[12:0]=13'h000d + HWSET_MR13_OP uvm_reg_field ... RW SHU_HWSET_MR13_0[23:16]=8'h08 (Mirror: 8'hc8) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13, P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) | + P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HWSET_VRCG_0 ral_reg_DRAMC_blk_SHU_HWSET_VRCG_0 - @5132 + HWSET_VRCG_MRSMA uvm_reg_field ... RW SHU_HWSET_VRCG_0[12:0]=13'h000d + HWSET_VRCG_OP uvm_reg_field ... RW SHU_HWSET_VRCG_0[23:16]=8'h00 (Mirror: 8'hc0) + VRCGDIS_PRDCNT uvm_reg_field ... RW SHU_HWSET_VRCG_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) | + P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HWSET_MR2_0 ral_reg_DRAMC_blk_SHU_HWSET_MR2_0 - @5122 + HWSET_MR2_MRSMA uvm_reg_field ... RW SHU_HWSET_MR2_0[12:0]=13'h0002 + HWSET_MR2_OP uvm_reg_field ... RW SHU_HWSET_MR2_0[23:16]=8'h2d (Mirror: 8'h12) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) | + P_Fld(0x2d, SHU_HWSET_MR2_HWSET_MR2_OP)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384 + tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h55 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h0c (Mirror: 8'h00) + tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | + P_Fld(0x55, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x0c, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | + P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523 + r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h0 + r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0 + r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46) + r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | + P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | + P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); + + mcDELAY_US(1); + + /*TINFO=---===BROADCAST OFF!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter + mcDELAY_US(1); + + mcDELAY_US(1); + + /*TINFO=---===BROADCAST ON!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338 + DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h10 (Mirror: 8'h00) + DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0 + DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0 + DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x10, SHU_DQSOSCR_DQSOSCRCNT) | + P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | + P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332 + DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1 + DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h011 (Mirror: 10'h00f) + DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x011, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h0317 (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h0317 (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0317, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0317, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h01c4 (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h01c4 (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x01c4, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x01c4, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h017 (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h00f (Mirror: 12'h001) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x017, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x00f, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h007 (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h005 (Mirror: 12'h001) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x007, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x005, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0d (Mirror: 6'h0e) + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0d, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 + ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000) + TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1b + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h64 + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x64, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + // Exit body + } + +void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p) +{ + // Enter body + // ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Enter: + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | + P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN2) | + P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x09, SHU_MISC_DRVING2_DQDRVN1) | + P_Fld(0x07, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x1, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x07, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | + P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | + P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | + P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | + P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Exit: + mcDELAY_US(1); + + mcDELAY_US(1); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) | + P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) | + P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) | + P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) | + P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) | + P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) | + P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) | + P_Fld(0x09, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) | + P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) | + P_Fld(0x1f, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) | + P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x1, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) | + P_Fld(0x1b, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) | + P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) | + P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) | + P_Fld(0x00, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA) | + P_Fld(0x1, SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) | + P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) | + P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x59, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) | + P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) | + P_Fld(0x3, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) | + P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) | + P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x7d, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) | + P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) | + P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) | + P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) | + P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) | + P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) | + P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x947a, SHU_PLL0_RG_RPHYPLL_TOP_REV) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) | + P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) | + P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) | + P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) | + P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) | + P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) | + P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) | + P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) | + P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) | + P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) | + P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET), 0x3338ac63, SHU_CA_CMD9_RG_ARPI_RESERVE_CA); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) | + P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) | + P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) | + P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x2, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0x7f8d04df, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0xa40fc3b2, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) | + P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) | + P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) | + P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x3f6e1851, SHU_CA_DLL2_RG_ARCMD_REV); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) | + P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) | + P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x8461c1a1, SHU_B0_DLL2_RG_ARDQ_REV_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0xad90b805, SHU_B1_DLL2_RG_ARDQ_REV_B1); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) | + P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) | + P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) | + P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit + // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) | + P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) | + P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) | + P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) | + P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) | + P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) | + P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) | + P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) | + P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) | + P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) | + P_Fld(0x10, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) | + P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) | + P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) | + P_Fld(0x08, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) | + P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) | + P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) | + P_Fld(0x02, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) | + P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) | + P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x2, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) | + P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) | + P_Fld(0x00, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA) | + P_Fld(0x1, SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA) | + P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) | + P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) | + P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) | + P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x76, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) | + P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) | + P_Fld(0x3, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) | + P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) | + P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x4c, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) | + P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) | + P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) | + P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) | + P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) | + P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) | + P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) | + P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) | + P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) | + P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1d17, SHU_PLL0_RG_RPHYPLL_TOP_REV) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) | + P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) | + P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) | + P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) | + P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) | + P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) | + P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) | + P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) | + P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) | + P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) | + P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) | + P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) | + P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) | + P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) | + P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) | + P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xd084ae4a, SHU_CA_CMD9_RG_ARPI_RESERVE_CA); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) | + P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) | + P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) | + P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x3, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x2, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x27759cf9, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x5a41c75f, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) | + P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) | + P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) | + P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) | + P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x2, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) | + P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) | + P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x249e9d9e, SHU_CA_DLL2_RG_ARCMD_REV); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) | + P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x2, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) | + P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) | + P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) | + P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) | + P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) | + P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x23566f78, SHU_B0_DLL2_RG_ARDQ_REV_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xaec2cdcb, SHU_B1_DLL2_RG_ARDQ_REV_B1); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) | + P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) | + P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) | + P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) | + P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) | + P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) | + P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) | + P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) | + P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) | + P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit + mcDELAY_US(1); + + mcDELAY_US(1); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN) | + P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN) | + P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA) | + P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0) | + P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0) | + P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1) | + P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1) | + P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX_MODE_SET related setting Enter + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x2, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) | + P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) | + P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) | + P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) | + P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Enter: + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0f, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xff0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x010, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0f, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_PHY)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL); + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL); + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x6, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x1e, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x17, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x6, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x1e, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x17, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x3, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x7, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x04, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x04, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x05, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x05, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x04, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x06, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x04, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x06, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x05, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x07, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x07, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Exit: + // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Enter: + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x09, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x09, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x09, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x09, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xa, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x0, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x0, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x009, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x009, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x009, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B0)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x09, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x09, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x09, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x09, SHURK_PI_RK0_ARPI_DQM_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0x7f8904df, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0xa409c3b2, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Exit: + // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX WCK auto-generation set Enter + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) | + P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) | + P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) | + P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) | + P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B0_UI) | + P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B1_UI)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B0_UI) | + P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B1_UI)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B0_UI) | + P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B1_UI)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B0_UI) | + P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B1_UI)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B0_UI) | + P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B1_UI)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B0_UI) | + P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B1_UI)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX WCK auto-generation set Exit + // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Enter: + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | + P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | + P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Exit + // ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Enter: + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x1, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0d, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x4, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x04, SHU_ACTIM_XRT_XRTW2W)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHU_ACTIM0_TWTR) | + P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x06, SHU_ACTIM0_TWR) | + P_Fld(0x0, SHU_ACTIM0_TRRD) | P_Fld(0x3, SHU_ACTIM0_TRCD) | + P_Fld(0xe, SHU_ACTIM0_TWTR_L)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_ACTIM1_TRPAB) | + P_Fld(0x3, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x1, SHU_ACTIM1_TRP) | + P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_ACTIM2_TXP) | + P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x1, SHU_ACTIM2_TRTP) | + P_Fld(0x04, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x09, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0x1e, SHU_ACTIM3_TRFC)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x02b, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x38, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) | + P_Fld(0x0c, SHU_ACTIM4_TZQCS)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x08, SHU_ACTIM5_TR2PD) | + P_Fld(0x08, SHU_ACTIM5_TWTPD) | P_Fld(0x0e, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x05, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x2, SHU_ACTIM6_TMRD) | P_Fld(0x0, SHU_ACTIM6_TMRW) | + P_Fld(0x22, SHU_ACTIM6_TW2MRW) | P_Fld(0x13, SHU_ACTIM6_TR2MRW)); + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | + P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); + vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) | + P_Fld(0xb, SHU_LP5_CMD_TCSH)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xb, SHU_ACTIM7_TCSH_CSCAL) | + P_Fld(0xb, SHU_ACTIM7_TCACSH)); + vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2b, SHU_WCKCTRL_WCKRDOFF) | + P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x2b, SHU_WCKCTRL_WCKWROFF) | + P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) | + P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) | + P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Exit + // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Enter. + // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Exit. + // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x6, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x6, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x17, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0be, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x0be, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x16, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0bd, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x0bd, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x17, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0be, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x0be, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x16, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set EXIT + // ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Enter + vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_COMMON0_FREQDIV4) | + P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x1, SHU_COMMON0_FREQDIV8) | + P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | + P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) | + P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) | + P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | + P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) | + P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); + vIO32WriteFldAlign(DRAMC_REG_SHU_WCKCTRL_1+(1*SHU_GRP_DRAMC_OFFSET), 0x1, SHU_WCKCTRL_1_WCKSYNC_PRE_MODE); + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | + P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | + P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3f, SHU_CONF0_DMPGTIM) | + P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | + P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | + P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); + vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MATYPE_MATYPE) | + P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); + vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER+(1*SHU_GRP_DRAMC_OFFSET), 0x1, SHU_SCHEDULER_DUALSCHEN); + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | + P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | + P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | + P_Fld(0x0, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL_DMSTBLAT) | + P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) | + P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) | + P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) | + P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | + P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | + P_Fld(0x2, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | + P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Exit + // ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Enter + // ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Exit + // ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Enter + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) | + P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP)); + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) | + P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Exit + // ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Enter + vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | + P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | + P_Fld(0x55, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Exit + // ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Enter + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | + P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | + P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); + + mcDELAY_US(1); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Enter + mcDELAY_US(1); + + mcDELAY_US(1); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + // ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Exit + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0c, SHU_DQSOSCR_DQSOSCRCNT) | + P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | + P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0844, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0844, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0a6, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x06f, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x036, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x024, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x06, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); + vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT)); + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + // Exit body +} + +void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p) +{ +// Enter body +// ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter: +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634 + DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00) + DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00) + DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00) + DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00) + DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00) + DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00) + DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0 + DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | + P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645 + CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00) + CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00) + CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00) + CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00) + DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00) + DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00) + DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655 + DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00) + DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00) + DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00) + DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00) + DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00) + DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664 + CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00) + CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00) + CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00) + CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00) + DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00) + DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682 + IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h0d (Mirror: 6'h01) + DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00 + DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x0d, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | + P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625 + IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h7 (Mirror: 3'h4) + IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00 + IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00 + IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4 + IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00) + IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x7, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | + P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | + P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | + P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit: +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h13 (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x13, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h13 (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h12 (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h12 (Mirror: 5'h00) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x13, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x12, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x12, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0) + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h3 (Mirror: 3'h0) + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x3, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h8 (Mirror: 4'h0) + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0 + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'hb (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h9 (Mirror: 4'h0) + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h9 (Mirror: 4'h0) + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'hc (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0xb, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0xc, MISC_SHU_RANKCTL_RANKINCTL_PHY)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'hb (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0xb, MISC_SHU_RK_DQSCTL_DQSINCTL); +/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'hb (Mirror: 4'h0) +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0xb, MISC_SHU_RK_DQSCTL_DQSINCTL); +/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hb (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hf (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xb, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xf, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); +/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Name Type Size Value +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h05 (Mirror: 7'h00) +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x05, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hd (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1b (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hb (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hf (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xb, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xf, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h05 (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x05, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hd (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1b (Mirror: 7'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'ha (Mirror: 4'h0) + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0xa, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h6 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h6 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x6, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h0 + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h0 + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h6 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h6 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x6, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h0 + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h0 + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h1 (Mirror: 1'h0) + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0) + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'hc (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0) + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0xc, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x05, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x05, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x0d, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x0d, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x05, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0f (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h11 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h11 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10426 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h1f (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h1f (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x1f, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h25 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h25 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x25, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x25, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10436 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h2c (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h2c (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x2c, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x2c, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h1f (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h1f (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h4 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x4, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h5 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h4 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x5, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h5 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h4 (Mirror: 3'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h4 (Mirror: 3'h0) + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h4 (Mirror: 3'h0) + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x4, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x4, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h5 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h5 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1) + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282 + dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h2 (Mirror: 4'h1) + dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h3 (Mirror: 4'h1) + dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 + dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 + dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h0 (Mirror: 4'h1) + dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 + dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x2, SHU_SELPH_DQS1_DLY_DQS0) | + P_Fld(0x3, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x7, SHU_SELPH_DQS1_DLY_OEN_DQS0) | + P_Fld(0x0, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h5 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h5 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h5 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h5 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1 + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1 + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h5 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h5 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x5, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1 + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1 + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h5 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h5 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x5, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h5 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h5 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h5 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h5 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h5 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h6 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h6 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h01f (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h025 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x025, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h01f (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h025 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x025, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h01f (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h025 (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x025, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h02c (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h01f (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h02c (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h01f (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h02c (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h01f (Mirror: 11'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h25 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h1f (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h25 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h1f (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x25, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x25, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h1f (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h2c (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h1f (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h2c (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x2c, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x2c, SHURK_PI_RK0_ARPI_DQM_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h14 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h14 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h14 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h14 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h14 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h14 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h14 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h14 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h14 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x14, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h04 (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h04 (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h04 (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h04 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h04 (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h04 (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h04 (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h04 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h04 (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @8838 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h34 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h34 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h34 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h34 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @8852 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h34 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h34 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h34 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h34 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @8879 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h34 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5345 + TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h3 (Mirror: 4'h0) + TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h3 (Mirror: 4'h0) + TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x3, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x3, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ9_0 ral_reg_DDRPHY_blk_SHU_B1_DQ9_0 - @9248 + RG_ARPI_RESERVE_B1 uvm_reg_field ... RW SHU_B1_DQ9_0[31:0]=32'hce301f15 (Mirror: 32'hce341f15) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xce301f15, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_WCK_WR_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0 - @4936 + WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h5 (Mirror: 4'h1) + WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h5 (Mirror: 4'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) | + P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_WCK_WR_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1 - @4941 + WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h5 (Mirror: 4'h1) + WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h5 (Mirror: 4'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) | + P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_WCK_RD_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0 - @4946 + WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h8 (Mirror: 4'h1) + WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h8 (Mirror: 4'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +#if LP5_DDR4266_RDBI_WORKAROUND +vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); +#else +vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x7, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x7, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); +#endif + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_WCK_RD_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1 - @4951 + WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h8 (Mirror: 4'h1) + WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h8 (Mirror: 4'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_WCK_FS_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0 - @4956 + WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h4 (Mirror: 4'h1) + WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h4 (Mirror: 4'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) | + P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_WCK_FS_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1 - @4961 + WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h4 (Mirror: 4'h1) + WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h4 (Mirror: 4'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) | + P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter: +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041 + TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052 + TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01 + TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | + P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | + P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060 + TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071 + TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082 + dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1 + dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1 + dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1) + dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1 + dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1 + dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1 + dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1 + dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199 + TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 + TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 + TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 + TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 + TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0 + TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0 + TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 + TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h0 + TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 + TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 + TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) + TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 + TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 + TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 + TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 + TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0) + TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0 + TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 + BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 + BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 + BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0) + TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 + TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) + XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h1 (Mirror: 1'h0) + TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0 + TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0 + TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0 + TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 + TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 + TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 + XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x1, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h09 (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h0e (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h0 (Mirror: 4'h1) + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h0d (Mirror: 5'h01) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x09, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x0e, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x0, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x0d, SHU_ACTIM_XRT_XRTW2W)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'h9 (Mirror: 4'h1) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h25 (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h3 (Mirror: 3'h0) + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2) + TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'hf (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x9, SHU_ACTIM0_TWTR) | + P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x25, SHU_ACTIM0_TWR) | + P_Fld(0x3, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) | + P_Fld(0xf, SHU_ACTIM0_TWTR_L)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'hc (Mirror: 4'ha) + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'he (Mirror: 4'h8) + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'ha (Mirror: 4'h2) + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h19 (Mirror: 5'h05) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xc, SHU_ACTIM1_TRPAB) | + P_Fld(0xe, SHU_ACTIM1_TMRWCKEL) | P_Fld(0xa, SHU_ACTIM1_TRP) | + P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x19, SHU_ACTIM1_TRC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h3 (Mirror: 4'h0) + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0f (Mirror: 5'h0e) + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h4 (Mirror: 3'h0) + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h12 (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h0d (Mirror: 5'h05) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x3, SHU_ACTIM2_TXP) | + P_Fld(0x0f, SHU_ACTIM2_TMRRI) | P_Fld(0x4, SHU_ACTIM2_TRTP) | + P_Fld(0x12, SHU_ACTIM2_TR2W) | P_Fld(0x0d, SHU_ACTIM2_TFAW)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h3f (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h8a (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x3f, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0x8a, SHU_ACTIM3_TRFC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h09a (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h1b (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h17 (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x09a, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x1b, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x17, SHU_ACTIM4_TMRR2W) | + P_Fld(0x2e, SHU_ACTIM4_TZQCS)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h20 (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h23 (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h30 (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x20, SHU_ACTIM5_TR2PD) | + P_Fld(0x23, SHU_ACTIM5_TWTPD) | P_Fld(0x30, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'ha (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'ha (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h17 (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h20 (Mirror: 6'h13) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) | + P_Fld(0xa, SHU_ACTIM6_TMRD) | P_Fld(0xa, SHU_ACTIM6_TMRW) | + P_Fld(0x17, SHU_ACTIM6_TW2MRW) | P_Fld(0x20, SHU_ACTIM6_TR2MRW)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2) + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | + P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x3, SHU_CKECTRL_TCKESRX)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_LP5_CMD_0 ral_reg_DRAMC_blk_SHU_LP5_CMD_0 - @5427 + LP5_CMD1TO2EN uvm_reg_field ... RW SHU_LP5_CMD_0[0:0]=1'h0 + TCSH uvm_reg_field ... RW SHU_LP5_CMD_0[7:4]=4'h4 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) | + P_Fld(0x4, SHU_LP5_CMD_TCSH)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIM7_0 ral_reg_DRAMC_blk_SHU_ACTIM7_0 - @5436 + TCSH_CSCAL uvm_reg_field ... RW SHU_ACTIM7_0[3:0]=4'h4 (Mirror: 4'h0) + TCACSH uvm_reg_field ... RW SHU_ACTIM7_0[7:4]=4'h3 (Mirror: 4'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0x4, SHU_ACTIM7_TCSH_CSCAL) | + P_Fld(0x3, SHU_ACTIM7_TCACSH)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_WCKCTRL_0 ral_reg_DRAMC_blk_SHU_WCKCTRL_0 - @5407 + WCKRDOFF uvm_reg_field ... RW SHU_WCKCTRL_0[5:0]=6'h13 (Mirror: 6'h00) + WCKRDOFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[7:7]=1'h0 + WCKWROFF uvm_reg_field ... RW SHU_WCKCTRL_0[13:8]=6'h0c (Mirror: 6'h00) + WCKWROFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[15:15]=1'h0 + WCKDUAL uvm_reg_field ... RW SHU_WCKCTRL_0[16:16]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x13, SHU_WCKCTRL_WCKRDOFF) | + P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x0c, SHU_WCKCTRL_WCKWROFF) | + P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MISC_TX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_TX_PIPE_CTRL_0 - @12708 + CMD_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) + CK_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[1:1]=1'h1 (Mirror: 1'h0) + TX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[2:2]=1'h0 + CS_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[3:3]=1'h0 + SKIP_TXPIPE_BYPASS uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[8:8]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL, P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) | + P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) | + P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h59 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h59 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h59 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h59 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h59 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h59 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h59 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h59 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x59, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x59, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h016 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h016 (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x016, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x016, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h58 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h58 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h58 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h58 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h58 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h58 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h58 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h58 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x58, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h015 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h015 (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x015, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x015, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h59 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h59 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h59 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h59 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h59 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h59 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h59 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h59 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h59 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h59 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x59, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x59, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h016 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h016 (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x016, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x016, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h58 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h58 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h58 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h58 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h58 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h58 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h58 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h58 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h58 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h58 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x58, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h015 (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h015 (Mirror: 9'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x015, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x015, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h5f (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h5f (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h19 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h19 (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x5f, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x5f, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x19, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x19, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h5f (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h5f (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h19 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h19 (Mirror: 6'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x5f, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x5f, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x19, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x19, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001 + FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0) + FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0 + FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h0 + DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0) + DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h0 + LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h1 (Mirror: 1'h0) + LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h1 (Mirror: 1'h0) + CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0 + BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0 + BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0) + LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0 + BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1 + LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h1 (Mirror: 1'h0) + SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) | + P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) | + P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | + P_Fld(0x1, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) | + P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) | + P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | + P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) | + P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_LP5_CMD_0 ral_reg_DRAMC_blk_SHU_LP5_CMD_0 - @5427 + LP5_CMD1TO2EN uvm_reg_field ... RW SHU_LP5_CMD_0[0:0]=1'h1 (Mirror: 1'h0) + TCSH uvm_reg_field ... RW SHU_LP5_CMD_0[7:4]=4'h4 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x1, SHU_LP5_CMD_LP5_CMD1TO2EN) | + P_Fld(0x4, SHU_LP5_CMD_TCSH)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255 + SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a) + TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0 + REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000 + TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | + P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | + P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0) + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356 + DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08) + ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0 + ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0) + PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0) + REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0) + REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) | + P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | + P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | + P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996 + MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0) + NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) | + P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899 + TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0 + TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0 + DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0 + TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1 + DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0 + OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0 + DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0 + WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0) + DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0 + DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0 + ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0 + TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0 + DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0 + DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0 + RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0 + DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) | + P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) | + P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) | + P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) | + P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) | + P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) | + P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) | + P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) | + P_Fld(0x0, TX_SET0_DRAMOEN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0) + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0) + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0) + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514 + DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0 + DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0 + r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0 + STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0) + STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0) + DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | + P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | + P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | + P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499 + DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0) + PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0) + DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0) + DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0) + DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h2 (Mirror: 2'h1) + DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1 + DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0 + STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0) + STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0) + DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0 + DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0 + DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) | + P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x2, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) | + P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562 + RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0) + RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0 + RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0 + RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1 + RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0 + RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0) + RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0 + RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | + P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751 + DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0) + RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0) + RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | + P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0) + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0) + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0) + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_HWSET_MR2_0 ral_reg_DRAMC_blk_SHU_HWSET_MR2_0 - @5122 + HWSET_MR2_MRSMA uvm_reg_field ... RW SHU_HWSET_MR2_0[12:0]=13'h0002 + HWSET_MR2_OP uvm_reg_field ... RW SHU_HWSET_MR2_0[23:16]=8'h3f (Mirror: 8'h12) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) | + P_Fld(0x3f, SHU_HWSET_MR2_HWSET_MR2_OP)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384 + tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h72 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h09 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | + P_Fld(0x72, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x09, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | + P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit +// ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523 + r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h0 + r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0 + r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46) + r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | + P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | + P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); + + mcDELAY_US(1); + +/*TINFO=---===BROADCAST OFF!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter + mcDELAY_US(1); + + mcDELAY_US(1); + +/*TINFO=---===BROADCAST ON!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); +// ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338 + DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h15 (Mirror: 8'h00) + DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0 + DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0 + DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x15, SHU_DQSOSCR_DQSOSCRCNT) | + P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | + P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332 + DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1 + DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h012 (Mirror: 10'h00f) + DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x012, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h025c (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h025c (Mirror: 16'h0000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x025c, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x025c, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h0159 (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h0159 (Mirror: 16'h0000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h00d (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h009 (Mirror: 12'h001) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x00d, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x009, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h004 (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h002 (Mirror: 12'h001) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x004, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h17 (Mirror: 6'h0e) + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x17, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 + ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0000 + TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1f (Mirror: 5'h1b) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0000, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1f, SHU_ZQ_SET0_TZQLAT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 + ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000) + TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1f +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1f, SHU_ZQ_SET0_TZQLAT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'ha (Mirror: 4'h0) + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h1 (Mirror: 1'h0) + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h1 (Mirror: 1'h0) + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0xa, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'ha (Mirror: 4'h0) + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h1 (Mirror: 1'h0) + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h1 (Mirror: 1'h0) + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0xa, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B0_DQ11_0 ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 - @7794 + RG_RX_ARDQ_RANK_SEL_SER_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[0:0]=1'h0 + RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[1:1]=1'h0 + RG_RX_ARDQ_OFFSETC_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[2:2]=1'h0 + RG_RX_ARDQ_OFFSETC_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[3:3]=1'h0 + RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[4:4]=1'h0 + RG_RX_ARDQ_FRATE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[5:5]=1'h0 + RG_RX_ARDQ_CDR_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[6:6]=1'h0 + RG_RX_ARDQ_DVS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQ_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[11:8]=4'h0 + RG_RX_ARDQ_DES_MODE_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[17:16]=2'h2 + RG_RX_ARDQ_BW_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[19:18]=2'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Name Type Size Value +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +SHU_B1_DQ11_0 ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 - @9197 + RG_RX_ARDQ_RANK_SEL_SER_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[0:0]=1'h0 + RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[1:1]=1'h0 + RG_RX_ARDQ_OFFSETC_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[2:2]=1'h0 + RG_RX_ARDQ_OFFSETC_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[3:3]=1'h0 + RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[4:4]=1'h0 + RG_RX_ARDQ_FRATE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[5:5]=1'h0 + RG_RX_ARDQ_CDR_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[6:6]=1'h0 + RG_RX_ARDQ_DVS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQ_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[11:8]=4'h0 + RG_RX_ARDQ_DES_MODE_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[17:16]=2'h2 + RG_RX_ARDQ_BW_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[19:18]=2'h0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +*/ +vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); +// Exit body +} + +void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p) +{ + // Enter body + // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634 + DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00) + DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00) + DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00) + DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00) + DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00) + DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00) + DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0 + DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | + P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645 + CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00) + CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00) + CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00) + CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00) + DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00) + DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00) + DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) | + P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) | + P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655 + DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00) + DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00) + DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00) + DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00) + DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00) + DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664 + CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00) + CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00) + CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00) + CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00) + DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00) + DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | + P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | + P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682 + IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h11 (Mirror: 6'h01) + DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00 + DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x11, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | + P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625 + IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h1 (Mirror: 3'h4) + IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00 + IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00 + IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4 + IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00) + IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x1, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | + P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | + P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | + P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734 + DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0d (Mirror: 5'h00) + RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) + RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 + SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfb9 (Mirror: 12'h000) + SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h047 (Mirror: 12'h000) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0d, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | + P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | + P_Fld(0xfb9, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x047, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604 + DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0d (Mirror: 5'h00) + DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0c (Mirror: 5'h00) + DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0c (Mirror: 5'h00) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0d, MISC_SHU_RDAT_DATLAT) | + P_Fld(0x0c, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0c, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540 + RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) + RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) + RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) + RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0 + RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h1 (Mirror: 3'h0) + RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | + P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | + P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | + P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530 + RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'hf (Mirror: 4'h0) + RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 + RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0 + RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h2 (Mirror: 4'h0) + RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h0 + RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h0 + RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h4 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0xf, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | + P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | + P_Fld(0x2, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL) | + P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_PHY)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757 + RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h1 (Mirror: 4'h0) + RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h1 (Mirror: 4'h0) + RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h1 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Name Type Size Value + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356 + DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0) + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hf (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h7 (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h2 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xf, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631 + DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h2 (Mirror: 4'h0) + DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'ha (Mirror: 4'h0) + DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h2 (Mirror: 4'h0) + DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h2 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(0xa, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642 + DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1e (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1e, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hf (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h7 (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h2 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xf, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034 + DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h2 (Mirror: 4'h0) + DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'ha (Mirror: 4'h0) + DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h2 (Mirror: 4'h0) + DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h2 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(0xa, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045 + DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1e (Mirror: 7'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1e, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550 + RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 + RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h0 + RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 + RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 + FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 + RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 + RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) + RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODT_LAT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | + P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | + P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h2 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h2 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h3 (Mirror: 3'h0) + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653 + RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h5 (Mirror: 3'h0) + RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h5 (Mirror: 3'h0) + RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h3 (Mirror: 3'h0) + RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h2 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h2 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h3 (Mirror: 3'h0) + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056 + RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h5 (Mirror: 3'h0) + RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h5 (Mirror: 3'h0) + RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h3 (Mirror: 3'h0) + RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323 + DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 + READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 + DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h0 + READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h0 + DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) + READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_RANK_SELPH_UI_DLY_0 ral_reg_DDRPHY_blk_SHU_B0_RANK_SELPH_UI_DLY_0 - @7890 + RANKSEL_UI_DLY_P0_B0 uvm_reg_field ... RW SHU_B0_RANK_SELPH_UI_DLY_0[2:0]=3'h0 + RANKSEL_UI_DLY_P1_B0 uvm_reg_field ... RW SHU_B0_RANK_SELPH_UI_DLY_0[6:4]=3'h0 + RANKSEL_MCK_DLY_P0_B0 uvm_reg_field ... RW SHU_B0_RANK_SELPH_UI_DLY_0[18:16]=3'h1 (Mirror: 3'h0) + RANKSEL_MCK_DLY_P1_B0 uvm_reg_field ... RW SHU_B0_RANK_SELPH_UI_DLY_0[22:20]=3'h1 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY, P_Fld(0x0, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B0) | + P_Fld(0x0, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B0) | P_Fld(0x1, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0) | + P_Fld(0x1, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_RANK_SELPH_UI_DLY_0 ral_reg_DDRPHY_blk_SHU_B1_RANK_SELPH_UI_DLY_0 - @9293 + RANKSEL_UI_DLY_P0_B1 uvm_reg_field ... RW SHU_B1_RANK_SELPH_UI_DLY_0[2:0]=3'h0 + RANKSEL_UI_DLY_P1_B1 uvm_reg_field ... RW SHU_B1_RANK_SELPH_UI_DLY_0[6:4]=3'h0 + RANKSEL_MCK_DLY_P0_B1 uvm_reg_field ... RW SHU_B1_RANK_SELPH_UI_DLY_0[18:16]=3'h1 (Mirror: 3'h0) + RANKSEL_MCK_DLY_P1_B1 uvm_reg_field ... RW SHU_B1_RANK_SELPH_UI_DLY_0[22:20]=3'h1 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY, P_Fld(0x0, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B1) | + P_Fld(0x0, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B1) | P_Fld(0x1, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1) | + P_Fld(0x1, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720 + RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) + RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 + RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 + RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) + RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 + RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0) + RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h3 (Mirror: 4'h0) + RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 + RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 + RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0 + RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | + P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x3, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | + P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377 + DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) + DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) + DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) + DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | + P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x1f, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x1f, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607 + CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00) + CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | + P_Fld(0x22, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010 + CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00) + CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | + P_Fld(0x22, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h27 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x1f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x27, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h27 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x1f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x27, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618 + NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00) + NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00) + NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h2a (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | + P_Fld(0x22, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x2a, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021 + NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00) + NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00) + NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h2a (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | + P_Fld(0x22, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x2a, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10426 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h10 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h26 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h26 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x26, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x26, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h21 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h21 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10436 + RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0 + RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0 + RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00 + RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h10 (Mirror: 6'h00) + RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | + P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592 + RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h21 (Mirror: 6'h00) + SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h21 (Mirror: 6'h00) + ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x21, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(0x21, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | + P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995 + RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 + RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 + SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h22 (Mirror: 6'h00) + SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h22 (Mirror: 6'h00) + ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 + DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 + DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | + P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | + P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377 + DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h1 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | + P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h2 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h2 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931 + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h2 (Mirror: 3'h0) + DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h2 (Mirror: 3'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | + P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371 + TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0) + TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) + TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | + P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271 + TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 + TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 + TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h2 (Mirror: 3'h1) + TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h2 (Mirror: 3'h1) + TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 + TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS0) | + P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | + P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282 + dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'hd (Mirror: 4'h1) + dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'he (Mirror: 4'h1) + dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 + dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 + dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'ha (Mirror: 4'h1) + dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'hb (Mirror: 4'h1) + dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 + dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0xd, SHU_SELPH_DQS1_DLY_DQS0) | + P_Fld(0xe, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0xa, SHU_SELPH_DQS1_DLY_OEN_DQS0) | + P_Fld(0xb, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | + P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'hb (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'hb (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h7 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0xb, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0xb, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'hb (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'hb (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h7 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h7 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0xb, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0xb, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757 + TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 + TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 + TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 + TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779 + TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1) + TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1) + TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 + TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 + TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h3 (Mirror: 3'h1) + TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 + TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801 + dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'hd (Mirror: 4'h1) + dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'hd (Mirror: 4'h1) + dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 + dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 + dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h9 (Mirror: 4'h1) + dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h9 (Mirror: 4'h1) + dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 + dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xd, SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(0xd, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x9, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(0x9, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823 + dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'hd (Mirror: 4'h1) + dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'hd (Mirror: 4'h1) + dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 + dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 + dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h9 (Mirror: 4'h1) + dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h9 (Mirror: 4'h1) + dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 + dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xd, SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(0xd, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x9, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(0x9, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h026 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h021 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x026, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h026 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h021 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x026, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h026 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h021 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x026, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839 + BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h021 (Mirror: 11'h000) + BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h022 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | + P_Fld(0x022, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849 + BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h021 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h022 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | + P_Fld(0x022, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887 + BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h021 (Mirror: 11'h000) + BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h022 (Mirror: 11'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | + P_Fld(0x022, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h21 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h26 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h21 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h26 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x26, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x26, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899 + RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h22 (Mirror: 6'h00) + RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h21 (Mirror: 6'h00) + RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h22 (Mirror: 6'h00) + RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h21 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x22, SHURK_PI_RK0_ARPI_DQ_B1) | + P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x22, SHURK_PI_RK0_ARPI_DQM_B1) | + P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h2c (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h2c (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h2c (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h2c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h2c (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h2c (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h2c (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h2c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h2c (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @8831 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h3c (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h3c (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h3c (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h3c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @8845 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h3c (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h3c (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h3c (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h3c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @8873 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h3c (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x3c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435 + TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h1c (Mirror: 8'h00) + TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h1c (Mirror: 8'h00) + TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h1c (Mirror: 8'h00) + TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h1c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | + P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | + P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449 + TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h1c (Mirror: 8'h00) + TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h1c (Mirror: 8'h00) + TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h1c (Mirror: 8'h00) + TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h1c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | + P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | + P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476 + TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h1c (Mirror: 8'h00) + TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | + P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @8838 + TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h18 (Mirror: 8'h00) + TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h18 (Mirror: 8'h00) + TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h18 (Mirror: 8'h00) + TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h18 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | + P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | + P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @8852 + TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h18 (Mirror: 8'h00) + TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h18 (Mirror: 8'h00) + TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h18 (Mirror: 8'h00) + TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h18 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | + P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | + P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @8879 + TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h18 (Mirror: 8'h00) + TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 + TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | + P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5345 + TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0) + TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0) + TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | + P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ9_0 ral_reg_DDRPHY_blk_SHU_B0_DQ9_0 - @7845 + RG_ARPI_RESERVE_B0 uvm_reg_field ... RW SHU_B0_DQ9_0[31:0]=32'h0c410eb3 (Mirror: 32'h0c430eb3) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0x0c410eb3, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ9_0 ral_reg_DDRPHY_blk_SHU_B1_DQ9_0 - @9248 + RG_ARPI_RESERVE_B1 uvm_reg_field ... RW SHU_B1_DQ9_0[31:0]=32'hfa89b179 (Mirror: 32'hfa8bb179) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xfa89b179, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_WR_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0 - @4936 + WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h3 (Mirror: 4'h1) + WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h3 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) | + P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_WR_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1 - @4941 + WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h3 (Mirror: 4'h1) + WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h3 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) | + P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_RD_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0 - @4946 + WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h5 (Mirror: 4'h1) + WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h5 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if LP5_DDR4266_RDBI_WORKAROUND + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); + #else + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_RD_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1 - @4951 + WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h5 (Mirror: 4'h1) + WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h5 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if LP5_DDR4266_RDBI_WORKAROUND + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); + #else + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) | + P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_FS_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0 - @4956 + WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h2 (Mirror: 4'h1) + WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h2 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) | + P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_FS_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1 - @4961 + WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h2 (Mirror: 4'h1) + WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h2 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) | + P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_WR_UI_0_0 ral_reg_DRAMC_blk_SHURK_WCK_WR_UI_0_0 - @4966 + WCK_WR_B0_UI uvm_reg_field ... RW SHURK_WCK_WR_UI_0_0[3:0]=4'h3 (Mirror: 4'h1) + WCK_WR_B1_UI uvm_reg_field ... RW SHURK_WCK_WR_UI_0_0[7:4]=4'h3 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI, P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B0_UI) | + P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B1_UI)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_WR_UI_0_1 ral_reg_DRAMC_blk_SHURK_WCK_WR_UI_0_1 - @4971 + WCK_WR_B0_UI uvm_reg_field ... RW SHURK_WCK_WR_UI_0_1[3:0]=4'h3 (Mirror: 4'h1) + WCK_WR_B1_UI uvm_reg_field ... RW SHURK_WCK_WR_UI_0_1[7:4]=4'h3 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B0_UI) | + P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B1_UI)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_RD_UI_0_0 ral_reg_DRAMC_blk_SHURK_WCK_RD_UI_0_0 - @4976 + WCK_RD_B0_UI uvm_reg_field ... RW SHURK_WCK_RD_UI_0_0[3:0]=4'h3 (Mirror: 4'h1) + WCK_RD_B1_UI uvm_reg_field ... RW SHURK_WCK_RD_UI_0_0[7:4]=4'h3 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if LP5_DDR4266_RDBI_WORKAROUND + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI, P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B0_UI) | + P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B1_UI)); + #else + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI, P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B0_UI) | + P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B1_UI)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_RD_UI_0_1 ral_reg_DRAMC_blk_SHURK_WCK_RD_UI_0_1 - @4981 + WCK_RD_B0_UI uvm_reg_field ... RW SHURK_WCK_RD_UI_0_1[3:0]=4'h3 (Mirror: 4'h1) + WCK_RD_B1_UI uvm_reg_field ... RW SHURK_WCK_RD_UI_0_1[7:4]=4'h3 (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + #if LP5_DDR4266_RDBI_WORKAROUND + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B0_UI) | + P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B1_UI)); + #else + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B0_UI) | + P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B1_UI)); + #endif + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_FS_UI_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_0 - @4986 + WCK_FS_B0_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_0[3:0]=4'hb (Mirror: 4'h1) + WCK_FS_B1_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_0[7:4]=4'hb (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI, P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B0_UI) | + P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B1_UI)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_WCK_FS_UI_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_1 - @4991 + WCK_FS_B0_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_1[3:0]=4'hb (Mirror: 4'h1) + WCK_FS_B1_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_1[7:4]=4'hb (Mirror: 4'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B0_UI) | + P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B1_UI)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041 + TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | + P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052 + TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01 + TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | + P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | + P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060 + TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | + P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071 + TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1) + TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1) + TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1) + TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1) + TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1) + TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1) + TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1) + TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | + P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082 + dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1 + dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1 + dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1) + dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1 + dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1 + dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1 + dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1 + dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | + P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018 + CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h0 (Mirror: 2'h3) + SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x0, SHU_SREF_CTRL_CKEHCMD) | + P_Fld(0x0, SHU_SREF_CTRL_SREF_CK_DLY)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h67 (Mirror: 8'h00) + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x67, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199 + TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h1 (Mirror: 1'h0) + TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 + TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0) + TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h1 (Mirror: 1'h0) + TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0) + TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0 + TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0) + TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h0 + TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 + TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 + TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) + TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h1 (Mirror: 1'h0) + TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h1 (Mirror: 1'h0) + TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 + TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 + TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h0 + TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0) + TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0) + BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 + BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 + BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0 + TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h1 (Mirror: 1'h0) + TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h0 + XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 + TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0) + TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0 + TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0) + TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0) + TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 + TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0) + XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRFC_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRCD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TFAW_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) | + P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | + P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | + P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x1, SHU_AC_TIME_05T_XRTW2R_M05T)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192 + XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h1b (Mirror: 5'h01) + XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h27 (Mirror: 6'h01) + XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h8 (Mirror: 4'h1) + XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h00 (Mirror: 5'h01) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x1b, SHU_ACTIM_XRT_XRTR2R) | + P_Fld(0x27, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x8, SHU_ACTIM_XRT_XRTW2R) | + P_Fld(0x00, SHU_ACTIM_XRT_XRTW2W)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138 + TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'h6 (Mirror: 4'h1) + CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h2 (Mirror: 3'h0) + TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'hba (Mirror: 8'h06) + TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h0 + TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2) + TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'hf (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x6, SHU_ACTIM0_TWTR) | + P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0xba, SHU_ACTIM0_TWR) | + P_Fld(0x0, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) | + P_Fld(0xf, SHU_ACTIM0_TWTR_L)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147 + TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'hd (Mirror: 4'ha) + TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h1 (Mirror: 4'h8) + TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h6 (Mirror: 4'h2) + TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h07 (Mirror: 6'h04) + TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h13 (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xd, SHU_ACTIM1_TRPAB) | + P_Fld(0x1, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x6, SHU_ACTIM1_TRP) | + P_Fld(0x07, SHU_ACTIM1_TRAS) | P_Fld(0x13, SHU_ACTIM1_TRC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155 + TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'ha (Mirror: 4'h0) + TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h17 (Mirror: 5'h0e) + TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0) + TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h33 (Mirror: 6'h00) + TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h1c (Mirror: 5'h05) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0xa, SHU_ACTIM2_TXP) | + P_Fld(0x17, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) | + P_Fld(0x33, SHU_ACTIM2_TR2W) | P_Fld(0x1c, SHU_ACTIM2_TFAW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163 + TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h2b (Mirror: 8'h00) + MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) + TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) + TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h4c (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x2b, SHU_ACTIM3_TRFCPB) | + P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | + P_Fld(0x4c, SHU_ACTIM3_TRFC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170 + TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h197 (Mirror: 10'h028) + TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0d (Mirror: 6'h00) + TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h1f (Mirror: 6'h00) + TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h12 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x197, SHU_ACTIM4_TXREFCNT) | + P_Fld(0x0d, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x1f, SHU_ACTIM4_TMRR2W) | + P_Fld(0x12, SHU_ACTIM4_TZQCS)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177 + TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h0a (Mirror: 7'h00) + TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h6a (Mirror: 7'h00) + TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h82 (Mirror: 8'h00) + TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h3 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0a, SHU_ACTIM5_TR2PD) | + P_Fld(0x6a, SHU_ACTIM5_TWTPD) | P_Fld(0x82, SHU_ACTIM5_TPBR2PBR) | + P_Fld(0x3, SHU_ACTIM5_TPBR2ACT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184 + TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h04 (Mirror: 5'h1f) + TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0) + TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h4 (Mirror: 4'h0) + TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h30 (Mirror: 6'h00) + TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h1c (Mirror: 6'h13) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x04, SHU_ACTIM6_TZQLAT2) | + P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x4, SHU_ACTIM6_TMRW) | + P_Fld(0x30, SHU_ACTIM6_TW2MRW) | P_Fld(0x1c, SHU_ACTIM6_TR2MRW)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262 + TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) + TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 + TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h4 (Mirror: 3'h1) + TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h0 (Mirror: 3'h1) + TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h5 (Mirror: 3'h2) + TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h1 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | + P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x4, SHU_CKECTRL_TPDE) | + P_Fld(0x0, SHU_CKECTRL_TPDX) | P_Fld(0x5, SHU_CKECTRL_TCKEPRD) | + P_Fld(0x1, SHU_CKECTRL_TCKESRX)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365 + REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 + DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h1 (Mirror: 3'h4) + DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | + P_Fld(0x1, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_LP5_CMD_0 ral_reg_DRAMC_blk_SHU_LP5_CMD_0 - @5427 + LP5_CMD1TO2EN uvm_reg_field ... RW SHU_LP5_CMD_0[0:0]=1'h0 + TCSH uvm_reg_field ... RW SHU_LP5_CMD_0[7:4]=4'hb (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) | + P_Fld(0xb, SHU_LP5_CMD_TCSH)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIM7_0 ral_reg_DRAMC_blk_SHU_ACTIM7_0 - @5436 + TCSH_CSCAL uvm_reg_field ... RW SHU_ACTIM7_0[3:0]=4'hb (Mirror: 4'h0) + TCACSH uvm_reg_field ... RW SHU_ACTIM7_0[7:4]=4'h2 (Mirror: 4'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0xb, SHU_ACTIM7_TCSH_CSCAL) | + P_Fld(0x2, SHU_ACTIM7_TCACSH)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_WCKCTRL_0 ral_reg_DRAMC_blk_SHU_WCKCTRL_0 - @5407 + WCKRDOFF uvm_reg_field ... RW SHU_WCKCTRL_0[5:0]=6'h18 (Mirror: 6'h00) + WCKRDOFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[7:7]=1'h1 (Mirror: 1'h0) + WCKWROFF uvm_reg_field ... RW SHU_WCKCTRL_0[13:8]=6'h02 (Mirror: 6'h00) + WCKWROFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[15:15]=1'h1 (Mirror: 1'h0) + WCKDUAL uvm_reg_field ... RW SHU_WCKCTRL_0[16:16]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x18, SHU_WCKCTRL_WCKRDOFF) | + P_Fld(0x1, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x02, SHU_WCKCTRL_WCKWROFF) | + P_Fld(0x1, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0157 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0157, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0157 (Mirror: 15'h0000) + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0157, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728 + RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h2 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | + P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | + P_Fld(0x2, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131 + RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e + RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 + RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 + RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 + RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 + RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h2 (Mirror: 4'h0) + RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | + P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | + P_Fld(0x2, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h53 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h53 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h53 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h53 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h53 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h53 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h53 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h53 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x53, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x53, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h00b (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h00b (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x00b, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x00b, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497 + RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h52 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h52 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511 + RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h52 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h52 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525 + RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h52 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h52 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539 + RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h52 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h52 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551 + RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0x52, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561 + RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h00a (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h00a (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x00a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | + P_Fld(0x00a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h53 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h53 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h53 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h53 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h53 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h53 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h53 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h53 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h53 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h53 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x53, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x53, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h00b (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h00b (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x00b, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x00b, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900 + RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h52 (Mirror: 8'h00) + RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h52 (Mirror: 8'h00) + RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914 + RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h52 (Mirror: 8'h00) + RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h52 (Mirror: 8'h00) + RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928 + RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h52 (Mirror: 8'h00) + RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h52 (Mirror: 8'h00) + RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942 + RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h52 (Mirror: 8'h00) + RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h52 (Mirror: 8'h00) + RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954 + RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h52 (Mirror: 8'h00) + RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h52 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0x52, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964 + RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h00a (Mirror: 9'h000) + RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h00a (Mirror: 9'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x00a, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | + P_Fld(0x00a, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 + RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | + P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | + P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | + P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | + P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 + RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 + RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 + R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 + R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 + R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 + R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 + R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 + R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 + R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | + P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | + P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | + P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | + P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313 + RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h57 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h57 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h13 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h13 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x57, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | + P_Fld(0x57, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x13, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | + P_Fld(0x13, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716 + RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h57 (Mirror: 7'h00) + RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h57 (Mirror: 7'h00) + RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h13 (Mirror: 6'h00) + RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h13 (Mirror: 6'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x57, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | + P_Fld(0x57, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x13, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | + P_Fld(0x13, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320 + RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | + P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | + P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723 + RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10 + RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1 + RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1 + RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 + RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1 + RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | + P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | + P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001 + FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h0 + FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0 + FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h1 (Mirror: 1'h0) + DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h0 + DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h1 (Mirror: 1'h0) + LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h1 (Mirror: 1'h0) + LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h1 (Mirror: 1'h0) + CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0 + BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0 + BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0) + LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0 + BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1 + LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h1 (Mirror: 1'h0) + SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x0, SHU_COMMON0_FREQDIV4) | + P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x1, SHU_COMMON0_FREQDIV8) | + P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x1, SHU_COMMON0_DLE256EN) | + P_Fld(0x1, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) | + P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) | + P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | + P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) | + P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255 + SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a) + TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0 + REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000 + TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | + P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | + P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 + DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 + DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 + DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 + CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 + FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0) + FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | + P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | + P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | + P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356 + DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08) + ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0 + ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0) + PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0) + REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0) + REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) | + P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | + P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | + P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996 + MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0) + NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) | + P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_SCHEDULER_0 ral_reg_DRAMC_blk_SHU_SCHEDULER_0 - @5023 + DUALSCHEN uvm_reg_field ... RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899 + TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0 + TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0 + DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0 + TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1 + DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0 + OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0 + DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0 + WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0) + DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0 + DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0 + ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0 + TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0 + DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0 + DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0 + RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0 + DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) | + P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) | + P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) | + P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) | + P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) | + P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) | + P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) | + P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) | + P_Fld(0x0, TX_SET0_DRAMOEN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0) + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0) + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0) + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514 + DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0 + DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0 + r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0 + STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0) + STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0) + DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | + P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | + P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | + P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499 + DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0) + PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0) + DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0) + DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0) + DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h3 (Mirror: 2'h1) + DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1 + DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0 + STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0) + STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0) + DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0 + DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0 + DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) | + P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x3, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | + P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) | + P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | + P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562 + RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0) + RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0 + RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0 + RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0) + RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1 + RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0 + RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0) + RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0 + RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | + P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | + P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751 + DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h3 (Mirror: 2'h0) + RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h2 (Mirror: 2'h0) + RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h2 (Mirror: 2'h0) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x3, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | + P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0) + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0) + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0) + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0) + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HWSET_MR2_0 ral_reg_DRAMC_blk_SHU_HWSET_MR2_0 - @5122 + HWSET_MR2_MRSMA uvm_reg_field ... RW SHU_HWSET_MR2_0[12:0]=13'h0002 + HWSET_MR2_OP uvm_reg_field ... RW SHU_HWSET_MR2_0[23:16]=8'h09 (Mirror: 8'h12) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) | + P_Fld(0x09, SHU_HWSET_MR2_HWSET_MR2_OP)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384 + tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h93 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h07 (Mirror: 8'h00) + tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | + P_Fld(0x93, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x07, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | + P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit + // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523 + r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h0 + r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0 + r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46) + r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | + P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | + P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); + + mcDELAY_US(1); + + /*TINFO=---===BROADCAST OFF!===---*/ + broadcast_off(); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter + mcDELAY_US(1); + + mcDELAY_US(1); + + /*TINFO=---===BROADCAST ON!===---*/ + broadcast_on(); + // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338 + DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h0e (Mirror: 8'h00) + DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0 + DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0 + DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x0e, SHU_DQSOSCR_DQSOSCRCNT) | + P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | + P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332 + DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1 + DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h009 (Mirror: 10'h00f) + DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | + P_Fld(0x009, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h01ca (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h01ca (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x01ca, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x01ca, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911 + DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h0106 (Mirror: 16'h0000) + DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h0106 (Mirror: 16'h0000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0106, SHURK_DQSOSC_DQSOSC_BASE_RK0) | + P_Fld(0x0106, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h007 (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h005 (Mirror: 12'h001) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x007, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x005, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921 + DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h002 (Mirror: 12'h001) + DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h001 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | + P_Fld(0x001, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 + DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 + DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 + TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 + TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 + WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 + DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 + WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 + TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 + WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 + TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 + TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 + OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 + DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h23 (Mirror: 6'h0e) + TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | + P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | + P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) | + P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) | + P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) | + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) | + P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x23, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | + P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 + ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000) + TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1b + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | + P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 + FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h67 + REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x67, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | + P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 + R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0157 + R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 + R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 + R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0157, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 + R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0157 + R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) + R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 + R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 + R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 + R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 + R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 + R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 + R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 + R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 + R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 + R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 + R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 + R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0157, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 + R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 + R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 + R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h8 (Mirror: 4'h0) + R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 + R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | + P_Fld(0x8, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | + P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 + R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 + R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 + R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 + R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h8 (Mirror: 4'h0) + R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 + R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 + R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 + R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 + R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 + R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 + R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 + R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 + R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 + R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 + R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 + R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 + R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | + P_Fld(0x8, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | + P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B0_DQ11_0 ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 - @7794 + RG_RX_ARDQ_RANK_SEL_SER_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[0:0]=1'h0 + RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[1:1]=1'h0 + RG_RX_ARDQ_OFFSETC_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[2:2]=1'h0 + RG_RX_ARDQ_OFFSETC_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[3:3]=1'h0 + RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[4:4]=1'h0 + RG_RX_ARDQ_FRATE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[5:5]=1'h0 + RG_RX_ARDQ_CDR_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[6:6]=1'h0 + RG_RX_ARDQ_DVS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQ_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[11:8]=4'h0 + RG_RX_ARDQ_DES_MODE_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[17:16]=2'h3 + RG_RX_ARDQ_BW_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[19:18]=2'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | + P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | + P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | + P_Fld(0x3, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); + /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + Name Type Size Value + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + SHU_B1_DQ11_0 ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 - @9197 + RG_RX_ARDQ_RANK_SEL_SER_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[0:0]=1'h0 + RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[1:1]=1'h0 + RG_RX_ARDQ_OFFSETC_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[2:2]=1'h0 + RG_RX_ARDQ_OFFSETC_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[3:3]=1'h0 + RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[4:4]=1'h0 + RG_RX_ARDQ_FRATE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[5:5]=1'h0 + RG_RX_ARDQ_CDR_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[6:6]=1'h0 + RG_RX_ARDQ_DVS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) + RG_RX_ARDQ_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[11:8]=4'h0 + RG_RX_ARDQ_DES_MODE_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[17:16]=2'h3 + RG_RX_ARDQ_BW_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[19:18]=2'h0 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | + P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | + P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | + P_Fld(0x3, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); + // Exit body +} +#endif + + diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c new file mode 100644 index 0000000000..fa01f516b0 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c @@ -0,0 +1,2221 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//----------------------------------------------------------------------------- +// Include files +//----------------------------------------------------------------------------- +#include "dramc_common.h" +#include "dramc_int_global.h" +#include "x_hal_io.h" + + +#define SHUFFLE_GROUP 4 //SHU1~4 + +//----------------------------------------------------------------------------- +// Global variables +//----------------------------------------------------------------------------- + +U8 _MappingFreqArray[DRAM_DFS_SRAM_MAX] = {0}; + +U8 gDVFSCtrlSel = 0; +U32 gu4Ddrphy0SPMCtrl0; +U32 gu4Ddrphy1SPMCtrl0; +U32 gu4Ddrphy0SPMCtrl2; +U32 gu4Ddrphy1SPMCtrl2; + + +void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable) +{ + p->pDFSTable = pFreqTable; +} + +void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable) +{ + vSetDFSTable(p, pFreqTable); + DDRPhyFreqSel(p, p->pDFSTable->freq_sel); +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + vSetVcoreByFreq(p); +#endif +} + +void vInitMappingFreqArray(DRAMC_CTX_T *p) +{ + U8 u1ShuffleIdx = 0; + DRAM_DFS_FREQUENCY_TABLE_T *pFreqTbl; + + pFreqTbl = gFreqTbl; + + for (u1ShuffleIdx = DRAM_DFS_SHUFFLE_1; u1ShuffleIdx < DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) + { + _MappingFreqArray[pFreqTbl[u1ShuffleIdx].shuffleIdx] = pFreqTbl[u1ShuffleIdx].shuffleIdx; + } +} + +DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_shuffleIndex(DRAMC_CTX_T *p, U8 index) +{ + U8 u1ShuffleIdx = 0; + DRAM_DFS_FREQUENCY_TABLE_T *pFreqTbl; + + pFreqTbl = gFreqTbl; + + for (u1ShuffleIdx = DRAM_DFS_SHUFFLE_1; u1ShuffleIdx < DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) + { + if (pFreqTbl[u1ShuffleIdx].shuffleIdx == index) + { + return & pFreqTbl[u1ShuffleIdx]; + } + } + return NULL; +} + +U8 get_shuffleIndex_by_Freq(DRAMC_CTX_T *p) +{ + U8 u1ShuffleIdx = 0; + DRAM_DFS_FREQUENCY_TABLE_T *pFreqTbl; + DRAM_DFS_SRAM_SHU_T eCurr_shu_level = vGet_Current_ShuLevel(p); + + pFreqTbl = gFreqTbl; + + for (u1ShuffleIdx = DRAM_DFS_SHUFFLE_1; u1ShuffleIdx < DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) + { + if (pFreqTbl[u1ShuffleIdx].shuffleIdx == eCurr_shu_level) + { + return _MappingFreqArray[pFreqTbl[u1ShuffleIdx].shuffleIdx]; + } + } + + return 0; +} + +#if 0 //@Darren, debug codes +void DramcWriteShuffleSRAMRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr, u32 u4Data) +{ + U32 ii, u4tmp, u4Offset=0; + + for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) + { + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset+SHU_GRP_DRAMC_OFFSET), u4Data); + u4Offset += 4; + mcDELAY_MS(1); + } +} + +void DdrphyWriteShuffleSRAMRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr, u32 u4Data) +{ + U32 ii, u4tmp, u4Offset=0; + + for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) + { + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset+SHU_GRP_DDRPHY_OFFSET), u4Data); + u4Offset += 4; + mcDELAY_MS(1); + } +} + +void FullRGDump(DRAMC_CTX_T *p, U8 step, U32 u4ShuOffset) +{ + U8 u1RankIdx=0; + + mcSHOW_DBG_MSG(("[FullRGDump] STEP%d\n", step)); + //Darren-DumpAoNonShuReg(); + for (u1RankIdx=RANK_0; u1RankIdx<p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + mcSHOW_DBG_MSG(("[FullRGDump] RANK%d\n", u1RankIdx)); + DumpAoShuReg(u4ShuOffset, u4ShuOffset); + } + //Darren-DumpNaoReg(); +} + +U32 SramDebugModeRead(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg) +{ + U32 u4Value=0; + U32 u4RegBackupAddress[] = + { + (DDRPHY_REG_MISC_SRAM_DMA0), + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR), +#if (CHANNEL_NUM==4) + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR), +#endif + }; + + //Backup regs + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + //vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); // SHU8 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL); + + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; + u4Value = u4IO32Read4B(DRAMC_REG_ADDR(u4Reg));// SHU1 + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + mcSHOW_DBG_MSG(("[SramDebugModeRead] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Value)); + + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x0, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); + + return u4Value; +} + +void SramDebugModeWrite(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg, U32 u4Data) +{ + U32 u4RegBackupAddress[] = + { + (DDRPHY_REG_MISC_SRAM_DMA0), + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR), +#if (CHANNEL_NUM==4) + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR), +#endif + }; + + //Backup regs + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); // SHU8 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL); + + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; + vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1 + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + mcSHOW_DBG_MSG(("[SramDebugModeWrite] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Data)); + + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x0, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); +} + +void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) +{ + U32 ii, u4tmp, u4Offset=0; + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; // SHU1 need use p->ShuRGAccessIdx=DRAM_DFS_REG_SHU1 for RK1 + + for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) + { + u4tmp = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset)); + mcDELAY_MS(1); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset), u4tmp); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + u4Offset += 4; + mcDELAY_MS(1); + } + + p->ShuRGAccessIdx = ShuRGAccessIdxBackup; +} + +void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) +{ + U32 ii, u4tmp, u4Offset=0; + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; // SHU1 need use p->ShuRGAccessIdx=DRAM_DFS_REG_SHU1 for RK1 + + for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) + { + u4tmp = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset)); + mcDELAY_MS(1); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset), u4tmp); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + u4Offset += 4; + mcDELAY_MS(1); + } + + p->ShuRGAccessIdx = ShuRGAccessIdxBackup; +} +#endif + +#if ENABLE_LP4Y_WA +void CmdBusTrainingLP4YWA(DRAMC_CTX_T *p, U8 u1OnOff) +{ + U8 u1MR51 = 0; + + if (p->frequency > 800) // skip DDR1600 up + return; + + if (u1OnOff == DISABLE) + u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] & ~(1 << 3); // disable CLK SE mode + else + u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] | (1 << 3); // enable CLK SE mode + + DramcModeRegWriteByRank(p, p->rank, 51, u1MR51Value[p->dram_fsp]); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( u1OnOff , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \ + | P_Fld( u1OnOff , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( u1OnOff , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK )); +} +#endif + +#if ENABLE_DFS_RUNTIME_MRW +void DFSRuntimeFspMRW(DRAMC_CTX_T *p) +{ + vIO32WriteFldAlign_All(DRAMC_REG_SA_RESERVE, p->dram_fsp, SA_RESERVE_DFS_FSP_RTMRW); +} + +void DFSRuntimeMRW_preset(DRAMC_CTX_T *p, U8 sram_shu_level) +{ + U8 u1ChIdx = 0, u1RankIdx = 0; + U8 u1MR03_Value = 0; + U8 ch_start = 0, ch_end = 0; + + ch_start = CHANNEL_A; + ch_end = CHANNEL_B; +#if (CHANNEL_NUM > 2) + ch_end = CHANNEL_D; +#endif + + //Darren-mcSHOW_DBG_MSG(("[DFSRuntimeMRW_preset] FSP%d\n", p->dram_fsp)); + //! save mr13 + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0, u1MR13Value[RANK_0], LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0); + //Darren-mcSHOW_DBG_MSG(("\tMR13 = 0x%x\n", u1MR13Value[RANK_0])); + +#if ENABLE_READ_DBI + u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0xbf) | (p->DBI_R_onoff[p->dram_fsp] << 6)); +#endif + +#if ENABLE_WRITE_DBI + u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0x7F) | (p->DBI_W_onoff[p->dram_fsp] << 7)); +#endif + + //! save shux mr1/mr2/mr3/mr11 + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4), + P_Fld(u1MR01Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0) | + P_Fld(u1MR02Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1) | + P_Fld(u1MR03_Value, LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2) | + P_Fld(u1MR11Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3)); + //Darren-mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR1 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03Value[p->dram_fsp], u1MR11Value[p->dram_fsp])); + + //! save shux mr22/mr51 + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4), + P_Fld(u1MR21Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5) | + P_Fld(u1MR22Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6) | + P_Fld(u1MR51Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7)); + //Darren-mcSHOW_DBG_MSG(("\tMR22 = 0x%x, MR51 = 0x%x\n", u1MR22Value[p->dram_fsp], u1MR51Value[p->dram_fsp])); + + //! save shux mr12/mr14 + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_0 + (sram_shu_level << 4), + P_Fld(u1MR12Value[ch_start][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_0) | + P_Fld(u1MR12Value[ch_start][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_1) | + P_Fld(u1MR12Value[ch_end][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_2) | + P_Fld(u1MR12Value[ch_end][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_3)); + + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_1 + (sram_shu_level << 4), + P_Fld(u1MR14Value[ch_start][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_4) | + P_Fld(u1MR14Value[ch_start][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_5) | + P_Fld(u1MR14Value[ch_end][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_6) | + P_Fld(u1MR14Value[ch_end][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_7)); + +#if 0 + for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++) + { + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + mcSHOW_DBG_MSG(("\tCH%d, RK%d, MR12 = 0x%x, MR14 = 0x%x\n", u1ChIdx, u1RankIdx,u1MR12Value[u1ChIdx][u1RankIdx][p->dram_fsp], u1MR14Value[u1ChIdx][u1RankIdx][p->dram_fsp])); + } + } +#endif +} + +static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1MR1, U8 u1MR2, U8 u1MR3, U8 u1MR11, U8 u1MR12, U8 u1MR13, U8 u1MR14, U8 u1MR21, U8 u1MR22, U8 u1MR51) +{ + U8 rt_response_ack = 1, rt_ack = 0; + U8 u1MRW_1ST_Num = 0x5; // MR13, MR1, MR2, MR3, MR11, MR12 + U8 u1MRW_2ND_Num = 0x2; // MR14, 22, 51 + +#if ENABLE_LP4Y_DFS + u1MRW_2ND_Num++; // for LP4Y MR21 +#endif + +#if 1 + //! MR13, MR1, MR2, MR3, MR11, MR12 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0), + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) | + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) | + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW2_RK) | + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW3_RK) | + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW4_RK) | + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW5_RK) | + P_Fld(u1MRW_1ST_Num, RTMRW_CTRL0_RTMRW_LEN) | + P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) | + P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT)); + + //! MA = 13, 1, 2, 3 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1), + P_Fld(13, RTMRW_CTRL1_RTMRW0_MA) | + P_Fld(1, RTMRW_CTRL1_RTMRW1_MA) | + P_Fld(2, RTMRW_CTRL1_RTMRW2_MA) | + P_Fld(3, RTMRW_CTRL1_RTMRW3_MA)); + + //! OP13, OP1, OP2, OP3 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2), + P_Fld(u1MR13, RTMRW_CTRL2_RTMRW0_OP) | + P_Fld(u1MR1, RTMRW_CTRL2_RTMRW1_OP) | + P_Fld(u1MR2, RTMRW_CTRL2_RTMRW2_OP) | + P_Fld(u1MR3, RTMRW_CTRL2_RTMRW3_OP)); + + //! MR11/MR12 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL3), + P_Fld(11, RTMRW_CTRL3_RTMRW4_MA) | + P_Fld(12, RTMRW_CTRL3_RTMRW5_MA) | + P_Fld(u1MR11, RTMRW_CTRL3_RTMRW4_OP) | + P_Fld(u1MR12, RTMRW_CTRL3_RTMRW5_OP)); + + //!runtime MRW trigger + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN); + + do { + rt_ack = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_RTMRW_RESPONSE); + } while(rt_response_ack != rt_ack); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x0, SWCMD_EN_RTMRWEN); +#endif + +#if 1 + //! MR14/22/51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0), + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) | + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) | + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW2_RK) | +#if ENABLE_LP4Y_DFS + P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW3_RK) | +#endif + P_Fld(u1MRW_2ND_Num, RTMRW_CTRL0_RTMRW_LEN) | + P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) | + P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT)); + + //! MA = 14, 22, 51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1), + P_Fld(14, RTMRW_CTRL1_RTMRW0_MA) | +#if ENABLE_LP4Y_DFS + P_Fld(21, RTMRW_CTRL1_RTMRW3_MA) | +#endif + P_Fld(22, RTMRW_CTRL1_RTMRW1_MA) | + P_Fld(51, RTMRW_CTRL1_RTMRW2_MA)); + + //! OP14, OP22, OP51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2), + P_Fld(u1MR14, RTMRW_CTRL2_RTMRW0_OP) | +#if ENABLE_LP4Y_DFS + P_Fld(u1MR21, RTMRW_CTRL2_RTMRW3_OP) | +#endif + P_Fld(u1MR22, RTMRW_CTRL2_RTMRW1_OP) | + P_Fld(u1MR51, RTMRW_CTRL2_RTMRW2_OP)); + + //!runtime MRW trigger + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN); + + do { + rt_ack = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_RTMRW_RESPONSE); + } while(rt_response_ack != rt_ack); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x0, SWCMD_EN_RTMRWEN); +#endif +} + +static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_shu_level, U8 pingpong_fsp) +{ + U8 u1MR13_OP = 0, u1VRCG_OP = 0; + U8 ch_start = 0, ch_end = 0, u1ChIdx = 0; + U8 ch_bak = vGetPHY2ChannelMapping(p); + + ch_start = CHANNEL_A; + ch_end = CHANNEL_B+1; +#if (CHANNEL_NUM > 2) + ch_end = CHANNEL_D+1; +#endif + + for (u1ChIdx = ch_start; u1ChIdx < ch_end; u1ChIdx++) + { + vSetPHY2ChannelMapping(p, u1ChIdx); + p->ShuRGAccessIdx = cur_shu_mux_index; // Currect + u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP); + p->ShuRGAccessIdx = pingpong_shu_level; // Next + u1VRCG_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), SHU_HWSET_VRCG_HWSET_VRCG_OP); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + + if(pingpong_fsp == FSP_1) + { + if (cur_shu_mux_index == PHYPLL_MODE) + { + u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + u1VRCG_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + } + else + { + u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + u1VRCG_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + } + } + else + { + if (cur_shu_mux_index == PHYPLL_MODE) + { + u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + u1VRCG_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + } + else + { + u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + u1VRCG_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + } + } + p->ShuRGAccessIdx = cur_shu_mux_index; // Currect + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); // Current + p->ShuRGAccessIdx = pingpong_shu_level; // Next + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), u1VRCG_OP, SHU_HWSET_VRCG_HWSET_VRCG_OP); // Next + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + } + + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + vSetPHY2ChannelMapping(p, ch_bak); +} + +static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level, U8 pingpong_fsp) +{ + U8 rtmr13 = 0; + U8 rtmr1 = 0, rtmr2 = 0, rtmr3 = 0, rtmr11 = 0; + U8 rtmr12 = 0, rtmr14 = 0; + U8 rtmr21 = 0, rtmr22 = 0, rtmr51 = 0; + U8 md32_rtmrw_hpri_en_bk = 0; + U32 bc_bak = 0, ch_bak = 0; + U8 ch_start = 0, ch_end = 0; + U8 u1ChIdx = 0, u1RankIdx = 0; + U8 u1FldIdx = 0; + + bc_bak = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + ch_bak = vGetPHY2ChannelMapping(p); + + ch_start = CHANNEL_A; + ch_end = CHANNEL_B+1; +#if (CHANNEL_NUM > 2) + ch_end = CHANNEL_D+1; +#endif + + //! get mr13 + rtmr13 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0, LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0); + //! get shux mr1/mr2/mr3/mr11 + rtmr1 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0); + rtmr2 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1); + rtmr3 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2); + rtmr11 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3); + //! get shux mr21/mr22/mr51 + rtmr21 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5); + rtmr22 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6); + rtmr51 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7); + + rtmr13 &= 0x3F; + if (pingpong_fsp == FSP_1) + { + if(cur_shu_mux_index == PHYPLL_MODE) + rtmr13 |= (0x1 << 7); //! MR13 OP7 = 1, OP6 = 0, from PHYPLL to CLRPLL + else + rtmr13 |= (0x1 << 6); //! MR13 OP7 = 0, OP6 = 1, from CLRPLL to PHYPLL + } + else + { + if(cur_shu_mux_index == PHYPLL_MODE) + rtmr13 |= (0x1 << 6); //! MR13 OP7 = 0, OP6 = 1, from CLRPLL to PHYPLL + else + rtmr13 |= (0x1 << 7); //! MR13 OP7 = 1, OP6 = 0, from PHYPLL to CLRPLL + } + +#if 0 // @Darren- + if (p->support_rank_num == RANK_DUAL) + md32_rtmrw_rank = 0x3; //! dual rank + else + md32_rtmrw_rank = 0x1; //! single rank +#endif + + //Darren-mcSHOW_DBG_MSG(("[DFSRuntimeMRWEn]\n")); + u1FldIdx = 0; // shift 8-bits field + for (u1ChIdx = ch_start; u1ChIdx < ch_end; u1ChIdx++) + { + vSetPHY2ChannelMapping(p, u1ChIdx); + md32_rtmrw_hpri_en_bk = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), MPC_CTRL_RTMRW_HPRI_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0x1, MPC_CTRL_RTMRW_HPRI_EN); + + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + //Darren-mcSHOW_DBG_MSG(("CH%d RK%d\n", u1ChIdx, u1RankIdx)); + //! get shux mr12/mr14/ + rtmr12 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_0 + (nxt_shu_level << 4), Fld(8, u1FldIdx*8)); + rtmr14 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_1 + (nxt_shu_level << 4), Fld(8, u1FldIdx*8)); + //Darren-mcSHOW_DBG_MSG(("\tMR1=0x%x, MR2=0x%x, MR3=0x%x, MR11=0x%x\n", rtmr1, rtmr2, rtmr3, rtmr11)); + //Darren-mcSHOW_DBG_MSG(("\tMR12=0x%x, MR13=0x%x, MR14=0x%x, MR22=0x%x, MR51=0x%x\n", rtmr12, rtmr13, rtmr14, rtmr22, rtmr51)); + TriggerRTMRW_SingleChannel(p, u1RankIdx, rtmr1, rtmr2, rtmr3, rtmr11, rtmr12, rtmr13, rtmr14, rtmr21, rtmr22, rtmr51); + u1FldIdx++; // shift 8-bits field + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), md32_rtmrw_hpri_en_bk, MPC_CTRL_RTMRW_HPRI_EN); + } + + vSetPHY2ChannelMapping(p, ch_bak); + DramcBroadcastOnOff(bc_bak); +} +#endif + +static void DFSHwSetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level) +{ + U8 u1MR13_OP = 0; + U8 ch_start = 0, ch_end = 0, u1ChIdx = 0; + U8 ch_bak = vGetPHY2ChannelMapping(p); + ch_start = CHANNEL_A; + ch_end = CHANNEL_B+1; +#if (CHANNEL_NUM > 2) + ch_end = CHANNEL_D+1; +#endif + for (u1ChIdx = ch_start; u1ChIdx < ch_end; u1ChIdx++) + { + vSetPHY2ChannelMapping(p, u1ChIdx); + p->ShuRGAccessIdx = cur_shu_mux_index; // NOTE: Currect shuffle + u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP); + if ((nxt_shu_level == SRAM_SHU0) || (nxt_shu_level == SRAM_SHU1)) // for term shuffle level + u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + else + u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); // Current + } + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + vSetPHY2ChannelMapping(p, ch_bak); +} +#if ENABLE_CONFIG_MCK_4TO1_MUX +void ConfigMCK4To1MUX(DRAMC_CTX_T *p, CLK_MUX_T eClkMux) +{ + U8 u1DVFS_52M_104M_SEL, u1DVFS_104M_208M_SEL; + + if (eClkMux == CLK_MUX_208M) + { + u1DVFS_52M_104M_SEL = 1; + u1DVFS_104M_208M_SEL = 1; + } + else if (eClkMux == CLK_MUX_104M) + { + u1DVFS_52M_104M_SEL = 1; + u1DVFS_104M_208M_SEL = 0; + } + else + { + u1DVFS_52M_104M_SEL = 0; + u1DVFS_104M_208M_SEL = 0; + } + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CKMUX_SEL, P_Fld(u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL) + | P_Fld(u1DVFS_104M_208M_SEL, MISC_CKMUX_SEL_RG_104M_208M_SEL)); + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, P_Fld(0x3, MISC_CG_CTRL0_CLK_MEM_SEL) + | P_Fld(0x1, MISC_CG_CTRL0_W_CHG_MEM)); + + mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_W_CHG_MEM); +} +#endif + +#if ENABLE_DFS_DEBUG_MODE +void WaitDFSDebugSM(DRAMC_CTX_T *p, U8 u1HangStatus) +{ + U8 u1Status[CHANNEL_NUM] = {0}, u1DvfsState[CHANNEL_NUM] = {0}, u1ChIdx = 0, u1ChStart = 0, u1ChEnd = 0; + DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p); + U32 u4While1Cnt = 100; + + u1ChStart = CHANNEL_A; + u1ChEnd = CHANNEL_B+1; +#if CHANNEL_NUM > 2 + u1ChEnd = CHANNEL_D+1; +#endif + + for (u1ChIdx = u1ChStart; u1ChIdx < u1ChEnd; u1ChIdx++) + { + vSetPHY2ChannelMapping(p, u1ChIdx); + do { + u1Status[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_DVFS_STATUS), DVFS_STATUS_CUT_PHY_ST_SHU); + u1DvfsState[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_DVFS_STATE); + //mcSHOW_DBG_MSG(("[WaitDFSDebugSM] CH%d DFS debug mode state (0x%x, 0x%x), Dvfs State = 0x%x\n", u1ChIdx, u1Status[u1ChIdx], u1HangStatus, u1DvfsState[u1ChIdx])); + if (u1Status[u1ChIdx] == u1HangStatus) + break; + + if (u4While1Cnt == 0) + { + DDRPhyFreqMeter(); + while(1); + } + u4While1Cnt--; + } while(1); + } + + vSetPHY2ChannelMapping(p, eOriChannel); +} + +void ExitDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode) +{ + if ((eDbgMode == BEF_DFS_MODE) || (eDbgMode == AFT_DFS_MODE)) + { + vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN) + | P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN)); + } + else if (eDbgMode == CHG_CLK_MODE) + { + vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN) + | P_Fld(0x0, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); // HW mode + } + else + { + mcSHOW_ERR_MSG(("DFS debug mode err!\n")); + #if __ETT__ + while (1); + #endif + } +} + +void ChkDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode) +{ + if (eDbgMode == BEF_DFS_MODE) + { + WaitDFSDebugSM(p, 0x1); + } + else if (eDbgMode == AFT_DFS_MODE) + { + WaitDFSDebugSM(p, 0x1d); + + } + else if (eDbgMode == CHG_CLK_MODE) + { + WaitDFSDebugSM(p, 0x1e); + + // HW shuffle will switch clock to 208MHz and continue DFS + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) + | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); + mcDELAY_US(1); // Wait 1T 26MHz + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) + | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); + + WaitDFSDebugSM(p, 0x1f); + + // HW shuffle will switch clock to MCK and continue DFS + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) + | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); + mcDELAY_US(1); // Wait 1T 26MHz + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) + | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); + + } + else + { + mcSHOW_ERR_MSG(("DFS debug mode err!\n")); + #if __ETT__ + while (1); + #endif + } +} + +void EntryDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode) +{ + if (eDbgMode == BEF_DFS_MODE) + { + vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN) + | P_Fld(0x1, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN)); + } + else if (eDbgMode == AFT_DFS_MODE) + { + vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x1, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN) + | P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN)); + } + else if (eDbgMode == CHG_CLK_MODE) + { + vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN) + | P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN)); + // for MD32 RG mode + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); + // for PHY RG mode (no support) + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); + } + else + { + mcSHOW_ERR_MSG(("DFS debug mode err!\n")); + #if __ETT__ + while (1); + #endif + } + +} +#endif + +#if DFS_NOQUEUE_FLUSH_WA +U32 u4PERFCTL0_backup=0; + +void EnableDFSNoQueueFlush(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0, DVFS_CTRL0_HWSET_WLRL) + | P_Fld(0, DVFS_CTRL0_DVFS_RXFIFOST_SKIP) // sync MP settings + | P_Fld(1, DVFS_CTRL0_DVFS_NOQUEFLUSH_EN) + | P_Fld(0, DVFS_CTRL0_R_DMDVFSMRW_EN)); + vIO32WriteFldMulti_All(DRAMC_REG_SHUCTRL1, P_Fld(0, SHUCTRL1_FC_PRDCNT) +#if ENABLE_LP4Y_WA + //@Berson, LP4Y tCKFSPE/X_SE violation at shuffle as DVFS noqueflush enable + // LP4Y tCKFSPE/X_SE violation at shuffle from 7.5ns to 15ns + | P_Fld(5, SHUCTRL1_CKFSPE_PRDCNT) + | P_Fld(5, SHUCTRL1_VRCGEN_PRDCNT) +#else + | P_Fld(0, SHUCTRL1_CKFSPE_PRDCNT) + | P_Fld(0, SHUCTRL1_VRCGEN_PRDCNT) +#endif + | P_Fld(0, SHUCTRL1_CKFSPX_PRDCNT)); + vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0, BYPASS_FSPOP_BPFSP_OPT); // sync MP settings + +#if ENABLE_DFS_RUNTIME_MRW // for Skip HW MR2 + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP) // OP CHG & VRCG High + | P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP) // VRCG Low + | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP)); // MR2 RL/WL (reduce 50ns) +#endif + +#if ENABLE_DFS_NOQUEUE_FLUSH_DBG + // for debug mode only (skip HW MRW) + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE) + | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE) + | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE)); +#endif +} + +static void NoQueueFlushWA(DRAMC_CTX_T *p, U8 u1WA_enable) +{ + U32 bc_bak=0; + + if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + { + bc_bak = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + + if (u1WA_enable == ENABLE) + { + u4PERFCTL0_backup = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_PERFCTL0)) >> Fld_shft(PERFCTL0_RWAGEEN)) & 0x3; + vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0, PERFCTL0_RWAGEEN) + | P_Fld(0, PERFCTL0_EMILLATEN)); + //mcSHOW_DBG_MSG(("[NoQueueFlushWA] PERFCTL0[11:10] backup = 0x%x\n", u4PERFCTL0_backup)); + } + else + { + vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(u4PERFCTL0_backup & 0x1, PERFCTL0_RWAGEEN) + | P_Fld((u4PERFCTL0_backup>>1) & 0x1, PERFCTL0_EMILLATEN)); + } + + if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + DramcBroadcastOnOff(bc_bak); +} +#endif + +#if ENABLE_TIMING_TXSR_DFS_WA +static void TimingTxsrWA(DRAMC_CTX_T *p, U32 next_shu_level) +{ + U32 onoff=0, bc_bak=0; + + if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + { + bc_bak = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + + if ((next_shu_level == SRAM_SHU4) || (next_shu_level == SRAM_SHU5) || (next_shu_level == SRAM_SHU6)) + onoff = DISABLE; + else + onoff = ENABLE; + + vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, onoff, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA); + + if (p->support_channel_num > CHANNEL_SINGLE) + DramcBroadcastOnOff(bc_bak); +} +#endif + +#if ENABLE_TX_REBASE_ODT_WA +void TxReadBaseODTWA(DRAMC_CTX_T *p, U8 next_shu_level) +{ + U32 termen_dis, bc_bak=0; + + if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + { + bc_bak = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + + if ((next_shu_level == SRAM_SHU0) || (next_shu_level == SRAM_SHU1)) // for DDR4266/DDR3200 + termen_dis = DISABLE; //term + else + termen_dis = ENABLE; // un-term + + //mcSHOW_DBG_MSG(("[TxReadBaseODTWA] SRAM SHU%d, termen_dis = %d\n", next_shu_level, termen_dis)); + vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, termen_dis, B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0); + vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, termen_dis, B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1); + vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, termen_dis, CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS); + + if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + DramcBroadcastOnOff(bc_bak); +} +#endif + +#if ENABLE_TX_REBASE_WDQS_DQS_PI_WA +static void TxReBaseWDQSDqsPiWA(DRAMC_CTX_T *p, U8 pingpong_shu_level) +{ + U32 bc_bak=0; + + if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + { + bc_bak = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + } + + p->ShuRGAccessIdx = pingpong_shu_level; + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13 , P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 ) + | P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 ) ); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13 , P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 ) + | P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 ) ); + mcDELAY_US(1); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13 , P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 ) + | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 ) ); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13 , P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 ) + | P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 ) ); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + + if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + DramcBroadcastOnOff(bc_bak); +} +#endif + +#if ENABLE_SRAM_DMA_WA +/*#define DDRPHY_REG_SHU_B0_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x07B4) + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0 Fld(7, 0) //[6:0] + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0 Fld(7, 8) //[14:8]*/ +U32 gSRAMBackupIdx[DRAM_DFS_SHUFFLE_MAX][4] = { // @Darren, LP5 don't use DDRPHY_REG_SHU_R0_CA_RXDLY6 !! +/*0*/ {DDRPHY_REG_SHU_B0_DQ9, DDRPHY_REG_SHU_B1_DQ9}, +/*1*/ {DDRPHY_REG_SHU_B0_DQ9, DDRPHY_REG_SHU_B1_DQ9}, +/*2*/ {DDRPHY_REG_SHU_B0_DQ9, DDRPHY_REG_SHU_B1_DQ9}, +/*3*/ {DDRPHY_REG_SHU_B0_DQ9, DDRPHY_REG_SHU_B1_DQ9}, +/*4*/ {DDRPHY_REG_SHU_B0_DQ9, DDRPHY_REG_SHU_B1_DQ9}, +/*5*/ {DDRPHY_REG_SHU_B0_DQ9, DDRPHY_REG_SHU_B1_DQ9}, +/*6*/ {DDRPHY_REG_SHU_B0_DQ9, DDRPHY_REG_SHU_B1_DQ9}, +}; +void DPHYSaveToSRAMShuWA(DRAMC_CTX_T *p, U8 sram_shu_level) +{ + U8 u1ChannelIdx=0, u1RankIdx=0; + U32 u4B0_DQ1=0, u4Offset=0; + U8 u1Ch_backup = p->channel, u1Rk_backup = p->rank; + U32 u4B0_PHY_VREF_SEL=0, u4B1_PHY_VREF_SEL=0, u4PHY_VREF_SEL=0; + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; + + for (u1ChannelIdx=CHANNEL_A; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + for (u1RankIdx = RANK_0; u1RankIdx < (p->support_rank_num); u1RankIdx++) + { + vSetRank(p, u1RankIdx); + u4Offset = 0; // B0 + u4B0_PHY_VREF_SEL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset)); + u4Offset = DDRPHY_AO_B0_B1_OFFSET; // B1 + u4B1_PHY_VREF_SEL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset)); + + u4PHY_VREF_SEL = (u4B1_PHY_VREF_SEL<<16) | u4B0_PHY_VREF_SEL; + + mcSHOW_DBG_MSG(("[DPHYSaveToSRAMShuWA] CH%d RK%d, B1B0_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u4PHY_VREF_SEL)); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + vIO32Write4B(DRAMC_REG_ADDR(gSRAMBackupIdx[sram_shu_level][u1RankIdx]), u4PHY_VREF_SEL); + } + } + + p->ShuRGAccessIdx = ShuRGAccessIdxBackup; + vSetPHY2ChannelMapping(p, u1Ch_backup); + vSetRank(p, u1Rk_backup); +} + +void DPHYSRAMShuWAToSHU1(DRAMC_CTX_T *p) +{ + U8 u1ChannelIdx=0, u1RankIdx=0; + U32 u4B0_DQ1=0, u4Offset=0; + U8 u1Ch_backup = p->channel, u1Rk_backup = p->rank; + U32 u4B0_PHY_VREF_SEL=0, u4B1_PHY_VREF_SEL=0, u4PHY_VREF_SEL=0; + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; + + for (u1ChannelIdx=CHANNEL_A; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + for (u1RankIdx = RANK_0; u1RankIdx < (p->support_rank_num); u1RankIdx++) + { + vSetRank(p, u1RankIdx); + u4Offset = 0; // B0 + u4B0_PHY_VREF_SEL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset)); + u4Offset = DDRPHY_AO_B0_B1_OFFSET; // B1 + u4B1_PHY_VREF_SEL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset)); + + u4PHY_VREF_SEL = (u4B1_PHY_VREF_SEL<<16) | u4B0_PHY_VREF_SEL; + mcSHOW_DBG_MSG(("[DPHYRxVrefWAToSHU1] CH%d RK%d, B1B0_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u4PHY_VREF_SEL)); + + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; + u4Offset = 0; // B0 + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset), u4B0_PHY_VREF_SEL); + u4Offset = DDRPHY_AO_B0_B1_OFFSET; // B1 + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset), u4B1_PHY_VREF_SEL); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + } + } + + p->ShuRGAccessIdx = ShuRGAccessIdxBackup; + vSetPHY2ChannelMapping(p, u1Ch_backup); + vSetRank(p, u1Rk_backup); +} + +void SRAMShuRestoreToDPHYWA(DRAMC_CTX_T *p, U8 sram_shu_level, U8 pingpong_shu_level) +{ + U8 u1ChannelIdx=0, u1RankIdx=0, u1ByteIdx=0; + U32 u4Offset=0; + U8 u1Ch_backup = p->channel, u1Rk_backup = p->rank; + U32 u4Byte_PHY_VREF_SEL=0, u4PHY_VREF_SEL=0; + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; + + for (u1ChannelIdx=CHANNEL_A; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + for (u1RankIdx = RANK_0; u1RankIdx < (p->support_rank_num); u1RankIdx++) + { + vSetRank(p, u1RankIdx); + p->ShuRGAccessIdx = pingpong_shu_level; + u4PHY_VREF_SEL = u4IO32Read4B(DRAMC_REG_ADDR(gSRAMBackupIdx[sram_shu_level][u1RankIdx])); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + + for(u1ByteIdx=0; u1ByteIdx<DQS_NUMBER_LP4; u1ByteIdx++) + { + u4Offset = u1ByteIdx*DDRPHY_AO_B0_B1_OFFSET; + u4Byte_PHY_VREF_SEL = (u4PHY_VREF_SEL >> (16*u1ByteIdx)) & 0xffff; + + //mcSHOW_DBG_MSG(("[SRAMShuRestoreToDPHYWA] CH%d RK%d B%d, u4Byte_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u1ByteIdx, u4Byte_PHY_VREF_SEL)); + + p->ShuRGAccessIdx = pingpong_shu_level; + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset), u4Byte_PHY_VREF_SEL); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + } + } + } + + p->ShuRGAccessIdx = ShuRGAccessIdxBackup; + vSetPHY2ChannelMapping(p, u1Ch_backup); + vSetRank(p, u1Rk_backup); +} +#endif + +void EnableDFSHwModeClk(DRAMC_CTX_T *p) +{ + //Shuffle HW mode for MCK/208M switch + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, + P_Fld(0x3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI) | // dvfs source clock selection when ddrphy shuffle + P_Fld(0x1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE)); // dvfs destination clock selection when ddrphy shuffle + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, + P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN) | //M_CK clock mux selection update enable by shuffle + P_Fld(0x1, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) | // by shuffle + P_Fld(0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE) | // HW mode by shuffle + P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL)); // 4-to-1 mux for PLLCK +} + +void DVFSSettings(DRAMC_CTX_T *p) +{ + U8 u1DVFS_52M_104M_SEL = 1; // DVFS_SM freq: 0: 52Mhz 1:104Mhz + U8 u1Master_DLL_Idle = 0x2b; // Master from MCK + U8 u1Slave_DLL_Idle = 0x43; // Slave from MCK +#if (fcFOR_CHIP_ID == fcA60868) // @Darren, for A60868 only + U8 u1ChClkIgnore[2] = {ENABLE, ENABLE}, u1Channel = 0; // 1=ignore +#endif + U32 backup_broadcast = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + if (vGet_Div_Mode(p) == DIV16_MODE) + { + u1Master_DLL_Idle = 0x37; // Master from MCK + u1Slave_DLL_Idle = 0x4D; // Slave from MCK + } + + //DVFS debug enable - MRR_STATUS2_DVFS_STATE + //@Lynx, A60868 HW always enable shuffle debug. remove RG: DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE + //vIO32WriteFldAlign_All(DRAMC_REG_DVFSDLL, 1, DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE); + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL); //Set DVFS_SM's clk +#if ENABLE_DFS_208M_CLOCK + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_RG_104M_208M_SEL); //Set DVFS_SM's clk to 208M +#endif + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(u1Master_DLL_Idle, MISC_SHU_DVFSDLL_R_DLL_IDLE) + | P_Fld(u1Slave_DLL_Idle, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); + + // @Darren, set current SRAM SHU index for SPM mode DFS latch/restore + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, vGet_Current_ShuLevel(p), MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM); + //mcSHOW_DBG_MSG(("[DVFSSettings] SHU_LEVEL_SRAM = %d\n", vGet_Current_ShuLevel(p))); + +#if (fcFOR_CHIP_ID == fcA60868) // @Darren, for A60868 only + for (u1Channel = CHANNEL_A; u1Channel < p->support_channel_num; u1Channel++) + u1ChClkIgnore[u1Channel] = DISABLE; + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(u1ChClkIgnore[1], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHB) + | P_Fld(u1ChClkIgnore[0], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHA)); +#endif + // DFS trigger by DDRPHY RG + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); // DFS RG mode for calibration + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS); // DFS RG mode for disable tx tracking + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_RG_MRW_AFTER_DFS); + + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1, P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) + | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) + | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) + | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_OPT, P_Fld(1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN) + | P_Fld(1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN)); +#if ENABLE_DFS_HW_SAVE_MASK + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY); // 0x1 = disable dfs hw save +#endif + +#if ENABLE_DVFS_CDC_SYNCHRONIZER_OPTION + //CDC option + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(1, MISC_DVFSCTL2_R_DVFS_CDC_OPTION) //Lewis@20170331: Not set SHUCTRL2_R_DVFS_CDC_OPTION to 1 since it will lead DDR reserve mode fail in DDR2400 and DDR1600 + | P_Fld(1, MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION)); +#endif + +#if 0 // @Darren, reserved from Mengru Dsim + U8 u1MarginNew = (u1DVFS_52M_104M_SEL == 1) ? 0x3 : 0x1; + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_OPT, 0x2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW) + | P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW) + | P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_FMEM_CK_MUX); + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0x1, DVFS_CTRL0_R_DRAMC_CHA) + | P_Fld(0x0, DVFS_CTRL0_DVFS_CKE_OPT) + | P_Fld(0x1, DVFS_CTRL0_SCARB_PRI_OPT) + | P_Fld(0x0, DVFS_CTRL0_SHU_PHYRST_SEL)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(0x1, MISC_DVFSCTL2_R_DVFS_PARK_N) + | P_Fld(0x1, MISC_DVFSCTL2_R_DVFS_OPTION)); +#endif + +#if ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL7, 1, MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(1, MISC_DVFSCTL_R_DVFS_PICG_POSTPONE) + | P_Fld(1, MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT)); +#endif + +#if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION // @Mazar + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 1, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE) + | P_Fld(3, MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN) + | P_Fld(3, MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW)); +#endif + +#if RDSEL_TRACKING_EN + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1ffff, MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN); +#endif + +#if (fcFOR_CHIP_ID == fcMargaux) // @Darren, for Mar_gaux New setting for ddrphy shuffle (sync mode) + vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL); + vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHB_ADDR, 1, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL); +#endif + + //Cann_on CDC options + //DLL_SHUFFLE should be set enable before switch frequency + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_RG_DLL_SHUFFLE); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(0, MISC_DVFSCTL2_R_DVFS_OPTION) + | P_Fld(0, MISC_DVFSCTL2_R_DVFS_PARK_N)); + +#if ENABLE_DFS_TIMING_ENLARGE + DFSEnlargeTimingSettings(p); +#endif + + //EnableDFSHwModeClk(p); // @Darren, for DFS shuffle change + + DramcBroadcastOnOff(backup_broadcast); +} + +#if ENABLE_DFS_SSC_WA +void DDRSSCSetting(DRAMC_CTX_T * p) +{ + U32 u4DELTA1 = 0; + + if (p->frequency == 1866) + { + u4DELTA1 = 0xE14; + } + else if (p->frequency == 1600) + { + u4DELTA1 = 0xC1C; + } + else if (p->frequency == 1200) + { + u4DELTA1 = 0x90F; + } + else + { + return; + } + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL1, 0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL1, 0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN); + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL6, 0x1, SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PH_INIT); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL6, 0x1, SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PH_INIT); + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL6, 0x0208, SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PRD); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL6, 0x0208, SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PRD); + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL7, 0x0, SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL7, 0x0, SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA); + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL7, u4DELTA1, SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA1); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL7, u4DELTA1, SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA1); + + //vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x1, PLL1_RG_RPHYPLL_SDM_SSC_EN); + //vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x1, PLL2_RG_RCLRPLL_SDM_SSC_EN); +} + +void DramcSSCHoppingOnOff(DRAMC_CTX_T *p, U8 cur_shu_level, U8 u1OnOff) +{ + if ((cur_shu_level == 0x0) || (cur_shu_level == 0x8) || (cur_shu_level == 0x9) || (cur_shu_level == 0x6) || (cur_shu_level == 0x5)) + { + if (!(p->u1PLLMode == PHYPLL_MODE)) + vIO32WriteFldAlign(DDRPHY_REG_CLRPLL0, u1OnOff, CLRPLL0_RG_RCLRPLL_SDM_SSC_EN); // CLRPLL SSC + else + vIO32WriteFldAlign(DDRPHY_REG_PHYPLL0, u1OnOff, PHYPLL0_RG_RPHYPLL_SDM_SSC_EN); // PHYPLL SSC + } +} +#endif + + +#if DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM || ENABLE_DFS_SSC_WA +void DVS_DMY_RD_ENTR(DRAMC_CTX_T *p) +{ + /*TINFO="DRAM : SPM DVS DMY RD ENTR"*/ + + /*TINFO="DRAM : set sc_ddrphy_fb_ck_en = 1"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 1, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); + + + mcDELAY_US(1); + + /*TINFO="DRAM : set sc_dmyrd_en_mod_sel = 1"*/ + //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL); + + mcDELAY_US(1); + + /*TINFO="DRAM : set sc_dmyrd_intv_sel = 1"*/ + //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL); + + mcDELAY_US(1); + + /*TINFO="DRAM : set sc_dmyrd_en = 1"*/ + //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_EN); + + mcDELAY_US(1); +} + +void DVS_DMY_RD_EXIT(DRAMC_CTX_T *p) +{ + /*TINFO="DRAM : SPM DVS DMY RD EXIT"*/ + + /*TINFO="DRAM : set sc_dmyrd_en = 0"*/ + //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_EN); + + mcDELAY_US(1); + + /*TINFO="DRAM : set sc_dmyrd_intv_sel = 0"*/ + //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL); + + mcDELAY_US(1); + + /*TINFO="DRAM : set sc_dmyrd_en_mod_sel = 0"*/ + //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL); + + mcDELAY_US(1); + + /*TINFO="DRAM : set sc_ddrphy_fb_ck_en = 0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); + + mcDELAY_US(1); + + + /*TINFO="DRAM : SPM DVS DMY RD EXIT end "*/ +} +#endif + + +#if 1//(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) + +void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable) +{ + U32 val, fld; + + fld = Fld(1, (Fld_shft(u4Field) + u1ShuIdx)); + + val = (u1Enable) ? 1 : 0; + + vIO32WriteFldAlign_All(u4Reg, u1Enable, fld); +} + +void DPMInit(DRAMC_CTX_T *p) +{ + U8 u1SetVal; + U8 u1Pll1Val, u1Pll2Val; + U8 u1ShuSramVal; + DRAM_DFS_SRAM_SHU_T u1CurrShuLevel = vGet_Current_ShuLevel(p); + + u1SetVal = (p->support_channel_num > 1) ? 0x3 : 0x1; + + // pre-setting DPM to dramc low power interface setting + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_PHYPLL_EN) | // both channel phy pll en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_EN) | // both channel dpy pll en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN) | // both channel dpy 2nd pll en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN) | // both channel dpy dll ck en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_VREF_EN)); // both channel dpy vref en + + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN) | // both channel mck8x en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN) | // both channel midpi en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN)); // both channel dpy pi resetb en + + if (p->u1PLLMode == PHYPLL_MODE) + { + mcSHOW_DBG_MSG(("PHYPLL\n")); + u1Pll1Val = u1SetVal; + u1Pll2Val = 0; + } + else + { + mcSHOW_DBG_MSG(("CLRPLL\n")); + u1Pll1Val = 0; + u1Pll2Val = u1SetVal; + } + + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, + P_Fld(u1Pll1Val, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN) | + P_Fld(u1Pll1Val, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW) | + P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN) | + P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW)); + + // all by lpif fw mode + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1, + /* TBA set control mux in DV initial */ + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) | // 0: MD32, 1: SPM + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) | // 0: MD32, 1: SPM + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) | // 0: MD32, 1: SPM + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND) | // 0: MD32, 1: SPM + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) | // 0: MD32 SCU, 1: MD32 CFG + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND) | // 0: MD32 SCU, 1: MD32 CFG + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL) | // 0: MD32 SCU, 1: MD32 CFG + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND)); // 0: MD32 SCU, 1: MD32 CFG + + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0, + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN) | // @Darren, fix dfs phypll init + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW)); + + u1ShuSramVal = u1CurrShuLevel; + + if (p->support_channel_num > 1) + u1ShuSramVal |= u1CurrShuLevel << 4; + + // NOTE: MD32 PST mode shuffle level = (LPIF_CTRL_CTRL1_LPIF_DRAMC_DR_SHU_LEVEL_SRAM | LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL) + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ShuSramVal, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL); + +#if __ETT__ + /* internal test mode */ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_SSPM_CFGREG_GPR0, 0xE7700E77, SSPM_CFGREG_GPR0_GPR0); +#endif + + // for DFS + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN); + + // enable DFD + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 , 0x1, LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN); +} + +//------------------------------------------------------------------------- +/** TransferPLLToSPMControl + * 1. Enable DVFS to SPM control + * 2. Configs SPM pinmux + * 3. To control PLL between PHYPLL and CLRPLL via SPM + * 4. set current SRAM SHU index for SPM mode DFS latch/restore + */ +//------------------------------------------------------------------------- +void TransferPLLToSPMControl(DRAMC_CTX_T *p, U32 MD32Offset) +{ + //U8 u1EnMd32Ch = 0, i; + //U16 u2SramLevel = 0; + //DRAM_DFS_SRAM_SHU_T u1CurrShuLevel = vGet_Current_ShuLevel(p); + + /*for (i = 0; i < DPM_CH_NUM; i++) + { + u1EnMd32Ch |= (0x1 << i); + u2SramLevel |= (u1CurrShuLevel << (4*i)); + }*/ + + /*TINFO="DRAM : enter SW DVFS"*/ + //! To DFS SPM mode after calibration + // Enable DVFS to SPM control + /*vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); + + vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, P_Fld(0x3, LPIF_LOW_POWER_CFG_0_PHYPLL_EN) // both channel phy pll en + | P_Fld(0x3, LPIF_LOW_POWER_CFG_0_DPY_DLL_EN) // both channel dpy pll en + | P_Fld(0x3, LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN) // both channel dpy 2nd pll en + | P_Fld(0x3, LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN) // both channel dpy dll ck en + | P_Fld(0x3, LPIF_LOW_POWER_CFG_0_DPY_VREF_EN) // both channel dpy vref en + | P_Fld(0x3, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN) // @Darren, fix dfs phypll init + | P_Fld(0x3, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW)); // bith channel phypll mode sw*/ + + // DFS trigger by DRAMC MD32 RG + /*vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_FSM_CFG_1+MD32Offset, P_Fld(0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) + | P_Fld(0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) + | P_Fld(0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) + | P_Fld(0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND) + | P_Fld(1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) // 1: MD32 RG mode, 0: MD32 PST mode + | P_Fld(1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND));*/ // 1: MD32 RG mode, 0: MD32 PST mode + + mcSHOW_DBG_MSG(("TransferPLLToSPMControl - MODE SW ")); + + if (p->u1PLLMode == PHYPLL_MODE) + { + /*mcSHOW_DBG_MSG(("PHYPLL\n")); + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN); + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN); // PHYPLL for part of SHU RG + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // same as DRAMC_DPY_CLK_SW_CON2_SW_PHYPLL2_MODE_SW by MUX + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW);*/ // same as DRAMC_DPY_CLK_SW_CON2_SW_PHYPLL_MODE_SW by MUX + vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0+MD32Offset, + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN) | // @Darren, fix dfs phypll init + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW)); + } + else + { + /*mcSHOW_DBG_MSG(("CLRPLL\n")); + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN); + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN); // CLRPLL for part of SHU RG + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // same as DRAMC_DPY_CLK_SW_CON2_SW_PHYPLL2_MODE_SW by MUX + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW);*/ // same as DRAMC_DPY_CLK_SW_CON2_SW_PHYPLL_MODE_SW by MUX + vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0+MD32Offset, + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN) | + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL2_SHU_EN) | // @Darren, fix dfs clrpll init + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL2_MODE_SW)); + } + mcDELAY_US(1); + + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN); + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN); + + //set current SRAM SHU index for SPM mode DFS latch/restore + // @Darren for MD32 RG mode only + // MD32 PST mode shuffle level = (LPIF_CTRL_CTRL1_LPIF_DRAMC_DR_SHU_LEVEL_SRAM | LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL) + //Darren-vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1+MD32Offset, u2SramLevel, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL); + //mcSHOW_DBG_MSG(("TransferPLLToSPMControl - Current SRAM SHU LEVEL = %d\n", u1CurrShuLevel)); + +#if DFS_NOQUEUE_FLUSH_WA + // Enable Max cnt for latency measure from shu_en to shu_ack + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_FSM_CFG+MD32Offset, 1, LPIF_FSM_CFG_DBG_LATENCY_CNT_EN); +#endif + + // MD32 clock is 208M + vIO32WriteFldMulti(DDRPHY_MD32_REG_SSPM_MCLK_DIV+MD32Offset, + P_Fld(0, SSPM_MCLK_DIV_MCLK_SRC) | + P_Fld(0, SSPM_MCLK_DIV_MCLK_DIV)); +} +#endif + + +#if ENABLE_DVFS_BYPASS_MR13_FSP +void DFSBypassMR13HwSet(DRAMC_CTX_T *p) +{ +#if __A60868_TO_BE_PORTING__ + U8 u1ShuffleIdx, BFSP = 0, u1SramShuIdx = 0; + REG_TRANSFER_T TransferReg; + + TransferReg.u4Addr = DRAMC_REG_BYPASS_FSPOP; + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU3; + for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) + { + u1SramShuIdx = gFreqTbl[u1ShuffleIdx].shuffleIdx; + switch (u1SramShuIdx) + { + case 0: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU0; + break; + case 1: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU1; + break; + case 2: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU2; + break; + case 3: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU3; + break; + case 4: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU4; + break; + case 5: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU5; + break; + case 6: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU6; + break; + case 7: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU7; + break; + case 8: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU8; + break; + case 9: + TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU9; + break; + default: + mcSHOW_ERR_MSG(("[DFSBypassMR13HwSet] fail at BPFSP_SHU%d incorrect !!!\n", u1SramShuIdx)); + break; + } + BFSP = (gFreqTbl[u1ShuffleIdx].freq_sel <= LP4_DDR2667)? 0x1: 0x0; //0x1 (Bypass), 0x0 (Not bypass) + //mcSHOW_DBG_MSG(("[DFSBypassMR13HwSet] BPFSP_SHU%d = 0x%x\n", u1SramShuIdx, BFSP)); + vIO32WriteFldAlign_All(TransferReg.u4Addr, BFSP, TransferReg.u4Fld); + } + vIO32WriteFldAlign_All(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0, 0x1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); // 1: shuffle level = 10, 0: shuffle level =4 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CDC_CTRL, 0x0, MISC_CDC_CTRL_REG_CDC_BYPASS_DBG); + vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0x1, BYPASS_FSPOP_BPFSP_OPT); +#endif +} +#endif + +#if FOR_DV_SIMULATION_USED +void DFSSwitchtoRGMode(DRAMC_CTX_T *p) +{ + vIO32WriteFldAlign(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); +} +#endif + +void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG) +{ + U8 u1ChIdx; + U8 u1value; + DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p); + + #if ENABLE_SRAM_DMA_WA + DPHYSaveToSRAMShuWA(p, p->pDFSTable->shuffleIdx); + #endif + + for (u1ChIdx = 0; u1ChIdx < p->support_channel_num; u1ChIdx++) + { + vSetPHY2ChannelMapping(p, u1ChIdx); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_SLV_SEL); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_STEP_EN_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SRAM_WR_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_WR_MODE); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), srcRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_APB); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), dstRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_DMA_FIRE); + do { + u1value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_SRAM_DONE); + u1value |= (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_APB_DONE) << 1); + mcSHOW_DBG_MSG3(("\twait dramc to shuffle sram done.\n")); + } while (u1value != 0x3); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_STEP_EN_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_MODE); + } + + vSetPHY2ChannelMapping(p, eOriChannel); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0, MISC_SRAM_DMA0_SRAM_WR_MODE); //MP setting:should disable WR MDOE +} + +void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG) +{ + U8 u1ChIdx; + U8 u1value; + DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p); + + for (u1ChIdx = 0; u1ChIdx < p->support_channel_num; u1ChIdx++) + { + vSetPHY2ChannelMapping(p, u1ChIdx); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_SLV_SEL); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_STEP_EN_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SRAM_WR_MODE); //diff with DramcSaveToShuffleSRAM + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_APB_WR_MODE); // diff with DramcSaveToShuffleSRAM + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), dstRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_APB); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), srcRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_DMA_FIRE); + do { + u1value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_SRAM_DONE); + u1value |= (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_APB_DONE) << 1); + mcSHOW_DBG_MSG3(("\twait shuffle sram to dramc done.\n")); + } while (u1value != 0x3); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_STEP_EN_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_MODE); + } + + vSetPHY2ChannelMapping(p, eOriChannel); +} + +static U8 WaitChShuEnAck(DRAMC_CTX_T *p, U32 u4Addr, U32 u4Fld, U8 u1Status) +{ + U8 u1WaitShuAckState = 0, u1ChIdx = 0, u1AckDone = 0; + DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p); + + for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++) + { + vSetPHY2ChannelMapping(p, u1ChIdx); + + do { + u1WaitShuAckState = u4IO32ReadFldAlign(DRAMC_REG_ADDR(u4Addr), u4Fld); + //mcSHOW_DBG_MSG(("[WaitChShuEnAck] Wait Shu Ack State = 0x%x\n", u1WaitShuAckState)); + if (u1WaitShuAckState == u1Status) + break; + } while(1); + + u1AckDone |= (0x1 << u1ChIdx); + } + vSetPHY2ChannelMapping(p, eOriChannel); + + return u1AckDone; // shu end +} + +void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level) +{ + U8 u1ShuAck = 0; + U8 i = 0; + U8 u1ChkComplete = 1; + + if (p->u1PLLMode == PHYPLL_MODE) + { + mcSHOW_DBG_MSG3(("Disable CLRPLL\n")); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); + } + else + { + mcSHOW_DBG_MSG3(("Disable PHYPLL\n")); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); + } + + for (i = 0; i < p->support_channel_num; i++) + { + u1ShuAck |= (0x1 << i); + } + + if (p->u1PLLMode == PHYPLL_MODE) + { + mcSHOW_DBG_MSG3(("DFSDirectJump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); + } + else + { + mcSHOW_DBG_MSG3(("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); + } + + /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); + + // sram latch + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH); + mcDELAY_US(1); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH); + + if (p->u1PLLMode == PHYPLL_MODE) + { + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, !p->u1PLLMode, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN); + mcSHOW_DBG_MSG3(("Enable CLRPLL\n")); + } + else + { + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, !p->u1PLLMode, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN); + mcSHOW_DBG_MSG3(("Enable PHYPLL\n")); + } + mcDELAY_US(1); + +#if 1 //Darren- + //vIO32WriteFldMulti((DDRPHY_MISC_SPM_CTRL3), P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH1) + // | P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH0)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM); + + //wait sram load ack. + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD); + //while (!u4IO32ReadFldAlign(DDRPHY_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK)); // wait SRAM PLL load ack + while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, u1ChkComplete) != u1ShuAck) + //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK)) + { + mcSHOW_DBG_MSG3(("\twait sram load ack.\n")); + } + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD); +#endif + + if (p->u1PLLMode == PHYPLL_MODE) + { + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + } + else + { + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + } + +#if DFS_NOQUEUE_FLUSH_WA + NoQueueFlushWA(p, ENABLE); +#endif + +#if ENABLE_SRAM_DMA_WA + SRAMShuRestoreToDPHYWA(p, shu_level, !p->u1PLLMode); +#endif + + #if 0//ENABLE_DFS_DEBUG_MODE + EntryDFSDebugMode(p, CHG_CLK_MODE); + #endif + +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + mcDELAY_US(20); // for SRAM shuffle DV sim spec > 20us +#else + mcDELAY_XUS(20); // for SRAM shuffle DV sim spec > 20us +#endif + +#if 0 + mcSHOW_DBG_MSG3(("Enable SHORT-QUEUE\n")); + vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE); + + mcSHOW_DBG_MSG3(("\twait 5us for short queue ack.\n")); + mcDELAY_US(5); +#endif + + //mcSHOW_DBG_MSG(("Disable RX-Tracking\n")); + //vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN); + + mcSHOW_DBG_MSG3(("SHUFFLE Start\n")); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from SHU_EN=1 to ACK, DV spec < 5.1us + +#if DFS_NOQUEUE_FLUSH_WA && ENABLE_DFS_NOQUEUE_FLUSH_DBG + WaitNoQueueFlushComplete(p); // for debug mode MRW skip +#endif + + // Fixed DV sim spec for DFS shu_en=1 < 5.1us and shu_en=0 < 120ns +#if 1//Darren-for test chip(FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n")); + //mcDELAY_US(5); + #if 0//ENABLE_DFS_DEBUG_MODE + ChkDFSDebugMode(p, CHG_CLK_MODE); + #endif + + //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END + //@tg Fix RG mode can not recevie shuffle end ack. + while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck +#if CHANNEL_NUM > 2 + || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck +#endif + ) + { + mcSHOW_DBG_MSG3(("\twait shu_en ack.\n")); + } +#else + while (u4IO32ReadFldAlign(DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE) != u1ShuAckState); // SHUFFLE_END +#endif + + #if 0//ENABLE_DFS_DEBUG_MODE + ExitDFSDebugMode(p, CHG_CLK_MODE); + #endif + +#if ENABLE_TX_REBASE_WDQS_DQS_PI_WA + TxReBaseWDQSDqsPiWA(p, !p->u1PLLMode); +#endif + +#if ENABLE_TX_REBASE_ODT_WA + TxReadBaseODTWA(p, shu_level); +#endif + + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from ACK to SHU_EN=0, DV spec < 120ns + mcSHOW_DBG_MSG3(("SHUFFLE End\n")); + + //if(shu_level == 0)//LP4-2CH + //{ + //mcSHOW_DBG_MSG(("Enable RX-Tracking for shuffle-0\n")); + //vIO32WriteFldAlign(SPM_SW_RSV_8, 3, SW_RSV_8_RX_TRACKING_EN); + //} + + if (p->u1PLLMode == PHYPLL_MODE) + { + /*TINFO="DRAM : set sc_phypll_mode_sw=0"*/ + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); // Disable PHYPLL + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + } + else + { + /*TINFO="DRAM : set sc_phypll2_mode_sw=0"*/ + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); // Disable CLRPLL + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + } + +#if 1 //Darren- + //wait sram restore ack. + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE); + while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, u1ChkComplete) != u1ShuAck) + //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK)) + { + mcSHOW_DBG_MSG3(("\twait sram restore ack.\n")); + } + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE); + +#if DFS_NOQUEUE_FLUSH_WA + NoQueueFlushWA(p, DISABLE); +#endif + + /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); +#endif + + #if ENABLE_TIMING_TXSR_DFS_WA + TimingTxsrWA(p, shu_level); + #endif + + mcSHOW_DBG_MSG3(("Shuffle flow complete\n")); + + p->u1PLLMode = !p->u1PLLMode; + return; +} + + +void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level) +{ + U8 u1ShuAck = 0; + U8 i = 0; + U8 u1shu_level = 0; + + if (p->u1PLLMode == PHYPLL_MODE) + { + mcSHOW_DBG_MSG3(("Disable CLRPLL\n")); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); + } + else + { + mcSHOW_DBG_MSG3(("Disable PHYPLL\n")); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); + } + + for (i = 0; i < p->support_channel_num; i++) + { + u1ShuAck |= (0x1 << i); + } + + if (p->u1PLLMode == PHYPLL_MODE) + { + mcSHOW_DBG_MSG3(("DFSDirectJump_RGMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); + } + else + { + mcSHOW_DBG_MSG3(("DFSDirectJump_RGMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); + } + + /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); + + if (shu_level == DRAM_DFS_SHUFFLE_1) + u1shu_level = shu_level; // Darren: shuffle to shu0 status (original calib flow.) + else + u1shu_level = 1; // Darren: Using shu1 for backup/restore, it diff with SPM mode + + if (p->u1PLLMode == PHYPLL_MODE) + { + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, u1shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN); + mcSHOW_DBG_MSG3(("Enable CLRPLL\n")); + } + else + { + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, u1shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN); + mcSHOW_DBG_MSG3(("Enable PHYPLL\n")); + } + mcDELAY_US(1); + + if (p->u1PLLMode == PHYPLL_MODE) + { + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + } + else + { + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + } + +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + mcDELAY_US(20); // for SRAM shuffle DV sim spec > 20us +#else + mcDELAY_XUS(20); // for SRAM shuffle DV sim spec > 20us +#endif + +#if 0 + mcSHOW_DBG_MSG3(("Enable SHORT-QUEUE\n")); + vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE); + + mcSHOW_DBG_MSG3(("\twait 5us for short queue ack.\n")); + mcDELAY_US(5); +#endif + + //mcSHOW_DBG_MSG(("Disable RX-Tracking\n")); + //vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN); + + + mcSHOW_DBG_MSG3(("SHUFFLE Start\n")); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); + + //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n")); + //mcDELAY_US(5); + //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END + //@tg Fix RG mode can not recevie shuffle end ack. + while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck +#if CHANNEL_NUM > 2 + || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck +#endif + ) + { + mcSHOW_DBG_MSG3(("\twait shu_en ack.\n")); + } + + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); + mcSHOW_DBG_MSG3(("SHUFFLE End\n")); + + //if(shu_level == 0)//LP4-2CH + //{ + //mcSHOW_DBG_MSG(("Enable RX-Tracking for shuffle-0\n")); + //vIO32WriteFldAlign(SPM_SW_RSV_8, 3, SW_RSV_8_RX_TRACKING_EN); + //} + + if (p->u1PLLMode == PHYPLL_MODE) + { + /*TINFO="DRAM : set sc_phypll_mode_sw=0"*/ + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); // Disable PHYPLL + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + } + else + { + /*TINFO="DRAM : set sc_phypll2_mode_sw=0"*/ + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); // Disable CLRPLL + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + } + + /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); + + mcSHOW_DBG_MSG3(("Shuffle flow complete\n")); + + p->u1PLLMode = !p->u1PLLMode; + return; +} + +static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level) +{ + U8 u1ShuAck = 0, u1EnMd32Ch = 0; + U8 i = 0; + U8 pingpong_shu_level = 0; // for shu0/1 + U8 u1PingPong = 0; + U16 u2SramLevel = 0; +#if ENABLE_DFS_RUNTIME_MRW + U8 cur_fsp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SA_RESERVE), SA_RESERVE_DFS_FSP_RTMRW); +#endif + + for (i = 0; i < DPM_CH_NUM; i++) + { + u1ShuAck |= (0x1 << i); + u1EnMd32Ch |= (0x1 << i); + } + + if (p->u1PLLMode == PHYPLL_MODE) + { + mcSHOW_DBG_MSG3(("DramcDFSDirectJump_SPMMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); + } + else + { + mcSHOW_DBG_MSG3(("DramcDFSDirectJump_SPMMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); + } + + //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x1, MISC_STBCAL2_STB_DBG_STATUS); // HJ Huang + /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnMd32Ch, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH); + mcDELAY_US(1); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH); + + //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[1:0] for CHA + //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[3:2] for CHB + pingpong_shu_level = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10, LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL); // read shuffle level for dramc conf0/1 + mcSHOW_DBG_MSG3(("Ping-pong CONF%d\n", (pingpong_shu_level & 0x1))); + for (i = 0; i < DPM_CH_NUM; i++) + { + u2SramLevel |= (shu_level << (i*4)); + u1PingPong |= (!((pingpong_shu_level >> (i*2)) & 0x1)) << (i*2); + } + pingpong_shu_level = u1PingPong; + + if (p->u1PLLMode == PHYPLL_MODE) + { + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, pingpong_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN); + mcSHOW_DBG_MSG3(("Enable CLRPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel)); + } + else + { + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, pingpong_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN); + mcSHOW_DBG_MSG3(("Enable PHYPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel)); + } + mcDELAY_US(1); + +#if ENABLE_DFS_RUNTIME_MRW + DFSRuntimeMRWEn(p, p->u1PLLMode, shu_level, cur_fsp); +#endif + +#if 0 //Darren test+ + vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, 0, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL); + vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, shu_level, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL); +#else + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u2SramLevel, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnMd32Ch, LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD); + while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_LOAD_ACK) & u1ShuAck) != u1ShuAck +#if CHANNEL_NUM > 2 + || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SRAM_LOAD_ACK) & u1ShuAck) != u1ShuAck +#endif + ) + { + mcSHOW_DBG_MSG3(("\twait sram load ack.\n")); + } + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD); +#endif + + //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x2, MISC_STBCAL2_STB_DBG_STATUS); + +#if ENABLE_DFS_SSC_WA + DVS_DMY_RD_ENTR(p); +#endif + + if (p->u1PLLMode == PHYPLL_MODE) + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); + else + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); + +#if ENABLE_DFS_SSC_WA + DramcSSCHoppingOnOff(p, cur_shu_level, ENABLE); +#endif + +#if DFS_NOQUEUE_FLUSH_WA + NoQueueFlushWA(p, ENABLE); +#endif + +#if ENABLE_SRAM_DMA_WA + SRAMShuRestoreToDPHYWA(p, shu_level, !p->u1PLLMode); +#endif + +#if ENABLE_DFS_RUNTIME_MRW + DFSRTMRW_HwsetWA(p, p->u1PLLMode, !p->u1PLLMode, cur_fsp); +#endif + + DFSHwSetWA(p, p->u1PLLMode, shu_level); + #if ENABLE_DFS_DEBUG_MODE + EntryDFSDebugMode(p, CHG_CLK_MODE); + #endif + + mcDELAY_US(20); + + /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); + + //EnableDramcTrackingByShuffle(p, shu_level, DISABLE); + + /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); + + //func_imp_tracking_value_backup(); + //func_imp_tracking_off(); + //func_force_mm_ultra(); + +#if ENABLE_DFS_SSC_WA + DVS_DMY_RD_EXIT(p); + //DramcSSCHoppingOnOff(p, cur_shu_level, ENABLE); // for waveform measure + //mcDELAY_US(10); // for waveform measure +#endif + +#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION + DDR800semiPowerSavingOn(p, shu_level, DISABLE); +#endif + +#if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE) + SPMTx_Track_Retry_OnOff(p, shu_level, ENABLE); +#endif + + mcSHOW_DBG_MSG3(("SHUFFLE Start\n")); + //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x3, MISC_STBCAL2_STB_DBG_STATUS); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_DR_SHU_EN); + + #if ENABLE_DFS_DEBUG_MODE + ChkDFSDebugMode(p, CHG_CLK_MODE); + // Add WA at here + ExitDFSDebugMode(p, CHG_CLK_MODE); + #endif + + while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck +#if CHANNEL_NUM > 2 + || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck +#endif + ) + { + mcSHOW_DBG_MSG3(("\twait shu_en ack.\n")); + } + +#if DFS_NOQUEUE_FLUSH_LATENCY_CNT + U8 MaxCnt = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_RESERVED_6, LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK); // show chx max cnt + // cnt * 8 * 4.8ns (208M) + mcSHOW_DBG_MSG(("\tMAX CNT = %d\n", MaxCnt)); +#endif + +#if ENABLE_TX_REBASE_WDQS_DQS_PI_WA + TxReBaseWDQSDqsPiWA(p, !p->u1PLLMode); +#endif + +#if ENABLE_TX_REBASE_ODT_WA + TxReadBaseODTWA(p, shu_level); +#endif + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DR_SHU_EN); + //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x4, MISC_STBCAL2_STB_DBG_STATUS); + mcSHOW_DBG_MSG3(("SHUFFLE End\n")); + + if (p->u1PLLMode == PHYPLL_MODE) + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // PHYPLL off + else + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // CLRPLL off + +#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION + DDR800semiPowerSavingOn(p, shu_level, ENABLE); +#endif + +#if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE) + SPMTx_Track_Retry_OnOff(p, shu_level, DISABLE); +#endif + +#if ENABLE_DFS_SSC_WA + DramcSSCHoppingOnOff(p, cur_shu_level, DISABLE); +#endif + + //func_imp_tracking_on(); +#if 1 //Darren test+ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnMd32Ch, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE); + while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_RESTORE_ACK) & u1ShuAck) != u1ShuAck +#if CHANNEL_NUM > 2 + || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SRAM_RESTORE_ACK) & u1ShuAck) != u1ShuAck +#endif + ) + { + mcSHOW_DBG_MSG3(("\twait sram restore ack.\n")); + } + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE); +#endif + +#if DFS_NOQUEUE_FLUSH_WA + NoQueueFlushWA(p, DISABLE); +#endif + + /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); + //Darren-EnableDramcTrackingByShuffle(p, shu_level, ENABLE); + + //----------------------------------- + // TRIGGER DRAM GATING ERROR + //----------------------------------- + //func_dram_dummy_read_on(); + //mcDELAY_US(2); + //func_dram_dummy_read_off(); + + p->u1PLLMode = !p->u1PLLMode; + + //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x5, MISC_STBCAL2_STB_DBG_STATUS); + mcSHOW_DBG_MSG3(("Shuffle flow complete\n")); + + return; +} + +void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level) +{ +#if (DRAMC_DFS_MODE == 2) + gDVFSCtrlSel = 2; // SRAM RG mode +#elif (DRAMC_DFS_MODE == 1) + gDVFSCtrlSel = 1; // MD32 +#elif (DRAMC_DFS_MODE == 0) + gDVFSCtrlSel = 0; // Legacy mode +#endif + + if (gDVFSCtrlSel == 0) + { + if (shu_level == SRAM_SHU0) // DDR4266 + DramcDFSDirectJump_RGMode(p, 0); // Legacy mode for CONF0 + else + DramcDFSDirectJump_RGMode(p, 1); // Legacy mode for CONF1 + } + else if (gDVFSCtrlSel == 1) + { + DramcDFSDirectJump_SPMMode(p, shu_level); + } + else + { + DramcDFSDirectJump_SRAMShuRGMode(p, shu_level); + } +} + +void ShuffleDfsToFSP1(DRAMC_CTX_T *p) +{ + U8 operating_fsp = p->dram_fsp; + + // Support single rank and dual ranks + // Double confirm from CLRPLL to PHYPLL + if (operating_fsp == FSP_1) + { + cbt_dfs_mr13_global(p, CBT_HIGH_FREQ); + cbt_switch_freq(p, CBT_HIGH_FREQ); + } +} + diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c new file mode 100644 index 0000000000..b503498dd0 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c @@ -0,0 +1,1001 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//----------------------------------------------------------------------------- +// Include files +//----------------------------------------------------------------------------- +#include "dramc_common.h" +#include "dramc_int_global.h" +#include "x_hal_io.h" +//----------------------------------------------------------------------------- +// Global variables +//----------------------------------------------------------------------------- +U8 gDRSEnableSelfWakeup = 0; + +//---------------------------------------- +// Auto Gen Code -- START +//---------------------------------------- +#if (CHECK_GOLDEN_SETTING == TRUE) +typedef struct _GOLDEN_FIELD_T +{ + char fieldName[64]; //field name + U32 group; + U32 field; + U32 u4ChaValue; +} GOLDEN_FIELD_T; +GOLDEN_FIELD_T *golden_setting_anwer; + +#if APPLY_LOWPOWER_GOLDEN_SETTINGS +// DCM On +GOLDEN_FIELD_T shuf_golden_setting_anwer[] = +{ + {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0}, + {"MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN", DDRPHY_REG_MISC_SHU_RX_CG_CTRL, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 0x0}, + {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 0x0}, + {"MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL", DDRPHY_REG_MISC_SHU_CG_CTRL0, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 0x33403000}, + {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0}, + {"SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1}, + {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0}, + {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 0x0}, + {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0}, + {"SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 0x0}, + {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0}, + {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0}, + {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0}, + {"SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 0x0}, + {"SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0}, + {"SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0}, + {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0}, + {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0}, + {"SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 0x0}, + {"SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0}, + {"MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG", DDRPHY_REG_MISC_SHU_ODTCTRL, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0}, + {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0}, + {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 0x0}, + {"SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0}, + {"SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1}, + {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0}, + {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0}, + {"SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 0x0}, + {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 0x0}, + {"SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1}, + {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0}, + {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0}, + {"SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0}, + {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0}, + {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0}, + {"SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA", DDRPHY_REG_SHU_CA_CMD13, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0}, + {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0}, + {"SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0}, + {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0}, + {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0}, + {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0}, + {"SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT", DRAMC_REG_SHU_APHY_TX_PICG_CTRL, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1}, + {"MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN", DDRPHY_REG_MISC_SHU_RX_CG_CTRL, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 0x1}, + {"SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0}, + {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0}, + {"SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1}, + {"MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN", DDRPHY_REG_MISC_SHU_RX_CG_CTRL, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 0x1}, +}; + +GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] = +{ + {"SCSMCTRL_CG_SCARB_SM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCARB_SM_CGAR, 0x0}, + {"MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x1}, + {"MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x0}, + {"MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0}, + {"DUMMY_RD_DUMMY_RD_PA_OPT", DRAMC_REG_DUMMY_RD, DUMMY_RD_DUMMY_RD_PA_OPT, 0x1}, + {"DVFS_CTRL0_DVFS_CG_OPT", DRAMC_REG_DVFS_CTRL0, DVFS_CTRL0_DVFS_CG_OPT, 0x0}, + {"MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0}, + {"MISC_CTRL3_ARPI_CG_MCTL_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_DQSIEN", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x1}, + {"MISC_CG_CTRL2_RG_MEM_DCM_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0}, + {"MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x0}, + {"RX_CG_SET0_RDATCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDATCKAR, 0x0}, + {"MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0}, + {"MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x0}, + {"MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0}, + {"MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x0}, + {"MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x0}, + {"RX_CG_SET0_RDYCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDYCKAR, 0x0}, + {"DDRCOMMON0_DISSTOP26M", DRAMC_REG_DDRCOMMON0, DDRCOMMON0_DISSTOP26M, 0x0}, + {"MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS", DRAMC_REG_MISCTL0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x0}, + {"DCM_CTRL0_BCLKAR", DRAMC_REG_DCM_CTRL0, DCM_CTRL0_BCLKAR, 0x0}, + {"DRAMC_PD_CTRL_DCMEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN, 0x1}, + {"MISC_CG_CTRL5_R_CA_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x1}, + {"CLKAR_REQQUECLKRUN", DRAMC_REG_CLKAR, CLKAR_REQQUECLKRUN, 0x0}, + {"CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT", DDRPHY_REG_CA_DLL_ARPI1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0}, + {"DRAMC_PD_CTRL_DCMENNOTRFC", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMENNOTRFC, 0x1}, + {"MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN", DDRPHY_REG_MISC_DUTYSCAN1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x0}, + {"TX_TRACKING_SET0_HMRRSEL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_HMRRSEL_CGAR, 0x0}, + {"ACTIMING_CTRL_SEQCLKRUN", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN, 0x0}, + {"MISC_CTRL3_ARPI_CG_CLK_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0}, + {"CMD_DEC_CTRL0_SELPH_CMD_CG_DIS", DRAMC_REG_CMD_DEC_CTRL0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_DQS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQS, 0x1}, + {"TX_TRACKING_SET0_RDDQSOSC_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_CMD", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CMD, 0x1}, + {"DRAMC_PD_CTRL_PHYCLKDYNGEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x1}, + {"MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x1}, + {"MISC_CTRL3_ARPI_CG_MCK_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1}, + {"MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0}, + {"DRAMC_PD_CTRL_COMBPHY_CLKENSAME", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x0}, + {"MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0}, + {"MISC_CTRL3_ARPI_CG_CMD_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_DQ", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQ, 0x1}, + {"MISC_CTRL3_ARPI_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0}, + {"MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x0}, + {"DRAMC_PD_CTRL_COMBCLKCTRL", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBCLKCTRL, 0x1}, + {"MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x1}, + {"MISC_CG_CTRL5_R_CA_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x1}, + {"MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x0}, + {"MISC_CTRL3_ARPI_CG_DQS_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0}, + {"TX_CG_SET0_TX_ATK_CLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_TX_ATK_CLKRUN, 0x0}, + {"ZQ_SET0_ZQCS_MASK_SEL_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x0}, + {"DRAMC_PD_CTRL_APHYCKCG_FIXOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x0}, + {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_CS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CS, 0x1}, + {"MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0}, + {"MISC_CTRL3_R_DDRPHY_COMB_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x0}, + {"MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0}, + {"DRAMC_PD_CTRL_DCMEN2", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN2, 0x1}, + {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1}, + {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0}, + {"MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5}, + {"SCSMCTRL_CG_SCSM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCSM_CGAR, 0x0}, + {"DRAMC_PD_CTRL_MIOCKCTRLOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_CLK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CLK, 0x1}, + {"MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x0}, + {"TX_CG_SET0_SELPH_4LCG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_4LCG_DIS, 0x0}, + {"ACTIMING_CTRL_SEQCLKRUN3", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN3, 0x1}, + {"ACTIMING_CTRL_SEQCLKRUN2", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN2, 0x0}, + {"MISC_CG_CTRL5_R_DQ0_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x1}, + {"MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN", DDRPHY_REG_MISC_RX_AUTOK_CFG0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x0}, + {"MISC_CTRL3_ARPI_CG_MCK_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0}, + {"MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0}, + {"MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x0}, + {"TX_CG_SET0_DWCLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_DWCLKRUN, 0x0}, + {"MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1}, + {"SREF_DPD_CTRL_SREF_CG_OPT", DRAMC_REG_SREF_DPD_CTRL, SREF_DPD_CTRL_SREF_CG_OPT, 0x0}, + {"TX_TRACKING_SET0_TXUIPI_CAL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x0}, + {"MISC_CTRL4_R_OPT2_MPDIV_CG", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_MPDIV_CG, 0x1}, + {"TX_CG_SET0_WDATA_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_WDATA_CG_DIS, 0x0}, + {"MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_MCK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_MCK, 0x1}, + {"MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3}, + {"MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17}, + {"TX_CG_SET0_SELPH_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_CG_DIS, 0x0}, + {"DRAMC_PD_CTRL_PHYGLUECLKRUN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x0}, + {"MISC_CG_CTRL5_R_DQ1_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x1}, + {"CLKAR_REQQUE_PACG_DIS", DRAMC_REG_CLKAR, CLKAR_REQQUE_PACG_DIS, 0x0}, + {"ZQ_SET0_ZQMASK_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQMASK_CGAR, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_DQM", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQM, 0x1}, +}; + +#else +// DCM Off +GOLDEN_FIELD_T shuf_golden_setting_anwer[] = +{ + {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x1}, + {"MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN", DDRPHY_REG_MISC_SHU_RX_CG_CTRL, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 0x0}, + {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 0x1}, + {"MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL", DDRPHY_REG_MISC_SHU_CG_CTRL0, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 0x33403000}, + {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0}, + {"SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1}, + {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x1}, + {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 0x1}, + {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x1}, + {"SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 0x1}, + {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0}, + {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0}, + {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x1}, + {"SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 0x1}, + {"SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x1}, + {"SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x1}, + {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x1}, + {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x1}, + {"SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 0x1}, + {"SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x1}, + {"MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG", DDRPHY_REG_MISC_SHU_ODTCTRL, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x1}, + {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x1}, + {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 0x1}, + {"SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x1}, + {"SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1}, + {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x1}, + {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x1}, + {"SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 0x1}, + {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 0x1}, + {"SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1}, + {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0}, + {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0}, + {"SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x1}, + {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x1}, + {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x1}, + {"SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA", DDRPHY_REG_SHU_CA_CMD13, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0}, + {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x1}, + {"SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x1}, + {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x1}, + {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0}, + {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0}, + {"SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT", DRAMC_REG_SHU_APHY_TX_PICG_CTRL, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x0}, + {"MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN", DDRPHY_REG_MISC_SHU_RX_CG_CTRL, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 0x1}, + {"SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x1}, + {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0}, + {"SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1}, + {"MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN", DDRPHY_REG_MISC_SHU_RX_CG_CTRL, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 0x1}, +}; + +GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] = +{ + {"SCSMCTRL_CG_SCARB_SM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCARB_SM_CGAR, 0x1}, + {"MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x0}, + {"MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x1}, + {"MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0}, + {"DUMMY_RD_DUMMY_RD_PA_OPT", DRAMC_REG_DUMMY_RD, DUMMY_RD_DUMMY_RD_PA_OPT, 0x1}, + {"DVFS_CTRL0_DVFS_CG_OPT", DRAMC_REG_DVFS_CTRL0, DVFS_CTRL0_DVFS_CG_OPT, 0x1}, + {"MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0}, + {"MISC_CTRL3_ARPI_CG_MCTL_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_DQSIEN", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0}, + {"MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x1}, + {"RX_CG_SET0_RDATCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDATCKAR, 0x1}, + {"MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0}, + {"MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x1}, + {"MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0}, + {"MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x1}, + {"MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x1}, + {"RX_CG_SET0_RDYCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDYCKAR, 0x1}, + {"DDRCOMMON0_DISSTOP26M", DRAMC_REG_DDRCOMMON0, DDRCOMMON0_DISSTOP26M, 0x1}, + {"MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS", DRAMC_REG_MISCTL0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x1}, + {"DCM_CTRL0_BCLKAR", DRAMC_REG_DCM_CTRL0, DCM_CTRL0_BCLKAR, 0x1}, + {"DRAMC_PD_CTRL_DCMEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN, 0x0}, + {"MISC_CG_CTRL5_R_CA_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x0}, + {"CLKAR_REQQUECLKRUN", DRAMC_REG_CLKAR, CLKAR_REQQUECLKRUN, 0x1}, + {"CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT", DDRPHY_REG_CA_DLL_ARPI1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0}, + {"DRAMC_PD_CTRL_DCMENNOTRFC", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMENNOTRFC, 0x0}, + {"MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN", DDRPHY_REG_MISC_DUTYSCAN1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x1}, + {"TX_TRACKING_SET0_HMRRSEL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_HMRRSEL_CGAR, 0x1}, + {"ACTIMING_CTRL_SEQCLKRUN", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN, 0x1}, + {"MISC_CTRL3_ARPI_CG_CLK_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0}, + {"CMD_DEC_CTRL0_SELPH_CMD_CG_DIS", DRAMC_REG_CMD_DEC_CTRL0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x1}, + {"MISC_CTRL4_R_OPT2_CG_DQS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQS, 0x0}, + {"TX_TRACKING_SET0_RDDQSOSC_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x1}, + {"MISC_CTRL4_R_OPT2_CG_CMD", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CMD, 0x0}, + {"DRAMC_PD_CTRL_PHYCLKDYNGEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x0}, + {"MISC_CTRL3_ARPI_CG_MCK_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1}, + {"MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0}, + {"DRAMC_PD_CTRL_COMBPHY_CLKENSAME", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x1}, + {"MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0}, + {"MISC_CTRL3_ARPI_CG_CMD_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_DQ", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQ, 0x0}, + {"MISC_CTRL3_ARPI_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0}, + {"MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x1}, + {"DRAMC_PD_CTRL_COMBCLKCTRL", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBCLKCTRL, 0x0}, + {"MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x0}, + {"MISC_CG_CTRL5_R_CA_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x0}, + {"MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x1}, + {"MISC_CTRL3_ARPI_CG_DQS_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0}, + {"TX_CG_SET0_TX_ATK_CLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_TX_ATK_CLKRUN, 0x1}, + {"ZQ_SET0_ZQCS_MASK_SEL_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x1}, + {"DRAMC_PD_CTRL_APHYCKCG_FIXOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x1}, + {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0}, + {"MISC_CTRL4_R_OPT2_CG_CS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CS, 0x0}, + {"MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0}, + {"MISC_CTRL3_R_DDRPHY_COMB_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x1}, + {"MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0}, + {"DRAMC_PD_CTRL_DCMEN2", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN2, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1}, + {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0}, + {"MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x1}, + {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5}, + {"SCSMCTRL_CG_SCSM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCSM_CGAR, 0x1}, + {"DRAMC_PD_CTRL_MIOCKCTRLOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x1}, + {"MISC_CTRL4_R_OPT2_CG_CLK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CLK, 0x0}, + {"MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x1}, + {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x1}, + {"TX_CG_SET0_SELPH_4LCG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_4LCG_DIS, 0x1}, + {"ACTIMING_CTRL_SEQCLKRUN3", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN3, 0x1}, + {"ACTIMING_CTRL_SEQCLKRUN2", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN2, 0x1}, + {"MISC_CG_CTRL5_R_DQ0_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x0}, + {"MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN", DDRPHY_REG_MISC_RX_AUTOK_CFG0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x1}, + {"MISC_CTRL3_ARPI_CG_MCK_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0}, + {"MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0}, + {"MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x1}, + {"TX_CG_SET0_DWCLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_DWCLKRUN, 0x1}, + {"MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1}, + {"SREF_DPD_CTRL_SREF_CG_OPT", DRAMC_REG_SREF_DPD_CTRL, SREF_DPD_CTRL_SREF_CG_OPT, 0x1}, + {"TX_TRACKING_SET0_TXUIPI_CAL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x1}, + {"MISC_CTRL4_R_OPT2_MPDIV_CG", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_MPDIV_CG, 0x0}, + {"TX_CG_SET0_WDATA_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_WDATA_CG_DIS, 0x1}, + {"MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x1}, + {"MISC_CTRL4_R_OPT2_CG_MCK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_MCK, 0x0}, + {"MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3}, + {"MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17}, + {"TX_CG_SET0_SELPH_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_CG_DIS, 0x1}, + {"DRAMC_PD_CTRL_PHYGLUECLKRUN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x1}, + {"MISC_CG_CTRL5_R_DQ1_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x0}, + {"CLKAR_REQQUE_PACG_DIS", DRAMC_REG_CLKAR, CLKAR_REQQUE_PACG_DIS, 0x7fff}, + {"ZQ_SET0_ZQMASK_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQMASK_CGAR, 0x1}, + {"MISC_CTRL4_R_OPT2_CG_DQM", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQM, 0x0}, +}; + +#endif +#endif + +static void EnableCommonDCMNonShuffle(DRAMC_CTX_T *p) +{ + vIO32WriteFldAlign_All(DRAMC_REG_ACTIMING_CTRL, 0x1, ACTIMING_CTRL_SEQCLKRUN3); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2, + P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE) | + P_Fld(0x17, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL) | + P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FSEL) | + P_Fld(0x0, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27) | + P_Fld(0x3, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL) | + P_Fld(0x0, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30) | + P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF) | + P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN) | + P_Fld(0x0, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG) | + P_Fld(0x5, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT)); + // RG group needs to be toggled!! + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); + vIO32WriteFldAlign_All(DDRPHY_REG_CA_DLL_ARPI1, 0x0, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT); + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DUMMY_RD_PA_OPT); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3, + P_Fld(0x0, MISC_CTRL3_ARPI_CG_DQS_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_CG_DQ_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_CG_CMD_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_CG_CLK_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT) | + P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCK_CA_OPT)); +return; +} + +static void EnableCommonDCMShuffle(DRAMC_CTX_T *p, U32 u4DramcShuOffset, U32 u4DDRPhyShuOffset) +{ + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13 + u4DDRPhyShuOffset, 0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL + u4DDRPhyShuOffset, + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN) | + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8 + u4DDRPhyShuOffset, + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_CG_CTRL0 + u4DDRPhyShuOffset, 0x33403000, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8 + u4DDRPhyShuOffset, + P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ7 + u4DDRPhyShuOffset, + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | + P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD7 + u4DDRPhyShuOffset, + P_Fld(0x0, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | + P_Fld(0x0, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW)); +#if TX_PICG_NEW_MODE + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ7 + u4DDRPhyShuOffset, + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | + P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0)); +#endif +return; +} + +void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn) +{ + // Special case + EnableCommonDCMNonShuffle(p); + + if(bEn) + { + vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, + P_Fld(0x0, TX_CG_SET0_DWCLKRUN) | + P_Fld(0x0, TX_CG_SET0_SELPH_CG_DIS) | + P_Fld(0x0, TX_CG_SET0_SELPH_4LCG_DIS) | + P_Fld(0x0, TX_CG_SET0_TX_ATK_CLKRUN) | + P_Fld(0x0, TX_CG_SET0_WDATA_CG_DIS)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5, + P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) | + P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN) | + P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) | + P_Fld(0x1, MISC_CG_CTRL5_R_CA_PI_DCM_EN) | + P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) | + P_Fld(0x1, MISC_CG_CTRL5_R_CA_DLY_DCM_EN)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2, + P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) | + P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN)); + // RG group needs to be toggled!! + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); + vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 0x0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS); + vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0x0, SREF_DPD_CTRL_SREF_CG_OPT); + vIO32WriteFldMulti_All(DRAMC_REG_RX_CG_SET0, + P_Fld(0x0, RX_CG_SET0_RDYCKAR) | + P_Fld(0x0, RX_CG_SET0_RDATCKAR)); + vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL, + P_Fld(0x0, ACTIMING_CTRL_SEQCLKRUN2) | + P_Fld(0x0, ACTIMING_CTRL_SEQCLKRUN)); + vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG, + P_Fld(0x0, SCSMCTRL_CG_SCARB_SM_CGAR) | + P_Fld(0x0, SCSMCTRL_CG_SCSM_CGAR)); + vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS); + vIO32WriteFldMulti_All(DRAMC_REG_CLKAR, + P_Fld(0x0, CLKAR_REQQUE_PACG_DIS) | + P_Fld(0x0, CLKAR_REQQUECLKRUN)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0x0, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN); + vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 0x0, DDRCOMMON0_DISSTOP26M); + vIO32WriteFldAlign_All(DRAMC_REG_DVFS_CTRL0, 0x0, DVFS_CTRL0_DVFS_CG_OPT); + vIO32WriteFldAlign_All(DRAMC_REG_DCM_CTRL0, 0x0, DCM_CTRL0_BCLKAR); + vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL, + P_Fld(0x1, DRAMC_PD_CTRL_PHYCLKDYNGEN) | + P_Fld(0x1, DRAMC_PD_CTRL_DCMEN2) | + P_Fld(0x1, DRAMC_PD_CTRL_DCMEN) | + P_Fld(0x0, DRAMC_PD_CTRL_PHYGLUECLKRUN) | + P_Fld(0x0, DRAMC_PD_CTRL_COMBPHY_CLKENSAME) | + P_Fld(0x0, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) | + P_Fld(0x0, DRAMC_PD_CTRL_MIOCKCTRLOFF) | + P_Fld(0x1, DRAMC_PD_CTRL_DCMENNOTRFC) | + P_Fld(0x1, DRAMC_PD_CTRL_COMBCLKCTRL)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3, + P_Fld(0x0, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG) | + P_Fld(0x0, MISC_CTRL3_R_DDRPHY_COMB_CG_IG)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4, +#if (RX_PICG_NEW_MODE || TX_PICG_NEW_MODE) + P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_MCK) | + P_Fld(0x1, MISC_CTRL4_R_OPT2_MPDIV_CG) | +#endif +#if RX_PICG_NEW_MODE + P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQSIEN) | +#endif +#if TX_PICG_NEW_MODE + P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQ) | + P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQS) | + P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQM) | +#endif + P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CMD) | + P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CLK) | + P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CS)); + vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0, + P_Fld(0x0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR) | + P_Fld(0x0, TX_TRACKING_SET0_RDDQSOSC_CGAR) | + P_Fld(0x0, TX_TRACKING_SET0_HMRRSEL_CGAR)); + vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, + P_Fld(0x0, ZQ_SET0_ZQCS_MASK_SEL_CGAR) | + P_Fld(0x0, ZQ_SET0_ZQMASK_CGAR)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 0x0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN); + } + else + { + vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, + P_Fld(0x1, TX_CG_SET0_DWCLKRUN) | + P_Fld(0x1, TX_CG_SET0_SELPH_CG_DIS) | + P_Fld(0x1, TX_CG_SET0_SELPH_4LCG_DIS) | + P_Fld(0x1, TX_CG_SET0_TX_ATK_CLKRUN) | + P_Fld(0x1, TX_CG_SET0_WDATA_CG_DIS)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5, + P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) | + P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2, + P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) | + P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN)); + // RG group needs to be toggled!! + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); + vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS); + vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0x1, SREF_DPD_CTRL_SREF_CG_OPT); + vIO32WriteFldMulti_All(DRAMC_REG_RX_CG_SET0, + P_Fld(0x1, RX_CG_SET0_RDYCKAR) | + P_Fld(0x1, RX_CG_SET0_RDATCKAR)); + vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL, + P_Fld(0x1, ACTIMING_CTRL_SEQCLKRUN2) | + P_Fld(0x1, ACTIMING_CTRL_SEQCLKRUN)); + vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG, + P_Fld(0x1, SCSMCTRL_CG_SCARB_SM_CGAR) | + P_Fld(0x1, SCSMCTRL_CG_SCSM_CGAR)); + vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x1, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS); + vIO32WriteFldMulti_All(DRAMC_REG_CLKAR, + P_Fld(0x7fff, CLKAR_REQQUE_PACG_DIS) | + P_Fld(0x1, CLKAR_REQQUECLKRUN)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0x1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN); + vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 0x1, DDRCOMMON0_DISSTOP26M); + vIO32WriteFldAlign_All(DRAMC_REG_DVFS_CTRL0, 0x1, DVFS_CTRL0_DVFS_CG_OPT); + vIO32WriteFldAlign_All(DRAMC_REG_DCM_CTRL0, 0x1, DCM_CTRL0_BCLKAR); + vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL, + P_Fld(0x0, DRAMC_PD_CTRL_PHYCLKDYNGEN) | + P_Fld(0x0, DRAMC_PD_CTRL_DCMEN2) | + P_Fld(0x0, DRAMC_PD_CTRL_DCMEN) | + P_Fld(0x1, DRAMC_PD_CTRL_PHYGLUECLKRUN) | + P_Fld(0x1, DRAMC_PD_CTRL_COMBPHY_CLKENSAME) | + P_Fld(0x1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) | + P_Fld(0x1, DRAMC_PD_CTRL_MIOCKCTRLOFF) | + P_Fld(0x0, DRAMC_PD_CTRL_DCMENNOTRFC) | + P_Fld(0x0, DRAMC_PD_CTRL_COMBCLKCTRL)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3, + P_Fld(0x1, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG) | + P_Fld(0x1, MISC_CTRL3_R_DDRPHY_COMB_CG_IG)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4, + P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQSIEN) | + P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CLK) | + P_Fld(0x0, MISC_CTRL4_R_OPT2_MPDIV_CG) | + P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQM) | + P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CMD) | + P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQS) | + P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_MCK) | + P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CS) | + P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQ)); + vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0, + P_Fld(0x1, TX_TRACKING_SET0_TXUIPI_CAL_CGAR) | + P_Fld(0x1, TX_TRACKING_SET0_RDDQSOSC_CGAR) | + P_Fld(0x1, TX_TRACKING_SET0_HMRRSEL_CGAR)); + vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, + P_Fld(0x1, ZQ_SET0_ZQCS_MASK_SEL_CGAR) | + P_Fld(0x1, ZQ_SET0_ZQMASK_CGAR)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 0x1, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN); + } + return; +} + +void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn, U32 u4DramcShuOffset, U32 u4DDRPhyShuOffset) +{ + // Special case + // DRAMC_REG_SHU_RX_CG_SET0 + u4DramcShuOffset - SHU_RX_CG_SET0_READ_START_EXTEND3: Special case + // DRAMC_REG_SHU_RX_CG_SET0 + u4DramcShuOffset - SHU_RX_CG_SET0_READ_START_EXTEND2: Special case + // DRAMC_REG_SHU_RX_CG_SET0 + u4DramcShuOffset - SHU_RX_CG_SET0_READ_START_EXTEND1: Special case + // DRAMC_REG_SHU_RX_CG_SET0 + u4DramcShuOffset - SHU_RX_CG_SET0_DLE_LAST_EXTEND1: Special case + // DRAMC_REG_SHU_RX_CG_SET0 + u4DramcShuOffset - SHU_RX_CG_SET0_DLE_LAST_EXTEND2: Special case + // DRAMC_REG_SHU_RX_CG_SET0 + u4DramcShuOffset - SHU_RX_CG_SET0_DLE_LAST_EXTEND3: Special case + EnableCommonDCMShuffle(p, u4DramcShuOffset, u4DDRPhyShuOffset); + + if(bEn) + { + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8 + u4DDRPhyShuOffset, + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) | + P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8 + u4DDRPhyShuOffset, + P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) | + P_Fld(0x0, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) | + P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) | + P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) | + P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) | + P_Fld(0x0, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) | + P_Fld(0x0, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA) | + P_Fld(0x0, SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA)); +#if TX_PICG_NEW_MODE + vIO32WriteFldAlign_All(DRAMC_REG_SHU_APHY_TX_PICG_CTRL + u4DramcShuOffset, 0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT); +#endif + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8 + u4DDRPhyShuOffset, + P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) | + P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL + u4DDRPhyShuOffset, 0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG); + } + else + { + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8 + u4DDRPhyShuOffset, + P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) | + P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8 + u4DDRPhyShuOffset, + P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) | + P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) | + P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) | + P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) | + P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) | + P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) | + P_Fld(0x1, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA) | + P_Fld(0x1, SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA)); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_APHY_TX_PICG_CTRL + u4DramcShuOffset, 0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8 + u4DDRPhyShuOffset, + P_Fld(0x1, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) | + P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL + u4DDRPhyShuOffset, 0x1, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG); + } + return; +} + +//---------------------------------------- +// Auto Gen Code -- END +//---------------------------------------- + +void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn) +{ + U32 u4WbrBackup = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + EnableDramcPhyDCMNonShuffle(p, bEn); + EnableDramcPhyDCMShuffle(p, bEn, 0, 0);//only need to set SHU0 RG while init, SHU0 will copy to others + +#if ((CHECK_GOLDEN_SETTING == TRUE) && (APPLY_LOWPOWER_GOLDEN_SETTINGS == 0)) + DRAM_STATUS_T stResult = CheckGoldenSetting(p); + mcSHOW_DBG_MSG(("Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG"))); +#endif + + DramcBroadcastOnOff(u4WbrBackup); + return; +} + + +#if RX_PICG_NEW_MODE +#if 0 +DRAM_STATUS_T CheckRxPICGNewModeSetting(DRAMC_CTX_T *p) +{ + U8 channel_idx; + U8 u1RankIdx; + U32 u4Value; + + + for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) + { + p->channel = channel_idx; + mcSHOW_DBG_MSG(("CH[%d] \n", channel_idx)); + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_MCK); + mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_MCK:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_MPDIV_CG); + mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_MPDIV_CG:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_DQSIEN); + mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_DQSIEN:0x%x \n", u4Value)); + + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), MISC_STBCAL1_STBCNT_SHU_RST_EN); + mcSHOW_DBG_MSG(("MISC_STBCAL1_STBCNT_SHU_RST_EN:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); + mcSHOW_DBG_MSG(("MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), MISC_SHU_STBCAL_DQSIEN_PICG_MODE); + mcSHOW_DBG_MSG(("MISC_SHU_STBCAL_DQSIEN_PICG_MODE:0x%x \n", u4Value)); + + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT); + mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT); + mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN); + mcSHOW_DBG_MSG(("MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN:0x%x \n", u4Value)); + + for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)//Should set 2 rank + { + + vSetRank(p, u1RankIdx); + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT); + mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT:0x%x \n", u1RankIdx, u4Value)); + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT); + mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT:0x%x \n", u1RankIdx, u4Value)); + } + vSetRank(p, RANK_0); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN); + mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN); + mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN); + mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN:0x%x \n", u4Value)); + + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN); + mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN); + mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN:0x%x \n", u4Value)); + + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN); + mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN:0x%x \n", u4Value)); + + } + p->channel = CHANNEL_A; +} +#endif +#endif + +#if (CHECK_GOLDEN_SETTING == TRUE) +DRAM_STATUS_T CheckGoldenField(DRAMC_CTX_T *p, GOLDEN_FIELD_T *golden_setting_anwer, U16 array_size) +{ + DRAM_STATUS_T eStatus = DRAM_OK; + U8 channel_idx; + U32 u4Value = 0; + U32 u4Answer = 0; + U16 array_cnt = array_size / sizeof(golden_setting_anwer[0]); + + U16 u2Idx = 0; + for(u2Idx = 0; u2Idx < array_cnt; u2Idx++) + { + for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)//comapre CHA && CHB + { + vSetPHY2ChannelMapping(p, channel_idx); + u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(golden_setting_anwer[u2Idx].group), golden_setting_anwer[u2Idx].field); + //mcSHOW_DBG_MSG(("%s: 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Value)); + + u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue);//golden_setting_anwer only has CHA value + + if(u4Answer != 0xffffffff)//0xffffffff: no need to compare + { + if(u4Answer == u4Value) + { + //mcSHOW_DBG_MSG(("OK [%s] 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Answer)); + } + else + { + mcSHOW_DBG_MSG(("*** fail ***[%s]CH[%d][0x%x][ANS:0x%x]****** fail\n", golden_setting_anwer[u2Idx].fieldName, channel_idx, u4Value, u4Answer)); + eStatus |= DRAM_FAIL; + } + } + } + } + return eStatus; +} + +DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p) +{ + U8 u1BkShuffleIdx = p->pDFSTable->shuffleIdx; + U8 u1SramShuffleIdx = 0; + U8 u1ShuffleIdx = 0; + U8 backup_channel = vGetPHY2ChannelMapping(p); + DRAM_STATUS_T eStatus = DRAM_OK; + + mcSHOW_DBG_MSG(("Golden setting check[Begin]\n")); + eStatus |= CheckGoldenField(p, nonshuf_golden_setting_anwer, sizeof(nonshuf_golden_setting_anwer)); + + + if(gAndroid_DVFS_en) + { + for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) + { + if (u1ShuffleIdx < DRAM_DFS_SRAM_MAX) + { + mcSHOW_DBG_MSG(("SRAM SHU%d\n", u1ShuffleIdx)); + u1SramShuffleIdx = u1ShuffleIdx; + } + else + { + mcSHOW_DBG_MSG(("CONF SHU0, DDR[%d]\n", p->frequency * 2)); + u1SramShuffleIdx = u1BkShuffleIdx; //Restore to original freq && check conf SHU0 + } + + //mcSHOW_DBG_MSG(("shuf_golden_setting_anwer:%d %d\n", sizeof(shuf_golden_setting_anwer), sizeof(shuf_golden_setting_anwer[0]))); + DramcDFSDirectJump(p, u1SramShuffleIdx); //fill conf SHU0 && SHU1 from SRAM SHU(0~9) while DVFS twice + DramcDFSDirectJump(p, u1SramShuffleIdx); + + eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer)); + } + } + else + { + mcSHOW_DBG_MSG(("CONF SHU0, DDR[%d]\n", p->frequency * 2)); + eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer)); + } + + mcSHOW_DBG_MSG(("Golden setting check[End]\n")); + + vSetPHY2ChannelMapping(p, backup_channel); + return eStatus; +} +#endif + +#ifdef CLK_FREE_FUN_FOR_DRAMC_PSEL +//If dramc enter SREF and power down, all configure need to sync 2T again after exit SREF. +//If Psel is 1, clock will be free run at the periof of 2T to let conf be applied. +//If Psel is 0, Clock will be gated +void ClkFreeRunForDramcPsel(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, P_Fld(0, TX_CG_SET0_PSEL_OPT1) + | P_Fld(0, TX_CG_SET0_PSEL_OPT2) + | P_Fld(0, TX_CG_SET0_PSEL_OPT3) + | P_Fld(0, TX_CG_SET0_PSELAR)); +} +#endif + +#if PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER +void DramcPAImprove(DRAMC_CTX_T *p) +{ + //U8 u1ShuIdx = 0, u1ShuCnt = 3; //TODO: change u1ShuCnt to actual shuffle num define + //U32 u4targetAddr = 0; //For SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, SHU_ODTCTRL_RODTEN_SELPH_CG_IG shuffle regs + vIO32WriteFldAlign_All(DRAMC_REG_CLKAR, 0x0, CLKAR_REQQUE_PACG_DIS); + vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS); + + /* Dummy_RD_PA_OPT should be set to 1, or else some functions would fail (YH Tsai) + * Already set to 1 in in UpdateInitialSettings(), so comment out set to 0 here + */ + //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), 0, DUMMY_RD_DUMMY_RD_PA_OPT); + vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG, P_Fld(0, SCSMCTRL_CG_SCSM_CGAR) + | P_Fld(0, SCSMCTRL_CG_SCARB_SM_CGAR)); + vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0, P_Fld(0, TX_TRACKING_SET0_RDDQSOSC_CGAR) + | P_Fld(0, TX_TRACKING_SET0_HMRRSEL_CGAR) + | P_Fld(0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR)); + + //Below loop sets SHU*_ODTCTRL_RODTENSTB_SELPH_CG_IG, SHU*_ODTCTRL_RODTEN_SELPH_CG_IG (wei-jen) + //for (u1ShuIdx = DRAM_DFS_SHUFFLE_1; u1ShuIdx < u1ShuCnt; u1ShuIdx++) + //{ + // u4targetAddr = DRAMC_REG_SHU_ODTCTRL + SHU_GRP_DRAMC_OFFSET * u1ShuIdx; + // vIO32WriteFldMulti_All(u4targetAddr, P_Fld(0x0, SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) + // | P_Fld(0x0, SHU_ODTCTRL_RODTEN_SELPH_CG_IG)); + //} +} +#endif + +#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION + +void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff) +{ + +} +#endif +#if 0 //Comment out unused code +void DramcDRS(DRAMC_CTX_T *p, U8 bEnable) +{ + //R_DMDRS_CNTX[6:0](DVT set 0, HQA set 4 or 5) + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DRSCTRL), P_Fld(0, DRSCTRL_DRSPB2AB_OPT) + | P_Fld(0, DRSCTRL_DRSMON_CLR) + | P_Fld(8, DRSCTRL_DRSDLY) + | P_Fld(0, DRSCTRL_DRSACKWAITREF) + | P_Fld(!bEnable, DRSCTRL_DRSDIS) + | P_Fld(1, DRSCTRL_DRSCLR_EN) + | P_Fld(3, DRSCTRL_DRS_CNTX) + | P_Fld(!gDRSEnableSelfWakeup, DRSCTRL_DRS_SELFWAKE_DMYRD_DIS) + | P_Fld(0, DRSCTRL_DRSOPT2)); +} +#endif + +#if 0 //Comment out unused code +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) +void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op) +{ + U8 ucstatus = 0; + U32 uiTemp; + U32 u4TimeCnt; + + u4TimeCnt = TIME_OUT_CNT; + + mcSHOW_DBG_MSG(("[EnterSelfRefresh] %s\n", ((op == 1) ? "enter" : "exit"))); + + if (op == 1) // enter self refresh + { + // ONLY work for LP4, not LP3 + // MISCA_SRFPD_DIS =1, self-refresh + // MISCA_SRFPD_DIS =0, self-refresh power down + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SRFPD_DIS); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SELFREF); + mcDELAY_US(2); + uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE); + while ((uiTemp == 0) && (u4TimeCnt > 0)) + { + mcSHOW_DBG_MSG2(("Still not enter self refresh(%d)\n", u4TimeCnt)); + mcDELAY_US(1); + uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE); + u4TimeCnt --; + } + } + else // exit self refresh + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 0, SREFCTRL_SELFREF); + + mcDELAY_US(2); + uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE); + while ((uiTemp != 0) && (u4TimeCnt > 0)) + { + mcSHOW_DBG_MSG2(("Still not exit self refresh(%d)\n", u4TimeCnt)); + mcDELAY_US(1); + uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE); + u4TimeCnt--; + } + } + + if (u4TimeCnt == 0) + { + mcSHOW_DBG_MSG(("Self refresh fail\n")); + } + else + { + mcSHOW_DBG_MSG(("Self refresh done\n")); + } +} +#endif +#endif //Comment out unused code + +#if ENABLE_RX_DCM_DPHY +void EnableRxDcmDPhy(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq) +{ + U8 u1PRECAL_CG_EN = 0; + + if (u2Freq <= 400) + u1PRECAL_CG_EN = 1; + else + u1PRECAL_CG_EN = 0; + + //power gain + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL + u4DDRPhyShuOffset, + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT) | + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) | + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT) | + P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN) | + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN) | // if Rx gating Auto K, set 0, Runtime set 1 +#if RDSEL_TRACKING_EN + P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN) | // if K, set 1, at runtime if enable, set 0, else 1 +#else + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN) | +#endif + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN) | + P_Fld(u1PRECAL_CG_EN, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN) | + P_Fld(0x2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) | + P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY)); + +} +#endif + diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c new file mode 100644 index 0000000000..34f3f57d68 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c @@ -0,0 +1,3687 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//----------------------------------------------------------------------------- +// Include files +//----------------------------------------------------------------------------- +//#include "..\Common\pd_common.h" +//#include "Register.h" +#include "dramc_common.h" +#include "dramc_dv_init.h" +#include "dramc_int_global.h" +#include "x_hal_io.h" +#include "dramc_actiming.h" + +#include "dramc_reg_base_addr.h" + +#include "dramc_top.h" + +//#include "DramC_reg.h" +//#include "System_reg.h" +//#include "string.h" + +//----------------------------------------------------------------------------- +// Global variables +//----------------------------------------------------------------------------- +U8 u1PrintModeRegWrite = 0; + +#if ENABLE_RODT_TRACKING_SAVE_MCK +// global variables for RODT tracking & ROEN +U8 u1ODT_ON; // infor of p->odt_onoff +U8 u1WDQS_ON = 0; // infor of WDQS on(ROEN=1) +U8 u1RODT_TRACK = 0; // infor of rodt tracking enable +U8 u1ROEN, u1ModeSel;//status of ROEN, MODESEL setting +#endif + +//MRR DRAM->DRAMC +const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = +{ + { + // for DSC + //CH-A + { + 0, 1, 7, 6, 4, 5, 2, 3, + 9, 8, 11, 10, 14, 15, 13, 12 + }, + #if (CHANNEL_NUM>1) + //CH-B + { + 1, 0, 5, 6, 3, 2, 7, 4, + 8, 9, 11, 10, 12, 14, 13, 15 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 0, 1, 7, 6, 4, 5, 2, 3, + 9, 8, 11, 10, 14, 15, 13, 12 + }, + //CH-D + { + 1, 0, 5, 6, 3, 2, 7, 4, + 8, 9, 11, 10, 12, 14, 13, 15 + }, + #endif + + }, + { + // for LPBK + // TODO: need porting + }, + { + // for EMCP + //CH-A + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 14, 11, 15, 13, 12 + }, + #if (CHANNEL_NUM>1) + //CH-B + { + 0, 1, 4, 7, 3, 5, 6, 2, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 14, 11, 15, 13, 12 + }, + //CH-D + { + 0, 1, 4, 7, 3, 5, 6, 2, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif + }, +}; + +#if (__LP5_COMBO__) +const U8 uiLPDDR5_MRR_Mapping_POP[CHANNEL_NUM][16] = +{ + { + 8, 9, 10, 11, 12, 15, 14, 13, + 0, 1, 2, 3, 4, 7, 6, 5, + }, + + #if (CHANNEL_NUM>1) + { + 8, 9, 10, 11, 12, 15, 14, 13, + 0, 1, 2, 3, 4, 7, 6, 5, + }, + #endif +}; +#endif + +//MRR DRAM->DRAMC +U8 uiLPDDR4_MRR_Mapping_POP[CHANNEL_NUM][16] = +{ + //CH-A + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 14, 11, 15, 13, 12 + }, + #if (CHANNEL_NUM>1) + //CH-B + { + 0, 1, 4, 7, 3, 5, 6, 2, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 14, 11, 15, 13, 12 + }, + //CH-D + { + 0, 1, 4, 7, 3, 5, 6, 2, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif +}; + +#if (fcFOR_CHIP_ID == fcMargaux) +static void Set_DRAM_Pinmux_Sel(DRAMC_CTX_T *p) +{ + #if (__LP5_COMBO__) + if (is_lp5_family(p)) + return; + #endif + +#if !FOR_DV_SIMULATION_USED + if (is_discrete_lpddr4()) + p->DRAMPinmux = PINMUX_DSC; + else +#endif + p->DRAMPinmux = PINMUX_EMCP; + + mcSHOW_DBG_MSG(("[Set_DRAM_Pinmux_Sel] DRAMPinmux = %d\n", p->DRAMPinmux)); + + memcpy(&uiLPDDR4_MRR_Mapping_POP, uiLPDDR4_MRR_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_MRR_Mapping_POP)); + memcpy(&uiLPDDR4_O1_Mapping_POP, uiLPDDR4_O1_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_O1_Mapping_POP)); + memcpy(&uiLPDDR4_CA_Mapping_POP, uiLPDDR4_CA_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_CA_Mapping_POP)); +} +#endif + +void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p) +{ + U8 *uiLPDDR_MRR_Mapping = NULL; + U8 backup_channel; + U32 backup_broadcast; + DRAM_CHANNEL_T chIdx = CHANNEL_A; + + //Backup channel & broadcast + backup_channel = vGetPHY2ChannelMapping(p); + backup_broadcast = GetDramcBroadcast(); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); //Disable broadcast + + //LP4: Set each channel's pinmux individually, LP3: Only has 1 channel (support_channel_num == 1) + for (chIdx = CHANNEL_A; chIdx < (int)p->support_channel_num; chIdx++) + { + vSetPHY2ChannelMapping(p, chIdx); + + #if (__LP5_COMBO__) + if (is_lp5_family(p)) + uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR5_MRR_Mapping_POP[chIdx]; + else + #endif + uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR4_MRR_Mapping_POP[chIdx]; + + //Set MRR pin mux + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1), P_Fld(uiLPDDR_MRR_Mapping[0], MRR_BIT_MUX1_MRR_BIT0_SEL) | P_Fld(uiLPDDR_MRR_Mapping[1], MRR_BIT_MUX1_MRR_BIT1_SEL) | + P_Fld(uiLPDDR_MRR_Mapping[2], MRR_BIT_MUX1_MRR_BIT2_SEL) | P_Fld(uiLPDDR_MRR_Mapping[3], MRR_BIT_MUX1_MRR_BIT3_SEL)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2), P_Fld(uiLPDDR_MRR_Mapping[4], MRR_BIT_MUX2_MRR_BIT4_SEL) | P_Fld(uiLPDDR_MRR_Mapping[5], MRR_BIT_MUX2_MRR_BIT5_SEL) | + P_Fld(uiLPDDR_MRR_Mapping[6], MRR_BIT_MUX2_MRR_BIT6_SEL) | P_Fld(uiLPDDR_MRR_Mapping[7], MRR_BIT_MUX2_MRR_BIT7_SEL)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3), P_Fld(uiLPDDR_MRR_Mapping[8], MRR_BIT_MUX3_MRR_BIT8_SEL) | P_Fld(uiLPDDR_MRR_Mapping[9], MRR_BIT_MUX3_MRR_BIT9_SEL) | + P_Fld(uiLPDDR_MRR_Mapping[10], MRR_BIT_MUX3_MRR_BIT10_SEL) | P_Fld(uiLPDDR_MRR_Mapping[11], MRR_BIT_MUX3_MRR_BIT11_SEL)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4), P_Fld(uiLPDDR_MRR_Mapping[12], MRR_BIT_MUX4_MRR_BIT12_SEL) | P_Fld(uiLPDDR_MRR_Mapping[13], MRR_BIT_MUX4_MRR_BIT13_SEL) | + P_Fld(uiLPDDR_MRR_Mapping[14], MRR_BIT_MUX4_MRR_BIT14_SEL) | P_Fld(uiLPDDR_MRR_Mapping[15], MRR_BIT_MUX4_MRR_BIT15_SEL)); + } + + //Recover channel & broadcast + vSetPHY2ChannelMapping(p, backup_channel); + DramcBroadcastOnOff(backup_broadcast); +} + + +void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p) +{ + U8 *uiLPDDR_DQO1_Mapping = NULL; + U8 backup_channel; + U32 backup_broadcast; + DRAM_CHANNEL_T chIdx = CHANNEL_A; + + //Backup channel & broadcast + backup_channel = vGetPHY2ChannelMapping(p); + backup_broadcast = GetDramcBroadcast(); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); //Disable broadcast + + //LP4: Set each channel's pinmux individually, LP3: Only has 1 channel (support_channel_num == 1) + for (chIdx = CHANNEL_A; chIdx < (int)p->support_channel_num; chIdx++) + { + vSetPHY2ChannelMapping(p, chIdx); + + #if (__LP5_COMBO__) + if (is_lp5_family(p)) + uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[chIdx]; + else + #endif + uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[chIdx]; + + //Set MRR pin mux + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0), P_Fld(uiLPDDR_DQO1_Mapping[0], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0) + | P_Fld(uiLPDDR_DQO1_Mapping[1], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1) + | P_Fld(uiLPDDR_DQO1_Mapping[2], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2) + | P_Fld(uiLPDDR_DQO1_Mapping[3], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3) + | P_Fld(uiLPDDR_DQO1_Mapping[4], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4) + | P_Fld(uiLPDDR_DQO1_Mapping[5], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5) + | P_Fld(uiLPDDR_DQO1_Mapping[6], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6) + | P_Fld(uiLPDDR_DQO1_Mapping[7], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1), P_Fld(uiLPDDR_DQO1_Mapping[8], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8) + | P_Fld(uiLPDDR_DQO1_Mapping[9], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9) + | P_Fld(uiLPDDR_DQO1_Mapping[10], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10) + | P_Fld(uiLPDDR_DQO1_Mapping[11], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11) + | P_Fld(uiLPDDR_DQO1_Mapping[12], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12) + | P_Fld(uiLPDDR_DQO1_Mapping[13], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13) + | P_Fld(uiLPDDR_DQO1_Mapping[14], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14) + | P_Fld(uiLPDDR_DQO1_Mapping[15], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15)); + } + + //Recover channel & broadcast + vSetPHY2ChannelMapping(p, backup_channel); + DramcBroadcastOnOff(backup_broadcast); +} + + +static void SetRankInfoToConf(DRAMC_CTX_T *p) +{ +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + EMI_SETTINGS *emi_set; + U32 u4value = 0; + +#if (!__ETT__)//preloader + if (emi_setting_index == -1) + emi_set = &default_emi_setting; + else + emi_set = &emi_settings[emi_setting_index]; +#else//ett + emi_set = &default_emi_setting; +#endif + + u4value = ((emi_set->EMI_CONA_VAL >> 17) & 0x1)? 0: 1;//CONA 17th bit 0: Disable dual rank mode 1: Enable dual rank mode + + vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, u4value, SA_RESERVE_SINGLE_RANK); + + mcSHOW_JV_LOG_MSG(("Rank info: %d emi_setting_index: %d CONA[0x%x]\n", u4value, emi_setting_index, emi_set->EMI_CONA_VAL)); +#endif + return; +} + +static void SetDramInfoToConf(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti_All(DRAMC_REG_SA_RESERVE, + P_Fld(p->dram_cbt_mode[RANK_0], SA_RESERVE_MODE_RK0) | + P_Fld(p->dram_cbt_mode[RANK_1], SA_RESERVE_MODE_RK1)); + + if(u2DFSGetHighestFreq(p) >= 2133) + { + vIO32WriteFldAlign_All(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SUPPORT_4266); + } +} + +void UpdateDFSTbltoDDR3200(DRAMC_CTX_T *p) +{ +#if(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) + EMI_SETTINGS *emi_set; + U16 u2HighestFreq = u2DFSGetHighestFreq(p); + DRAM_PLL_FREQ_SEL_T highestfreqsel = 0; + U8 u1ShuffleIdx = 0; + +#if (!__ETT__)//preloader + if(emi_setting_index == -1) + emi_set = &default_emi_setting; + else + emi_set = &emi_settings[emi_setting_index]; +#else//ett + emi_set = &default_emi_setting; +#endif + + // lookup table to find highest freq + highestfreqsel = GetSelByFreq(p, u2HighestFreq); + for (u1ShuffleIdx = DRAM_DFS_SHUFFLE_1; u1ShuffleIdx < DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) + if (gFreqTbl[u1ShuffleIdx].freq_sel == highestfreqsel) + break; + + gFreqTbl[u1ShuffleIdx].freq_sel = LP4_DDR3200; // for DSC DRAM + + gUpdateHighestFreq = TRUE; + u2HighestFreq = u2DFSGetHighestFreq(p); // @Darren, Update u2FreqMax variables + #if __ETT__ + UpdateEttDFVSTbltoDDR3200(p, u2HighestFreq); //@Darren, Update for DDR3200 ETT DVFS stress + #endif + mcSHOW_DBG_MSG(("[UpdateDFSTbltoDDR3200] Get Highest Freq is %d\n", u2HighestFreq)); +#endif +} + +void Global_Option_Init(DRAMC_CTX_T *p) +{ + //SaveCurrDramCtx(p); + vSetChannelNumber(p); + SetRankInfoToConf(p); + vSetRankNumber(p); + vSetFSPNumber(p); +#if (fcFOR_CHIP_ID == fcMargaux) + Set_DRAM_Pinmux_Sel(p); +#endif + Set_MRR_Pinmux_Mapping(p); + Set_DQO1_Pinmux_Mapping(p); + + vInitGlobalVariablesByCondition(p); + vInitMappingFreqArray(p); +#if ENABLE_TX_TRACKING + DramcDQSOSCInit(); +#endif + +#ifdef FOR_HQA_TEST_USED + HQA_measure_message_reset_all_data(p); +#endif +} + +#if CBT_MOVE_CA_INSTEAD_OF_CLK +void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), P_Fld(value, SHU_SELPH_CA7_DLY_RA0) | + P_Fld(value, SHU_SELPH_CA7_DLY_RA1) | + P_Fld(value, SHU_SELPH_CA7_DLY_RA2) | + P_Fld(value, SHU_SELPH_CA7_DLY_RA3) | + P_Fld(value, SHU_SELPH_CA7_DLY_RA4) | + P_Fld(value, SHU_SELPH_CA7_DLY_RA5) | + P_Fld(value, SHU_SELPH_CA7_DLY_RA6)); + + // Note: CKE UI must sync CA UI (CA and CKE delay circuit are same) @Lin-Yi + // To avoid tXP timing margin issue + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), value, SHU_SELPH_CA5_DLY_CKE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), value, SHU_SELPH_CA6_DLY_CKE1); + + ///TODO: Yirong : new calibration flow : change CS UI to 0 +// vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); +} +#endif + +void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq) +{ + U8 u1RankIdx; + U8 backup_rank; + + backup_rank = u1GetRank(p); + + for(u1RankIdx =0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + + if (freq == CBT_LOW_FREQ) + { + DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); + DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE); + } + else // CBT_HIGH_FREQ + { + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE); + } + } + + vSetRank(p, backup_rank); +} + +void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq) +{ +#if (FOR_DV_SIMULATION_USED == TRUE) // @Darren+ for DV sim + return; +#endif + +#if MR_CBT_SWITCH_FREQ +#if (fcFOR_CHIP_ID == fcMargaux) + static U8 _CurFreq = CBT_UNKNOWN_FREQ; + if (_CurFreq == freq) + { + return; // Do nothing no meter the frequency is. + } + _CurFreq = freq; + + EnableDFSHwModeClk(p); + + if (freq == CBT_LOW_FREQ) + { + DramcDFSDirectJump_RGMode(p, DRAM_DFS_SHUFFLE_2); // Darren NOTE: Dramc shu1 for MRW (DramcModeRegInit_LP4 and CBT) + } + else + { + DramcDFSDirectJump_RGMode(p, DRAM_DFS_SHUFFLE_1); + } + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) + | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN)); + + DDRPhyFreqMeter(); +#else + #error Need check of the DRAM_DFS_SHUFFLE_X for your chip !!! +#endif +#endif +} + + +void DramcPowerOnSequence(DRAMC_CTX_T *p) +{ +#ifdef DUMP_INIT_RG_LOG_TO_DE + //CKE high + CKEFixOnOff(p, CKE_WRITE_TO_ALL_RANK, CKE_FIXON, CKE_WRITE_TO_ALL_CHANNEL); + return; +#endif + + #if APPLY_LP4_POWER_INIT_SEQUENCE + //static U8 u1PowerOn=0; + //if(u1PowerOn ==0) + { + //reset dram = low + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x0, MISC_CTRL1_R_DMDA_RRESETB_I); + + //vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_CKE2RANK_OPT2); + + //CKE low + CKEFixOnOff(p, CKE_WRITE_TO_ALL_RANK, CKE_FIXOFF, CKE_WRITE_TO_ALL_CHANNEL); + + // delay tINIT1=200us(min) & tINIT2=10ns(min) + mcDELAY_US(200); + + //reset dram = low + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x1, MISC_CTRL1_R_DMDA_RRESETB_I); + + // Disable HW MIOCK control to make CLK always on + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON); + + //tINIT3=2ms(min) + mcDELAY_MS(2); + + //CKE high + CKEFixOnOff(p, CKE_WRITE_TO_ALL_RANK, CKE_FIXON, CKE_WRITE_TO_ALL_CHANNEL); + + // tINIT5=2us(min) + mcDELAY_US(2); + //u1PowerOn=1; + + //// Enable HW MIOCK control to make CLK dynamic + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_TCKFIXON); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); + mcSHOW_DBG_MSG3(("APPLY_LP4_POWER_INIT_SEQUENCE\n")); + } + #endif +} + +DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround) +{ + static U8 CATermWA[CHANNEL_NUM] = {0}; + U8 u1ChannelIdx, u1RankIdx, u1RankIdxBak; + U32 backup_broadcast; + U8 u1MR11_Value; + U8 u1MR22_Value; + + u1ChannelIdx = vGetPHY2ChannelMapping(p); + + if (CATermWA[u1ChannelIdx] == bWorkAround) + return DRAM_OK; + + CATermWA[u1ChannelIdx] = bWorkAround; + + backup_broadcast = GetDramcBroadcast(); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + u1RankIdxBak = u1GetRank(p); + + for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++) + { + vSetRank(p, u1RankIdx); + + mcSHOW_DBG_MSG(("[DramcModeRegInit_CATerm] CH%u RK%u bWorkAround=%d\n", u1ChannelIdx, u1RankIdx, bWorkAround)); + /* FSP_1: 1. For term freqs 2. Assumes "data rate >= DDR2667" are terminated */ + #if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); + #endif + DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, TO_MR); + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR); + + //MR12 use previous value + + if (p->dram_type == TYPE_LPDDR4P) + { + u1MR11_Value = 0x0; //ODT disable + } + else + { +#if ENABLE_SAMSUNG_NT_ODT + if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7)) // 1ynm process for NT-ODT + { + u1MR11_Value = 0x2; //@Darren, DQ ODT:120ohm -> parallel to 60ohm + u1MR11_Value |= (0x1 << 3); //@Darren, MR11[3]=1 to enable NT-ODT for B707 + } + else +#endif + u1MR11_Value = 0x3; //DQ ODT:80ohm + + #if FSP1_CLKCA_TERM + if (p->dram_cbt_mode[u1RankIdx] == CBT_NORMAL_MODE) + { + u1MR11_Value |= 0x40; //CA ODT:60ohm for byte mode + } + else + { + u1MR11_Value |= 0x20; //CA ODT:120ohm for byte mode + } + #endif + } + #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST + if (gDramcDqOdtRZQAdjust >= 0) + u1MR11_Value = gDramcDqOdtRZQAdjust; + #endif + u1MR11Value[p->dram_fsp] = u1MR11_Value; + DramcModeRegWriteByRank(p, u1RankIdx, 11, u1MR11Value[p->dram_fsp]); //ODT + + if (p->dram_type == TYPE_LPDDR4) + { + u1MR22_Value = 0x24; //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA + } + else //TYPE_LPDDR4x, LP4P + { + u1MR22_Value = 0x3c; //Disable CA-CS-CLK ODT, SOC ODT=RZQ/4 + #if FSP1_CLKCA_TERM + if (bWorkAround) + { + u1MR22_Value = 0x4; + } + else + { + if (u1RankIdx == RANK_0) + { + u1MR22_Value = 0x4; //Enable CA-CS-CLK ODT, SOC ODT=RZQ/4 + } + else + { + u1MR22_Value = 0x2c; //Enable CS ODT, SOC ODT=RZQ/4 + } + } + #endif + } + #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST + if (gDramcMR22SoCODTAdjust[u1MRFsp] >= 0) + { + u1MR22_Value = (u1MR22_Value & ~(0x7)) | gDramcMR22SoCODTAdjust[u1MRFsp]; + } + #endif + u1MR22Value[p->dram_fsp] = u1MR22_Value; + DramcModeRegWriteByRank(p, u1RankIdx, 22, u1MR22_Value); + } + + vSetRank(p, u1RankIdxBak); +// vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), RANK_0, MRS_MRSRK); + + DramcBroadcastOnOff(backup_broadcast); + + return DRAM_OK; +} + +DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) +{ + U32 u4RankIdx;//, u4CKE0Bak, u4CKE1Bak, u4MIOCKBak, u4AutoRefreshBak; + U8 u1MRFsp= FSP_0; + U8 u1ChannelIdx; + U8 backup_channel, backup_rank; + U8 operating_fsp = p->dram_fsp; + U32 backup_broadcast; + U8 u1MR11_Value; + U8 u1MR22_Value; + U8 u1nWR=0; + U16 u2FreqMax = u2DFSGetHighestFreq(p); + U8 u1set_mrsrk=0; + + backup_broadcast = GetDramcBroadcast(); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + + DramcPowerOnSequence(p); + + backup_channel = p->channel; + backup_rank = p->rank; + + +#if VENDER_JV_LOG + vPrintCalibrationBasicInfo_ForJV(p); +#endif + + /* Fix nWR value to 30 (MR01[6:4] = 101B) for DDR3200 + * Fix nWR value to 34 (MR01[6:4] = 110B) for DDR3733 + * Other vendors: Use default MR01 for each FSP (Set in vInitGlobalVariablesByCondition() ) + */ + { + /* Clear MR01 OP[6:4] */ + u1MR01Value[FSP_0] &= 0x8F; + u1MR01Value[FSP_1] &= 0x8F; + if (u2FreqMax == 2133) + { + /* Set MR01 OP[6:4] to 111B = 7 */ + u1MR01Value[FSP_0] |= (0x7 << 4); + u1MR01Value[FSP_1] |= (0x7 << 4); + u1nWR = 40; + } + else if (u2FreqMax == 1866) + { + /* Set MR01 OP[6:4] to 110B = 6 */ + u1MR01Value[FSP_0] |= (0x6 << 4); + u1MR01Value[FSP_1] |= (0x6 << 4); + u1nWR = 34; + } + else // Freq <= 1600 + { + /* Set MR01 OP[6:4] to 101B = 5 */ + u1MR01Value[FSP_0] |= (0x5 << 4); + u1MR01Value[FSP_1] |= (0x5 << 4); + u1nWR = 30; + } + + mcSHOW_DBG_MSG(("nWR fixed to %d\n", u1nWR)); + mcDUMP_REG_MSG(("nWR fixed to %d\n", u1nWR)); + } + +#ifndef DUMP_INIT_RG_LOG_TO_DE + if(p->dram_fsp == FSP_1) + { + // @Darren, VDDQ = 600mv + CaVref default is 301mV (no impact) + // Fix high freq keep FSP0 for CA term (PPR abnormal) + vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + cbt_switch_freq(p, CBT_LOW_FREQ); + vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(0, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(1, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + } +#endif + + for(u1ChannelIdx=0; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + + for(u4RankIdx =0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++) + { + vSetRank(p, u4RankIdx); + + mcSHOW_DBG_MSG(("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx)); + mcDUMP_REG_MSG(("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx)); + #if VENDER_JV_LOG + mcSHOW_JV_LOG_MSG(("\n[ModeRegInit_LP4] CH%u RK%d\n", u1ChannelIdx, u4RankIdx)); + #endif + #if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); + #endif + + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u4RankIdx, MRS_MRSRK); + + // Note : MR37 for LP4P should be set before any Mode register. + // MR37 is not shadow register, just need to set by channel and rank. No need to set by FSP + if(p->dram_type == TYPE_LPDDR4P) + { + //temp solution, need remove later + #ifndef MT6779_FPGA + #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) + #if __Petrus_TO_BE_PORTING__ + dramc_set_vddq_voltage(p->dram_type, 600000); + #endif + #endif + #endif + + DramcModeRegWriteByRank(p, u4RankIdx, 37, 0x1); + + //temp solution, need remove later + #ifndef MT6779_FPGA + #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) + #if __Petrus_TO_BE_PORTING__ + dramc_set_vddq_voltage(p->dram_type, 400000); + #endif + #endif + #endif + } + + + // if(p->frequency<=1200) + { + /* FSP_0: 1. For un-term freqs 2. Assumes "data rate < DDR2667" are un-term */ + u1MRFsp = FSP_0; + mcSHOW_DBG_MSG3(("\tFsp%d\n", u1MRFsp)); + #if VENDER_JV_LOG + mcSHOW_JV_LOG_MSG(("\tFsp%d\n", u1MRFsp)); + #endif + + u1MR13Value[u4RankIdx] = 0; + MRWriteFldMulti(p, 13, P_Fld(1, MR13_PRO) | + P_Fld(1, MR13_VRCG), + TO_MR); + + //MR12 use previous value + DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); + DramcModeRegWriteByRank(p, u4RankIdx, 1, u1MR01Value[u1MRFsp]); + + //MR2 set Read/Write Latency + if (p->freqGroup <= 400) // DDR800, DDR400 + { + u1MR02Value[u1MRFsp] = 0x12; // the minimum of WL is 8, and the minimum of RL is 14 (Jouling and HJ) + } + else if ((p->freqGroup == 800) || (p->freqGroup == 600)) // DDR1600, DDR1200 + { + u1MR02Value[u1MRFsp] = 0x12; + } + else if (p->freqGroup == 933) // DDR1866 + { + u1MR02Value[u1MRFsp] = 0x1b; //RL=20, WL=10 + } + else if (p->freqGroup == 1200) // DDR2280, DDR2400 (DDR2667 uses FSP_1) + { + u1MR02Value[u1MRFsp] = 0x24; + } + + DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]); + //if(p->odt_onoff) + u1MR11Value[u1MRFsp] = 0x0; + DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]); //ODT disable + +#if ENABLE_LP4Y_DFS + // For LPDDR4Y <= DDR1600 un-term + if (p->freqGroup <= 800) + { + u1MR21Value[u1MRFsp] |= (0x1 << 5); // Low Speed CA buffer for LP4Y + u1MR51Value[u1MRFsp] |= (0x3 << 1); // CLK[3]=0, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y + } + else +#endif + { + u1MR21Value[u1MRFsp] = 0; + u1MR51Value[u1MRFsp] = 0; + } + DramcModeRegWriteByRank(p, u4RankIdx, 21, u1MR21Value[u1MRFsp]); + DramcModeRegWriteByRank(p, u4RankIdx, 51, u1MR51Value[u1MRFsp]); + + if(p->dram_type == TYPE_LPDDR4) + { + u1MR22_Value = 0x20; //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA + } + else //TYPE_LPDDR4x, LP4P + { + u1MR22_Value = 0x38; //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA + } + #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST + if (gDramcMR22SoCODTAdjust[u1MRFsp]>=0) + { + u1MR22_Value = (u1MR22_Value&~(0x7))|gDramcMR22SoCODTAdjust[u1MRFsp]; + } + #endif + u1MR22Value[u1MRFsp] = u1MR22_Value; + DramcModeRegWriteByRank(p, u4RankIdx, 22, u1MR22Value[u1MRFsp]); + + //MR14 use previous value + DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR14 VREF-DQ + + #if CALIBRATION_SPEED_UP_DEBUG + mcSHOW_DBG_MSG(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f))); + mcSHOW_DBG_MSG(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp,u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f))); + #endif + + //MR3 set write-DBI and read-DBI (Disabled during calibration, enabled after K) + u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&0x3F); + + if(p->dram_type == TYPE_LPDDR4X || p->dram_type == TYPE_LPDDR4P) + { + u1MR03Value[u1MRFsp] &= 0xfe; + } + #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST + if (gDramcMR03PDDSAdjust[u1MRFsp]>=0) + { + u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&~(0x7<<3))|(gDramcMR03PDDSAdjust[u1MRFsp]<<3); + } + #endif + DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]); + DramcModeRegWriteByRank(p, u4RankIdx, 4, u1MR04Value[u4RankIdx]); + DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]); + } + //else + { + /* FSP_1: 1. For term freqs 2. Assumes "data rate >= DDR2667" are terminated */ + u1MRFsp = FSP_1; + mcSHOW_DBG_MSG3(("\tFsp%d\n", u1MRFsp)); + #if VENDER_JV_LOG + mcSHOW_JV_LOG_MSG(("\tFsp%d\n", u1MRFsp)); + #endif + + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR); + + //MR12 use previous value + DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR12 VREF-CA + DramcModeRegWriteByRank(p, u4RankIdx, 1, u1MR01Value[u1MRFsp]); + + //MR2 set Read/Write Latency + if (p->freqGroup == 2133) + { + u1MR02Value[u1MRFsp] = 0x3f; + } + else if (p->freqGroup == 1866) + { + u1MR02Value[u1MRFsp] = 0x36; + } + else if (p->freqGroup == 1600) + { + u1MR02Value[u1MRFsp] = 0x2d; + } + else if (p->freqGroup == 1333) + { + u1MR02Value[u1MRFsp] = 0x24; + } + DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]); + + if(p->dram_type == TYPE_LPDDR4P) + u1MR11_Value = 0x0; //ODT disable + else + { +#if ENABLE_SAMSUNG_NT_ODT + if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7)) // 1ynm process for NT-ODT + { + u1MR11_Value = 0x2; //@Darren, DQ ODT:120ohm -> parallel to 60ohm + u1MR11_Value |= (0x1 << 3); //@Darren, MR11[3]=1 to enable NT-ODT for B707 + } + else +#endif + u1MR11_Value = 0x3; //DQ ODT:80ohm + + #if FSP1_CLKCA_TERM + if(p->dram_cbt_mode[u4RankIdx]==CBT_NORMAL_MODE) + { + u1MR11_Value |= 0x40; //CA ODT:60ohm for normal mode die + } + else + { + u1MR11_Value |= 0x20; //CA ODT:120ohm for byte mode die + } + #endif + } + #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST + if (gDramcDqOdtRZQAdjust>=0) + { + u1MR11_Value &= ~(0x7); + u1MR11_Value = gDramcDqOdtRZQAdjust; + } + #endif + u1MR11Value[u1MRFsp] = u1MR11_Value; + DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]); //ODT + + u1MR21Value[u1MRFsp] = 0; + u1MR51Value[u1MRFsp] = 0; + DramcModeRegWriteByRank(p, u4RankIdx, 21, u1MR21Value[u1MRFsp]); + DramcModeRegWriteByRank(p, u4RankIdx, 51, u1MR51Value[u1MRFsp]); + + if(p->dram_type == TYPE_LPDDR4) + { + u1MR22_Value = 0x24; //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA + } + else //TYPE_LPDDR4x, LP4P + { + u1MR22_Value = 0x3c; //Disable CA-CS-CLK ODT, SOC ODT=RZQ/4 + #if FSP1_CLKCA_TERM + if(u4RankIdx==RANK_0) + { + u1MR22_Value = 0x4; //Enable CA-CS-CLK ODT, SOC ODT=RZQ/4 + } + else + { + u1MR22_Value = 0x2c; //Enable CS ODT, SOC ODT=RZQ/4 + } + #endif + } + #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST + if (gDramcMR22SoCODTAdjust[u1MRFsp]>=0) + { + u1MR22_Value = (u1MR22_Value&~(0x7))|gDramcMR22SoCODTAdjust[u1MRFsp]; + } + #endif + u1MR22Value[u1MRFsp] = u1MR22_Value; + DramcModeRegWriteByRank(p, u4RankIdx, 22, u1MR22Value[u1MRFsp]); + + //MR14 use previous value + DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR14 VREF-DQ + + #if CALIBRATION_SPEED_UP_DEBUG + mcSHOW_DBG_MSG(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f))); + mcSHOW_DBG_MSG(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f))); + #endif + + //MR3 set write-DBI and read-DBI (Disabled during calibration, enabled after K) + u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&0x3F); + + if(p->dram_type == TYPE_LPDDR4X || p->dram_type == TYPE_LPDDR4P) + { + u1MR03Value[u1MRFsp] &= 0xfe; + } + #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST + if (gDramcMR03PDDSAdjust[u1MRFsp]>=0) + { + u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&~(0x7<<3))|(gDramcMR03PDDSAdjust[u1MRFsp]<<3); + } + #endif + DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]); + DramcModeRegWriteByRank(p, u4RankIdx, 4, u1MR04Value[u4RankIdx]); + DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]); + } + + +#if ENABLE_LP4_ZQ_CAL + DramcZQCalibration(p, u4RankIdx); //ZQ calobration should be done before CBT calibration by switching to low frequency +#endif + + /* freq < 1333 is assumed to be odt_off -> uses FSP_0 */ + //if (p->frequency < MRFSP_TERM_FREQ) + if(operating_fsp == FSP_0) + { + DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); + DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE); + } + else + { + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE); + } + + } + vSetRank(p, backup_rank); + +#if 0 + for(u4RankIdx =0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++) + { + DramcModeRegWriteByRank(p, u4RankIdx, 13, u1MR13Value[RANK_0]); + } +#else + + /* MRS two ranks simutaniously */ + if (p->support_rank_num == RANK_DUAL) + u1set_mrsrk = 0x3; + else + u1set_mrsrk = RANK_0; + DramcModeRegWriteByRank(p, u1set_mrsrk, 13, u1MR13Value[RANK_0]); +#endif + + /* Auto-MRW related register write (Used during HW DVFS frequency switch flow) + * VRCG seems to be enabled/disabled even when switching to same FSP(but different freq) to simplify HW DVFS flow + */ + // 1. MR13 OP[3] = 1 : Enable "high current mode" to reduce the settling time when changing FSP(freq) during operation + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(u1MR13Value[RANK_0] | (0x1 << 3), SHU_HWSET_MR13_HWSET_MR13_OP) + | P_Fld(13, SHU_HWSET_MR13_HWSET_MR13_MRSMA)); + // 2. MR13 OP[3] = 1 : Enable "high current mode" after FSP(freq) switch operation for calibration + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(u1MR13Value[RANK_0] | (0x1 << 3), SHU_HWSET_VRCG_HWSET_VRCG_OP) + | P_Fld(13, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA)); + // 3. MR2 : Set RL/WL after FSP(freq) switch + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2), P_Fld(u1MR02Value[operating_fsp], SHU_HWSET_MR2_HWSET_MR2_OP) + | P_Fld(2, SHU_HWSET_MR2_HWSET_MR2_MRSMA)); + } + +#ifndef DUMP_INIT_RG_LOG_TO_DE + //switch to high freq + if(p->dram_fsp == FSP_1) + { + // @Darren, no effect via DDR1600 (purpose to keep @FSP0) + // Fix high freq keep FSP0 for CA term (PPR abnormal) + vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + cbt_switch_freq(p, CBT_HIGH_FREQ); + vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(0, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(1, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + } +#endif + vSetPHY2ChannelMapping(p, backup_channel); + + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), RANK_0, SWCMD_CTRL0_MRSRK); + + DramcBroadcastOnOff(backup_broadcast); + +#if SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER + vApplyProgramSequence(p); +#endif + + return DRAM_OK; +} + +void MPLLInit(void) +{ +#if (FOR_DV_SIMULATION_USED==0) +#if 0//__A60868_TO_BE_PORTING__ + +#if (FOR_DV_SIMULATION_USED == 0) + unsigned int tmp; + + DRV_WriteReg32(AP_PLL_CON0, 0x11); // CLKSQ Enable + mcDELAY_US(100); + DRV_WriteReg32(AP_PLL_CON0, 0x13); // CLKSQ LPF Enable + mcDELAY_MS(1); + DRV_WriteReg32(MPLL_PWR_CON0, 0x3); // power on MPLL + mcDELAY_US(30); + DRV_WriteReg32(MPLL_PWR_CON0, 0x1); // turn off ISO of MPLL + mcDELAY_US(1); + tmp = DRV_Reg32(MPLL_CON1); + DRV_WriteReg32(MPLL_CON1, tmp | 0x80000000); // Config MPLL freq + DRV_WriteReg32(MPLL_CON0, 0x181); // enable MPLL + mcDELAY_US(20); +#endif +#else + unsigned int tmp; + + DRV_WriteReg32(MPLL_CON3, 0x3); // power on MPLL + + mcDELAY_US(30); + + tmp = DRV_Reg32(MPLL_CON3); + DRV_WriteReg32(MPLL_CON3, tmp & 0xFFFFFFFD); // turn off ISO of MPLL + + mcDELAY_US(1); + + DRV_WriteReg32(MPLL_CON1, 0x84200000); // Config MPLL freq + + tmp = DRV_Reg32(MPLL_CON0); + DRV_WriteReg32(MPLL_CON0, tmp | 0x1); // enable MPLL + + mcDELAY_US(20); + + tmp = DRV_Reg32(PLLON_CON0); + DRV_WriteReg32(PLLON_CON0, tmp & ~(0x1 << 2)); // PLL_ISO from SPM + + tmp = DRV_Reg32(PLLON_CON0); + DRV_WriteReg32(PLLON_CON0, tmp & ~(0x1 << 11)); // PLL_EN from SPM + + tmp = DRV_Reg32(PLLON_CON1); + DRV_WriteReg32(PLLON_CON1, tmp & ~(0x1 << 20)); // PLL_PWR from SPM + + tmp = DRV_Reg32(PLLON_CON2); + DRV_WriteReg32(PLLON_CON2, tmp & ~(0x1 << 2)); // PLL SPEC + + tmp = DRV_Reg32(PLLON_CON3); + DRV_WriteReg32(PLLON_CON3, tmp & ~(0x1 << 2)); // PLL SPEC +#endif +#endif +} + + +#if ENABLE_RODT_TRACKING_SAVE_MCK +void SetTxWDQSStatusOnOff(U8 u1OnOff) +{ + u1WDQS_ON = u1OnOff; +} +#endif + + +#if XRTRTR_NEW_CROSS_RK_MODE +void XRTRTR_SHU_Setting(DRAMC_CTX_T * p) +{ + U8 u1RkSelUIMinus = 0, u1RkSelMCKMinus = 0; + //U8 u1RankIdx = 0; + //U8 u1Rank_backup = u1GetRank(p); + + if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) // DDR800semi + u1RkSelMCKMinus = 1; + else if (p->frequency >= 1600) //DDR3200 up + u1RkSelUIMinus = 2; + + // DV codes is included + /*vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ6, u1ShuRkMode, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ6, u1ShuRkMode, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1);*/ + + //DRAMC setting - @Darren, DV no set (double confirm) + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(u1RkSelMCKMinus, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS) + | P_Fld(u1RkSelUIMinus, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) + | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) + | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) + | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) + | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) + | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) + | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) // @HJ, no use + | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) + | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN)); + //Darren-vIO32WriteFldAlign_All(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DQSIEN_RX_SELPH_OPT); //@HJ, internal wire assign to 1'b1 + + /*for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN) + | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) + | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) + | P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT)); + } + vSetRank(p, u1Rank_backup);*/ +} +#endif + +#if XRTWTW_NEW_CROSS_RK_MODE +void XRTWTW_SHU_Setting(DRAMC_CTX_T * p) +{ + U8 u1RankIdx, u1ByteIdx; + U8 u1Rank_bak = u1GetRank(p); + U16 u2TxDly_OEN_RK[2][2] = {0}, u2TxPI_UPD[2] = {0}, u2TxRankINCTL, u2TxDly_OEN_RK_max, u2TxPI_UPD_max; + + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + + u2TxDly_OEN_RK[u1RankIdx][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); //Byte0 + u2TxDly_OEN_RK[u1RankIdx][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); //Byte1 + } + vSetRank(p, u1Rank_bak); + + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + u2TxDly_OEN_RK_max = (u2TxDly_OEN_RK[0][u1ByteIdx] > u2TxDly_OEN_RK[1][u1ByteIdx])? u2TxDly_OEN_RK[0][u1ByteIdx]: u2TxDly_OEN_RK[1][u1ByteIdx]; + if (p->frequency >= 1200) + u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 2)? (u2TxDly_OEN_RK_max - 2): 0; //Byte0 + else + u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 1)? (u2TxDly_OEN_RK_max - 1): 0; //Byte0 + } + + u2TxPI_UPD_max = (u2TxPI_UPD[0] > u2TxPI_UPD[1])? u2TxPI_UPD[0]: u2TxPI_UPD[1]; + u2TxRankINCTL = (u2TxPI_UPD_max > 1)? (u2TxPI_UPD_max - 1): 0; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL), P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE) + | P_Fld(u2TxPI_UPD[0], SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) + | P_Fld(u2TxPI_UPD[1], SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_RANKCTL), P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT) + | P_Fld(u2TxRankINCTL, SHU_TX_RANKCTL_TXRANKINCTL) + | P_Fld(u2TxRankINCTL, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY)); +} +#endif + + +#if CMD_CKE_WORKAROUND_FIX +void CMD_CKE_Modified_txp_Setting(DRAMC_CTX_T * p) +{ +#if __A60868_TO_BE_PORTING__ + + U8 u1CmdTxPipe = 0, u1CkTxPipe = 0, u1SrefPdSel = 0; + + if (vGet_Div_Mode(p) == DIV4_MODE) + { + u1CkTxPipe = 1; + u1SrefPdSel = 1; + } + else if (p->frequency >= 1866) + { + u1CmdTxPipe = 1; + u1CkTxPipe = 1; + } + + vIO32WriteFldAlign(DDRPHY_SHU_MISC0, u1CkTxPipe, SHU_MISC0_RG_CK_TXPIPE_BYPASS_EN); + vIO32WriteFldAlign(DDRPHY_SHU_MISC0, u1CmdTxPipe, SHU_MISC0_RG_CMD_TXPIPE_BYPASS_EN); + //vIO32WriteFldAlign(DRAMC_REG_SHU_CONF0, u1SrefPdSel, SHU_CONF0_SREF_PD_SEL); +#endif //__A60868_TO_BE_PORTING__ +} +#endif + +#if TX_OE_EXTEND +static void UpdateTxOEN(DRAMC_CTX_T *p) +{ + U8 u1ByteIdx, backup_rank, ii; + U8 u1DQ_OE_CNT; + + // For LP4 + // 1. R_DMDQOE_OPT (dramc_conf 0x8C0[11]) + // set 1'b1: adjust DQSOE/DQOE length with R_DMDQOE_CNT + // 2. R_DMDQOE_CNT (dramc_conf 0x8C0[10:8]) + // set 3'h3 + // 3. Initial TX setting OE/DATA + // OE = DATA - 4 UI + + // For LP3 + // 1. R_DMDQOE_OPT (dramc_conf 0x8C0[11]) + // set 1'b1: adjust DQSOE/DQOE length with R_DMDQOE_CNT + // 2. R_DMDQOE_CNT (dramc_conf 0x8C0[10:8]) + // set 3'h2 + // 3. Initial TX setting OE/DATA + // OE = DATA - 2 UI + + u1DQ_OE_CNT = 3; + + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(1, SHU_TX_SET0_DQOE_OPT) | P_Fld(u1DQ_OE_CNT, SHU_TX_SET0_DQOE_CNT)); + + backup_rank = u1GetRank(p); + + LP4_ShiftDQS_OENUI(p, -1, ALL_BYTES); + ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES); + +} +#endif + +#if ENABLE_DUTY_SCAN_V2 +#ifdef DDR_INIT_TIME_PROFILING +U32 gu4DutyCalibrationTime; +#endif +#endif + +static void vReplaceDVInit(DRAMC_CTX_T *p) +{ + U8 u1RandIdx, backup_rank = 0; + + backup_rank = p->rank; + + //Disable RX Tracking + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), P_Fld(0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), P_Fld(0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0), P_Fld(0, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0) + | P_Fld(0, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0), P_Fld(0, B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1) + | P_Fld(0, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 )); + + for(u1RandIdx = RANK_0; u1RandIdx < p->support_rank_num; u1RandIdx++) + { + vSetRank(p, u1RandIdx); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0) + | P_Fld(0, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0) + | P_Fld(0, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1) + | P_Fld(0, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1) + | P_Fld(0, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1)); + } + vSetRank(p, backup_rank); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1), 0, CBT_WLEV_CTRL1_CATRAINLAT); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1), 0, SWCMD_CTRL1_WRFIFO_MODE2); + + + //Bringup setting review + + { + U32 backup_broadcast = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + U8 u1DQ_HYST_SEL=0x1, u1CA_HYST_SEL=0x1; + U8 u1DQ_CAP_SEL=0x18, u1CA_CAP_SEL=0x18; + //Critical + //APHY + if(p->frequency<=933) + { + u1DQ_HYST_SEL = 0x1; + u1CA_HYST_SEL = 0x1; + } + else + { + u1DQ_HYST_SEL = 0x0; + u1CA_HYST_SEL = 0x0; + } + + if(p->frequency<=933) + { + u1DQ_CAP_SEL= 0x18; + u1CA_CAP_SEL= 0x18; + } + else if(p->frequency<=1200) + { + u1DQ_CAP_SEL= 0x14; + u1CA_CAP_SEL= 0x14; + } + else if(p->frequency<=1600) + { + u1DQ_CAP_SEL= 0x4; + u1CA_CAP_SEL= 0x4; + } + else if(p->frequency<=2133) + { + u1DQ_CAP_SEL= 0x2; + u1CA_CAP_SEL= 0x2; + } + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ6, P_Fld(u1DQ_HYST_SEL, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) + | P_Fld(u1DQ_CAP_SEL, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ6, P_Fld(u1DQ_HYST_SEL, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) + | P_Fld(u1DQ_CAP_SEL, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6, P_Fld(u1CA_HYST_SEL, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) + | P_Fld(u1CA_CAP_SEL, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA)); + + //Jeremy + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2,P_Fld((p->frequency>=2133), SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) + | P_Fld((p->frequency>=2133), SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) + | P_Fld(0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) + | P_Fld(0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ2,P_Fld((p->frequency>=2133), SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) + | P_Fld((p->frequency>=2133), SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) + | P_Fld(0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) + | P_Fld(0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD2,P_Fld((p->frequency>=2133), SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) + | P_Fld((p->frequency>=2133), SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) + | P_Fld((p->frequency<=300), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) + | P_Fld((p->frequency<=300), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA)); + + //disable RX PIPE for RX timing pass + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x0, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); + + //Disable MD32 IRQ + vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL1, 0x0); + vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL4, 0x0); + vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL7, 0x0); + + //Disable NEW RX DCM mode + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY) + | P_Fld(2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) + | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) + | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT)); + + vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0, HMR4_MR4INT_LIMITEN); + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REFPEND_OPT1); + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0, REFCTRL3_REF_DERATING_EN); + + vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_IRQ_EN, P_Fld(0x3fff, DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV) + | P_Fld(0x0, DRAMC_IRQ_EN_MR4INT_EN)); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0, SHU_CONF0_PBREFEN); + + + + vIO32WriteFldAlign_All(DDRPHY_REG_CA_TX_MCK, 0x1, CA_TX_MCK_R_DMRESET_FRPHY_OPT); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x1, MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 0x1, MISC_IMPCAL_IMPBINARY); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ10, P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) + | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ10, P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) + | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1)); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8, P_Fld(1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) + | P_Fld(1, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8, P_Fld(1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) + | P_Fld(1, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1)); + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL2, 0x1, SHU_B0_DLL2_RG_ARDQ_REV_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL2, 0x1, SHU_B1_DLL2_RG_ARDQ_REV_B1); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DLL2, 0x1, SHU_CA_DLL2_RG_ARCMD_REV); //Jeremy + + #if 1 + //Follow DE - DRAMC + //vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 1, DDRCOMMON0_DISSTOP26M); + //vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A3, 1, TEST2_A3_TEST_AID_EN); + //vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 0, TEST2_A4_TESTAGENTRKSEL); + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0, DUMMY_RD_DQSG_DMYRD_EN); + vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_DBG_SEL1, 0x1e, DRAMC_DBG_SEL1_DEBUG_SEL_0); + vIO32WriteFldAlign_All(DRAMC_REG_SWCMD_CTRL2, 0x20, SWCMD_CTRL2_RTSWCMD_AGE); + vIO32WriteFldAlign_All(DRAMC_REG_RTMRW_CTRL0, 0x20, RTMRW_CTRL0_RTMRW_AGE); + + + vIO32WriteFldMulti_All(DRAMC_REG_DLLFRZ_CTRL, P_Fld(0, DLLFRZ_CTRL_DLLFRZ) | P_Fld(0, DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT)); + vIO32WriteFldMulti_All(DRAMC_REG_MPC_CTRL, P_Fld(1, MPC_CTRL_RTSWCMD_HPRI_EN) | P_Fld(1, MPC_CTRL_RTMRW_HPRI_EN)); + vIO32WriteFldMulti_All(DRAMC_REG_HW_MRR_FUN, P_Fld(0, HW_MRR_FUN_R2MRRHPRICTL) | P_Fld(0, HW_MRR_FUN_TR2MRR_ENA)); + vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL, P_Fld(1, ACTIMING_CTRL_REFNA_OPT) | P_Fld(1, ACTIMING_CTRL_SEQCLKRUN3)); + vIO32WriteFldAlign_All(DRAMC_REG_CKECTRL, 1, CKECTRL_RUNTIMEMRRCKEFIX); + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0, DVFS_CTRL0_DVFS_SYNC_MASK) | P_Fld(1, DVFS_CTRL0_R_DVFS_SREF_OPT)); + vIO32WriteFldAlign_All(DRAMC_REG_DVFS_TIMING_CTRL1, 1, DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT); + vIO32WriteFldMulti_All(DRAMC_REG_HMR4, P_Fld(1, HMR4_REFRCNT_OPT) + | P_Fld(0, HMR4_REFR_PERIOD_OPT) + | P_Fld(1, HMR4_SPDR_MR4_OPT)//Resume from S0, trigger HW MR4 + | P_Fld(0, HMR4_HMR4_TOG_OPT)); + vIO32WriteFldAlign_All(DRAMC_REG_RX_SET0, 0, RX_SET0_SMRR_UPD_OLD); + vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 1, DRAMCTRL_SHORTQ_OPT); + vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 1, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS); +#if ENABLE_EARLY_BG_CMD==0 + vIO32WriteFldAlign_All(DRAMC_REG_PERFCTL0, 0, PERFCTL0_EBG_EN); +#endif + vIO32WriteFldMulti_All(DRAMC_REG_CLKAR, P_Fld(1, CLKAR_REQQUECLKRUN) | P_Fld(0x7fff, CLKAR_REQQUE_PACG_DIS)); + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_PBREF_BK_REFA_ENA) | P_Fld(0, REFCTRL0_PBREF_BK_REFA_NUM)); + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA); + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REFPB2AB_IGZQCS); + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPENDINGINT_OPT1); // @Darren, sync MP settings from Derping + vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE1,5, REF_BOUNCE1_REFRATE_DEBOUNCE_TH); + vIO32WriteFldAlign_All(DRAMC_REG_REFPEND2, 8, REFPEND2_MPENDREFCNT_TH8); + vIO32WriteFldAlign_All(DRAMC_REG_SCSMCTRL, 0, SCSMCTRL_SC_PG_MAN_DIS); + vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG, P_Fld(1, SCSMCTRL_CG_SCSM_CGAR) + | P_Fld(1, SCSMCTRL_CG_SCARB_SM_CGAR)); + vIO32WriteFldAlign_All(DRAMC_REG_RTSWCMD_CNT, 0x30, RTSWCMD_CNT_RTSWCMD_CNT); + vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_IRQ_EN, 0x3fff, DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_DCM_CTRL0, 1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x1ff, SHU_HMR4_DVFS_CTRL0_REFRCNT) | P_Fld(0, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT)); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, 11, SHU_HWSET_VRCG_VRCGDIS_PRDCNT); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_MISC, 2, SHU_MISC_REQQUE_MAXCNT); + + + //Follow DE - DDRPHY + vIO32WriteFldMulti_All(DDRPHY_REG_B0_DLL_ARPI4, P_Fld(1, B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0) | P_Fld(1, B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_B1_DLL_ARPI4, P_Fld(1, B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1) | P_Fld(1, B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1)); + vIO32WriteFldMulti_All(DDRPHY_REG_CA_DLL_ARPI4, P_Fld(1, CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA) | P_Fld(1, CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA)); + vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD11, P_Fld(0xa, CA_CMD11_RG_RRESETB_DRVN) | P_Fld(0xa, CA_CMD11_RG_RRESETB_DRVP)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0x1f, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL); + +#if 1 // Darren- for DDR400 open loop mode disable + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL9, P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF) + | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF) + | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN) + | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF) + | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF) + | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN) + | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF) + | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF) + | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN) + | P_Fld(0, MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN)); +#endif + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL, 1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(1, MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE) + | P_Fld(0, MISC_DVFSCTL2_RG_DLL_SHUFFLE)); // Darren- + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, P_Fld(0x10, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK) + | P_Fld(1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE) + | P_Fld(3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI) + | P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK) + | P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK)); + + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DDR_RESERVE, 0xf, MISC_DDR_RESERVE_WDT_CONF_ISO_CNT); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMP_CTRL1, P_Fld(1, MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT) | P_Fld(1, MISC_IMP_CTRL1_IMP_ABN_LAT_CLR)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV) + | P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT) + | P_Fld(1, MISC_IMPCAL_IMPBINARY) + | P_Fld(1, MISC_IMPCAL_DQDRVSWUPD) + | P_Fld(0, MISC_IMPCAL_DRVCGWREF)); + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DUTYSCAN1, P_Fld(1, MISC_DUTYSCAN1_EYESCAN_DQS_OPT) | P_Fld(1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL0, P_Fld(0, MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT) + | P_Fld(1, MISC_CTRL0_IMPCAL_CDC_ECO_OPT) + | P_Fld(1, MISC_CTRL0_IMPCAL_LP_ECO_OPT)); + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4, P_Fld(0, MISC_CTRL4_R_OPT2_CG_CS) + | P_Fld(0, MISC_CTRL4_R_OPT2_CG_CLK) + | P_Fld(0, MISC_CTRL4_R_OPT2_CG_CMD) + | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQSIEN) + | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQ) + | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQS) + | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQM) + | P_Fld(0, MISC_CTRL4_R_OPT2_CG_MCK) + | P_Fld(0, MISC_CTRL4_R_OPT2_MPDIV_CG)); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL6, P_Fld(1, MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT) | P_Fld(1, MISC_CTRL6_RG_PHDET_EN_SHU_OPT)); + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 1, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ1, P_Fld(1, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0) + | P_Fld(1, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) + | P_Fld(1, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ1, P_Fld(1, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1) + | P_Fld(1, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) + | P_Fld(1, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1)); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ10, P_Fld(1, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0) + | P_Fld(1, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) //Critical ? + | P_Fld(1, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0)); //Critical ? + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ10, P_Fld(1, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1) + | P_Fld(1, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) //Critical ? + | P_Fld(1, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1)); //Critical ? + + { + U8 u1DQ_BW_SEL_B0=0, u1DQ_BW_SEL_B1=0, u1CA_BW_SEL_CA=0, u1CLK_BW_SEL_CA=0; + if (p->frequency <= 1200) + { + u1CLK_BW_SEL_CA = 1; + } + if (p->frequency >= 2133) + { + u1DQ_BW_SEL_B0 = 1; + u1DQ_BW_SEL_B1 = 1; + u1CA_BW_SEL_CA = 1; + } + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11, u1DQ_BW_SEL_B0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, u1DQ_BW_SEL_B1, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, u1CA_BW_SEL_CA, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, u1CLK_BW_SEL_CA, SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA); + } + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD1, P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA) | P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA)); + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8, P_Fld(1, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) + | P_Fld(1, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) + | P_Fld(1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) + | P_Fld(1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) + | P_Fld(1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) + | P_Fld(1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) + | P_Fld(1, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA) + | P_Fld(1, SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA)); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD12, 0, SHU_CA_CMD12_RG_RIMP_REV); + + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS) + | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS) + | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS) + | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS) + | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS) + | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS)); + + //Darren-vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(67, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE) | P_Fld(43, MISC_SHU_DVFSDLL_R_DLL_IDLE)); + + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_IMPCAL1, 0, SHU_MISC_IMPCAL1_IMPCALCNT); + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, 0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN); + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING6, 7, SHU_MISC_DRVING6_IMP_TXDLY_CMD); + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY) + | P_Fld(2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) + | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) + | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT)); + #endif + DramcBroadcastOnOff(backup_broadcast); + } +} + + +void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p) +{ +#if __A60868_TO_BE_PORTING__ + + U8 read_xrtw2w, shu_index; + U8 u1RankIdx, u1RankIdxBak; + u1RankIdxBak = u1GetRank(p); + + //Clk free run {Move to Init_DRAM() and only call once} +#if (SW_CHANGE_FOR_SIMULATION == 0) + EnableDramcPhyDCM(p, 0); +#endif + + //Set LP3/LP4 Rank0/1 CA/TX delay chain to 0 +#if (FOR_DV_SIMULATION_USED == 0) + //CA0~9 per bit delay line -> CHA_CA0 CHA_CA3 CHA_B0_DQ6 CHA_B0_DQ7 CHA_B0_DQ2 CHA_B0_DQ5 CHA_B0_DQ4 CHA_B0_DQ1 CHA_B0_DQ0 CHA_B0_DQ3 + vResetDelayChainBeforeCalibration(p); +#endif + + //MR4 refresh cnt set to 0x1ff (2ms update) + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_REFRCNT); + + //The counter for Read MR4 cannot be reset after SREF if DRAMC no power down. + vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 1, SPCMDCTRL_SRFMR4_CNTKEEP_B); + + //---- ZQ CS init -------- + vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV, 0x1B, SHU_SCINTV_TZQLAT); //ZQ Calibration Time, unit: 38.46ns, tZQCAL min is 1 us. need to set larger than 0x1b + //for(shu_index = DRAM_DFS_SHUFFLE_1; shu_index < DRAM_DFS_SHUFFLE_MAX; shu_index++) + //vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3 + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 + //vIO32WriteFldAlign_All(DRAMC_REG_SHU2_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 + //vIO32WriteFldAlign_All(DRAMC_REG_SHU3_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 + vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 0, DRAMCTRL_ZQCALL); // HW send ZQ command for both rank, disable it due to some dram only have 1 ZQ pin for two rank. + + //Dual channel ZQCS interlace, 0: disable, 1: enable + if (p->support_channel_num == CHANNEL_SINGLE) + { + //single channel, ZQCSDUAL=0, ZQCSMASK=0 + vIO32WriteFldMulti(DRAMC_REG_ZQCS, P_Fld(0, ZQCS_ZQCSDUAL) | P_Fld(0x0, ZQCS_ZQCSMASK)); + } + else if (p->support_channel_num == CHANNEL_DUAL) + { + // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin. + #ifdef ZQCS_ENABLE_LP4 + // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1 + + vIO32WriteFldMulti_All(DRAMC_REG_ZQCS, P_Fld(1, ZQCS_ZQCSDUAL) | \ + P_Fld(0, ZQCS_ZQCSMASK_OPT) | \ + P_Fld(0, ZQCS_ZQMASK_CGAR) | \ + P_Fld(0, ZQCS_ZQCS_MASK_SEL_CGAR)); + + /* DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0. + * ZQCSMASK setting: (Ch A, Ch B) = (1,0) or (0,1) + * if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first + */ + vIO32WriteFldAlign(DRAMC_REG_ZQCS + (CHANNEL_A << POS_BANK_NUM), 1, ZQCS_ZQCSMASK); + vIO32WriteFldAlign(DRAMC_REG_ZQCS + SHIFT_TO_CHB_ADDR, 0, ZQCS_ZQCSMASK); + + // DRAMC CHA(CHN0):ZQCS_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQCS_ZQCS_MASK_SEL=0. + vIO32WriteFldAlign_All(DRAMC_REG_ZQCS, 0, ZQCS_ZQCS_MASK_SEL); + #endif + } + + // Disable LP3 HW ZQ + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCSDISB); //LP3 ZQCSDISB=0 + // Disable LP4 HW ZQ + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCALDISB); //LP4 ZQCALDISB=0 + // ---- End of ZQ CS init ----- + + //Disable write-DBI of DRAMC (Avoids pre-defined data pattern being modified) + DramcWriteDBIOnOff(p, DBI_OFF); + //Disable read-DBI of DRAMC (Avoids pre-defined data pattern being modified) + DramcReadDBIOnOff(p, DBI_OFF); + //disable MR4 read, REFRDIS=1 + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 1, SPCMDCTRL_REFRDIS); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x1, DQSOSCR_DQSOSCRDIS); //MR18, MR19 Disable + //for(shu_index = DRAM_DFS_SHUFFLE_1; shu_index < DRAM_DFS_SHUFFLE_MAX; shu_index++) + //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV) + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV), 0x1, SHU_SCINTV_DQSOSCENDIS); + //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU2_SCINTV), 0x1, SHU2_SCINTV_DQSOSCENDIS); + //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU3_SCINTV), 0x1, SHU3_SCINTV_DQSOSCENDIS); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN) + | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN) + | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN) + | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG)); + + // Disable HW gating tracking first, 0x1c0[31], need to disable both UI and PI tracking or the gating delay reg won't be valid. + DramcHWGatingOnOff(p, 0); + + // Disable gating debug + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_STBCAL2), 0, STBCAL2_STB_GERRSTOP); + + for (u1RankIdx = RANK_0; u1RankIdx < RANK_MAX; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + + // Disable RX delay tracking + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1); + + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1); + + //RX delay mux, delay vlaue from reg. + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_CA_RXDVS2), 0x0, R0_CA_RXDVS2_R_RK0_DVS_MODE_CA); + } + vSetRank(p, u1RankIdxBak); + + // Set to all-bank refresh + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_PBREFEN); + + // set MRSRK to 0, MPCRKEN always set 1 (Derping) + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_MRS), 0, MRS_MRSRK); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN); + + //RG mode + vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0); + vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1); + vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_BIAS_PS); + +#if ENABLE_RX_TRACKING + DramcRxInputDelayTrackingInit_byFreq(p); +#endif + +#ifdef LOOPBACK_TEST +#ifdef LPBK_INTERNAL_EN + DramcLoopbackTest_settings(p, 0); //0: internal loopback test 1: external loopback test +#else + DramcLoopbackTest_settings(p, 1); //0: internal loopback test 1: external loopback test +#endif +#endif + +#if ENABLE_TMRRI_NEW_MODE + SetCKE2RankIndependent(p); +#endif + +#ifdef DUMMY_READ_FOR_TRACKING + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 1, DUMMY_RD_DMY_RD_RX_TRACK); +#endif + + vIO32WriteFldAlign_All(DRAMC_REG_DRSCTRL, 1, DRSCTRL_DRSDIS); + +#ifdef IMPEDANCE_TRACKING_ENABLE + // set correct setting to control IMPCAL HW Tracking in shuffle RG + // if p->freq >= 1333, enable IMP HW tracking(SHU_DRVING1_DIS_IMPCAL_HW=0), else SHU_DRVING1_DIS_IMPCAL_HW = 1 + U8 u1DisImpHw; + U32 u4TermFreq; + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + u4TermFreq = LP5_MRFSP_TERM_FREQ; + else +#endif + u4TermFreq = LP4_MRFSP_TERM_FREQ; + + u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1; + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING1, u1DisImpHw, SHU_MISC_DRVING1_DIS_IMPCAL_HW); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING1, u1DisImpHw, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, u1DisImpHw, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD12, u1DisImpHw, SHU_CA_CMD12_RG_RIMP_UNTERM_EN); +#endif + + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION && RX_DELAY_PRE_CAL + s2RxDelayPreCal = PASS_RANGE_NA; // reset variable for fast k test +#endif +#endif +} + +static void DramcInit_DutyCalibration(DRAMC_CTX_T *p) +{ +#if ENABLE_DUTY_SCAN_V2 + U32 u4backup_broadcast= GetDramcBroadcast(); +#ifdef DDR_INIT_TIME_PROFILING + U32 u4low_tick0, u4high_tick0, u4low_tick1, u4high_tick1; +#if __ETT__ + u4low_tick0 = GPT_GetTickCount(&u4high_tick0); +#else + u4low_tick0 = get_timer(0); +#endif +#endif + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); +#ifndef DUMP_INIT_RG_LOG_TO_DE + if (Get_MDL_Used_Flag()==NORMAL_USED) + { + DramcNewDutyCalibration(p); + } +#endif + DramcBroadcastOnOff(u4backup_broadcast); + +#ifdef DDR_INIT_TIME_PROFILING +#if __ETT__ + u4low_tick1 = GPT_GetTickCount(&u4high_tick1); + gu4DutyCalibrationTime = ((u4low_tick1 - u4low_tick0) * 76) / 1000000; +#else + u4low_tick1 = get_timer(u4low_tick0); + gu4DutyCalibrationTime = u4low_tick1; +#endif +#endif +#endif +} + +static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p) +{ + + + //CInit_ConfigFromTBA(); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + + //if(LPDDR4_EN_S && DramcConfig->freq_sel == LP4_DDR1600) + if(!is_lp5_family(p)) + { + if(p->frequency>=2133) //Term + { + mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_4266 \n")); + sv_algorithm_assistance_LP4_4266(p); + } + else if(p->frequency>=1333) //Term + { + mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_3733 \n")); + sv_algorithm_assistance_LP4_3733(p); + } + else if(p->frequency>400) //Unterm + { + mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_1600 \n")); + sv_algorithm_assistance_LP4_1600(p); + } + else /*if(p->frequency==400)*/ //DDR800 Semi-Open + { + //mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP4_1600 \n")); + //CInit_golden_mini_freq_related_vseq_LP4_1600(p); + //CInit_golden_mini_freq_related_vseq_LP4_1600_SHU1(DramcConfig); + mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_800 \n")); + sv_algorithm_assistance_LP4_800(p); + } + /*else //DDR250 Open Loop (DV random seed not ready) + { + mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_250 \n")); + sv_algorithm_assistance_LP4_250(p); + }*/ + } + #if __LP5_COMBO__ + else + { + if(p->freq_sel==LP5_DDR4266) + { + mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP5_4266 \n")); + CInit_golden_mini_freq_related_vseq_LP5_4266(p); + } + else if(p->freq_sel==LP5_DDR5500) + { + mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP5_5500 \n")); + CInit_golden_mini_freq_related_vseq_LP5_5500(p); + } + else + { + mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP5_3200 \n")); + CInit_golden_mini_freq_related_vseq_LP5_3200(p); + CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(p); + } + } + #endif + + RESETB_PULL_DN(p); + ANA_init(p); + DIG_STATIC_SETTING(p); + DIG_CONFIG_SHUF(p,0,0); //temp ch0 group 0 + + if(!is_lp5_family(p)) + { + LP4_UpdateInitialSettings(p); + } + else + { + LP5_UpdateInitialSettings(p); + } + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); +} +DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) +{ +#ifdef FOR_HQA_REPORT_USED + if (gHQALog_flag==1) + { + mcSHOW_DBG_MSG(("[HQA] Log parsing, ")); + mcSHOW_DBG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n")); + } +#endif + mcSHOW_DBG_MSG(("MEM_TYPE=%d, freq_sel=%d\n", MEM_TYPE, p->freq_sel)); + SV_BroadcastOn_DramcInit(p); // @Darren, Broadcast Off after SV_BroadcastOn_DramcInit done + #if PRINT_CALIBRATION_SUMMARY + //default set DRAM status = NO K + memset(p->aru4CalResultFlag, 0xffff, sizeof(p->aru4CalResultFlag)); + memset(p->aru4CalExecuteFlag, 0, sizeof(p->aru4CalExecuteFlag)); + #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK + memset(p->FastKResultFlag, 0xffff, sizeof(p->FastKResultFlag)); + memset(p->FastKExecuteFlag, 0, sizeof(p->FastKExecuteFlag)); + #endif + #endif + + EnableDramcPhyDCM(p, DCM_OFF); //Let CLK always free-run + vResetDelayChainBeforeCalibration(p); + + if(!is_lp5_family(p)) + DVFSSettings(p); + + vSetRank(p, RANK_0); + //LP4_DRAM_INIT(p); + Dramc8PhaseCal(p); + DramcInit_DutyCalibration(p); + DramcModeRegInit_LP4(p); + + DDRPhyFreqMeter(); + + DdrUpdateACTiming(p); + + memset(p->isWLevInitShift, FALSE, sizeof(p->isWLevInitShift)); + + #if BYPASS_CALIBRATION + if(p->freq_sel==LP4_DDR4266 || p->freq_sel==LP4_DDR3200) + { + Apply_LP4_4266_Calibraton_Result(p); + } + + else if(p->freq_sel==LP4_DDR1600) + { + mcSHOW_DBG_MSG(("BYPASS CALIBRATION LP4 1600 \n")); + Apply_LP4_1600_Calibraton_Result(p); + } + #endif + +#if 0//__A60868_TO_BE_PORTING__ + + U32 save_ch, dram_t; //Darren + #if (!__ETT__ && !FOR_DV_SIMULATION_USED && SW_CHANGE_FOR_SIMULATION == 0) + EMI_SETTINGS *emi_set; //Darren + #endif + U8 dram_cbt_mode; + + mcSHOW_DBG_MSG(("\n[DramcInit]\n")); + + vSetPHY2ChannelMapping(p, CHANNEL_A); + + //default set DRAM status = NO K + memset(p->aru4CalResultFlag, 0xffff, sizeof(p->aru4CalResultFlag)); + memset(p->aru4CalExecuteFlag, 0, sizeof(p->aru4CalExecuteFlag)); + + DramcSetting_Olympus_LP4_ByteMode(p); + + DramcInit_DutyCalibration(p); + + DramcModeRegInit_LP4(p); + + //DdrUpdateACTiming(p); + +#if 0 //update refresh rate + // for free-run clk 26MHz, 0x62 * (1/26) = 3.8ns + vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0x62, DRAMC_PD_CTRL_REFCNT_FR_CLK); + // for non-fre-run clk, reg = 3.8 ns * f / 4 / 16; + u4RefreshRate = 38 * p->frequency / 640; + vIO32WriteFldAlign_All(DRAMC_REG_CONF2, u4RefreshRate, CONF2_REFCNT); +#endif + +#if (fcFOR_CHIP_ID == fcLafite) + // For kernel api for check LPDDR3/4/4X (Darren), only for fcOlympus and fcElbrus. + // For Other chip, please confirm the register is free for SW use. + save_ch = vGetPHY2ChannelMapping(p); + vSetPHY2ChannelMapping(p, CHANNEL_A); + + switch (p->dram_type) + { + case TYPE_LPDDR4: + dram_t = 2; + break; + case TYPE_LPDDR4X: + dram_t = 3; + break; + case TYPE_LPDDR4P: + dram_t = 4; + break; + default: + dram_t = 0; + mcSHOW_ERR_MSG(("Incorrect DRAM Type!\n")); + break; + } + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), dram_t, ARBCTL_RSV_DRAM_TYPE); + + // For DRAM normal, byte and mixed mode + if ((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + dram_cbt_mode = CBT_R0_R1_NORMAL; + else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1)) + dram_cbt_mode = CBT_R0_R1_BYTE; + else if ((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1)) + dram_cbt_mode = CBT_R0_NORMAL_R1_BYTE; + else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) + dram_cbt_mode = CBT_R0_BYTE_R1_NORMAL; + else + dram_cbt_mode = CBT_R0_R1_NORMAL; + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RSTMASK), dram_cbt_mode, RSTMASK_RSV_DRAM_CBT_MIXED); + + // Sagy: Keep original setting till OS kernel ready, if ready, remove it + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), (p->dram_cbt_mode[RANK_0] | p->dram_cbt_mode[RANK_1]), ARBCTL_RSV_DRAM_CBT); + + vSetPHY2ChannelMapping(p, save_ch); +#endif + + mcSHOW_DBG_MSG3(("[DramcInit] Done\n")); +#endif//__A60868_TO_BE_PORTING__ + return DRAM_OK; +} + +#if ENABLE_TMRRI_NEW_MODE +void SetCKE2RankIndependent(DRAMC_CTX_T *p) +{ + #if ENABLE_TMRRI_NEW_MODE//Newly added CKE control mode API + mcSHOW_DBG_MSG(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON\n")); + vCKERankCtrl(p, CKE_RANK_INDEPENDENT); + #else //Legacy individual CKE control register settings + mcSHOW_DBG_MSG(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: OFF\n")); + vCKERankCtrl(p, CKE_RANK_DEPENDENT); + #endif +} +#endif + + +#if ENABLE_WRITE_DBI +void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p) +{ + U8 channel_idx, rank_idx; + U8 ch_backup, rank_backup, u1FSPIdx = 0; + + ch_backup = p->channel; + rank_backup = p->rank; + + for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) + { + vSetPHY2ChannelMapping(p, channel_idx); + for (rank_idx = RANK_0; rank_idx < p->support_rank_num; rank_idx++) + { + vSetRank(p, rank_idx); + for (u1FSPIdx = FSP_0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++) + { + DramcMRWriteFldAlign(p, 13, u1FSPIdx, MR13_FSP_WR, TO_MR); + SetDramModeRegForWriteDBIOnOff(p, u1FSPIdx, p->DBI_W_onoff[u1FSPIdx]); + } + } + } + + vSetRank(p, rank_backup); + vSetPHY2ChannelMapping(p, ch_backup); +} +#endif + +#if ENABLE_READ_DBI +void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p) +{ + U8 channel_idx, rank_idx; + U8 ch_backup, rank_backup, u1FSPIdx = 0; + S8 u1ShuffleIdx; + + ch_backup = p->channel; + rank_backup = p->rank; + + for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) + { + vSetPHY2ChannelMapping(p, channel_idx); + for (rank_idx = RANK_0; rank_idx < p->support_rank_num; rank_idx++) + { + vSetRank(p, rank_idx); + for (u1FSPIdx = FSP_0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++) + { + DramcMRWriteFldAlign(p, 13, u1FSPIdx, MR13_FSP_WR, TO_MR); + SetDramModeRegForReadDBIOnOff(p, u1FSPIdx, p->DBI_R_onoff[u1FSPIdx]); + } + } + } + + //[Ei_ger] DVT item RD2MRR & MRR2RD + vIO32WriteFldMulti_All(DRAMC_REG_HW_MRR_FUN, P_Fld(0x1, HW_MRR_FUN_TR2MRR_ENA) + | P_Fld(0x1, HW_MRR_FUN_R2MRRHPRICTL) + | P_Fld(0x1, HW_MRR_FUN_MANTMRR_EN)); + + vSetRank(p, rank_backup); + vSetPHY2ChannelMapping(p, ch_backup); +} +#endif + + +static void SetMr13VrcgToNormalOperationShuffle(DRAMC_CTX_T *p)//Only set DRAM_DFS_SHUFFLE_1 +{ + + U32 u4Value = 0; + + //DVFS MRW + u4Value = u4IO32ReadFldAlign(DRAMC_REG_SHU_HWSET_VRCG, SHU_HWSET_VRCG_HWSET_VRCG_OP); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, u4Value & ~(0x1 << 3), SHU_HWSET_VRCG_HWSET_VRCG_OP); + return; +} + +void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p) +{ + + DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p); + DRAM_RANK_T eOriRank = u1GetRank(p); + U8 u1ChIdx = CHANNEL_A; + U8 u1RankIdx = 0; + +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + + + for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++) + { + vSetPHY2ChannelMapping(p, u1ChIdx); + //To DRAM: MR13[3] = 0 + for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + DramcMRWriteFldAlign(p, 13, 0, MR13_VRCG, TO_MR); + } + } + vSetPHY2ChannelMapping(p, (U8)eOriChannel); + vSetRank(p, (U8)eOriRank); + return; +} + +static void DramcShuTrackingDcmEnBySRAM(DRAMC_CTX_T *p) +{ +#if (fcFOR_CHIP_ID == fcA60868) + U8 u1ShuffleIdx, ShuRGAccessIdxBak; + U32 u4DramcShuOffset = 0; + U32 u4DDRPhyShuOffset = 0; + + ShuRGAccessIdxBak = p->ShuRGAccessIdx; + mcSHOW_DBG_MSG(("\n==[DramcShuTrackingDcmEnBySRAM]==\n")); + for (u1ShuffleIdx = 0; u1ShuffleIdx <= 1; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX) + { + //Aceess DMA SRAM by APB bus use debug mode by conf SHU3 + u4DramcShuOffset = 0; + u4DDRPhyShuOffset = 0; + p->ShuRGAccessIdx = u1ShuffleIdx; + #ifdef HW_GATING + //DramcHWGatingOnOff(p, 1, u4DramcShuOffset); // Enable HW gating tracking + #endif + + #if ENABLE_TX_TRACKING + Enable_TX_Tracking(p, u4DramcShuOffset); + #endif + + #if RDSEL_TRACKING_EN + Enable_RDSEL_Tracking(p, u4DramcShuOffset); + #endif + + #ifdef HW_GATING + Enable_Gating_Tracking(p, u4DDRPhyShuOffset); // Enable HW gating tracking + #endif + } + p->ShuRGAccessIdx = ShuRGAccessIdxBak; +#else + DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable; // from dramc conf shu0 + U8 u1ShuffleIdx; + U32 u4DramcShuOffset = 0; + U32 u4DDRPhyShuOffset = 0; + U16 u2Freq = 0; + + U32 u4RegBackupAddress[] = + { + (DDRPHY_REG_MISC_SRAM_DMA0), + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR), +#if (CHANNEL_NUM==4) + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR), + (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR), +#endif + }; + + //Backup regs + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + #if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE) + Enable_and_Trigger_TX_Retry(p); + #endif + + //Aceess DMA SRAM by APB bus use debug mode by conf SHU3 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); + + for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX) + { + if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX) + { + //for SHU0 restore to SRAM + vSetDFSTable(p, pFreqTable);//Restore DFS table + //Restore regs, or SHU0 RG cannot be set + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;//Since access conf SHU0 + } + else + { + //Aceess DMA SRAM by APB bus use debug mode by conf SHU1 + vSetDFSTable(p, get_FreqTbl_by_shuffleIndex(p, u1ShuffleIdx));//Update DFS table + u2Freq = GetFreqBySel(p, p->pDFSTable->freq_sel); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, u1ShuffleIdx, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); + //APB bus use debug mode by conf SHU1 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);//Trigger DEBUG MODE + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; + } + // add your function + // For example: EnableDramcPhyDCMShuffle(p, enable_dcm, u4DramcShuOffset, u4DDRPhyShuOffset, u1ShuffleIdx); +#if ENABLE_TX_TRACKING + Enable_TX_Tracking(p, u4DramcShuOffset); +#endif +#if RDSEL_TRACKING_EN + Enable_RDSEL_Tracking(p, u4DramcShuOffset); +#endif +#ifdef HW_GATING + Enable_Gating_Tracking(p, u4DDRPhyShuOffset); // Enable HW gating tracking +#endif +#if ENABLE_RX_DCM_DPHY + EnableRxDcmDPhy(p, u4DDRPhyShuOffset, u2Freq); +#endif + Enable_ClkTxRxLatchEn(p, u4DDRPhyShuOffset); // for new xrank mode +#if ENABLE_TX_WDQS // @Darren, To avoid unexpected DQS toggle during calibration + Enable_TxWDQS(p, u4DDRPhyShuOffset, u2Freq); +#endif + +#if (SW_CHANGE_FOR_SIMULATION == 0) +#if APPLY_LOWPOWER_GOLDEN_SETTINGS + int enable_dcm = (doe_get_config("dramc_dcm")) ? 0 : 1; + EnableDramcPhyDCMShuffle(p, enable_dcm, u4DramcShuOffset, u4DDRPhyShuOffset); +#else + EnableDramcPhyDCMShuffle(p, 0, u4DramcShuOffset, u4DDRPhyShuOffset); +#endif +#endif + SetMr13VrcgToNormalOperationShuffle(p); + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + } +#endif +} + +#if (ENABLE_PER_BANK_REFRESH == 1) +void DramcEnablePerBankRefresh(DRAMC_CTX_T *p, bool en) +{ + if (en) + { + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_PBREF_BK_REFA_ENA) | P_Fld(2, REFCTRL0_PBREF_BK_REFA_NUM)); + + #if PER_BANK_REFRESH_USE_MODE==0 + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); //Original mode + mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Original Mode\n")); + #endif + + #if PER_BANK_REFRESH_USE_MODE==1 + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(1, REFCTRL0_KEEP_PBREF_OPT)); //Hybrid mode + mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Hybrid Mode\n")); + #endif + + #if PER_BANK_REFRESH_USE_MODE==2 + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); //Always per-bank mode + mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Always Per-Bank Mode\n")); + #endif + + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPB2AB_IGZQCS); + } + + #if IMP_TRACKING_PB_TO_AB_REFRESH_WA + // disable all shu pb-ref + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0, SHU_CONF0_PBREFEN); + #else + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, en, SHU_CONF0_PBREFEN); + #endif +} +#endif + +#ifdef TEMP_SENSOR_ENABLE +void DramcHMR4_Presetting(DRAMC_CTX_T *p) +{ + U8 backup_channel = p->channel; + U8 channelIdx; + + for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++) + { + vSetPHY2ChannelMapping(p, channelIdx); + // vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), Refr_rate_manual_trigger, REFCTRL1_REFRATE_MANUAL_RATE_TRIG); + // vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), Refr_rate_manual, REFCTRL1_REFRATE_MANUAL); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFR_PERIOD_OPT); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_REFRCNT_OPT); // 0: 3.9us * cnt, 1: 15.6us * cnt + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HMR4_DVFS_CTRL0), 0x80, SHU_HMR4_DVFS_CTRL0_REFRCNT); + + // Support byte mode, default disable + // Support byte/normal mode + if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_HMR4_BYTEMODE_EN); + else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_HMR4_BYTEMODE_EN); + + // Toggle to clear record + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 0, REFCTRL1_REFRATE_MON_CLR); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 1, REFCTRL1_REFRATE_MON_CLR); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 0, REFCTRL1_REFRATE_MON_CLR); + } + vSetPHY2ChannelMapping(p, backup_channel); + +} +#endif + +static void SwitchHMR4(DRAMC_CTX_T *p, bool en) +{ +#ifdef __LP5_COMBO__ + if (is_lp5_family(p)) + { + vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 9, REF_BOUNCE2_PRE_MR4INT_TH); + + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL2, 9, REFCTRL2_MR4INT_TH); + + } + else +#endif + { + vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 5, REF_BOUNCE2_PRE_MR4INT_TH); + + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL2, 5, REFCTRL2_MR4INT_TH); + } + + // TOG_OPT, 0: Read rank0 only, 1: read both rank0 and rank1 + if (en && p->support_rank_num == RANK_DUAL) + vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 1, HMR4_HMR4_TOG_OPT); // Read both rank0 and rank1 + else + vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0, HMR4_HMR4_TOG_OPT); // Read rank0 only (need for manual/SW MRR) + + vIO32WriteFldAlign_All(DRAMC_REG_HMR4, !en, HMR4_REFRDIS); + +#if 0 // Reading HMR4 repeatedly for debugging + while(1) + { + mcSHOW_DBG_MSG(("@@ --------------------\n")); + mcSHOW_DBG_MSG(("@@ MISC_STATUSA_REFRESH_RATE: %d\n", + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_RATE))); + mcSHOW_DBG_MSG(("@@ MIN: %d, MAX: %d\n", + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MIN_MON), + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MAX_MON))); + + // if HMR4_HMR4_TOG_OPT == 1 + { + mcSHOW_DBG_MSG(("@@ MIN MAX\n")); + mcSHOW_DBG_MSG(("@@ RK0_B0: %d %d\n", + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK0_B0), + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK0_B0))); + mcSHOW_DBG_MSG(("@@ RK1_B0: %d %d\n", + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK1_B0), + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK1_B0))); + mcSHOW_DBG_MSG(("@@ RK0_B1: %d %d\n", + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK0_B1), + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK0_B1))); + mcSHOW_DBG_MSG(("@@ RK1_B1: %d %d\n", + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK1_B1), + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK1_B1))); + } + + mcSHOW_DBG_MSG(("@@ Wait to measure!!\n\n")); + Sleep(500); + } +#endif +} + +#if ENABLE_REFRESH_RATE_DEBOUNCE +static void DramcRefreshRateDeBounceEnable(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti_All(DRAMC_REG_REF_BOUNCE1, P_Fld(0x4 , REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT) | // when De-bounce counter >= this count, then dramc apply new dram's MR4 value + P_Fld(5 , REF_BOUNCE1_REFRATE_DEBOUNCE_TH) | // MR4 value >= 0.5X refresh rate, then de-bounce count active + P_Fld(0 , REF_BOUNCE1_REFRATE_DEBOUNCE_OPT) | + P_Fld(0xff1f , REF_BOUNCE1_REFRATE_DEBOUNCE_DIS) ); //all bits set 1 to disable debounce function +} +#endif + +#if DRAMC_MODIFIED_REFRESH_MODE +void DramcModifiedRefreshMode(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti_All(DRAMC_REG_REFPEND1, P_Fld(2, REFPEND1_MPENDREFCNT_TH0) + | P_Fld(2, REFPEND1_MPENDREFCNT_TH1) + | P_Fld(4, REFPEND1_MPENDREFCNT_TH2) + | P_Fld(5, REFPEND1_MPENDREFCNT_TH3) + | P_Fld(5, REFPEND1_MPENDREFCNT_TH4) + | P_Fld(3, REFPEND1_MPENDREFCNT_TH5) + | P_Fld(3, REFPEND1_MPENDREFCNT_TH6) + | P_Fld(3, REFPEND1_MPENDREFCNT_TH7)); + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL1, P_Fld(1, REFCTRL1_REFPEND_OPT1) | P_Fld(1, REFCTRL1_REFPEND_OPT2)); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_REF0, 4, SHU_REF0_MPENDREF_CNT); +} +#endif + +#if DRAMC_CKE_DEBOUNCE +void DramcCKEDebounce(DRAMC_CTX_T *p) +{ + U8 u1CKE_DBECnt = 15; + U8 rank_backup, u1RKIdx=0; + if(p->frequency>=1866) + { + rank_backup = p->rank; + for(u1RKIdx=0; u1RKIdx<p->support_rank_num; u1RKIdx++) + { + vSetRank(p, u1RKIdx); + vIO32WriteFldAlign_All(DRAMC_REG_SHURK_CKE_CTRL, u1CKE_DBECnt, SHURK_CKE_CTRL_CKE_DBE_CNT); + mcSHOW_DBG_MSG(("CKE Debounce cnt = %d\n", u1CKE_DBECnt)); + } + vSetRank(p, rank_backup); + } +} +#endif + +//1.Some RG setting will need to be DCM on, since not consider S0 2.ENABLE_RX_DCM_DPHY should be 1 +static void S0_DCMOffWA(DRAMC_CTX_T *p)//For S0 + DCM off +{ + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) | + P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE)); +} + +void DramcRunTimeConfig(DRAMC_CTX_T *p) +{ +#if (fcFOR_CHIP_ID == fcA60868) + u1EnterRuntime = 1; +#endif + + mcSHOW_DBG_MSG(("[DramcRunTimeConfig]\n")); + + SetDramInfoToConf(p); + +#if defined(DPM_CONTROL_AFTERK) && ((DRAMC_DFS_MODE%2) != 0) // for MD32 RG/PST mode + DPMInit(p); + mcSHOW_DBG_MSG(("DPM_CONTROL_AFTERK: ON\n")); +#else + mcSHOW_DBG_MSG(("!!! DPM_CONTROL_AFTERK: OFF\n")); + mcSHOW_DBG_MSG(("!!! DPM could not control APHY\n")); +#endif + +#if ENABLE_PER_BANK_REFRESH + #if IMP_TRACKING_PB_TO_AB_REFRESH_WA + // enable pb-ref for current shu + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0x1, SHU_CONF0_PBREFEN); + #endif + mcSHOW_DBG_MSG(("PER_BANK_REFRESH: ON\n")); +#else + mcSHOW_DBG_MSG(("PER_BANK_REFRESH: OFF\n")); +#endif + +///TODO:KIWI +#if __A60868_TO_BE_PORTING__ + +#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION + if (vGet_DDR800_Mode(p) == DDR800_SEMI_LOOP) + { + EnableDllCg(p, ENABLE); //open CG to save power + } +#endif + +#endif //__A60868_TO_BE_PORTING__ + +#if REFRESH_OVERHEAD_REDUCTION + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA); + mcSHOW_DBG_MSG(("REFRESH_OVERHEAD_REDUCTION: ON\n")); +#else + mcSHOW_DBG_MSG(("REFRESH_OVERHEAD_REDUCTION: OFF\n")); +#endif + +#if CMD_PICG_NEW_MODE + mcSHOW_DBG_MSG(("CMD_PICG_NEW_MODE: ON\n")); +#else + mcSHOW_DBG_MSG(("CMD_PICG_NEW_MODE: OFF\n")); +#endif + +#if XRTWTW_NEW_CROSS_RK_MODE + if (p->support_rank_num == RANK_DUAL) + { + //ENABLE_XRTWTW_Setting(p); // @Darren, DV codes is included + mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: ON\n")); + } +#else + mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: OFF\n")); +#endif + +#if XRTRTR_NEW_CROSS_RK_MODE + if (p->support_rank_num == RANK_DUAL) + { + //ENABLE_XRTRTR_Setting(p); // @Darren, DV codes is included + mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: ON\n")); + } +#else + mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: OFF\n")); +#endif + +#if ENABLE_TX_TRACKING + mcSHOW_DBG_MSG(("TX_TRACKING: ON\n")); +#else + mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n")); +#endif + +#if RDSEL_TRACKING_EN + mcSHOW_DBG_MSG(("RDSEL_TRACKING: ON\n")); +#else + mcSHOW_DBG_MSG(("RDSEL_TRACKING: OFF\n")); +#endif + +#if TDQSCK_PRECALCULATION_FOR_DVFS + mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: ")); + /* Maoauo: Enable DQS precalculation for LP4, disable for LP3(same as Kibo) */ + DramcDQSPrecalculation_enable(p); + mcSHOW_DBG_MSG(("ON\n")); +#else + mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: OFF\n")); +#endif + +#if ENABLE_RX_TRACKING + DramcRxInputDelayTrackingInit_Common(p); + DramcRxInputDelayTrackingHW(p); + mcSHOW_DBG_MSG(("RX_TRACKING: ON\n")); +#else + mcSHOW_DBG_MSG(("RX_TRACKING: OFF\n")); +#endif + +#if (ENABLE_RX_TRACKING && RX_DLY_TRACK_ONLY_FOR_DEBUG && defined(DUMMY_READ_FOR_TRACKING)) + mcSHOW_DBG_MSG(("RX_DLY_TRACK_DBG: ON\n")); + DramcRxDlyTrackDebug(p); +#endif + +/* HW gating - Disabled by default(in preloader) to save power (DE: HJ Huang) */ +#if (defined(HW_GATING)) + mcSHOW_DBG_MSG(("HW_GATING DBG: ON\n")); + DramcHWGatingDebugOnOff(p, ENABLE); +#else + mcSHOW_DBG_MSG(("HW_GATING DBG: OFF\n")); + DramcHWGatingDebugOnOff(p, DISABLE); +#endif + +#ifdef ZQCS_ENABLE_LP4 + // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first +#if (fcFOR_CHIP_ID == fcPetrus) + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB); + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB); + + mcDELAY_US(1); + + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_B << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB); + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_C << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB); +#elif (fcFOR_CHIP_ID == fcMargaux) + vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET1, 1, ZQ_SET1_ZQCALDISB);// LP3 and LP4 are different, be careful. +#endif + mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: ON\n")); +#else + vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET1, 0, ZQ_SET1_ZQCALDISB);// LP3 and LP4 are different, be careful. + mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: OFF\n")); +#endif + +///TODO:JEREMY +#if 0 +#ifdef DUMMY_READ_FOR_DQS_GATING_RETRY + DummyReadForDqsGatingRetryNonShuffle(p, 1); + mcSHOW_DBG_MSG(("DUMMY_READ_FOR_DQS_GATING_RETRY: ON\n")); +#else + DummyReadForDqsGatingRetryNonShuffle(p, 0); + mcSHOW_DBG_MSG(("DUMMY_READ_FOR_DQS_GATING_RETRY: OFF\n")); +#endif +#endif + +#if RX_PICG_NEW_MODE + mcSHOW_DBG_MSG(("RX_PICG_NEW_MODE: ON\n")); +#else + mcSHOW_DBG_MSG(("RX_PICG_NEW_MODE: OFF\n")); +#endif + +#if TX_PICG_NEW_MODE + TXPICGNewModeEnable(p); + mcSHOW_DBG_MSG(("TX_PICG_NEW_MODE: ON\n")); +#else + mcSHOW_DBG_MSG(("TX_PICG_NEW_MODE: OFF\n")); +#endif + +#if ENABLE_RX_DCM_DPHY + mcSHOW_DBG_MSG(("ENABLE_RX_DCM_DPHY: ON\n")); +#else + mcSHOW_DBG_MSG(("ENABLE_RX_DCM_DPHY: OFF\n")); +#endif + +#if (SW_CHANGE_FOR_SIMULATION == 0) +#if APPLY_LOWPOWER_GOLDEN_SETTINGS + int enable_dcm = (doe_get_config("dramc_dcm"))? 0: 1; + const char *str = (enable_dcm == 1)? ("ON") : ("OFF"); +// EnableDramcPhyDCM(p, enable_dcm); + EnableDramcPhyDCMNonShuffle(p, enable_dcm); + mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): %s\n", str)); + + if(enable_dcm == 0) + { + S0_DCMOffWA(p);//For S0 + DCM off + } + +#else +// EnableDramcPhyDCM(p, DCM_OFF); + EnableDramcPhyDCMNonShuffle(p, 0); + mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): OFF\n")); + + S0_DCMOffWA(p);//For S0 + DCM off +#endif +#endif + +//DumpShuRG(p); + + + +#if 1 + DramcShuTrackingDcmEnBySRAM(p); +#endif + + +//Dummy read should NOT be enabled before gating tracking +#ifdef DUMMY_READ_FOR_TRACKING + DramcDummyReadForTrackingEnable(p); +#else + mcSHOW_DBG_MSG(("DUMMY_READ_FOR_TRACKING: OFF\n")); +#endif + + +#ifdef SPM_CONTROL_AFTERK + DVFS_PRE_config(p); + TransferToSPMControl(p); + mcSHOW_DBG_MSG(("SPM_CONTROL_AFTERK: ON\n")); +#else + mcSHOW_DBG_MSG(("!!! SPM_CONTROL_AFTERK: OFF\n")); + mcSHOW_DBG_MSG(("!!! SPM could not control APHY\n")); +#endif + +// when time profiling multi times, SW impedance tracking will fail when trakcing enable. +// ignor SW impedance tracking when doing time profling +#ifndef DDR_INIT_TIME_PROFILING +#ifdef IMPEDANCE_TRACKING_ENABLE + if (p->dram_type == TYPE_LPDDR4 || p->dram_type == TYPE_LPDDR4X) + { + DramcImpedanceTrackingEnable(p); + mcSHOW_DBG_MSG(("IMPEDANCE_TRACKING: ON\n")); + +#ifdef IMPEDANCE_HW_SAVING + DramcImpedanceHWSaving(p); +#endif + } +#else + mcSHOW_DBG_MSG(("IMPEDANCE_TRACKING: OFF\n")); +#endif +#endif + + //0x1c0[31] + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSCAL0), 0, DQSCAL0_STBCALEN); + +#ifdef TEMP_SENSOR_ENABLE + SwitchHMR4(p, ON); + mcSHOW_DBG_MSG(("TEMP_SENSOR: ON\n")); +#else + SwitchHMR4(p, OFF); + mcSHOW_DBG_MSG(("TEMP_SENSOR: OFF\n")); +#endif + +#ifdef HW_SAVE_FOR_SR + mcSHOW_DBG_MSG(("HW_SAVE_FOR_SR: ON, no implementation\n")); +#else + mcSHOW_DBG_MSG(("HW_SAVE_FOR_SR: OFF\n")); +#endif + +#ifdef CLK_FREE_FUN_FOR_DRAMC_PSEL + ClkFreeRunForDramcPsel(p); + mcSHOW_DBG_MSG(("CLK_FREE_FUN_FOR_DRAMC_PSEL: ON\n")); +#else + mcSHOW_DBG_MSG(("CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF\n")); +#endif + +#if PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER + DramcPAImprove(p); + mcSHOW_DBG_MSG(("PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON\n")); +#else + mcSHOW_DBG_MSG(("PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF\n")); +#endif + +#if ENABLE_RODT_TRACKING + mcSHOW_DBG_MSG(("Read ODT Tracking: ON\n")); +#else + mcSHOW_DBG_MSG(("Read ODT Tracking: OFF\n")); +#endif + +#if ENABLE_REFRESH_RATE_DEBOUNCE + mcSHOW_DBG_MSG(("Refresh Rate DeBounce: ON\n")); + DramcRefreshRateDeBounceEnable(p); +#endif + +#if ENABLE_DVFS_BYPASS_MR13_FSP + DFSBypassMR13HwSet(p); +#endif + + +#if (CHECK_GOLDEN_SETTING == TRUE) + DRAM_STATUS_T stResult = CheckGoldenSetting(p); + mcSHOW_DBG_MSG(("End of run time ==>Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG"))); +#endif + +#if DFS_NOQUEUE_FLUSH_WA + EnableDFSNoQueueFlush(p); + mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH: ON\n")); +#else + mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH: OFF\n")); +#endif + +#if DFS_NOQUEUE_FLUSH_LATENCY_CNT + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_FSM_CFG, 1, LPIF_FSM_CFG_DBG_LATENCY_CNT_EN); + // MD32 clock is 208M + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_SSPM_MCLK_DIV, P_Fld(0, SSPM_MCLK_DIV_MCLK_SRC) + | P_Fld(0, SSPM_MCLK_DIV_MCLK_DIV)); + mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: ON\n")); +#else + mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF\n")); +#endif + +#if ENABLE_DFS_RUNTIME_MRW + DFSRuntimeFspMRW(p); + mcSHOW_DBG_MSG(("ENABLE_DFS_RUNTIME_MRW: ON\n")); +#else + mcSHOW_DBG_MSG(("ENABLE_DFS_RUNTIME_MRW: OFF\n")); +#endif + + //CheckRxPICGNewModeSetting(p); + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x0, REFCTRL0_REFDIS); //After k, auto refresh should be enable + +#if DDR_RESERVE_NEW_MODE + mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: ON\n")); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DDR_RESERVE, P_Fld(1, MISC_DDR_RESERVE_WDT_LITE_EN) | P_Fld(0, MISC_DDR_RESERVE_WDT_SM_CLR)); +#else + mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: OFF\n")); + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DDR_RESERVE, P_Fld(0, MISC_DDR_RESERVE_WDT_LITE_EN) | P_Fld(1, MISC_DDR_RESERVE_WDT_SM_CLR)); +#endif + +#if MR_CBT_SWITCH_FREQ + mcSHOW_DBG_MSG(("MR_CBT_SWITCH_FREQ: ON\n")); +#else + mcSHOW_DBG_MSG(("MR_CBT_SWITCH_FREQ: OFF\n")); +#endif + + mcSHOW_DBG_MSG(("=========================\n")); +} + +#if 0 //no use? +void DramcTest_DualSch_stress(DRAMC_CTX_T *p) +{ + U32 count = 0; + U16 u2Value = 0; + +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + + //vIO32WriteFldAlign_All(DRAMC_REG_PERFCTL0, 1, PERFCTL0_DUALSCHEN); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCHEDULER, 1, SHU_SCHEDULER_DUALSCHEN); + + while (count < 10) + { + count++; + + u1MR12Value[p->channel][p->rank][p->dram_fsp] = 0x14; + DramcModeRegWriteByRank(p, p->rank, 12, u1MR12Value[p->channel][p->rank][p->dram_fsp]); + DramcModeRegReadByRank(p, p->rank, 12, &u2Value); + //mcSHOW_DBG_MSG(("MR12 = 0x%0X\n", u1Value)); + } +} +#endif + +#if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE) +void SPMTx_Track_Retry_OnOff(DRAMC_CTX_T *p, U8 shu_level, U8 onoff) +{ + static U8 gIsddr800TxRetry = 0; + + // MCK still available for DRAMC RG access from Joe comment + if (shu_level == SRAM_SHU6) + { + gIsddr800TxRetry = 1; + } + + if ((gIsddr800TxRetry == 1) && (shu_level != SRAM_SHU6)) //Need to do tx retry when DDR800 -> DDr1200 + { + if (onoff == ENABLE) + { + mcSHOW_DBG_MSG(("TX track retry: ENABLE! (DDR800 to DDR1200)\n")); + vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK); + mcDELAY_US(1); + #if TX_RETRY_CONTROL_BY_SPM + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN); + #else //control by DRAMC + vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_EN); + #endif + } + else //DISABLE + { + mcSHOW_DBG_MSG(("TX track retry: DISABLE! (DDR800 to DDR1200)\n")); + #if TX_RETRY_CONTROL_BY_SPM + vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN); + #else //control by DRAMC + vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_EN); + #endif + mcDELAY_US(1); //add 1us delay to wait emi and tx retry be done (because PPR_CTRL_TX_RETRY_SHU_RESP_OPT=1) + vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK); //enable block emi to let tx retry be finish + gIsddr800TxRetry = 0; + } + } +} + +#if SW_TX_RETRY_ENABLE +void SWTx_Track_Retry_OnOff(DRAMC_CTX_T *p) +{ + U8 u4Response; + + mcSHOW_DBG_MSG(("SW TX track retry!\n")); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 1, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 1, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN); + do + { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_TX_RETRY_DONE_RESPONSE); + mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + mcSHOW_DBG_MSG3(("still wait tx retry be done\n", u4Response)); + }while (u4Response == 0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK); +} +#endif +#endif + +// The "ENABLE_RANK_NUMBER_AUTO_DETECTION" use this API +void DFSInitForCalibration(DRAMC_CTX_T *p) +{ +#ifdef DDR_INIT_TIME_PROFILING + U32 CPU_Cycle; + mcSHOW_TIME_MSG(("*** Data rate %d ***\n\n", p->frequency << 1)); + + TimeProfileBegin(); +#endif + + u1PrintModeRegWrite = 1; + +#if MRW_BACKUP + U8 u1RKIdx; + + for(u1RKIdx=0; u1RKIdx<p->support_rank_num; u1RKIdx++) + { + gFSPWR_Flag[u1RKIdx]=p->dram_fsp; + } +#endif + + DramcInit(p); + u1PrintModeRegWrite = 0; + vBeforeCalibration(p); + +#ifdef DUMP_INIT_RG_LOG_TO_DE + while (1); +#endif + + +#if ENABLE_DUTY_SCAN_V2 +#ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle = TimeProfileEnd(); + mcSHOW_TIME_MSG((" (1) DFSInitForCalibration() take %d ms\n\n", (CPU_Cycle / 1000) - gu4DutyCalibrationTime)); + mcSHOW_TIME_MSG((" (2) DramcNewDutyCalibration take %d ms\n\r", gu4DutyCalibrationTime)); +#endif +#endif + +#ifndef DUMP_INIT_RG_LOG_TO_DE + #ifdef ENABLE_MIOCK_JMETER + if ((Get_MDL_Used_Flag()==NORMAL_USED) && (p->frequency >= 800)) + { + Get_RX_DelayCell(p); + } + #endif +#endif + +#if !__ETT__ + if (p->frequency >= 1333) +#endif + { +#ifdef DDR_INIT_TIME_PROFILING + TimeProfileBegin(); +#endif + +#ifndef DUMP_INIT_RG_LOG_TO_DE + #ifdef ENABLE_MIOCK_JMETER + if (Get_MDL_Used_Flag()==NORMAL_USED) + { + PRE_MIOCK_JMETER_HQA_USED(p); + } + #endif +#endif + +#ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG((" (3) JMeter takes %d ms\n\r", CPU_Cycle / 1000)); +#endif + } + +} + +#if 0 /* cc mark to use DV initial setting */ +void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p) +{ +#ifdef HW_GATING +#if DramcHWDQSGatingTracking_FIFO_MODE + //REFUICHG=0, STB_SHIFT_DTCOUT_IG=0, DQSG_MODE=1, NARROW_IG=0 + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), + P_Fld(1, MISC_STBCAL_STB_DQIEN_IG) | + P_Fld(1, MISC_STBCAL_PICHGBLOCK_NORD) | + P_Fld(0, MISC_STBCAL_REFUICHG) | + P_Fld(0, MISC_STBCAL_PHYVALID_IG) | + P_Fld(0, MISC_STBCAL_STBSTATE_OPT) | + P_Fld(0, MISC_STBCAL_STBDLELAST_FILTER) | + P_Fld(0, MISC_STBCAL_STBDLELAST_PULSE) | + P_Fld(0, MISC_STBCAL_STBDLELAST_OPT) | + P_Fld(1, MISC_STBCAL_PIMASK_RKCHG_OPT)); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), + P_Fld(1, MISC_STBCAL1_STBCAL_FILTER) | + //cc mark P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) | + P_Fld(1, MISC_STBCAL1_STB_SHIFT_DTCOUT_IG)); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0), + P_Fld(1, MISC_CTRL0_R_DMDQSIEN_FIFO_EN) | + P_Fld(0, MISC_CTRL0_R_DMVALID_DLY) | + P_Fld(0, MISC_CTRL0_R_DMVALID_DLY_OPT) | + P_Fld(0, MISC_CTRL0_R_DMVALID_NARROW_IG)); + //cc mark P_Fld(0, MISC_CTRL0_R_DMDQSIEN_SYNCOPT)); + + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), + 0, B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), + 0, B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), + 0, CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL); + +#else + //REFUICHG=0, STB_SHIFT_DTCOUT_IG=0, DQSG_MODE=1, NARROW_IG=0 + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), + P_Fld(1, MISC_STBCAL_STB_DQIEN_IG) | + P_Fld(1, MISC_STBCAL_PICHGBLOCK_NORD) | + P_Fld(0, MISC_STBCAL_REFUICHG) | + P_Fld(0, MISC_STBCAL_PHYVALID_IG) | + P_Fld(0, MISC_STBCAL_STBSTATE_OPT) | + P_Fld(0, MISC_STBCAL_STBDLELAST_FILTER) | + P_Fld(0, MISC_STBCAL_STBDLELAST_PULSE) | + P_Fld(0, MISC_STBCAL_STBDLELAST_OPT) | + P_Fld(1, MISC_STBCAL_PIMASK_RKCHG_OPT)); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), + P_Fld(1, MISC_STBCAL1_STBCAL_FILTER) | + //cc mark P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) | + P_Fld(0, MISC_STBCAL1_STB_SHIFT_DTCOUT_IG)); + + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0), + P_Fld(0, MISC_CTRL0_R_DMDQSIEN_FIFO_EN) | + P_Fld(3, MISC_CTRL0_R_DMVALID_DLY) | + P_Fld(1, MISC_CTRL0_R_DMVALID_DLY_OPT) | + P_Fld(0, MISC_CTRL0_R_DMVALID_NARROW_IG)); + //cc mark P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT)); + + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), + 1, B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), + 1, B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), + 1, CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL); +#endif +#endif +} +#endif + +#if TX_PICG_NEW_MODE +#if 0 +void GetTXPICGSetting(DRAMC_CTX_T * p) +{ + U32 u4DQS_OEN_final, u4DQ_OEN_final; + U16 u2DQS_OEN_2T[2], u2DQS_OEN_05T[2], u2DQS_OEN_Delay[2]; + U16 u2DQ_OEN_2T[2], u2DQ_OEN_05T[2], u2DQ_OEN_Delay[2]; + U16 u2COMB_TX_SEL[2]; + U16 u2Shift_Div[2]; + U16 u2COMB_TX_PICG_CNT; + U8 u1CHIdx, u1RankIdx, u1Rank_bak = u1GetRank(p), u1backup_CH = vGetPHY2ChannelMapping(p), u1Div_ratio; + + mcSHOW_DBG_MSG(("****** GetTXPICGSetting DDR[%d] @@@\n", p->frequency * 2)); + + for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++) + { + vSetPHY2ChannelMapping(p, u1CHIdx); + //Set TX DQS PICG + //DQS0 + u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0);//m + u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0);//n + //DQS1 + u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);//m + u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);//n + + mcSHOW_DBG_MSG(("CH%d\n", u1CHIdx)); + mcSHOW_DBG_MSG(("DQS0 m=%d n=%d \n", u2DQS_OEN_2T[0], u2DQS_OEN_05T[0])); + mcSHOW_DBG_MSG(("DQS1 m=%d n=%d \n", u2DQS_OEN_2T[1], u2DQS_OEN_05T[1])); + + + + u2COMB_TX_SEL[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0); + u2COMB_TX_SEL[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1); + u2COMB_TX_PICG_CNT = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT); + + mcSHOW_DBG_MSG(("TX_DQS_SEL_P0 %d \n", u2COMB_TX_SEL[0])); + mcSHOW_DBG_MSG(("TX_DQS_SEL_P1 %d \n", u2COMB_TX_SEL[1])); + mcSHOW_DBG_MSG(("COMB_TX_PICG_CNT %d \n", u2COMB_TX_PICG_CNT)); + + //Set TX RK0 and RK1 DQ PICG + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + mcSHOW_DBG_MSG(("Rank%d\n", u1RankIdx)); + + vSetRank(p, u1RankIdx); + //DQ0 + u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0);//p + u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0);//q + //DQ1 + u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);//p + u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1);//q + + mcSHOW_DBG_MSG(("DQ0 p=%d q=%d \n", u2DQ_OEN_2T[0], u2DQ_OEN_05T[0])); + mcSHOW_DBG_MSG(("DQ1 p=%d q=%d \n", u2DQ_OEN_2T[1], u2DQ_OEN_05T[1])); + + u2COMB_TX_SEL[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0); + u2COMB_TX_SEL[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1); + + mcSHOW_DBG_MSG(("TX_DQ_RK_SEL_P0 %d \n", u2COMB_TX_SEL[0])); + mcSHOW_DBG_MSG(("TX_DQ_RK_SEL_P1 %d \n", u2COMB_TX_SEL[1])); + } + vSetRank(p, u1Rank_bak); + } + vSetPHY2ChannelMapping(p, u1backup_CH); +} +#endif + +#define ADD_1UI_TO_APHY 1 //After A60-868/Pe-trus +void TXPICGSetting(DRAMC_CTX_T * p) +{ + U32 u4DQS_OEN_final, u4DQ_OEN_final; + U16 u2DQS_OEN_2T[2], u2DQS_OEN_05T[2], u2DQS_OEN_Delay[2]; + U16 u2DQ_OEN_2T[2], u2DQ_OEN_05T[2], u2DQ_OEN_Delay[2]; + U16 u2COMB_TX_SEL[2]; + U16 u2Shift_DQS_Div[2]; + U16 u2Shift_DQ_Div[2]; + U16 u2COMB_TX_PICG_CNT; + U8 u1CHIdx, u1RankIdx, u1Rank_bak = u1GetRank(p), u1backup_CH = vGetPHY2ChannelMapping(p), u1Div_ratio; + + u2COMB_TX_PICG_CNT = 3;//After Pe-trus, could detect HW OE=1 -> 0 automatically, and prolong TX picg + if (vGet_Div_Mode(p) == DIV8_MODE) + { + u2Shift_DQS_Div[0] = 10;//phase 0 + u2Shift_DQS_Div[1] = 6;//phase 1 + u2Shift_DQ_Div[0] = 8;//phase 0 + u2Shift_DQ_Div[1] = 4;//phase 1 + u1Div_ratio = 3; + } + else //DIV4_MODE + { + u2Shift_DQS_Div[0] = 2;//phase 0 + u2Shift_DQS_Div[1] = 0;//phase 1, no use + u2Shift_DQ_Div[0] = 0;//phase 0 + u2Shift_DQ_Div[1] = 0;//phase 1, no use + u1Div_ratio = 2; + } + + for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++) + { + vSetPHY2ChannelMapping(p, u1CHIdx); + //Set TX DQS PICG + //DQS0 + u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0);//m + u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0);//n + u2DQS_OEN_Delay[0] = (u2DQS_OEN_2T[0] << u1Div_ratio) + u2DQS_OEN_05T[0]; + //DQS1 + u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);//m + u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);//n + u2DQS_OEN_Delay[1] = (u2DQS_OEN_2T[1] << u1Div_ratio) + u2DQS_OEN_05T[1]; + + u4DQS_OEN_final = (u2DQS_OEN_Delay[0] > u2DQS_OEN_Delay[1])? u2DQS_OEN_Delay[1]: u2DQS_OEN_Delay[0]; //choose minimum value + u4DQS_OEN_final += ADD_1UI_TO_APHY; + + + u2COMB_TX_SEL[0] = (u4DQS_OEN_final > u2Shift_DQS_Div[0])? ((u4DQS_OEN_final - u2Shift_DQS_Div[0]) >> u1Div_ratio): 0; + + if (vGet_Div_Mode(p) == DIV4_MODE) + u2COMB_TX_SEL[1] = 0; + else + u2COMB_TX_SEL[1] = (u4DQS_OEN_final > u2Shift_DQS_Div[1])? ((u4DQS_OEN_final - u2Shift_DQS_Div[1]) >> u1Div_ratio): 0; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) + | P_Fld(u2COMB_TX_SEL[1], SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) + | P_Fld(u2COMB_TX_PICG_CNT, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT)); + //Set TX RK0 and RK1 DQ PICG + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + //DQ0 + u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); + u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0); + u2DQ_OEN_Delay[0] = (u2DQ_OEN_2T[0] << u1Div_ratio) + u2DQ_OEN_05T[0]; + //DQ1 + u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); + u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1); + u2DQ_OEN_Delay[1] = (u2DQ_OEN_2T[1] << u1Div_ratio) + u2DQ_OEN_05T[1]; + + + u4DQ_OEN_final = (u2DQ_OEN_Delay[0] > u2DQ_OEN_Delay[1])? u2DQ_OEN_Delay[1]: u2DQ_OEN_Delay[0]; //choose minimum value + u4DQ_OEN_final += ADD_1UI_TO_APHY; + + u2COMB_TX_SEL[0] = (u4DQ_OEN_final > u2Shift_DQ_Div[0])? ((u4DQ_OEN_final - u2Shift_DQ_Div[0]) >> u1Div_ratio): 0; + + if (vGet_Div_Mode(p) == DIV4_MODE) + u2COMB_TX_SEL[1] = 0; + else + u2COMB_TX_SEL[1] = (u4DQ_OEN_final > u2Shift_DQ_Div[1])? ((u4DQ_OEN_final - u2Shift_DQ_Div[1]) >> u1Div_ratio): 0; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) + | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); + } + vSetRank(p, u1Rank_bak); + } + vSetPHY2ChannelMapping(p, u1backup_CH); +} +#endif + + +#if RX_PICG_NEW_MODE +void RXPICGSetting(DRAMC_CTX_T * p) +{ + DRAM_RANK_T bkRank = u1GetRank(p); + U8 u1RankIdx = 0; + + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 0, MISC_SHU_STBCAL_STBCALEN); + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 0, MISC_SHU_STBCAL_STB_SELPHCALEN); + + //PI_CG_DQSIEN new mode + vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL1, 1, MISC_STBCAL1_STBCNT_SHU_RST_EN); + vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE); + + //APHY control new mode + vIO32WriteFldAlign(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL, 1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT); + vIO32WriteFldAlign(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL, 1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT); + + //Dummy code (based on DVT document Verification plan of RX PICG efficiency improvment.docx) + //No need to set since HW setting or setting in other place + //Pls. don't remove for the integrity + { + U8 u1TAIL_LAT = (vGet_Div_Mode(p) == DIV4_MODE) ? 1: 0; + vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0, MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN); + + for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)//Should set 2 rank + { + vSetRank(p, u1RankIdx); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL, P_Fld(u1TAIL_LAT, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT) + | P_Fld(0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT)); + } + vSetRank(p, bkRank); + + vIO32WriteFldMulti(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL, P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN) + | P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN) + | P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN)); + + vIO32WriteFldMulti(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL, P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN) + | P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN) + | P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN)); + + } +#if 0 + vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0, STBCAL2_STB_STBENRST_EARLY_1T_EN); + vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(u1TAIL_LAT, SHU_STBCAL_R1_DQSIEN_PICG_TAIL_EXT_LAT) + | P_Fld(0, SHU_STBCAL_R1_DQSIEN_PICG_HEAD_EXT_LAT) + | P_Fld(u1TAIL_LAT, SHU_STBCAL_R0_DQSIEN_PICG_TAIL_EXT_LAT) + | P_Fld(0, SHU_STBCAL_R0_DQSIEN_PICG_HEAD_EXT_LAT)); + vIO32WriteFldMulti(DRAMC_REG_PHY_RX_INCTL, P_Fld(0, PHY_RX_INCTL_DIS_IN_BUFF_EN) + | P_Fld(0, PHY_RX_INCTL_FIX_IN_BUFF_EN) + | P_Fld(0, PHY_RX_INCTL_RX_IN_BUFF_EN_4BYTE_EN) + | P_Fld(0, PHY_RX_INCTL_DIS_IN_GATE_EN) + | P_Fld(0, PHY_RX_INCTL_FIX_IN_GATE_EN) + | P_Fld(0, PHY_RX_INCTL_RX_IN_GATE_EN_4BYTE_EN)); +#endif +} +#endif + +#ifndef DPM_CONTROL_AFTERK +void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p) +{ +#if !__ETT__ + //set for SPM DRAM self refresh + vIO32WriteFldAlign(SPM_POWERON_CONFIG_EN, 1, POWERON_CONFIG_EN_BCLK_CG_EN); + vIO32WriteFldAlign(SPM_DRAMC_DPY_CLK_SW_CON_2, 1, SPM_DRAMC_DPY_CLK_SW_CON_2_SW_PHYPLL_MODE_SW); + vIO32WriteFldAlign(SPM_POWER_ON_VAL0, 1, SPM_POWER_ON_VAL0_SC_PHYPLL_MODE_SW); +#endif + //Preloader exit with legacy mode for CTP load used + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN); +} +#endif + +#if TX_PICG_NEW_MODE +void TXPICGNewModeEnable(DRAMC_CTX_T * p) +{ + //Switch TX PICG to new mode + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3, P_Fld(0, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT) + | P_Fld(0, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT) + | P_Fld(0, MISC_CTRL3_ARPI_CG_DQS_OPT) + | P_Fld(0, MISC_CTRL3_ARPI_CG_DQ_OPT)); +} +#endif + +#if ENABLE_WRITE_DBI_Protect +void ApplyWriteDBIProtect(DRAMC_CTX_T *p, U8 onoff) +{ +#if __A60868_TO_BE_PORTING__ + U8 *uiLPDDR_O1_Mapping; + U16 Temp_PinMux_MaskWrite_WriteDBIOn = 0; + U8 B0_PinMux_MaskWrite_WriteDBIOn = 0, B1_PinMux_MaskWrite_WriteDBIOn = 0; + int DQ_index; + + uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel]; + + // Write DMI/DBI Protect Function + // Byte0 can not have bit swap between Group1(DQ0/1) and Group2(DQ02~DQ07). + // Byte1 can not have bit swap between Group1(DQ8/9) and Group2(DQ10~DQ15). + // DBIWR_IMP_EN=1 and DBIWR_PINMUX_EN=1 + // set DBIWR_OPTB0[7:0] meet with Byte0 pin MUX table. + // set DBIWR_OPTB1[7:0] meet with Byte1 pin MUX table. + + for (DQ_index = 0; DQ_index < 16; DQ_index++) + { + Temp_PinMux_MaskWrite_WriteDBIOn |= ((0x7C7C >> uiLPDDR_O1_Mapping[DQ_index]) & 0x1) << DQ_index; + } + B1_PinMux_MaskWrite_WriteDBIOn = (U8)(Temp_PinMux_MaskWrite_WriteDBIOn >> 8) & 0xff; + B0_PinMux_MaskWrite_WriteDBIOn = (U8) Temp_PinMux_MaskWrite_WriteDBIOn & 0xff; + + vIO32WriteFldMulti_All(DRAMC_REG_ARBCTL, P_Fld(B1_PinMux_MaskWrite_WriteDBIOn, ARBCTL_DBIWR_OPT_B1) + | P_Fld(B0_PinMux_MaskWrite_WriteDBIOn, ARBCTL_DBIWR_OPT_B0) + | P_Fld(onoff, ARBCTL_DBIWR_PINMUX_EN) + | P_Fld(onoff, ARBCTL_DBIWR_IMP_EN)); +#endif +} +#endif + +#if ENABLE_WRITE_DBI +void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff) +{ + + // set DBIWR_IMP_EN = 1 + // DBIWR_OPTB0[1:0]=0, DBIWR_OPT_B0[7]=0 + // DBIWR_OPTB1[1:0]=0, DBIWR_OPT_B1[7]=0 + vIO32WriteFldMulti_All(DRAMC_REG_DBIWR_PROTECT, P_Fld(0, DBIWR_PROTECT_DBIWR_OPT_B1) + | P_Fld(0, DBIWR_PROTECT_DBIWR_OPT_B0) + | P_Fld(0, DBIWR_PROTECT_DBIWR_PINMUX_EN) + | P_Fld(onoff, DBIWR_PROTECT_DBIWR_IMP_EN)); +} +/* DDR800 mode struct declaration (declared here due Fld_wid for each register type) */ +/* +typedef struct _DDR800Mode_T +{ + U8 dll_phdet_en_b0: Fld_wid(SHU_B0_DLL0_RG_ARDLL_PHDET_EN_B0_SHU); + U8 dll_phdet_en_b1: Fld_wid(SHU_B1_DLL0_RG_ARDLL_PHDET_EN_B1_SHU); + U8 dll_phdet_en_ca_cha: Fld_wid(SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU); + U8 dll_phdet_en_ca_chb: Fld_wid(SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU); + U8 phypll_ada_mck8x_en: Fld_wid(SHU_PLL22_RG_RPHYPLL_ADA_MCK8X_EN_SHU); + U8 ddr400_en_b0: Fld_wid(SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0); + U8 ddr400_en_b1: Fld_wid(SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1); + U8 ddr400_en_ca: Fld_wid(SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA); + U8 phypll_ddr400_en: Fld_wid(SHU_PLL1_RG_RPHYPLL_DDR400_EN); + U8 ddr400_dqs_ps_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_DQS_PS_B0); + U8 ddr400_dqs_ps_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_DQS_PS_B1); + U8 ddr400_dq_ps_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_DQ_PS_B0); + U8 ddr400_dq_ps_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_DQ_PS_B1); + U8 ddr400_dqs_ps_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_DQS_PS_CA); + U8 ddr400_dq_ps_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_DQ_PS_CA); + U8 ddr400_semi_en_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_SEMI_EN_B0); + U8 ddr400_semi_en_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_SEMI_EN_B1); + U8 ddr400_semi_en_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_SEMI_EN_CA); + U8 ddr400_semi_open_en: Fld_wid(SHU_PLL0_RG_DDR400_SEMI_OPEN_EN); + U8 pll0_ada_mck8x_chb_en: Fld_wid(SHU_PLL0_ADA_MCK8X_CHB_EN); + U8 pll0_ada_mck8x_cha_en: Fld_wid(SHU_PLL0_ADA_MCK8X_CHA_EN); +} DDR800Mode_T; +*/ +#endif + + +void RODTSettings(DRAMC_CTX_T *p) +{ + U8 u1VrefSel; + U8 u1RankIdx, u1RankIdxBak; + + //VREF_EN + vIO32WriteFldAlign(DDRPHY_REG_B0_DQ5, 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); + vIO32WriteFldAlign(DDRPHY_REG_B1_DQ5, 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); + + //Update related setting of APHY RX and ODT + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_VREF, !(p->odt_onoff), SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_VREF, !(p->odt_onoff), SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); + + if(p->odt_onoff==ODT_ON) + { + if (p->dram_type==TYPE_LPDDR5) + u1VrefSel = 0x46;//term LP5 + else + u1VrefSel = 0x2c;//term LP4 + } + else + { + if (p->dram_type==TYPE_LPDDR5) + u1VrefSel = 0x37;//unterm LP5 + else + u1VrefSel = 0x37;//unterm LP4 + } + + u1RankIdxBak = u1GetRank(p); + for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++) + { + vSetRank(p, u1RankIdx); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_PHY_VREF_SEL, + P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | + P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_PHY_VREF_SEL, + P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) | + P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1)); + } + vSetRank(p, u1RankIdxBak); + + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_VREF, 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_VREF, 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1); + +#if ENABLE_TX_WDQS + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 1, MISC_SHU_ODTCTRL_RODTEN); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ7, 1, SHU_B0_DQ7_R_DMRODTEN_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ7, 1, SHU_B1_DQ7_R_DMRODTEN_B1); +#else + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, p->odt_onoff, MISC_SHU_ODTCTRL_RODTEN); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ7, p->odt_onoff, SHU_B0_DQ7_R_DMRODTEN_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ7, p->odt_onoff, SHU_B1_DQ7_R_DMRODTEN_B1); +#endif + +#if ENABLE_RODT_TRACKING + //RODT tracking + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) + | P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) + | P_Fld(0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME)); +#endif + + //Darren-vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, !(p->odt_onoff), B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0); + //Darren-vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, !(p->odt_onoff), B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1); + //Darren-vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, !(p->odt_onoff), CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ13, !(p->odt_onoff), SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ13, !(p->odt_onoff), SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1); + vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD13, !(p->odt_onoff), SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA); + + //APHY CG disable + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13, P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) + | P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ14, 0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0); + + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13, P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) + | P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1)); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ14, 0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1); +} + +/* LP4 use 7UI mode (1) + * LP5 lower than 4266 use 7UI mode (1) + * LP5 higher than 4266 use 11UI mode (2) + * LP5 higher than 4266 with better SI use 11/24UI mode (3) + */ +void DQSSTBSettings(DRAMC_CTX_T *p) +{ + unsigned int dqsien_mode = 1; + +#if (__LP5_COMBO__) + U8 rpre_mode = LPDDR5_RPRE_4S_0T; + + if (is_lp5_family(p)) + { + if (p->frequency > 1600) + rpre_mode = LPDDR5_RPRE_2S_2T; + } + + if (rpre_mode == LPDDR5_RPRE_2S_2T) + dqsien_mode = 2; + else if (rpre_mode == LPDDR5_RPRE_XS_4T) + dqsien_mode = 3; +#endif + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + dqsien_mode, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10), + dqsien_mode, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10), + dqsien_mode, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1); +} + +static void SetMck8xLowPwrOption(DRAMC_CTX_T *p) +{ +#if ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION + U32 u4Mck8xMode = 1; +#else + U32 u4Mck8xMode = 0; +#endif + + vIO32WriteFldMulti(DDRPHY_REG_MISC_LP_CTRL, P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL ) \ + | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL ) \ + | P_Fld( u4Mck8xMode, MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL ) \ + | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL ) \ + | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL) \ + | P_Fld( u4Mck8xMode, MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL ) \ + | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL )); + +} + +void LP4_UpdateInitialSettings(DRAMC_CTX_T *p) +{ + U8 u1RankIdx, u1RankIdxBak; + ///TODO: + //BRINGUP-TEST + vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL3, 0, MISC_CTRL3_ARPI_CG_CLK_OPT); + vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, 0, MISC_CTRL4_R_OPT2_CG_CLK); + + //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA) | P_Fld(0, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA)); + //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCLKB_OE_TIE_EN_CA) | P_Fld(0, CA_CMD2_RG_TX_ARCLKB_OE_TIE_SEL_CA)); + //Set_MRR_Pinmux_Mapping(p); //Update MRR pinmux + + vReplaceDVInit(p); + + //Let CA and CS be independent + vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD14, 0xC0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA); //@Darren, confirm with Alucary + //Disable perbyte option + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) + | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) + | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) + | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) + | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1)); + +#if RX_PICG_NEW_MODE + RXPICGSetting(p); +#endif + +#if SIMULATION_SW_IMPED // Darren: Need porting by E2 IMP Calib DVT owner + #if FSP1_CLKCA_TERM + U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ; + #else + U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ; + #endif + U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ; + + if (p->dram_type == TYPE_LPDDR4X) + DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_SHUFFLE_1); +#endif + + DQSSTBSettings(p); + + RODTSettings(p); + + //WDBI-OFF + vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_DBIWR); + +#if CBT_MOVE_CA_INSTEAD_OF_CLK + U8 u1CaPI = 0, u1CaUI = 0; + + u1CaUI = 1; + u1CaPI = 0; + + // CA delay shift u1CaUI*UI + DramcCmdUIDelaySetting(p, u1CaUI); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); + + // Rank0/1 u1CaPI*PI CA delay + + u1RankIdxBak = u1GetRank(p); + + for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++) + { + vSetRank(p, u1RankIdx); + + CBTDelayCACLK(p, u1CaPI); + } + + vSetRank(p, u1RankIdxBak); +#endif + +#if ENABLE_TPBR2PBR_REFRESH_TIMING + vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA); //@Derping + vIO32WriteFldAlign(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA); //@Unique + vIO32WriteFldAlign(DRAMC_REG_SCHEDULER_COM, 0x1, SCHEDULER_COM_PBR2PBR_OPT); //@YH +#endif + +#if RDSEL_TRACKING_EN + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); //DMDATLAT_I should be set as 0 before set datlat k value, otherwise the status flag wil be set as 1 +#endif + +#if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK + vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, p->dram_fsp, SHU_TX_SET0_WPST1P5T); //Set write post-amble by FSP with MR3 +#else + vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_WPST1P5T); //Set write post-amble by FSP with MR3 +#endif + +#if (!XRTRTR_NEW_CROSS_RK_MODE) + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, 0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN); +#endif + + //MP Setting + vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DMYRD_REORDER_DIS) | P_Fld(0x1, DUMMY_RD_SREF_DMYRD_EN)); + vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x0, DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN) + | P_Fld(0x1, DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN) + | P_Fld(0x1, DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN)); + vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 1, MISC_STBCAL2_DQSGCNT_BYP_REF); + //@Darren- enable bit11 via FMeter, vIO32WriteFldAlign(DDRPHY_REG_MISC_CG_CTRL7, 0, MISC_CG_CTRL7_CK_BFE_DCM_EN); + + //1:8 --> data rate<=1600 set 0, data rate<=3200 set 1, else 2 + //1:4 --> data rate<= 800 set 0, data rate<=1600 set 1, else 2 + if(p->frequency<=800) + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD); + else if(p->frequency<=1200) + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD); + else + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD); + vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL1, 1, MISC_CTRL1_R_DMARPIDQ_SW); + vIO32WriteFldMulti(DDRPHY_REG_CA_TX_MCK, P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVP_FRPHY) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVN_FRPHY)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | + P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); + + SetMck8xLowPwrOption(p); +} + + +void LP5_UpdateInitialSettings(DRAMC_CTX_T *p) +{ + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD14, 0x0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA); //Let CA and CS be independent + //Set_MRR_Pinmux_Mapping(p); //Update MRR pinmux + + //Disable perbyte option + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) + | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) + | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0)); + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) + | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) + | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1)); + + ///TODO: Temp solution. May need to resolve in init flow + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5, /* Will cause PI un-adjustable */ + P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) | + P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN)); + + DQSSTBSettings(p); + + RODTSettings(p); + +#if SIMULATION_SW_IMPED + #if FSP1_CLKCA_TERM + U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ; + #else + U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ; + #endif + U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ; + + if (p->dram_type == TYPE_LPDDR5) + DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_SHUFFLE_1); +#endif + +#if RDSEL_TRACKING_EN + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); //DMDATLAT_I should be set as 0 before set datlat k value, otherwise the status flag wil be set as 1 +#endif + +#if (!XRTRTR_NEW_CROSS_RK_MODE) + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, 0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN); +#endif + SetMck8xLowPwrOption(p); +} + +#define CKGEN_FMETER 0x0 +#define ABIST_FMETER 0x1 + +unsigned int DDRPhyFreqMeter(void) +{ +#if 0 //temp remove for bringup +#if (FOR_DV_SIMULATION_USED==0) + + unsigned int reg0=0, reg1=0; + unsigned int before_value=0, after_value=0; + unsigned int frq_result=0; +#if (fcFOR_CHIP_ID == fcMargaux) + unsigned int chb_mctl_ca_en = (DRV_Reg32(Channel_B_DDRPHY_AO_BASE_ADDRESS + 0xBA8) >> 19) & 0x1; +#endif + +#if 1//def HJ_SIM + /*TINFO="\n[PhyFreqMeter]"*/ + + reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c) ; + DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 | (1 << 16)); + reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c) ; + DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 | (1 << 16)); + + // abist_clk29: AD_MPLL_CK + frq_result = FMeter(ABIST_FMETER, 29) ; + mcSHOW_DBG_MSG(("AD_MPLL_CK FREQ=%d\n", frq_result)); + /*TINFO="AD_MPLL_CK FREQ=%d\n", frq_result*/ + + // abist_clk40: DA_MPLL_52M_DIV_CK + //! frq_result = FMeter(ABIST_FMETER, 40) ; + /*TINFO="DA_MPLL_52M_DIV_CK FREQ=%d\n", frq_result*/ + #if 1 + if((DRV_Reg32(Channel_A_DDRPHY_NAO_BASE_ADDRESS + 0x50c) & (1<<8))==0) + { + // abist_clk31: AD_RCLRPLL_DIV4_CK_ch02 + //frq_result = FMeter(ABIST_FMETER, 31) ; + mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result)); + /*TINFO="AD_RCLRPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result*/ + } + else + { + // abist_clk33: AD_RPHYRPLL_DIV4_CK_ch02 + frq_result = FMeter(ABIST_FMETER, 33) ; + mcSHOW_DBG_MSG(("AD_RPHYPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result)); + /*TINFO="AD_RPHYPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result*/ + } + #endif + //! ch0 + reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504) ; + DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11)); + + // abistgen_clk44: fmem_ck_aft_dcm_ch0 (DRAMC CHA's clock after idle mask) + before_value = FMeter(ABIST_FMETER, 44); + mcSHOW_DBG_MSG(("fmem_ck_aft_dcm_ch0 FREQ=%d\n", before_value)); + /*TINFO="fmem_ck_aft_dcm_ch0 FREQ=%d\n", after_value*/ + +#if (fcFOR_CHIP_ID == fcMargaux) + if (chb_mctl_ca_en == 1) +#endif + { + reg0 = DRV_Reg32(Channel_B_DDRPHY_AO_BASE_ADDRESS + 0x504) ; + DRV_WriteReg32 (Channel_B_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11)); + // abistgen_clk45: fmem_ck_aft_dcm_ch1 (DRAMC CHB's clock after idle mask) + after_value = FMeter(ABIST_FMETER, 45); + mcSHOW_DBG_MSG(("fmem_ck_aft_dcm_ch1 FREQ=%d\n", after_value)); + } + /*TINFO="fmem_ck_aft_dcm_ch1 FREQ=%d\n", after_value*/ + + gddrphyfmeter_value = after_value<<2; + + reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c) ; + DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 & ~(1 << 16)); + reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c) ; + DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 & ~(1 << 16)); + + + #if (CHANNEL_NUM>2) + reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c) ; + DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 | (1 << 16)); + reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c) ; + DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 | (1 << 16)); + #if 1 + if((DRV_Reg32(Channel_C_DDRPHY_NAO_BASE_ADDRESS + 0x50c) & (1<<8))==0) + { + // abist_clk32: AD_RCLRPLL_DIV4_CK_ch13 + //frq_result = FMeter(ABIST_FMETER, 32) ; + mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result)); + /*TINFO="AD_RCLRPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result*/ + } + else + { + // abist_clk34: AD_RPHYRPLL_DIV4_CK_ch13 + frq_result = FMeter(ABIST_FMETER, 34) ; + mcSHOW_DBG_MSG(("AD_RPHYPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result)); + /*TINFO="AD_RPHYPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result*/ + } + #endif + + reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504) ; + DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11)); + reg0 = DRV_Reg32(Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504) ; + DRV_WriteReg32 (Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11)); + + // abistgen_clk46: fmem_ck_aft_dcm_ch2 (DRAMC CHC's clock after idle mask) + before_value = FMeter(ABIST_FMETER, 46); + mcSHOW_DBG_MSG(("fmem_ck_aft_dcm_ch2 FREQ=%d\n", before_value)); + /*TINFO="fmem_ck_aft_dcm_ch2 FREQ=%d\n", after_value*/ + + // abistgen_clk47: fmem_ck_aft_dcm_ch3 (DRAMC CHC's clock after idle mask) + after_value = FMeter(ABIST_FMETER, 47); + mcSHOW_DBG_MSG(("fmem_ck_aft_dcm_ch3 FREQ=%d\n", after_value)); + /*TINFO="fmem_ck_aft_dcm_ch3 FREQ=%d\n", after_value*/ + + reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c) ; + DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 & ~(1 << 16)); + reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c) ; + DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 & ~(1 << 16)); + #endif + + return (before_value<<16 | after_value); +#endif //! end DSIM +#endif + +#endif + return 0; +} diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c new file mode 100644 index 0000000000..1181cdca8c --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c @@ -0,0 +1,11121 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//----------------------------------------------------------------------------- +// Include files +//----------------------------------------------------------------------------- +#include "dramc_common.h" +#include "dramc_int_global.h" +#include "x_hal_io.h" +#include "sv_c_data_traffic.h" + +#define BITMAP_BITS_MAX 128 + +#if CBT_MOVE_CA_INSTEAD_OF_CLK +#define MAX_CA_PI_DELAY 95 +#else +#define MAX_CA_PI_DELAY 63 +#endif +#define MAX_CS_PI_DELAY 63 +#define MAX_CLK_PI_DELAY 31 + +#define PASS_RANGE_NA 0x7fff + +#define DIE_NUM_MAX 1 //LP4 only +static U8 fgwrlevel_done = 0; + + +#if __ETT__ +U8 gETT_WHILE_1_flag = 1; +#endif + +U8 u1MR01Value[FSP_MAX]; +U8 u1MR02Value[FSP_MAX]; +U8 u1MR03Value[FSP_MAX]; +U8 u1MR11Value[FSP_MAX]; +U8 u1MR18Value[FSP_MAX]; +U8 u1MR19Value[FSP_MAX]; +U8 u1MR20Value[FSP_MAX]; +U8 u1MR21Value[FSP_MAX]; +U8 u1MR22Value[FSP_MAX]; +U8 u1MR51Value[FSP_MAX]; + +U8 u1MR04Value[RANK_MAX]; +U8 u1MR13Value[RANK_MAX]; +U8 u1MR26Value[RANK_MAX]; +U8 u1MR30Value[RANK_MAX]; + +U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; +U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; +U16 gu2MR0_Value[RANK_MAX] = {0xffff, 0xffff}; + +#if PINMUX_AUTO_TEST_PER_BIT_RX +S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; +#endif +#if PINMUX_AUTO_TEST_PER_BIT_TX +S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; +#endif +#if PINMUX_AUTO_TEST_PER_BIT_CA +S16 gFinalCAPerbitFirstPass[CHANNEL_NUM][RANK_MAX][CATRAINING_NUM_LP4]; +#endif + +#ifdef FOR_HQA_TEST_USED +U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX]; +U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10]; +U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; +U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; +U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX]; +U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX]; +U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX]; +S8 gFinalClkDuty[CHANNEL_NUM]; +U32 gFinalClkDutyMinMax[CHANNEL_NUM][2]; +S8 gFinalDQSDuty[CHANNEL_NUM][DQS_NUMBER]; +U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_NUMBER][2]; +#endif + +U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX]; +U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2]; +U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX]; + +#if defined(RELEASE) +U8 gEye_Scan_color_flag = 0; +U8 gCBT_EYE_Scan_flag = 0; +U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1; +U8 gRX_EYE_Scan_flag = 0; +U8 gRX_EYE_Scan_only_higheset_freq_flag = 1; +U8 gTX_EYE_Scan_flag = 1; +U8 gTX_EYE_Scan_only_higheset_freq_flag = 1; +U8 gEye_Scan_unterm_highest_flag = 0; +#elif (CFG_DRAM_LOG_TO_STORAGE) +U8 gEye_Scan_color_flag = 0; +U8 gCBT_EYE_Scan_flag = 0; +U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1; +U8 gRX_EYE_Scan_flag = 1; +U8 gRX_EYE_Scan_only_higheset_freq_flag = 1; +U8 gTX_EYE_Scan_flag = 1; +U8 gTX_EYE_Scan_only_higheset_freq_flag = 1; +U8 gEye_Scan_unterm_highest_flag = 0; +#else +U8 gEye_Scan_color_flag = 1; +U8 gCBT_EYE_Scan_flag = 0; +U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1; +U8 gRX_EYE_Scan_flag = 0; +U8 gRX_EYE_Scan_only_higheset_freq_flag = 1; +U8 gTX_EYE_Scan_flag = 0; +U8 gTX_EYE_Scan_only_higheset_freq_flag = 1; +U8 gEye_Scan_unterm_highest_flag = 0; +#endif + +#ifdef FOR_HQA_REPORT_USED +#if CFG_DRAM_LOG_TO_STORAGE +U8 gHQALog_flag = 1; +#else +U8 gHQALog_flag = 0; +#endif +U16 gHQALOG_RX_delay_cell_ps_075V = 0; +#endif + +#if (TX_AUTO_K_ENABLE && TX_AUTO_K_WORKAROUND) +U32 u4DQM_MCK_RK1_backup; +U32 u4DQM_UI_RK1_backup; +U32 u4DQM_PI_RK1_backup[2]; +U32 u4DQ_MCK_RK1_backup; +U32 u4DQ_UI_RK1_backup; +U32 u4DQ_PI_RK1_backup[2]; +#endif + +#if SIMULATION_RX_DVS +U8 u1DVS_increase[RANK_MAX][DQS_NUMBER_LP4]; +#endif + +static S32 CATrain_CmdDelay[CHANNEL_NUM][RANK_MAX]; +static U32 CATrain_CsDelay[CHANNEL_NUM][RANK_MAX]; + +static S32 wrlevel_dqs_final_delay[RANK_MAX][DQS_NUMBER]; // 3 is channel number +static U16 u2g_num_dlycell_perT = 49; +U16 u2gdelay_cell_ps; +U16 u2g_num_dlycell_perT_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM];///TODO: to be removed by Francis +U16 u2gdelay_cell_ps_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM];///TODO: to be removed by Francis +U32 u4gVcore[DRAM_DFS_SHUFFLE_MAX]; + +U8 gFinalRXVrefDQForSpeedUp[CHANNEL_NUM][RANK_MAX][2/*ODT_onoff*/][2/*2bytes*/] = {0}; +U32 gDramcSwImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX] = {{0,0,0,0},{0,0,0,0},{0,0,0,0}};//ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN + +S16 gu2RX_DQS_Duty_Offset[DQS_NUMBER][2]; + +#define RX_DELAY_PRE_CAL 1 +#if RX_DELAY_PRE_CAL +S16 s2RxDelayPreCal=PASS_RANGE_NA; +#endif + +#if MRW_CHECK_ONLY +U16 u2MRRecord[CHANNEL_NUM][RANK_MAX][FSP_MAX][MR_NUM]; +#endif +#if MRW_CHECK_ONLY || MRW_BACKUP +U8 gFSPWR_Flag[RANK_MAX]={FSP_0}; +#endif + +#define IN_CBT (0) +#define OUT_CBT (1) + +#if PRINT_CALIBRATION_SUMMARY +static void vSetCalibrationResult(DRAMC_CTX_T *p, U8 ucCalType, U8 ucResult) +{ + U32 *Pointer_CalExecute,*Pointer_CalResult; + if (ucCalType == DRAM_CALIBRATION_SW_IMPEDANCE) + { + Pointer_CalExecute = &p->SWImpCalExecute; + Pointer_CalResult = &p->SWImpCalResult; + } + else + { + Pointer_CalExecute = &p->aru4CalExecuteFlag[p->channel][p->rank]; + Pointer_CalResult = &p->aru4CalResultFlag[p->channel][p->rank]; + } + + if (ucResult == DRAM_FAIL) // Calibration FAIL + { + *Pointer_CalExecute |= (1<<ucCalType); // ececution done + *Pointer_CalResult |= (1<<ucCalType); // no result found + } + else if(ucResult == DRAM_OK) // Calibration OK + { + *Pointer_CalExecute |= (1<<ucCalType); // ececution done + *Pointer_CalResult &= (~(1<<ucCalType)); // result found + } + else if(ucResult == DRAM_FAST_K) // FAST K + { + *Pointer_CalExecute &= (~(1<<ucCalType)); // no ececution + *Pointer_CalResult &= (~(1<<ucCalType)); // result found + } + else // NO K + { + *Pointer_CalExecute &= (~(1<<ucCalType)); // no ececution + *Pointer_CalResult |= (1<<ucCalType); // no result found + } +} + +#if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK +void Fast_K_CheckResult(DRAMC_CTX_T *p, U8 ucCalType) +{ + U32 CheckResult=0xFFFFFFFF; + U32 debug_cnt[2], u4all_result_R, u4all_result_F; + BOOL FastK_Check_flag=0; + U32 *Pointer_FastKExecute,*Pointer_FastKResult; + + Pointer_FastKExecute = &p->FastKExecuteFlag[p->channel][p->rank]; + Pointer_FastKResult = &p->FastKResultFlag[p->channel][p->rank]; + + if ((ucCalType==DRAM_CALIBRATION_TX_PERBIT)||(ucCalType==DRAM_CALIBRATION_DATLAT)||(ucCalType==DRAM_CALIBRATION_RX_PERBIT)) + { + DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); + CheckResult = DramcEngine2Run(p,TE_OP_WRITE_READ_CHECK , TEST_XTALK_PATTERN); + DramcEngine2End(p); + FastK_Check_flag=1; + } + else if (ucCalType==DRAM_CALIBRATION_RX_RDDQC) + { + DramcRxWinRDDQCInit(p); + CheckResult = DramcRxWinRDDQCRun(p); + DramcRxWinRDDQCEnd(p); + FastK_Check_flag=1; + } + else if (ucCalType==DRAM_CALIBRATION_GATING) + { + DramcEngine2Init(p, 0x55000000, 0xaa000000 |0x23, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT); + + //Gating Counter Reset + DramPhyReset(p); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, + MISC_STBCAL2_DQSG_CNT_RST); + mcDELAY_US(1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, + MISC_STBCAL2_DQSG_CNT_RST); + + DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN); + + debug_cnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B0)); + debug_cnt[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B1)); + + //mcSHOW_DBG_MSG((" 0x%X ",u4DebugCnt)) + if (debug_cnt[0]==0x4646 && debug_cnt[1]==0x4646) + CheckResult=0; + + DramcEngine2End(p); + FastK_Check_flag=1; + } + + + if ((FastK_Check_flag==1)&&(CheckResult==0)) + { + //mcSHOW_DBG_MSG((" [FAST K CHECK]->PASS\n")) + *Pointer_FastKResult &= (~(1<<ucCalType)); // result PASS + *Pointer_FastKExecute |= (1<<ucCalType);; // Excuted + } + else if ((FastK_Check_flag==1)&&(CheckResult !=0)) + { + //mcSHOW_DBG_MSG((" [FAST K CHECK]->FAIL\n")) + *Pointer_FastKResult |= (1<<ucCalType); // result FAIL + *Pointer_FastKExecute |= (1<<ucCalType);; // Excuted + } +} +#endif + +const char *szCalibStatusName[DRAM_CALIBRATION_MAX]= +{ + "SW Impedance ", + "DUTY Scan ", + "ZQ Calibration ", + "Jitter Meter ", + "CBT Training ", + "Write leveling ", + "RX DQS gating ", + "RX DQ/DQS(RDDQC) ", + "TX DQ/DQS ", + "RX DATLAT ", + "RX DQ/DQS(Engine)", + "TX OE ", +}; + +void vPrintCalibrationResult(DRAMC_CTX_T *p) +{ + U8 ucCHIdx, ucRankIdx, ucCalIdx; + U32 ucCalResult_All, ucCalExecute_All; + U8 ucCalResult, ucCalExecute; + U8 u1CalibrationFail; + + mcSHOW_DBG_MSG(("\n\n[Calibration Summary] %d Mbps\n", p->frequency * 2)); + + //for(ucFreqIdx=0; ucFreqIdx<DRAM_DFS_SHUFFLE_MAX; ucFreqIdx++) + { + //mcSHOW_DBG_MSG(("==Freqency = %d==\n", get_FreqTbl_by_shuffleIndex(p,ucFreqIdx)->frequency)); + for(ucCHIdx=0; ucCHIdx<p->support_channel_num; ucCHIdx++) + { + for(ucRankIdx=0; ucRankIdx<p->support_rank_num; ucRankIdx++) + { + u1CalibrationFail =0; + ucCalExecute_All = p->aru4CalExecuteFlag[ucCHIdx][ucRankIdx]; + ucCalResult_All = p->aru4CalResultFlag[ucCHIdx][ucRankIdx]; + mcSHOW_DBG_MSG(("CH %d, Rank %d\n", ucCHIdx, ucRankIdx)); + //mcSHOW_DBG_MSG(("[vPrintCalibrationResult] Channel = %d, Rank= %d, Freq.= %d, (ucCalExecute_All 0x%x, ucCalResult_All 0x%x)\n", ucCHIdx, ucRankIdx, ucFreqIdx, ucCalExecute_All, ucCalResult_All)); + + for(ucCalIdx =0; ucCalIdx<DRAM_CALIBRATION_MAX; ucCalIdx++) + { + if(ucCalIdx==0) + { + ucCalExecute = (U8)p->SWImpCalExecute; //for SW Impedence + ucCalResult = (U8)p->SWImpCalResult; //for SW Impedence + } + else + { + ucCalExecute = (U8)((ucCalExecute_All >>ucCalIdx) & 0x1); + ucCalResult = (U8)((ucCalResult_All >>ucCalIdx) & 0x1); + } + + #if PRINT_CALIBRATION_SUMMARY_DETAIL + mcSHOW_DBG_MSG(("%s: ", szCalibStatusName[ucCalIdx])) + if(ucCalExecute==1 && ucCalResult ==1) // excuted and fail + { + u1CalibrationFail =1; + mcSHOW_DBG_MSG(("%s\n", "@_@FAIL@_@")) + } + else if (ucCalExecute==1 && ucCalResult ==0) // DRAM_OK + { + mcSHOW_DBG_MSG(("%s\n", "PASS")) + } + else if (ucCalExecute==0 && ucCalResult ==0) // DRAM_FAST K + { + mcSHOW_DBG_MSG(("%s\n", "FAST K")) + } + else //DRAM_NO K + { + mcSHOW_DBG_MSG(("%s\n", "NO K")) + } + + #else + if(ucCalExecute==1 && ucCalResult ==1) // excuted and fail + { + u1CalibrationFail =1; + mcSHOW_DBG_MSG(("%s: %s\n", szCalibStatusName[ucCalIdx],"@_@FAIL@_@")) + } + #endif + } + + if(u1CalibrationFail ==0) + { + mcSHOW_DBG_MSG(("All Pass.\n")); + } + mcSHOW_DBG_MSG(("\n")); + } + } + } + +} +#endif + +#if __FLASH_TOOL_DA__ +#define CA_THRESHOLD 20 +#define RX_THRESHOLD 150 +#define TX_THRESHOLD 20 +#define PERCENTAGE_THRESHOLD 50 +#define PRINT_WIN_SIZE 0 +U8* print_Impedence_LOG_type(U8 print_type) +{ + switch (print_type) + { + case 0: return "DRVP"; + case 1: return "DRVN"; + case 2: return "ODTP"; + case 3: return "ODTN"; + default: return "ERROR"; + } +} +void vPrintPinInfoResult(DRAMC_CTX_T *p) +{ + U8 u1CHIdx, u1RankIdx, u1CAIdx, u1ByteIdx, u1ByteIdx_DQ, u1BitIdx, u1BitIdx_DQ, u1FreqRegionIdx, u1ImpIdx; + U8 u1PinError=0; + mcSHOW_DBG_MSG(("\n\n[Pin Info Summary] Freqency %d\n", p->frequency)); + for (u1FreqRegionIdx=0;u1FreqRegionIdx<2/*IMP_VREF_MAX*/;u1FreqRegionIdx++) + { + for (u1ImpIdx=0;u1ImpIdx<IMP_DRV_MAX;u1ImpIdx++) + { + mcSHOW_DBG_MSG(("IMP %s type:%s %s\n", u1FreqRegionIdx?"Region1":"Region0", print_Impedence_LOG_type(u1ImpIdx), ((PINInfo_flashtool.IMP_ERR_FLAG>>(u1FreqRegionIdx*4+u1ImpIdx)&0x1)?"ERROR":"PASS"))); + } + } + { + for(u1CHIdx=0; u1CHIdx<p->support_channel_num; u1CHIdx++) + { + for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) + { + mcSHOW_DBG_MSG(("CH %d, Rank %d\n", u1CHIdx, u1RankIdx)); + for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++) + { + #if 1//Transfer to Percentage + PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]= (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]* 100 + 63) /64; + if ((PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]==0)||(PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]<=PERCENTAGE_THRESHOLD)) + #else + if ((PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]==0)||(PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]<=CA_THRESHOLD)) + #endif + { + PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx] |= (1<<u1CAIdx); + PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2)); + } + mcSHOW_DBG_MSG(("CA %d: %s ", u1CAIdx, ((PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx]>>u1CAIdx)&0x1)?"ERROR":"PASS")); + #if PRINT_WIN_SIZE + mcSHOW_DBG_MSG(("(WIN_SIZE: %d %% )", (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]))); + #endif + mcSHOW_DBG_MSG(("\n")); + } + for (u1BitIdx =0; u1BitIdx <DQ_DATA_WIDTH_LP4; u1BitIdx++) + { + u1ByteIdx = (u1BitIdx>=8?1:0); + u1BitIdx_DQ = uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx]; + u1ByteIdx_DQ = (u1BitIdx_DQ>=8?1:0); + #if 1//Transfer to Percentage + PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx] = ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]* gHQALOG_RX_delay_cell_ps_075V * p->frequency * 2)+ (1000000 - 1)) / 1000000; + if (PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=PERCENTAGE_THRESHOLD) + #else + if ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=RX_THRESHOLD)\ + ||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=TX_THRESHOLD)) + #endif + { + PINInfo_flashtool.DQ_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] |= (1<<(u1BitIdx-(u1ByteIdx==1?8:0))); + PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ] |= (1<<(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0))); + PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2+1)); + } + #if 1//Transfer to Percentage + PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx] = (PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]* 100+ (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32); + if (PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=PERCENTAGE_THRESHOLD) + #else + if ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=RX_THRESHOLD)\ + ||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=TX_THRESHOLD)) + #endif + { + PINInfo_flashtool.DQ_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] |= (1<<(u1BitIdx-(u1ByteIdx==1?8:0))); + PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ] |= (1<<(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0))); + PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2+1)); + } + } + for (u1BitIdx_DQ=0; u1BitIdx_DQ<DQ_DATA_WIDTH_LP4; u1BitIdx_DQ++) + { + u1ByteIdx_DQ = (u1BitIdx_DQ>=8?1:0); + mcSHOW_DBG_MSG(("DRAM DQ %d: RX %s, TX %s ", u1BitIdx_DQ, (((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS"),\ + (((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS"))); + #if PRINT_WIN_SIZE + mcSHOW_DBG_MSG(("(RX WIN SIZE: %d %%, TX WIN SIZE: %d %% )", PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]], PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]])); + #endif + mcSHOW_DBG_MSG(("\n")); + } + } + } + } +} +void vGetErrorTypeResult(DRAMC_CTX_T *p) +{ + U8 u1CHIdx, u1CHIdx_EMI, u1RankIdx, u1CAIdx, u1ByteIdx, u1BitIdx, u1FreqRegionIdx, u1ImpIdx; + mcSHOW_DBG_MSG(("\n[Get Pin Error Type Result]\n")); + if (PINInfo_flashtool.TOTAL_ERR==0 && PINInfo_flashtool.IMP_ERR_FLAG==0)//ALL PASS + { + mcSHOW_DBG_MSG(("ALL PASS\n")); + } + if (PINInfo_flashtool.IMP_ERR_FLAG) + { + mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: Impedance calibration fail\n")); + mcSHOW_DBG_MSG(("Suspect EXTR contact issue\n")); + mcSHOW_DBG_MSG(("Suspect EXTR related resistor contact issue\n")); + } + if ((PINInfo_flashtool.TOTAL_ERR == 0xffff) && (PINInfo_flashtool.WL_ERR_FLAG== 0xff)) + { + mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: ALL calibration fail\n")); + mcSHOW_DBG_MSG(("Suspect RESET_N contact issue\n")); + mcSHOW_DBG_MSG(("Suspect DRAM Power (VDD1/VDD2/VDDQ) contact issue\n")); + } + else + { + for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++) + { + #if (CHANNEL_NUM > 2) + if(u1CHIdx == CHANNEL_B) + u1CHIdx_EMI = CHANNEL_C; + else if(u1CHIdx == CHANNEL_C) + u1CHIdx_EMI = CHANNEL_B; + else //CHANNEL_A,CHANNEL_D + #endif + u1CHIdx_EMI = u1CHIdx; + if ((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4) & 0xf) == 0xf) + { + mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d all calibration fail\n",u1CHIdx)); + mcSHOW_DBG_MSG(("Suspect EMI%d_CK_T contact issue\n",u1CHIdx_EMI)); + mcSHOW_DBG_MSG(("Suspect EMI%d_CK_C contact issue\n",u1CHIdx_EMI)); + for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++) + { + mcSHOW_DBG_MSG(("Suspect EMI%d_CA%d contact issue\n",u1CHIdx_EMI,u1CAIdx)); + } + } + else + { + for(u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + if ((((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4+u1RankIdx*2)) & 0x3)==0x3) && \ + (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_0] == 0xff) && \ + (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_1] == 0xff)&& \ + (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_0] == 0xff) && \ + (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_1] == 0xff)) + { + mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d RK%d all calibration fail\n",u1CHIdx,u1RankIdx)); + mcSHOW_DBG_MSG(("Suspect EMI%d_CKE_%d contact issue\n",u1CHIdx_EMI,u1RankIdx)); + mcSHOW_DBG_MSG(("Suspect EMI%d_CS_%d contact issue\n",u1CHIdx_EMI,u1RankIdx)); + } + else + { + for (u1ByteIdx = 0; u1ByteIdx < DQS_NUMBER_LP4; u1ByteIdx++) + { + if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) &&\ + (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff)) + { + mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d RK%d Byte%d WL/Read/Write calibration fail\n",u1CHIdx,u1RankIdx,u1ByteIdx)); + mcSHOW_DBG_MSG(("Suspect EMI%d_DQS%d_T contact issue\n",u1CHIdx_EMI,u1ByteIdx)); + mcSHOW_DBG_MSG(("Suspect EMI%d_DQS%d_C contact issue\n",u1CHIdx_EMI,u1ByteIdx)); + } + else if (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]&&\ + PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]) + { + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) + { + if (((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1)&&\ + ((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1)) + { + mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d RK%d DRAM DQ%d Read/Write fail\n",u1CHIdx,u1RankIdx,u1ByteIdx*8+u1BitIdx)); + mcSHOW_DBG_MSG(("Suspect EMI%d_DQ%d contact issue\n",u1CHIdx_EMI,u1ByteIdx*8+u1BitIdx)); + } + } + } + else if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) ||\ + (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff)) + { + mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d RK%d Byte%d Suspect other special contact or calibration issue\n",u1CHIdx_EMI,u1RankIdx,u1ByteIdx)); + } + } + } + } + } + } + } + mcSHOW_DBG_MSG(("\n")); + return; +} +#endif +void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p) +{ + U8 u1CHIdx, u1RankIdx, u1FSPIdx; + + u1MR01Value[FSP_0] = 0x26; + u1MR01Value[FSP_1] = 0x56; + + u1MR03Value[FSP_0] = 0x31; //Set write post-amble as 0.5 tck + u1MR03Value[FSP_1] = 0x31; //Set write post-amble as 0.5 tck +#ifndef ENABLE_POST_PACKAGE_REPAIR + u1MR03Value[FSP_0] |= 0x4; //MR3 OP[2]=1 for PPR protection enabled + u1MR03Value[FSP_1] |= 0x4; //MR3 OP[2]=1 for PPR protection enabled +#endif +#if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK + u1MR03Value[FSP_1] |= 0x2; //MR3 OP[1]=1 for Set write post-amble as 1.5 tck, support after Eig_er E2 +#endif + u1MR04Value[RANK_0] = 0x3; + u1MR04Value[RANK_1] = 0x3; + + // @Darren, for LP4Y single-end mode + u1MR21Value[FSP_0] = 0x0; + u1MR21Value[FSP_1] = 0x0; + u1MR51Value[FSP_0] = 0x0; + u1MR51Value[FSP_1] = 0x0; + + for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++) + { + u1MR02Value[u1FSPIdx] = 0x1a; + } + + for (u1CHIdx = 0; u1CHIdx < CHANNEL_NUM; u1CHIdx++) + for (u1RankIdx = 0; u1RankIdx < RANK_MAX; u1RankIdx++) + for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++) + { + // MR14 default value, LP4 default 0x4d, LP4X 0x5d + u1MR14Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x18; //0x18: customize for Eig_er + #if FSP1_CLKCA_TERM + u1MR12Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x1b; + #else + u1MR12Value[u1CHIdx][u1RankIdx][u1FSPIdx] = 0x5d; + #endif + #if MRW_CHECK_ONLY + for (u1MRIdx = 0; u1MRIdx < MR_NUM; u1MRIdx++) + u2MRRecord[u1CHIdx][u1RankIdx][u1FSPIdx][u1MRIdx] = 0xffff; + #endif + } + + memset(gu2RX_DQS_Duty_Offset, 0, sizeof(gu2RX_DQS_Duty_Offset)); +} + +const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6] = +{ + { + // for DSC + //CH-A + { + 1, 4, 5, 3, 2, 0 + }, + + #if (CHANNEL_NUM>1) + //CH-B + { + 3, 5, 0, 2, 4, 1 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 5, 0, 4, 3, 1, 2 + }, + //CH-D + { + 2, 5, 3, 0, 4, 1 + }, + #endif + }, + { + // for LPBK + // TODO: need porting + }, + { + // for EMCP + //CH-A + { + 2, 4, 3, 5, 1, 0 + }, + + #if (CHANNEL_NUM>1) + //CH-B + { + 4, 5, 2, 0, 3, 1 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 5, 4, 0, 2, 1, 3 + }, + //CH-D + { + 3, 5, 2, 4, 0, 1 + }, + #endif + } +}; + +//O1 DRAM->APHY +const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = +{ + { + // for DSC + //CH-A + { + 0, 1, 7, 6, 4, 5, 2, 3, + 9, 8, 11, 10, 14, 15, 13, 12 + }, + #if (CHANNEL_NUM>1) + //CH-B + { + 1, 0, 5, 6, 3, 2, 7, 4, + 8, 9, 11, 10, 12, 14, 13, 15 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 0, 1, 7, 6, 4, 5, 2, 3, + 9, 8, 11, 10, 14, 15, 13, 12 + }, + //CH-D + { + 1, 0, 5, 6, 3, 2, 7, 4, + 8, 9, 11, 10, 12, 14, 13, 15 + }, + #endif + }, + { + // for LPBK + // TODO: need porting + }, + { + // for EMCP + //CH-A + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 14, 11, 15, 13, 12 + }, + #if (CHANNEL_NUM>1) + //CH-B + { + 0, 1, 4, 7, 3, 5, 6, 2, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 14, 11, 15, 13, 12 + }, + //CH-D + { + 0, 1, 4, 7, 3, 5, 6, 2, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif + } +}; + +//CA APHY->DRAM +#if (CA_PER_BIT_DELAY_CELL || PINMUX_AUTO_TEST_PER_BIT_CA) +const U8 uiLPDDR5_CA_Mapping_POP[CHANNEL_NUM][7] = +{ + //CH-A + { + 0, 1, 2, 3, 4, 5, 6 + }, + +#if (CHANNEL_NUM>1) + //CH-B + { + 0, 4, 2, 3, 1, 5, 6 + } +#endif +}; + +U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6] = +{ + //CH-A + { + 5, 4, 0, 2, 1, 3 + }, + +#if (CHANNEL_NUM>1) + //CH-B + { + 3, 5, 2, 4, 0, 1 + }, +#endif +#if (CHANNEL_NUM>2) + //CH-C + { + 5, 4, 0, 2, 1, 3 + }, + //CH-D + { + 3, 5, 2, 4, 0, 1 + }, +#endif +}; +#endif + +#if (__LP5_COMBO__) +const U8 uiLPDDR5_O1_Mapping_POP[CHANNEL_NUM][16] = +{ + { + 8, 9, 10, 11, 12, 15, 14, 13, + 0, 1, 2, 3, 4, 7, 6, 5, + }, + + #if (CHANNEL_NUM>1) + { + 8, 9, 10, 11, 12, 15, 14, 13, + 0, 1, 2, 3, 4, 7, 6, 5, + }, + #endif +}; +#endif + +//O1 DRAM->APHY +U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16] = +{ + //CH-A + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 14, 11, 15, 13, 12 + }, + #if (CHANNEL_NUM>1) + //CH-B + { + 0, 1, 4, 7, 3, 5, 6, 2, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 14, 11, 15, 13, 12 + }, + //CH-D + { + 0, 1, 4, 7, 3, 5, 6, 2, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif +}; + +void vBeforeCalibration(DRAMC_CTX_T *p) +{ +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + DramcMRInit_LP5(p); + } + else +#endif + { + //DramcMRInit_LP4(p); + } + +#if SIMULATION_RX_DVS || ENABLE_RX_TRACKING + DramcRxInputDelayTrackingInit_byFreq(p); +#endif + + DramcHWGatingOnOff(p, 0); //disable gating tracking + + CKEFixOnOff(p, CKE_WRITE_TO_ALL_RANK, CKE_FIXON, CKE_WRITE_TO_ALL_CHANNEL); //Let CLK always on during calibration + +#if ENABLE_TMRRI_NEW_MODE + SetCKE2RankIndependent(p); //CKE should be controlled independently +#endif + + //WDBI-OFF + vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_DBIWR); + +#ifdef IMPEDANCE_TRACKING_ENABLE + // set correct setting to control IMPCAL HW Tracking in shuffle RG + // if p->freq >= 1333, enable IMP HW tracking(SHU_DRVING1_DIS_IMPCAL_HW=0), else SHU_DRVING1_DIS_IMPCAL_HW = 1 + U8 u1DisImpHw; + U32 u4TermFreq; + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + u4TermFreq = LP5_MRFSP_TERM_FREQ; + else +#endif + u4TermFreq = LP4_MRFSP_TERM_FREQ; + + u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1; + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS) + | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS) + | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS) + | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS) + | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS)); + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_IMPCAL1, (u1DisImpHw? 0x0:0x40), SHU_MISC_IMPCAL1_IMPCALCNT); + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING1, u1DisImpHw, SHU_MISC_DRVING1_DIS_IMPCAL_HW); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING1, u1DisImpHw, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, u1DisImpHw, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD12, u1DisImpHw, SHU_CA_CMD12_RG_RIMP_UNTERM_EN); +#endif + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) + | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN)); + + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ZQ_SET0, + P_Fld(0x1ff, SHU_ZQ_SET0_ZQCSCNT) | //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 + P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT)); + + if (p->support_channel_num == CHANNEL_SINGLE) + { + //single channel, ZQCSDUAL=0, ZQCSMASK=0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0), P_Fld(0, ZQ_SET0_ZQCSDUAL) | P_Fld(0x0, ZQ_SET0_ZQCSMASK)); + } + else if (p->support_channel_num == CHANNEL_DUAL) + { + // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin. + #ifdef ZQCS_ENABLE_LP4 + // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1 + + vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, P_Fld(1, ZQ_SET0_ZQCSDUAL) | + P_Fld(0, ZQ_SET0_ZQCSMASK_OPT) | + P_Fld(0, ZQ_SET0_ZQMASK_CGAR) | + P_Fld(0, ZQ_SET0_ZQCS_MASK_SEL_CGAR)); + + // DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0. + // ZQCSMASK setting: (Ch A, Ch B) = (1,0) or (0,1) + // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + SHIFT_TO_CHB_ADDR, 0, ZQ_SET0_ZQCSMASK); + + // DRAMC CHA(CHN0):ZQ_SET0_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQ_SET0_ZQCS_MASK_SEL=0. + vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET0, 0, ZQ_SET0_ZQCS_MASK_SEL); + #endif + } +#if (CHANNEL_NUM > 2) + else if (p->support_channel_num == CHANNEL_FOURTH) + { + // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin. + #ifdef ZQCS_ENABLE_LP4 + // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1 + + vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, P_Fld(1, ZQ_SET0_ZQCSDUAL) | + P_Fld(0, ZQ_SET0_ZQCALL) | + P_Fld(0, ZQ_SET0_ZQ_SRF_OPT) | + P_Fld(0, ZQ_SET0_ZQCSMASK_OPT) | + P_Fld(0, ZQ_SET0_ZQMASK_CGAR) | + P_Fld(0, ZQ_SET0_ZQCS_MASK_SEL_CGAR)); + + // DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0. + // ZQCSMASK setting: (Ch A, Ch C) = (1,0) or (0,1), (Ch B, Ch D) = (1,0) or (0,1) + // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first + #if fcFOR_CHIP_ID == fcPetrus + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_B << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK); + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_C << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK); + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); + #endif + + // DRAMC CHA(CHN0):ZQ_SET0_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQ_SET0_ZQCS_MASK_SEL=0. + vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET0, 0, ZQ_SET0_ZQCS_MASK_SEL); + #endif + } +#endif + + // Set 0 to be able to adjust TX DQS/DQ/DQM PI during calibration, for new cross rank mode. + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2, 0, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2, 0, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1); + +#if ENABLE_PA_IMPRO_FOR_TX_AUTOK + vIO32WriteFldAlign_All(DRAMC_REG_DCM_SUB_CTRL, 0x0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK); +#endif + // ARPI_DQ SW mode mux, TX DQ use 1: PHY Reg 0: DRAMC Reg + #if ENABLE_PA_IMPRO_FOR_TX_TRACKING + vIO32WriteFldAlign_All(DRAMC_REG_DCM_SUB_CTRL, 0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING); + #endif + //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL1, 1, MISC_CTRL1_R_DMARPIDQ_SW); @Darren, remove to LP4_UpdateInitialSettings + //Disable HW MR18/19 to prevent fail case when doing SW MR18/19 in DQSOSCAuto + vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); + + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS); //disable refresh + + vIO32WriteFldAlign_All(DRAMC_REG_SHU_MATYPE, u1MaType, SHU_MATYPE_MATYPE); + + TX_Path_Algorithm(p); +} + +void vAfterCalibration(DRAMC_CTX_T *p) +{ +#if ENABLE_READ_DBI + EnableDRAMModeRegReadDBIAfterCalibration(p); +#endif + +#if ENABLE_WRITE_DBI + EnableDRAMModeRegWriteDBIAfterCalibration(p); +#endif + + SetMr13VrcgToNormalOperation(p);// Set VRCG{MR13[3]} to 0 + CKEFixOnOff(p, CKE_WRITE_TO_ALL_RANK, CKE_DYNAMIC, CKE_WRITE_TO_ALL_CHANNEL); //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) + + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, p->support_rank_num, DUMMY_RD_RANK_NUM); + +#if FOR_DV_SIMULATION_USED == 1 + cal_sv_rand_args_t *psra = get_psra(); + + if (psra) { + u1MR03Value[p->dram_fsp] = psra->mr3_value; + } +#endif + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL7, 0, MISC_CG_CTRL7_CK_BFE_DCM_EN); + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL); // Rank selection is controlled by Test Agent + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A2, 0x20, TEST2_A2_TEST2_OFF); //@Chris, MP setting for runtime TA2 Length + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0, MISC_DUTYSCAN1_DQSERRCNT_DIS); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT); +} + +static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) +{ + #if 0//O1_SETTING_RESTORE + const U32 u4O1RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)) + }; + #endif + + U8 u1VrefSel; + + if (u1OnOff == ON) + { + // These RG will be restored when leaving each calibration flow + // ------------------------------------------------------- + // VREF_UNTERM_EN + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF), 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF), 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); + + #if (__LP5_COMBO__ == TRUE) + if (p->dram_type==TYPE_LPDDR5) + u1VrefSel = 0x37;//unterm LP5 + else + #endif + u1VrefSel = 0x37;//unterm LP4 + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), + P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | + P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL), + P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) | + P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1)); + } + + // DQ_O1 enable/release + // ------------------------------------------------------- + // Actually this RG naming is O1_EN in APHY + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), u1OnOff, B0_DQ6_RG_RX_ARDQ_O1_SEL_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), u1OnOff, B1_DQ6_RG_RX_ARDQ_O1_SEL_B1); + + // DQ_IN_BUFF_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), + P_Fld(u1OnOff, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0) | + P_Fld(u1OnOff, B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), + P_Fld(u1OnOff, B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1) | + P_Fld(u1OnOff, B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1)); + + // DQ_BUFF_EN_SEL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), u1OnOff, B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), u1OnOff, B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1); + + // Gating always ON + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL),(u1OnOff << 1) | u1OnOff, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN); + + mcDELAY_US(1); +} + +/* + * set_cbt_intv -- set interval related rg according to speed. + * + * TODO, move these to ACTimingTable ????!!! + */ + +struct cbt_intv { + DRAM_PLL_FREQ_SEL_T freq_sel; + DIV_MODE_T divmode; + u8 tcmdo1lat; + u8 catrain_intv; + u8 new_cbt_pat_intv; + u8 wlev_dqspat_lat; +}; + +static void set_cbt_intv_rg(DRAMC_CTX_T *p, struct cbt_intv *pintv) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1), + P_Fld(pintv->tcmdo1lat, CBT_WLEV_CTRL1_TCMDO1LAT) | + P_Fld(pintv->catrain_intv, CBT_WLEV_CTRL1_CATRAIN_INTV)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), + P_Fld(pintv->new_cbt_pat_intv, CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + P_Fld(pintv->wlev_dqspat_lat, CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT)); +} + +static struct cbt_intv *lookup_cbt_intv(struct cbt_intv *intv, int cnt, + DRAM_PLL_FREQ_SEL_T fsel, DIV_MODE_T dmode) +{ + struct cbt_intv *pintv = NULL; + int i; + + for (i = 0; i < cnt; i++) { + if (intv[i].freq_sel == fsel && intv[i].divmode == dmode) { + pintv = &intv[i]; + break; + } + } + + return pintv; +} + +static void set_cbt_wlev_intv_lp4(DRAMC_CTX_T *p) +{ + struct cbt_intv intv[] = { + { + LP4_DDR4266, + DIV8_MODE, + 17, /*tcmdo1lat*/ + 14, /* catrain_intv */ + 19, /* new_cbt_pat_intv */ + 19, /* wlev_dqspat_lat */ + }, { + LP4_DDR3733, + DIV8_MODE, + 16, /*tcmdo1lat*/ + 13, /* catrain_intv */ + 18, /* new_cbt_pat_intv */ + 18, /* wlev_dqspat_lat */ + }, { + LP4_DDR3200, + DIV8_MODE, + 14, /*tcmdo1lat*/ + 11, /* catrain_intv */ + 16, /* new_cbt_pat_intv */ + 16, /* wlev_dqspat_lat */ + }, { + LP4_DDR2667, + DIV8_MODE, + 13, /*tcmdo1lat*/ + 10, /* catrain_intv */ + 15, /* new_cbt_pat_intv */ + 15, /* wlev_dqspat_lat */ + }, { + LP4_DDR2400, + DIV8_MODE, + 12, /*tcmdo1lat*/ + 9, /* catrain_intv */ + 14, /* new_cbt_pat_intv */ + 14, /* wlev_dqspat_lat */ + }, { + LP4_DDR1866, + DIV8_MODE, + 11, /*tcmdo1lat*/ + 9, /* catrain_intv */ + 13, /* new_cbt_pat_intv */ + 13, /* wlev_dqspat_lat */ + }, { + LP4_DDR1600, + DIV8_MODE, + 10, /*tcmdo1lat*/ + 8, /* catrain_intv */ + 12, /* new_cbt_pat_intv */ + 12, /* wlev_dqspat_lat */ + }, { + LP4_DDR1200, + DIV8_MODE, + 9, /*tcmdo1lat*/ + 8, /* catrain_intv */ + 11, /* new_cbt_pat_intv */ + 11, /* wlev_dqspat_lat */ + }, { + LP4_DDR800, + DIV8_MODE, + 8, /*tcmdo1lat*/ + 8, /* catrain_intv */ + 10, /* new_cbt_pat_intv */ + 10, /* wlev_dqspat_lat */ + }, { + LP4_DDR1600, + DIV4_MODE, + 16, /*tcmdo1lat*/ + 13, /* catrain_intv */ + 16, /* new_cbt_pat_intv */ + 16, /* wlev_dqspat_lat */ + }, { + LP4_DDR1200, + DIV4_MODE, + 14, /*tcmdo1lat*/ + 13, /* catrain_intv */ + 14, /* new_cbt_pat_intv */ + 14, /* wlev_dqspat_lat */ + }, { + LP4_DDR800, + DIV4_MODE, + 12, /*tcmdo1lat*/ + 13, /* catrain_intv */ + 12, /* new_cbt_pat_intv */ + 12, /* wlev_dqspat_lat */ + }, { + LP4_DDR400, + DIV4_MODE, + 12, /*tcmdo1lat*/ + 13, /* catrain_intv */ + 12, /* new_cbt_pat_intv */ + 12, /* wlev_dqspat_lat */ + }, + }; + + struct cbt_intv *pintv; + + pintv = lookup_cbt_intv(intv, ARRAY_SIZE(intv), + p->freq_sel, vGet_Div_Mode(p)); + if (!pintv) { + mcSHOW_DBG_MSG(("not found entry!\n")); + return; + } + + set_cbt_intv_rg(p, pintv); +} + +#if __LP5_COMBO__ +static void set_cbt_wlev_intv_lp5(DRAMC_CTX_T *p) +{ + struct cbt_intv intv[] = { + { + LP5_DDR6400, + UNKNOWN_MODE, + 15, /*tcmdo1lat*/ + 15, /* catrain_intv */ + 17, /* new_cbt_pat_intv */ + 17, /* wlev_dqspat_lat */ + }, { + LP5_DDR6000, + UNKNOWN_MODE, + 15, /*tcmdo1lat*/ + 15, /* catrain_intv */ + 17, /* new_cbt_pat_intv */ + 17, /* wlev_dqspat_lat */ + }, { + LP5_DDR5500, + UNKNOWN_MODE, + 14, /*tcmdo1lat*/ + 14, /* catrain_intv */ + 16, /* new_cbt_pat_intv */ + 16, /* wlev_dqspat_lat */ + }, { + LP5_DDR4800, + UNKNOWN_MODE, + 13, /*tcmdo1lat*/ + 13, /* catrain_intv */ + 15, /* new_cbt_pat_intv */ + 15, /* wlev_dqspat_lat */ + }, { + LP5_DDR4266, + UNKNOWN_MODE, + 20, /*tcmdo1lat*/ + 20, /* catrain_intv */ + 22, /* new_cbt_pat_intv */ + 20, /* wlev_dqspat_lat */ + }, { + LP5_DDR3733, + UNKNOWN_MODE, + 19, /*tcmdo1lat*/ + 19, /* catrain_intv */ + 21, /* new_cbt_pat_intv */ + 19, /* wlev_dqspat_lat */ + }, { + LP5_DDR3200, + UNKNOWN_MODE, + 15, /*tcmdo1lat*/ + 15, /* catrain_intv */ + 17, /* new_cbt_pat_intv */ + 17, /* wlev_dqspat_lat */ + }, { + LP5_DDR2400, + UNKNOWN_MODE, + 13, /*tcmdo1lat*/ + 13, /* catrain_intv */ + 15, /* new_cbt_pat_intv */ + 15, /* wlev_dqspat_lat */ + }, { + LP5_DDR1600, + UNKNOWN_MODE, + 17, /*tcmdo1lat*/ + 17, /* catrain_intv */ + 19, /* new_cbt_pat_intv */ + 17, /* wlev_dqspat_lat */ + }, { + LP5_DDR1200, + UNKNOWN_MODE, + 15, /*tcmdo1lat*/ + 15, /* catrain_intv */ + 17, /* new_cbt_pat_intv */ + 15, /* wlev_dqspat_lat */ + }, { + LP5_DDR800, + UNKNOWN_MODE, + 13, /*tcmdo1lat*/ + 13, /* catrain_intv */ + 15, /* new_cbt_pat_intv */ + 13, /* wlev_dqspat_lat */ + }, + }; + + struct cbt_intv *pintv; + + pintv = lookup_cbt_intv(intv, ARRAY_SIZE(intv), p->freq_sel, UNKNOWN_MODE); + if (!pintv) { + mcSHOW_DBG_MSG(("not found entry!\n")); + return; + } + + set_cbt_intv_rg(p, pintv); +} +#endif /* __LP5_COMBO__ */ + +static void set_cbt_wlev_intv(DRAMC_CTX_T *p) +{ +#if __LP5_COMBO__ + if (is_lp5_family(p)) + set_cbt_wlev_intv_lp5(p); + else +#endif + set_cbt_wlev_intv_lp4(p); +} + +#if SIMUILATION_CBT == 1 +/* To process LPDDR5 Pinmux */ +struct cbt_pinmux { + u8 dram_dq_b0; /* EMI_B0 is mapped to which DRAMC byte ?? */ + u8 dram_dq_b1; + u8 dram_dmi_b0; /* EMI_DMI0 is mapped to which DRAMC DMI ?? */ + u8 dram_dmi_b1; + + u8 dram_dq7_b0; /* EMI_DQ7 is mapped to which DRAMC DQ ?? */ + u8 dram_dq7_b1; /* EMI_DQ15 is mapped to which DRAMC DQ ?? */ +}; + +/* Per-project definition */ +static struct cbt_pinmux lp4_cp[CHANNEL_NUM] = { + { + /* CHA */ + .dram_dq_b0 = 0, + .dram_dq_b1 = 1, + + .dram_dmi_b0 = 0, + .dram_dmi_b1 = 1, + }, + #if (CHANNEL_NUM>1) + { + /* CHB */ + .dram_dq_b0 = 0, + .dram_dq_b1 = 1, + + .dram_dmi_b0 = 0, + .dram_dmi_b1 = 1, + }, + #endif + #if (CHANNEL_NUM>2) + { + /* CHC */ + .dram_dq_b0 = 0, + .dram_dq_b1 = 1, + + .dram_dmi_b0 = 0, + .dram_dmi_b1 = 1, + }, + { + /* CHD */ + .dram_dq_b0 = 0, + .dram_dq_b1 = 1, + + .dram_dmi_b0 = 0, + .dram_dmi_b1 = 1, + }, + #endif +}; + +static inline u8 is_byte_mode(DRAMC_CTX_T *p) +{ + return p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1? 1: 0; +} + +static void vSetDramMRCBTOnOff(DRAMC_CTX_T *p, U8 u1OnOff, U8 operating_fsp) +{ + if (u1OnOff) + { + // op[7] = !(p->dram_fsp), dram will switch to another FSP_OP automatically + if (operating_fsp) + { + MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) | + P_Fld(1, MR13_FSP_WR) | + P_Fld(1, MR13_CBT), + TO_MR); + } + else + { + MRWriteFldMulti(p, 13, P_Fld(1, MR13_FSP_OP) | + P_Fld(0, MR13_FSP_WR) | + P_Fld(1, MR13_CBT), + TO_MR); + } + + if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(1, CBT_WLEV_CTRL0_BYTEMODECBTEN) | + P_Fld(1, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); //BYTEMODECBTEN=1 + } + } + else + { + if (operating_fsp) + { + // !! Remain MR13_FSP_OP = 0, because of system is at low frequency now. + MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) | + P_Fld(1, MR13_FSP_WR) | + P_Fld(0, MR13_CBT), + TO_MR); + } + else + { + MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) | + P_Fld(0, MR13_FSP_WR) | + P_Fld(0, MR13_CBT), + TO_MR); + } + } + +} + +static void CBTEntryLP4(DRAMC_CTX_T *p, U8 operating_fsp, U16 operation_frequency) +{ + struct cbt_pinmux *cp = &lp4_cp[p->channel]; + + #if MR_CBT_SWITCH_FREQ + if (p->dram_fsp == FSP_1) + DramcModeRegInit_CATerm(p, 1); + #endif + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), + 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); + + CKEFixOnOff(p, p->rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + // yr: CA train old mode and CS traing need to check MRSRK at this point + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK); + + //Step 0: MRW MR13 OP[0]=1 to enable CBT + vSetDramMRCBTOnOff(p, ENABLE, operating_fsp); + + //Step 0.1: before CKE low, Let DQS=0 by R_DMwrite_level_en=1, spec: DQS_t has to retain a low level during tDQSCKE period + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + 1, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); + + //TODO, pinmux + //force byte0 tx + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + 0x1, CBT_WLEV_CTRL0_DQSOEAOEN); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + (1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN); + } + + mcDELAY_US(1); + + //Step 1.0: let CKE go low + CKEFixOnOff(p, p->rank, CKE_FIXOFF, CKE_WRITE_TO_ONE_CHANNEL); + + // Adjust u1MR13Value + (operating_fsp == FSP_1)? + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE): + DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); + + // Step 1.1 : let IO to O1 path valid + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) + { + // Let R_DMFIXDQIEN1=1 (byte1), 0xd8[13] ==> Note: Do not enable again. + //Currently set in O1PathOnOff + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_PADCTRL), 0x3, PADCTRL_FIXDQIEN); + + // Let DDRPHY RG_RX_ARDQ_SMT_EN_B1=1 (byte1) + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); + O1PathOnOff(p, ON); + } + + if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) + { + // let IO to O1 path valid by DDRPHY RG_RX_ARDQ_SMT_EN_B0=1 + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); + O1PathOnOff(p, ON); + } + + // Wait tCAENT + mcDELAY_US(1); +} + +static void CBTExitLP4(DRAMC_CTX_T *p, U8 operating_fsp, U8 operation_frequency) +{ + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) + { + //Step 1: CKE go high (Release R_DMCKEFIXOFF, R_DMCKEFIXON=1) + CKEFixOnOff(p, p->rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + //Step 2:wait tCATX, wait tFC + mcDELAY_US(1); + + //Step 3: MRW to command bus training exit (MR13 OP[0]=0 to disable CBT) + vSetDramMRCBTOnOff(p, DISABLE, operating_fsp); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + 0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); + } + + //Step 4: + //Disable O1 path output + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) + { + //Let DDRPHY RG_RX_ARDQ_SMT_EN_B1=0 + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B1_DQ3), 0, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); + O1PathOnOff(p, OFF); + //Let FIXDQIEN1=0 ==> Note: Do not enable again. + //Moved into O1PathOnOff + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_PADCTRL), 0, PADCTRL_FIXDQIEN); + } + + if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) + { + //Let DDRPHY RG_RX_ARDQ_SMT_EN_B0=0 + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B0_DQ3), 0, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); + O1PathOnOff(p, OFF); + + //Disable Byte mode CBT enable bit + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(0, CBT_WLEV_CTRL0_BYTEMODECBTEN) | + P_Fld(0, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); //BYTEMODECBTEN=1 + } + + // Wait tCAENT + mcDELAY_US(1); +} + +/* + * get_mck_ck_ratio -- get ratio of mck:ck + * + * TODO, remove later, get the ratio from dram ctx dfs table!!!! + * + * + * return 1 means 1:1 + * return 0 means 1:2 + */ +static u8 get_mck_ck_ratio(DRAMC_CTX_T *p) +{ + /* + * as per DE's comments, LP5 mck:ck has only 1:1 and 1:2. + * read SHU_LP5_CMD.LP5_CMD1TO2EN to decide which one. + */ + u32 ratio; + + ratio = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD), + SHU_LP5_CMD_LP5_CMD1TO2EN); + + mcSHOW_DBG_MSG5(("LP5 MCK:CK=%s\n", ratio == 1 ? "1:1" : "1:2")); + + return ratio; +} + +static u8 get_cbtui_adjustable_maxvalue(DRAMC_CTX_T *p) +{ + u8 ratio; + + /* + * MCK:CK=1:1, + * ther are only 0~1 for ui adjust, if ui value is larger than 1, adjust MCK. + * + * MCK:CK=1:2, + * ther are only 0~3 for ui adjust, if ui value is larger than 3, adjust MCK. + * + * MCK:CK=1:4, (for LP4) + * ther are only 0~7 for ui adjust, if ui value is larger than 7, adjust MCK. + * + */ + ratio = get_mck_ck_ratio(p); + + /* here just for LP5 */ + return ratio == 1? 1: 3; +} + +static inline u32 get_ca_mck(DRAMC_CTX_T *p) +{ + u32 dly; + + dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3)); + return dly & 0x0FFFFFFFU; +} + +static inline void put_ca_mck(DRAMC_CTX_T *p, u32 ca_mck) +{ + u32 dly; + + dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3)); + dly &= 0xF0000000U; + ca_mck &= 0x0FFFFFFFU; + dly |= ca_mck; + + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), dly); +} + +static inline u32 get_ca_ui(DRAMC_CTX_T *p) +{ + u32 dly; + + dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7)); + return dly & 0x0FFFFFFFU; +} + +static inline void put_ca_ui(DRAMC_CTX_T *p, u32 ca_ui) +{ + u32 dly; + + dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7)); + dly &= 0xF0000000U; + ca_ui &= 0x0FFFFFFFU; + dly |= ca_ui; + + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), dly); + + // Note: CKE UI must sync CA UI (CA and CKE delay circuit are same) @Lin-Yi + // To avoid tXP timing margin issue + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), ca_ui & 0xF, SHU_SELPH_CA5_DLY_CKE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), ca_ui & 0xF, SHU_SELPH_CA6_DLY_CKE1); +} + +static void xlate_ca_mck_ui(DRAMC_CTX_T *p, u32 ui_delta, + u32 mck_old, u32 ui_old, u32 *mck_new, u32 *ui_new) +{ + u8 i; + u32 mask, max; + u32 bit_ui, bit_mck; + u32 ui_tmp = 0, mck_tmp = 0; + + max = get_cbtui_adjustable_maxvalue(p); + mask = max; + + for (i = 0; i < CATRAINING_NUM_LP5; i++) { + bit_mck = 0; + bit_ui = ((ui_old >> (i * 4)) & mask) + ui_delta; + if (bit_ui > max) { + bit_mck = bit_ui / (max + 1); + bit_ui = bit_ui % (max + 1); + } + + mck_tmp += (bit_mck << (i * 4)); + ui_tmp += (bit_ui << (i * 4)); + } + + if (ui_new) + *ui_new = ui_tmp; + + if (mck_new) + *mck_new = mck_old + mck_tmp; +} + +static inline u8 get_ca_pi_per_ui(DRAMC_CTX_T *p) +{ +#if __LP5_COMBO__ + if (p->freq_sel == LP5_DDR4266) + return 64; + else +#endif + return 32; +} + +static int get_capi_max(DRAMC_CTX_T *p) +{ + if (u1IsPhaseMode(p) == TRUE) + { + return 32; + } + + return 64; +} + +static S16 adjust_ca_ui(DRAMC_CTX_T *p, U32 ca_mck, + U32 ca_ui, S16 pi_dly) +{ + S16 p2u; + S16 ui, pi; + U32 ui_new = 0, mck_new = 0; + + if (pi_dly < get_capi_max(p)) + { + return pi_dly; + } + + p2u = get_ca_pi_per_ui(p); + + ui = pi_dly / p2u; + pi = pi_dly % p2u; + + xlate_ca_mck_ui(p, ui, ca_mck, ca_ui, &mck_new, &ui_new); + + put_ca_ui(p, ui_new); + put_ca_mck(p, mck_new); + mcSHOW_DBG_MSG5(("mck_new: 0x%x, ui_new: 0x%x, pi:%d\n", + mck_new, ui_new, pi)); + + return pi; +} + +static inline u32 get_cs_mck(DRAMC_CTX_T *p) +{ + if (p->rank == RANK_1) + return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), + SHU_SELPH_CA1_TXDLY_CS1); + else + return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), + SHU_SELPH_CA1_TXDLY_CS); +} + +static inline void put_cs_mck(DRAMC_CTX_T *p, u32 cs_ui) +{ + if (p->rank == RANK_1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), + cs_ui, SHU_SELPH_CA1_TXDLY_CS1); + else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), + cs_ui, SHU_SELPH_CA1_TXDLY_CS); +} + +static inline u32 get_cs_ui(DRAMC_CTX_T *p) +{ + if (p->rank == RANK_1) + return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), + SHU_SELPH_CA5_DLY_CS1); + else + return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), + SHU_SELPH_CA5_DLY_CS); +} + +static inline void put_cs_ui(DRAMC_CTX_T *p, u32 cs_ui) +{ + if (p->rank == RANK_1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), + cs_ui, SHU_SELPH_CA5_DLY_CS1); + else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), + cs_ui, SHU_SELPH_CA5_DLY_CS); +} + +//void LP5_ShiftCSUI(DRAMC_CTX_T *p, S8 iShiftUI) +//{ +// REG_TRANSFER_T TransferUIRegs = {DRAMC_REG_SHU_SELPH_CA5, SHU_SELPH_CA5_DLY_CS}; +// REG_TRANSFER_T TransferMCKRegs = {DRAMC_REG_SHU_SELPH_CA1, SHU_SELPH_CA1_TXDLY_CS}; +// +// ExecuteMoveDramCDelay(p, TransferUIRegs[i], TransferMCKRegs[i], iShiftUI); +//} + +static S16 adjust_cs_ui(DRAMC_CTX_T *p, u32 cs_mck, u32 cs_ui, S16 pi_dly) +{ + S16 p2u; + S16 ui = 0, pi = 0; + u8 ratio; + u32 ui_max; + u32 cs_bit_mask, cs_ui_tmp, cs_mck_tmp; + + if (pi_dly < get_capi_max(p)) + { + return pi_dly; + } + + p2u = get_ca_pi_per_ui(p); + + ui = pi_dly / p2u; + pi = pi_dly % p2u; + + ratio = get_mck_ck_ratio(p); + if (ratio) { + /* 1:1 */ + cs_bit_mask = 1; + } else { + /* 1:2 */ + cs_bit_mask = 3; + } + + ui_max = get_cbtui_adjustable_maxvalue(p); + cs_ui_tmp = (cs_ui & cs_bit_mask) + ui; + cs_mck_tmp = 0; + if (cs_ui_tmp > ui_max) { + cs_mck_tmp = cs_ui_tmp / (ui_max + 1); + cs_ui_tmp = cs_ui_tmp % (ui_max + 1); + } + + cs_mck_tmp += cs_mck; + put_cs_ui(p, cs_ui_tmp); + put_cs_mck(p, cs_mck_tmp); + + mcSHOW_DBG_MSG5(("csmck:%d, csui: %d, pi:%d before\n", + cs_mck, cs_ui, 0)); + mcSHOW_DBG_MSG5(("csmck:%d, csui: %d, pi:%d after\n", + cs_mck_tmp, cs_ui_tmp, pi)); + + return pi; +} + +static u32 get_capi_step(DRAMC_CTX_T *p) +{ + u32 step; + + switch (p->freq_sel) { + case LP5_DDR800: + case LP5_DDR1200: + case LP5_DDR1600: + case LP5_DDR3733: + step = 8; + break; + default: + if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) + { + step = 8; + } + else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) + { + step = 16; + } + else + { + step = 1; + } + break; + } + +#if FOR_DV_SIMULATION_USED + return 8; +#else + return step; +#endif +} + +#if CBT_O1_PINMUX_WORKAROUND +static u32 CBTCompareWordaroundDecodeO1Pinmux(DRAMC_CTX_T *p, u32 o1_value, U8 *uiLPDDR_O1_Mapping) +{ + U8 u1Idx; + U32 u4Result; + + u4Result = 0; + + for (u1Idx = 0;u1Idx < p->data_width;u1Idx++) + u4Result |= ((o1_value >> uiLPDDR_O1_Mapping[u1Idx]) & 0x1) << u1Idx; + + return u4Result; +} + +static u32 CBTDelayCACLKCompareWorkaround(DRAMC_CTX_T *p) +{ + u8 u1pattern_index, u1ca_index, u1dq_index, u1dq_start, u1dq_end, u1ca_number_per_bit, u1bit_num_per_byte, u1pattern_choose; + U8 *uiLPDDR_O1_Mapping = NULL; + u32 u4TimeCnt, rdy, u4dq_o1, u4data_receive, u4ca_pattern, u4Result, u4Ready; + u8 u1pattern_num; + + const U8 u1LP5CBT_Pattern_Mapping[2][7] = + { + { + 1, 2, 4, 8, 16, 32, 64 + }, + + { + 126, 125, 123, 119, 111, 95, 63 + }, + }; + const U8 u1LP4CBT_Pattern_Mapping[2][6] = + { + { + 1, 2, 4, 8, 16, 32 + }, + + { + 62, 61, 59, 55, 47, 31 + }, + }; + + u4Result = 0; + u1bit_num_per_byte = 8; + +#if (__LP5_COMBO__) + if (is_lp5_family(p)) + { + uiLPDDR_O1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[p->channel]; + u1pattern_num = 8; + u1ca_number_per_bit = CATRAINING_NUM_LP5; + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) + { + u1dq_start = 0; + u1dq_end = 6; + } + else + { + u1dq_start = 0; + u1dq_end = 14; + } + } + else +#endif + { + uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel]; + u1pattern_num = 4; + u1ca_number_per_bit = CATRAINING_NUM_LP4; + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) + { + u1dq_start = 8; + u1dq_end = 13; + } + else + { + u1dq_start = 0; + u1dq_end = 13; + } + } + + vIO32WriteFldMulti(DRAMC_REG_CBT_WLEV_CTRL3, P_Fld(0x1, CBT_WLEV_CTRL3_CATRAIN_PAT_STOP0) + | P_Fld(0x1, CBT_WLEV_CTRL3_CATRAIN_PAT_STOP1)); + + for (u1pattern_index = 0; u1pattern_index < u1pattern_num; u1pattern_index++) + { + u1pattern_choose = (u1pattern_index > 3) ? (u1pattern_index % 2) : /* LP5 mapping */ + ((u1pattern_index > 1)? (3 - u1pattern_index) : u1pattern_index); /* LP5 & LP4 mapping */ + for (u1ca_index = 0; u1ca_index < u1ca_number_per_bit; u1ca_index++) + { + #if (__LP5_COMBO__) + if (is_lp5_family(p)) + { + u4ca_pattern = u1LP5CBT_Pattern_Mapping[u1pattern_choose][u1ca_index]; + } + else + #endif + { + u4ca_pattern = u1LP4CBT_Pattern_Mapping[u1pattern_choose][u1ca_index]; + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3), P_Fld((u1pattern_index+1), CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL0) + | P_Fld((u1ca_index+1), CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL1)); + + u4TimeCnt = TIME_OUT_CNT; + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_CAPATEN); + + //Check CA training compare ready (dramc_conf_nao 0x3fc , CATRAIN_CMP_CPT) + do + { + u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_CPT); + u4TimeCnt --; + mcDELAY_US(1); + }while ((u4Ready == 0) && (u4TimeCnt > 0)); + + if (u4TimeCnt == 0)//time out + { + mcSHOW_DBG_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n")); + mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test + //return DRAM_FAIL; + } + + u4dq_o1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQO1), MISC_DQO1_DQO1_RO); + + u4dq_o1 = CBTCompareWordaroundDecodeO1Pinmux(p, u4dq_o1, uiLPDDR_O1_Mapping); + + if (u1dq_end >= u1ca_number_per_bit) + u4ca_pattern |= u4ca_pattern << u1bit_num_per_byte; + + u4dq_o1 ^= u4ca_pattern; + + for(u1dq_index=u1dq_start; u1dq_index<=u1dq_end; u1dq_index++) + { + if ((p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) && (u1dq_index == u1ca_number_per_bit)) + u1dq_index = u1bit_num_per_byte; + + u4data_receive = (u4dq_o1 >> u1dq_index) & 0x1; + + if (u1dq_index < u1bit_num_per_byte) + u4Result |= u4data_receive << u1dq_index; + else + u4Result |= u4data_receive << u1dq_index - u1bit_num_per_byte; + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_CBT_CAPATEN); + + } + if (u4Result == ((0x1 << u1ca_number_per_bit) - 1)) + break; + } + return u4Result; +} + +static u32 new_cbt_pat_compare_workaround(DRAMC_CTX_T *p, new_cbt_pat_cfg_t *ncm) +{ + u8 u1pattern_index, u1ca_index, u1dq_index, u1dq_start, u1dq_end, u1ca_number_per_bit, u1bit_num_per_byte; + U8 *uiLPDDR_O1_Mapping = NULL; + u32 u4TimeCnt, rdy, u4dq_o1, u4data_receive, u4ca_pattern_a, u4ca_pattern, u4Result, u4Ready; + u8 u1pattern_num; + + u4Result = 0; + u1bit_num_per_byte = 8; + +#if (__LP5_COMBO__) + if (is_lp5_family(p)) + { + uiLPDDR_O1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[p->channel]; + u1pattern_num = 8; + u1ca_number_per_bit = 7; + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) + { + u1dq_start = 0; + u1dq_end = 6; + } + else + { + u1dq_start = 0; + u1dq_end = 14; + } + } + else +#endif + { + uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel]; + u1pattern_num = 4; + u1ca_number_per_bit = 6; + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) + { + u1dq_start = 8; + u1dq_end = 13; + } + else + { + u1dq_start = 0; + u1dq_end = 13; + } + } + + for (u1pattern_index = 0; u1pattern_index < u1pattern_num; u1pattern_index++) + { + u4ca_pattern_a = ((ncm->pat_a[u1pattern_index] >> ncm->ca_golden_sel) & 0x1) ? ((0x1 << u1ca_number_per_bit) - 1) : 0x0; + + for (u1ca_index = 0; u1ca_index < u1ca_number_per_bit; u1ca_index++) + { + u4ca_pattern = u4ca_pattern_a & ~(0x1 << u1ca_index); + + if ((ncm->pat_v[u1pattern_index] >> ncm->ca_golden_sel) & 0x1) + u4ca_pattern |= 0x1 << u1ca_index; + + if (ncm->invert_num) + u4ca_pattern ^= (0x1 << u1ca_number_per_bit) - 1; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), P_Fld(u1pattern_index, CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM) + | P_Fld(u1ca_index, CBT_WLEV_CTRL5_NEW_CBT_CA_NUM)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 1, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN); + + //Check CA training compare ready (dramc_conf_nao 0x3fc , CATRAIN_CMP_CPT) + do + { + u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT); + u4TimeCnt --; + mcDELAY_US(1); + }while ((u4Ready == 0) && (u4TimeCnt > 0)); + + if (u4TimeCnt == 0)//time out + { + mcSHOW_DBG_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n")); + mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test + //return DRAM_FAIL; + } + + u4dq_o1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQO1), MISC_DQO1_DQO1_RO); + + u4dq_o1 = CBTCompareWordaroundDecodeO1Pinmux(p, u4dq_o1, uiLPDDR_O1_Mapping); + + if (u1dq_end >= u1ca_number_per_bit) + u4ca_pattern |= u4ca_pattern << u1bit_num_per_byte; + + u4dq_o1 ^= u4ca_pattern; + + for(u1dq_index=u1dq_start; u1dq_index<=u1dq_end; u1dq_index++) + { + if ((p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) && (u1dq_index == u1ca_number_per_bit)) + u1dq_index = u1bit_num_per_byte; + + u4data_receive = (u4dq_o1 >> u1dq_index) & 0x1; + + if (u1dq_index < u1bit_num_per_byte) + u4Result |= u4data_receive << u1dq_index; + else + u4Result |= u4data_receive << u1dq_index - u1bit_num_per_byte; + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 0, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN); + } + if (u4Result == ((0x1 << u1ca_number_per_bit) - 1)) + break; + } + return u4Result; +} +#endif + +void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay) +{ + if (iDelay < 0) + { /* Set CLK delay */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CMD) | + P_Fld(-iDelay, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(-iDelay, SHU_R0_CA_CMD0_RG_ARPI_CS)); + } +/* + else if (iDelay >= 64) + { + DramcCmdUIDelaySetting(p, 2); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), + P_Fld(iDelay - 64, SHU_R0_CA_CMD0_RG_ARPI_CMD) | + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS)); + } +*/ + else + { /* Set CA output delay */ +// DramcCmdUIDelaySetting(p, 0); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), + P_Fld(iDelay, SHU_R0_CA_CMD0_RG_ARPI_CMD) | + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK) | + P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS)); + } +} + +static void CBTAdjustCS(DRAMC_CTX_T *p, int autok) +{ + S32 iFirstCSPass = 0, iLastCSPass = 0, iCSFinalDelay;//iCSCenter + + U8 backup_rank, ii; + u32 pi_dly; + u32 cs_ui, cs_mck; + + backup_rank = u1GetRank(p); + + cs_ui = get_cs_ui(p); + cs_mck = get_cs_mck(p); + +#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) + if (p->femmc_Ready == 1) + { + CATrain_CsDelay[p->channel][p->rank] = p->pSavetimeData->u1CBTCsDelay_Save[p->channel][p->rank]; + } +#endif + + // if dual rank, use average position of both rank + if(backup_rank == RANK_1) + { + iCSFinalDelay = (CATrain_CsDelay[p->channel][RANK_0] + CATrain_CsDelay[p->channel][RANK_1]) >> 1; + } + else + { + iCSFinalDelay = CATrain_CsDelay[p->channel][p->rank]; + } + + //Set CS output delay after training + /* p->rank = RANK_0, save to Reg Rank0 and Rank1, p->rank = RANK_1, save to Reg Rank1 */ + for (ii = RANK_0; ii <= backup_rank; ii++) + { + vSetRank(p, ii); + + pi_dly = adjust_cs_ui(p, cs_mck, cs_ui, iCSFinalDelay); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), pi_dly, SHU_R0_CA_CMD0_RG_ARPI_CS); + } + + vSetRank(p, backup_rank); + + mcSHOW_DBG_MSG(("CS Dly: %d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass)); +} + +#if CA_PER_BIT_DELAY_CELL +static void CATrainingSetPerBitDelayCell(DRAMC_CTX_T *p, S16 *iCAFinalCenter, U8 ca_pin_num) +{ + U8 *uiLPDDR_CA_Mapping = NULL; + U8 u1CA; + S8 iCA_PerBit_DelayLine[8] = {0}; + +#if __LP5_COMBO__ + if (is_lp5_family(p)) + { + uiLPDDR_CA_Mapping = (U8 *)uiLPDDR5_CA_Mapping_POP[p->channel]; + } + else +#endif + { + uiLPDDR_CA_Mapping = (U8 *)uiLPDDR4_CA_Mapping_POP[p->channel]; + } + + for (u1CA = 0;u1CA < ca_pin_num;u1CA++) + { + iCA_PerBit_DelayLine[uiLPDDR_CA_Mapping[u1CA]] = iCAFinalCenter[u1CA]; + } + + // Set CA perbit delay line calibration results + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_TXDLY0), + P_Fld(iCA_PerBit_DelayLine[0], SHU_R0_CA_TXDLY0_TX_ARCA0_DLY) | + P_Fld(iCA_PerBit_DelayLine[1], SHU_R0_CA_TXDLY0_TX_ARCA1_DLY) | + P_Fld(iCA_PerBit_DelayLine[2], SHU_R0_CA_TXDLY0_TX_ARCA2_DLY) | + P_Fld(iCA_PerBit_DelayLine[3], SHU_R0_CA_TXDLY0_TX_ARCA3_DLY)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_TXDLY1), + P_Fld(iCA_PerBit_DelayLine[4], SHU_R0_CA_TXDLY1_TX_ARCA4_DLY) | + P_Fld(iCA_PerBit_DelayLine[5], SHU_R0_CA_TXDLY1_TX_ARCA5_DLY) | + P_Fld(iCA_PerBit_DelayLine[6], SHU_R0_CA_TXDLY1_TX_ARCA6_DLY) | + P_Fld(iCA_PerBit_DelayLine[7], SHU_R0_CA_TXDLY1_TX_ARCA7_DLY)); +} +#endif// end of CA_PER_BIT_DELAY_CELL + +static void CBTSetCACLKResult(DRAMC_CTX_T *p, U32 u4MCK, U32 u4UI, S8 iFinalCACLK, U8 ca_pin_num) +{ + U8 backup_rank, rank_i, uiCA; + S16 iCAFinalCenter[CATRAINING_NUM]={0}; //for CA_PER_BIT + +#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) + if (p->femmc_Ready == 1) + { + CATrain_CmdDelay[p->channel][p->rank] = p->pSavetimeData->s1CBTCmdDelay_Save[p->channel][p->rank]; + vSetCalibrationResult(p, DRAM_CALIBRATION_CA_TRAIN, DRAM_FAST_K); + #if CA_PER_BIT_DELAY_CELL + for (uiCA = 0; uiCA < ca_pin_num; uiCA++) + iCAFinalCenter[uiCA] = p->pSavetimeData->u1CBTCA_PerBit_DelayLine_Save[p->channel][p->rank][uiCA]; + #endif + } +#endif + + iFinalCACLK = CATrain_CmdDelay[p->channel][p->rank]; + + mcSHOW_DBG_MSG(("\n[CBTSetCACLKResult] CA Dly = %d\n", iFinalCACLK)); + + iFinalCACLK = adjust_ca_ui(p, u4MCK, u4UI, iFinalCACLK); + + backup_rank = u1GetRank(p); + + for (rank_i = RANK_0; rank_i <= backup_rank;rank_i++) + { + vSetRank(p, rank_i); + + CBTDelayCACLK(p, iFinalCACLK); + +#if CA_PER_BIT_DELAY_CELL + CATrainingSetPerBitDelayCell(p, iCAFinalCenter, ca_pin_num); +#endif + } + + vSetRank(p, backup_rank); +} + +#if (__LP5_COMBO__) +/* Return (Vref_B0 | (Vref_B1 << 8) to support Byte mode */ +static U8 GetCBTVrefPinMuxValue_lp5(DRAMC_CTX_T *p, U8 u1VrefLevel) +{ + U8 u2VrefBit, u2Vref_org; + U16 u2Vref_new; + + u2Vref_org = u1VrefLevel & 0x7f; + + u2Vref_new = 0; + + for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++) + { + //mcSHOW_DBG_MSG(("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit])); + if (u2Vref_org & (1 << u2VrefBit)) + { + u2Vref_new |= (1 << uiLPDDR5_O1_Mapping_POP[p->channel][u2VrefBit]); + } + } + + mcSHOW_DBG_MSG3(("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new)); + + if (lp5_cp[p->channel].dram_dq_b0) + u2Vref_new >>= 8; + + return u2Vref_new; +} + +#endif + +static U8 GetCBTVrefPinMuxValue(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel) +{ + U8 u2VrefBit, u2Vref_org; + U16 u2Vref_new; + + if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) + return ((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f); + + u2Vref_org = ((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f); + + u2Vref_new = 0; + for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++) + { + //mcSHOW_DBG_MSG(("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit])); + if (u2Vref_org & (1 << u2VrefBit)) + { + u2Vref_new |= (1 << uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]); + } + } + + mcSHOW_DBG_MSG3(("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new)); + + if (lp4_cp[p->channel].dram_dq_b0) + u2Vref_new >>= 8; + + return u2Vref_new; +} + +static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 operating_fsp, U8 stateFlag) +{ + U32 fld; + U8 u4DbgValue; + U8 u1VrefValue_pinmux; + struct cbt_pinmux *cp = &lp4_cp[p->channel]; + + if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) && + (stateFlag == IN_CBT)) + { + u1VrefValue_pinmux = GetCBTVrefPinMuxValue(p, u1VrefRange, u1VrefLevel); + +#if !REDUCE_LOG_FOR_PRELOADER + mcSHOW_DBG_MSG(("\nCH_%d, RK_%d, Range=%d, VrefValue_pinmux = 0x%x\n", p->channel, p->rank, u1VrefRange, u1VrefValue_pinmux)); +#endif + u1MR12Value[p->channel][p->rank][operating_fsp] = ((u1VrefRange & 0x1) << 6) | u1VrefLevel; + + fld = (cp->dram_dq_b0) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0; + + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_WRITE_LEV), ((u1VrefRange&0x1) <<6) | (u1VrefLevel & 0x3f), WRITE_LEV_DMVREFCA); //MR12, bit[25:20]=OP[5:0] bit 26=OP[6] + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + u1VrefValue_pinmux, fld); //MR12, bit[25:20]=OP[5:0] bit 26=OP[6] + + //DQS_SEL=1, DQS_B1_G=1, Toggle R_DMDQS_WLEV (1 to 0) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), (0x1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3), 0xa, CBT_WLEV_CTRL3_DQSBX_G); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG); + mcDELAY_US(1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG); + + } + else + { + if (operating_fsp == FSP_1) + { + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR); + } + + u4DbgValue = (((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f)); + u1MR12Value[p->channel][p->rank][operating_fsp] = u4DbgValue; + mcSHOW_DBG_MSG3(("u4DbgValue = 0x%x\n", u4DbgValue)); + + DramcModeRegWriteByRank(p, p->rank, 12, u4DbgValue); + } + + //wait tVREF_LONG + mcDELAY_US(1); +} + + +#if __LP5_COMBO__ +static inline u8 is_training_mode1(DRAMC_CTX_T *p) +{ + return is_lp5_family(p) && p->lp5_training_mode == TRAINING_MODE1? 1: 0; +} + +static inline u8 is_training_mode2(DRAMC_CTX_T *p) +{ + return is_lp5_family(p) && p->lp5_training_mode == TRAINING_MODE2? 1: 0; +} + +static inline u8 is_phase_falling(DRAMC_CTX_T *p) +{ + return is_lp5_family(p) && p->lp5_cbt_phase == CBT_PHASE_FALLING? 1: 0; +} + +static void force_dq7(DRAMC_CTX_T *p, u8 level) +{ + u32 fld_b0, fld_b1; + u8 dq; + u8 dramc_byte; + struct cbt_pinmux *cp = &lp5_cp[p->channel]; + /* + * TODO + * + * pinmux to selec dq7 + * + */ + + fld_b0 = (cp->dram_dq_b0) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0; + fld_b1 = (cp->dram_dq_b1) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0; + + dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + fld_b0); + dq &= ~(1 << (cp->dram_dq7_b0 % 8)); + dq |= ((level & 1) << (cp->dram_dq7_b0 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + P_Fld(dq, fld_b0)); + + if (is_byte_mode(p)) { + dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + fld_b1); + dq &= ~(1 << (cp->dram_dq7_b1 % 8)); + dq |= ((level & 1) << (cp->dram_dq7_b1 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + P_Fld(dq, fld_b1)); + } +} + +static inline void force_dmi(DRAMC_CTX_T *p, u8 level) +{ + struct cbt_pinmux *cp = &lp5_cp[p->channel]; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + P_Fld(level, (cp->dram_dmi_b0) ? CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 : CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5)); + + if (is_byte_mode(p)) { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + P_Fld(level, (cp->dram_dmi_b1 ? CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 : CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5))); + } +} + +static void toggle_wck(DRAMC_CTX_T *p, u8 toggle) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + P_Fld(toggle, CBT_WLEV_CTRL0_CBT_WLEV_WCKAO)); +} + +static void set_vref_by_mrw(DRAMC_CTX_T *p, u8 vref) +{ + DramcModeRegWriteByRank(p, p->rank, 12, vref); +} + +static void set_vref_by_dq(DRAMC_CTX_T *p, u16 vref) +{ + u8 dq; + struct cbt_pinmux *cp = &lp5_cp[p->channel]; + + force_dmi(p, 0); + /* wait tCBTRTW */ + mcDELAY_US(1); + + if (is_byte_mode(p)) { + /* DRAMC B0/B1 as TX */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + 3, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN); + + /* Set DRAM Byte 1 */ + dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + (cp->dram_dq_b1 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0)); + + /* Shall be carefully processed in case DQ[7] is changed */ + dq &= (1 << (cp->dram_dq7_b1 % 8)); + dq |= ((vref >> 8) & 0xff); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + P_Fld(dq, (cp->dram_dq_b1 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0))); + } else { + /* DRAMC B0 as TX */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + (1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN); + } + + /* Set DRAM Byte 0 */ + dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + (cp->dram_dq_b0 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0)); + dq &= (1 << (cp->dram_dq7_b0 % 8)); + dq |= (vref & 0xff); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), + P_Fld(dq, (cp->dram_dq_b0 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0))); + + /* wait tDQStrain */ + mcDELAY_US(1); + force_dmi(p, 1); + mcDELAY_US(1); + /* DRAMC B0/B1 as RX */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + 0, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN); + mcDELAY_US(1); +} + +static void switch_oe_tie(DRAMC_CTX_T *p, u8 sw) +{ + u8 dq_oe; + struct cbt_pinmux *cp = &lp5_cp[p->channel]; + + if (sw) { + /* Set DRAM Byte 0 */ + if (cp->dram_dq_b0) { + dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1); + dq_oe |= (1 << (cp->dram_dq7_b0 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) | + P_Fld(1, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) | + P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1)); + } else { + dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0); + dq_oe |= (1 << (cp->dram_dq7_b0 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) | + P_Fld(1, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) | + P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0)); + } + + /* Set DRAM Byte 1 */ + if (is_byte_mode(p)) { + /* Set DRAM Byte 0 */ + if (cp->dram_dq_b1) { + dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1); + dq_oe |= (1 << (cp->dram_dq7_b1 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) | + P_Fld(1, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) | + P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1)); + } else { + dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0); + dq_oe |= (1 << (cp->dram_dq7_b1 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) | + P_Fld(1, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) | + P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0)); + } + } + } else { + /* Set DRAM Byte 0 */ + if (cp->dram_dq_b0) { + dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1); + dq_oe &= ~(1 << (cp->dram_dq7_b0 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) | + P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) | + P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1)); + } else { + dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0); + dq_oe &= ~(1 << (cp->dram_dq7_b0 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) | + P_Fld(0, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) | + P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0)); + } + + /* Set DRAM Byte 1 */ + if (is_byte_mode(p)) { + /* Set DRAM Byte 0 */ + if (cp->dram_dq_b1) { + dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1); + dq_oe &= ~(1 << (cp->dram_dq7_b1 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) | + P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), + P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) | + P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1)); + } else { + dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0); + dq_oe &= ~(0 << (cp->dram_dq7_b1 % 8)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) | + P_Fld(0, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), + P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) | + P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0)); + } + } + } +} + +static void lp5_cbt_entry(DRAMC_CTX_T *p, u8 operating_fsp, + u16 operation_frequency) +{ + lp5heff_save_disable(p); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), + 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); + + /* TCMDEN and CATRAINEN use MRSRK */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), + p->rank, SWCMD_CTRL0_MRSRK); + + #if 0 + if (p->rank == RANK_0) { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), + P_Fld(0, CKECTRL_CKEFIXOFF) | + P_Fld(1, CKECTRL_CKEFIXON)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), + P_Fld(1, CKECTRL_CKE1FIXOFF) | + P_Fld(0, CKECTRL_CKE1FIXON)); + } else if (p->rank == RANK_1) { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), + P_Fld(0, CKECTRL_CKE1FIXOFF) | + P_Fld(1, CKECTRL_CKE1FIXON)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), + P_Fld(1, CKECTRL_CKEFIXOFF) | + P_Fld(0, CKECTRL_CKEFIXON)); + } + #else + if (p->rank == RANK_0) { + CKEFixOnOff(p, RANK_0, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + CKEFixOnOff(p, RANK_1, CKE_FIXOFF, CKE_WRITE_TO_ONE_CHANNEL); + } else if (p->rank == RANK_1){ + CKEFixOnOff(p, RANK_1, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + CKEFixOnOff(p, RANK_0, CKE_FIXOFF, CKE_WRITE_TO_ONE_CHANNEL); + } + #endif + + /* + * APHY TX PI Spec mode option + * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail + */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL), + 1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE); + + /* + * APHY TX PI Spec mode option + * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail + */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL), + 1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE); + + /* + * APHY TX PI Spec mode option + * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail + */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL), + 1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + P_Fld(0x1, CBT_WLEV_CTRL0_WRITE_LEVEL_EN)); + + /* + * TODO + * BYTEMODE, PINMUX + */ + if (is_training_mode1(p)) { + /* DRAMC B0 as RX */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + 0, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN); + } + + switch_oe_tie(p, 1); + + /* + * MR13 OP[6], cbt mode + * 0, training mode 1 + * 1, training mode 2 + * + * TODO + * MR13 values?? + */ + DramcModeRegWriteByRank(p, p->rank, 13, p->lp5_training_mode << 6); + + if (operating_fsp == FSP_2) { + /* + * dram will switch to another FSP_OP automatically + */ + DramcModeRegWriteByRank(p, p->rank, 16, + (2 << MR16_FSP_WR_SHIFT) | + (2 << MR16_FSP_OP_SHIFT) | + (p->lp5_cbt_phase << MR16_CBT_PHASE) | + /* CBT enabled fsp[2] */ + (3 << MR16_FSP_CBT) | + (1 << MR16_VRCG)); + } else if (operating_fsp == FSP_1) { + /* + * dram will switch to another FSP_OP automatically + */ + DramcModeRegWriteByRank(p, p->rank, 16, + (1 << MR16_FSP_WR_SHIFT) | + (1<< MR16_FSP_OP_SHIFT) | + (p->lp5_cbt_phase << MR16_CBT_PHASE) | + /* CBT enabled fsp[1] */ + (2 << MR16_FSP_CBT) | + (1 << MR16_VRCG)); + } else { + /* FSP_0 */ + DramcModeRegWriteByRank(p, p->rank, 16, + (0 << MR16_FSP_WR_SHIFT) | + (0 << MR16_FSP_OP_SHIFT) | + (p->lp5_cbt_phase << MR16_CBT_PHASE) | + /* CBT enabled fsp[0] */ + (1 << MR16_FSP_CBT) | + (1 << MR16_VRCG)); + } + + /* wait tCBTWCKPRE_static */ + mcDELAY_US(1); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3), + P_Fld(0x5, CBT_WLEV_CTRL3_DQSBX_G) | + P_Fld(0x5, CBT_WLEV_CTRL3_DQSBY_G) | + P_Fld(0x5, CBT_WLEV_CTRL3_DQSBX1_G) | + P_Fld(0x5, CBT_WLEV_CTRL3_DQSBY1_G)); + + if (is_byte_mode(p)) { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 3, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(1, CBT_WLEV_CTRL0_BYTEMODECBTEN) | + P_Fld(1, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); //BYTEMODECBTEN=1 + } else { + if (lp5_cp[p->channel].dram_dq7_b0) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0x2, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL); + else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0x1, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL); + } + + /* toggle WCK */ + toggle_wck(p, 1); + + /* wait tWCK2DQ7H */ + mcDELAY_US(1); + + /* DQ[7] = High */ + force_dq7(p, 1); + + /* wait tDQ7HWCK to switch FSP */ + mcDELAY_US(1); + + /* stop toggle WCK */ + toggle_wck(p, 0); + + /* wait tDQ72DQ */ + mcDELAY_US(1); + + O1PathOnOff(p, 1); + + /* start toggle WCK */ + toggle_wck(p, 1); + + /* Wait tCAENT */ + mcDELAY_US(1); +} + +static void lp5_cbt_exit(DRAMC_CTX_T *p, u8 operating_fsp, + u8 operation_frequency) +{ + /* drive dq7 low */ + force_dq7(p, 0); + + /* wait tDQ7WCK */ + mcDELAY_US(1); + + /* stop wck toggle */ + toggle_wck(p, 0); + + /* wait tVREFCA_LOGNG */ + mcDELAY_US(1); + + if (operating_fsp == FSP_2) { + DramcModeRegWriteByRank(p, p->rank, 16, + (2 << MR16_FSP_WR_SHIFT) | + (2 << MR16_FSP_OP_SHIFT) | + (0 << MR16_CBT_PHASE) | + /* normal operation */ + (0 << MR16_FSP_CBT) | + (1 << MR16_VRCG)); + } else if (operating_fsp == FSP_1) { + DramcModeRegWriteByRank(p, p->rank, 16, + (1 << MR16_FSP_WR_SHIFT) | + (1 << MR16_FSP_OP_SHIFT) | + (0 << MR16_CBT_PHASE) | + /* normal operation */ + (0 << MR16_FSP_CBT) | + (1 << MR16_VRCG)); + } else { + DramcModeRegWriteByRank(p, p->rank, 16, + (0 << MR16_FSP_WR_SHIFT) | + (0 << MR16_FSP_OP_SHIFT) | + (0 << MR16_CBT_PHASE) | + /* normal operation */ + (0 << MR16_FSP_CBT) | + (1 << MR16_VRCG)); + } + + /* wait tMRD */ + mcDELAY_US(1); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), + P_Fld(0x0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN)); + switch_oe_tie(p, 0); + + /* + * APHY TX PI Spec mode option + * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail + */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL), + 0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE); + + /* Disable O1 path output */ + O1PathOnOff(p, 0); + + if (is_byte_mode(p)) { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(0, CBT_WLEV_CTRL0_BYTEMODECBTEN) | + P_Fld(0, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); //BYTEMODECBTEN=1 + } + + #if 0 + if (p->rank == RANK_0) { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), + P_Fld(0, CKECTRL_CKEFIXOFF) | + P_Fld(0, CKECTRL_CKEFIXON)); + } else if (p->rank == RANK_1) { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), + P_Fld(0, CKECTRL_CKE1FIXOFF) | + P_Fld(0, CKECTRL_CKE1FIXON)); + } + #else + CKEFixOnOff(p, CKE_WRITE_TO_ALL_RANK, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + #endif + + lp5heff_restore(p); +} +#endif + +static void CBTEntryLP45(DRAMC_CTX_T *p, U8 u1FSP, U16 u2Freq) +{ +#if __LP5_COMBO__ + if (is_lp5_family(p)) + { + lp5_cbt_entry(p, u1FSP, u2Freq); + } + else +#endif + { + if(p->dram_fsp == FSP_1) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(1, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + cbt_switch_freq(p, CBT_LOW_FREQ); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(0, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(1, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + } +#if ENABLE_LP4Y_WA //@Darren, debugging for DFS stress + CmdBusTrainingLP4YWA(p, DISABLE); +#endif + CBTEntryLP4(p, u1FSP, u2Freq); + if(p->dram_fsp == FSP_1) + { + cbt_switch_freq(p, CBT_HIGH_FREQ); + } + } +} + +static void CBTExitLP45(DRAMC_CTX_T *p, U8 u1FSP, U8 u2Freq, U8 stateFlag) +{ + /* by yirong.wang + * if stateFlag == OUT_CBT, it means we finished CBT, exit CBT + * if stateFlag == IN_CBT, it means we are trying to setup vref by MRW + * IN_CBT case, only for LP5 mode 1 and LP4 byte mode + */ +#if __LP5_COMBO__ + if (is_lp5_family(p)) + { + if (stateFlag == OUT_CBT || is_training_mode1(p)) + { + lp5_cbt_exit(p, u1FSP, u2Freq); + } + } + else +#endif + { + if (stateFlag == OUT_CBT || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) + { + (p->dram_fsp == FSP_1)? cbt_switch_freq(p, CBT_LOW_FREQ): NULL; + CBTExitLP4(p, u1FSP, u2Freq); +#if ENABLE_LP4Y_WA //@Darren, debugging for DFS stress + CmdBusTrainingLP4YWA(p, ENABLE); +#endif + } + } +} + +static void CBTSetVrefLP45(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 u1FSP, U16 u2Freq, U8 stateFlag) +{ + /* by yirong.wang + * if stateFlag == OUT_CBT, it means we are not in CBT, setup vref by MRW + * if stateFlag == IN_CBT, it means we are doing CBT + * LP5 training mode 1 and LP4 byte mode, exit CBT and setup vref by MRW, then re-enter CBT + * LP5 training mode 2 and LP4 normal mode, setup vref by DQ + */ +#if __LP5_COMBO__ + if (is_lp5_family(p)) + { + if (stateFlag == IN_CBT && is_training_mode2(p)) + { + /* + * training mode2 + * TODO, according to pinmux to adjust u1VrefLevel + */ + set_vref_by_dq(p, GetCBTVrefPinMuxValue_lp5(p, u1VrefLevel)); + } + else + { + if (stateFlag == IN_CBT && is_training_mode1(p)) + { + lp5_cbt_exit(p, u1FSP, u2Freq); + } + + set_vref_by_mrw(p, u1VrefLevel); + + if (stateFlag == IN_CBT && is_training_mode1(p)) + { + lp5_cbt_entry(p, u1FSP, u2Freq); + } + } + } + else +#endif + { + if (stateFlag == IN_CBT && p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) + { + // BYTE MODE: We are not in CBT now, set Vref & enter CBT + (p->dram_fsp == FSP_1)? cbt_switch_freq(p, CBT_LOW_FREQ): NULL; + CBTExitLP4(p, u1FSP, u2Freq); + + CBTSetVrefLP4(p, u1VrefRange, u1VrefLevel, u1FSP, stateFlag); + + CBTEntryLP4(p, u1FSP, u2Freq); + if(p->dram_fsp == FSP_1) + { + cbt_switch_freq(p, CBT_HIGH_FREQ); + } + } + else + { + CBTSetVrefLP4(p, u1VrefRange, u1VrefLevel, u1FSP, stateFlag); + } + } +} + +DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok) +{ + U8 u1FinalVref, u1FinalRange=0; + S8 iFinalCACLK; + U32 uiCAWinSumMax; + U8 operating_fsp; + U16 operation_frequency; +#if CA_PER_BIT_DELAY_CELL + S16 iCAFinalCenter[CATRAINING_NUM] = {0}; //for CA_PER_BIT +#endif +#if ENABLE_EYESCAN_GRAPH + U8 u1CBTEyeScanEnable; + U8 EyeScan_index[CATRAINING_NUM]; +#endif + + S16 pi_step; + S16 pi_start, pi_end; + u32 ca_ui, ca_ui_default; + u32 ca_mck; + u32 ca_cmd0; + u8 ca_pin_num; + u16 p2u; + u8 step_respi = AUTOK_RESPI_1; + + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)), + (DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL2)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4)), + (DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)), + (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)), + + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), //in O1PathOnOff() + }; + + p2u = get_ca_pi_per_ui(p); + + pi_end = p2u * 2 - 1; + +#if FOR_DV_SIMULATION_USED == 1 + pi_step = (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) ? 16 : 8; //for simulation speed up +#else + pi_step = get_capi_step(p); +#endif + + switch (p->freq_sel) { + case LP5_DDR4266: + case LP5_DDR800: + case LP5_DDR1200: + case LP5_DDR1600: + case LP5_DDR3733: + case LP5_DDR2400: + case LP5_DDR3200: + case LP5_DDR4800: + case LP5_DDR5500: + case LP5_DDR6000: + case LP5_DDR6400: + pi_start = -8; + break; + + default: + /* LPDDR4 */ + if (u1IsPhaseMode(p) == TRUE) + { + step_respi = AUTOK_RESPI_8; + } + + #if CBT_MOVE_CA_INSTEAD_OF_CLK + pi_start = -16; + pi_end = p2u * 3 - 1; + #else + if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) + { + pi_start = -24; + } + else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) + { + pi_start = -16; + } + else + { + pi_start = -MAX_CLK_PI_DELAY; + } + #endif + + break; + } + +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + +#if __LP5_COMBO__ + if (is_lp5_family(p)) + { + u1FinalVref = u1MR12Value[p->channel][p->rank][p->dram_fsp]; + ca_pin_num = CATRAINING_NUM_LP5; + } + else +#endif + { + u1FinalRange = u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6; + u1FinalVref = u1MR12Value[p->channel][p->rank][p->dram_fsp] & 0x3f; + ca_pin_num = CATRAINING_NUM_LP4; + } + +#if ENABLE_EYESCAN_GRAPH + u1CBTEyeScanEnable =GetEyeScanEnable(p, 0); + + for (u1vrefidx = 0; u1vrefidx < VREF_VOLTAGE_TABLE_NUM_LP5-1; u1vrefidx++) + { + for (uiCA = 0; uiCA < ca_pin_num; uiCA++) + { + for (ii = 0; ii < EYESCAN_BROKEN_NUM; ii++) + { + gEyeScan_Min[u1vrefidx][uiCA][ii] = EYESCAN_DATA_INVALID; + gEyeScan_Max[u1vrefidx][uiCA][ii] = EYESCAN_DATA_INVALID; + } + } + } +#endif + + vPrintCalibrationBasicInfo(p); + mcSHOW_DBG_MSG(("pi_start=%d, pi_end=%d, pi_step=%d, new_cbt_mode=%d, autok=%d\n", + pi_start, pi_end, pi_step, p->new_cbt_mode, autok)); + +#if __LP5_COMBO__ + if (is_lp5_family(p)) + { + mcSHOW_DBG_MSG(("lp5_training_mode=%d, lp5_cbt_phase=%d\n", p->lp5_training_mode, p->lp5_cbt_phase)); + } +#endif + + //Back up dramC register + DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); + + //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_CA_TRAIN, DRAM_FAIL); + +#if CA_PER_BIT_DELAY_CELL + CATrainingSetPerBitDelayCell(p, iCAFinalCenter, ca_pin_num); +#endif + +#if CBT_MOVE_CA_INSTEAD_OF_CLK + if (u1IsLP4Family(p->dram_type)) + { + U8 u1CaPI = 0, u1CaUI = 0; + + u1CaUI = 1; + u1CaPI = 0; + + DramcCmdUIDelaySetting(p, u1CaUI); + + CBTDelayCACLK(p, u1CaPI); + } +#endif + + /* read ca ui and mck */ + ca_ui_default = ca_ui = get_ca_ui(p); + ca_mck = get_ca_mck(p); + ca_cmd0 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)); + + vAutoRefreshSwitch(p, DISABLE); //When doing CA training, should make sure that auto refresh is disable + + /* + * TOOD + * + * here just pass simulation, + * remove after ACTiming OK(ACTiming Table includes CATRAIN_INTV) + */ + //vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1), + // P_Fld(0x1F, CBT_WLEV_CTRL1_CATRAIN_INTV)); + set_cbt_wlev_intv(p); + + /* + * tx_rank_sel is selected by SW + * Lewis@20180509: tx_rank_sel is selected by SW in CBT if TMRRI design has changed. + */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), + p->rank, TX_SET0_TXRANK); + /* TXRANKFIX should be write after TXRANK or the rank will be fix at rank 1 */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), + 1, TX_SET0_TXRANKFIX); + + //SW variable initialization + uiCAWinSumMax = 0; + + iFinalCACLK = 0; + operating_fsp = p->dram_fsp; + operation_frequency = p->frequency; + + // free-run dramc/ddrphy clk (DCMEN2=0, MIOCKCTRLOFF=1, PHYCLKDYNGEN=0, COMBCLKCTRL=0) + // free-run dram clk(APHYCKCG_FIXOFF =1, TCKFIXON=1) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), + P_Fld(0, DRAMC_PD_CTRL_DCMEN2) | + P_Fld(1, DRAMC_PD_CTRL_MIOCKCTRLOFF) | + P_Fld(0, DRAMC_PD_CTRL_PHYCLKDYNGEN) | + P_Fld(0, DRAMC_PD_CTRL_COMBCLKCTRL) | + P_Fld(1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) | + P_Fld(1, DRAMC_PD_CTRL_TCKFIXON)); + + //Note : Assume that there is a default CS value that can apply for CA. + CBTEntryLP45(p, operating_fsp, operation_frequency); + +#if PINMUX_AUTO_TEST_PER_BIT_CA + CheckCADelayCell(p); +#endif + + //Step 3: set vref range and step by ddr type + +#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && (BYPASS_VREF_CAL || BYPASS_CBT)) + if (p->femmc_Ready == 1) + { + u1FinalVref = p->pSavetimeData->u1CBTVref_Save[p->channel][p->rank]; + } +#endif + + mcSHOW_DBG_MSG(("\n[CmdBusTrainingLP45] Vref(ca) range %d: %d\n", u1FinalRange, u1FinalVref)); + +#ifdef FOR_HQA_TEST_USED + gFinalCBTVrefCA[p->channel][p->rank] = u1FinalVref; +#endif + + //Set Vref after training + // BYTE MODE: Set Vref & enter CBT + CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, IN_CBT); +#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) + #if CBT_MOVE_CA_INSTEAD_OF_CLK + // scan UI from 0, not from the UI we used to enter CBT + DramcCmdUIDelaySetting(p, 0); + ca_ui = get_ca_ui(p); + #endif +#endif + put_ca_ui(p, ca_ui); + //Set CA_PI_Delay after training + CBTSetCACLKResult(p, ca_mck, ca_ui, iFinalCACLK, ca_pin_num); + +#if ENABLE_EYESCAN_GRAPH + gEyeScan_CaliDelay[0] = CATrain_CmdDelay[p->channel][p->rank] -pi_start; +#endif + + //mcSHOW_DBG_MSG(("\nAverage CA Dly: %d\n", iFinalCACLK)); + + /* ------------- CS and CLK ---------- */ + /* delay ca 1UI before K CS */ +#if __LP5_COMBO__ + if (is_phase_falling(p)) { + ca_mck = get_ca_mck(p); + ca_ui = get_ca_ui(p); + xlate_ca_mck_ui(p, 1, + ca_mck, ca_ui, + &ca_mck_tmp, &ca_ui_tmp); + put_ca_mck(p, ca_mck_tmp); + put_ca_ui(p, ca_ui_tmp); + } +#endif + + CBTAdjustCS(p, autok); + + /* restore ca mck and ui */ +#if __LP5_COMBO__ + if (is_phase_falling(p)) { + put_ca_mck(p, ca_mck); + put_ca_ui(p, ca_ui); + } +#endif + +//------- Going to exit Command bus training(CBT) mode.------------- + CBTExitLP45(p, operating_fsp, operation_frequency, OUT_CBT); + CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, OUT_CBT); + +#if __LP5_COMBO__ + if (!is_lp5_family(p)) +#endif + { + if (p->dram_fsp == FSP_1) + { + #if MR_CBT_SWITCH_FREQ + DramcModeRegInit_CATerm(p, 0); + #else + DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, TO_MR); + #endif + } + } + +#if EYESCAN_LOG || defined(FOR_HQA_TEST_USED) + gFinalCBTVrefDQ[p->channel][p->rank] = u1FinalVref; +#endif + + mcSHOW_DBG_MSG3(("\n[CmdBusTrainingLP45] Done\n")); + + //tx_rank_sel is selected by HW //Lewis@20180509: tx_rank_sel is selected by SW in CBT if TMRRI design has changed. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK or the rank will be fix at rank 1 + + //Restore setting registers + DramcRestoreRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); + + return DRAM_OK; +} +#endif /* SIMUILATION_CBT */ + +//------------------------------------------------------------------------- +/** DramcWriteLeveling + * start Write Leveling Calibration. + * @param p Pointer of context created by DramcCtxCreate. + * @param apply (U8): 0 don't apply the register we set 1 apply the register we set ,default don't apply. + * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL + */ +//------------------------------------------------------------------------- +#define WRITE_LEVELING_MOVD_DQS 1//UI + +U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p) +{ +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + //in LP4 1:8 mode, 8 small UI = 1 large UI + if (vGet_Div_Mode(p) == DIV4_MODE) + { + return MCK_TO_4UI_SHIFT; + } + else if (vGet_Div_Mode(p) == DIV16_MODE) + { + return MCK_TO_16UI_SHIFT; + } + else + { + return MCK_TO_8UI_SHIFT; + } + } + else +#endif + { + //in LP4 1:8 mode, 8 small UI = 1 large UI + if (vGet_Div_Mode(p) == DIV4_MODE) + { + return MCK_TO_4UI_SHIFT; + } + else + { + return MCK_TO_8UI_SHIFT; + } + } +} + +static DRAM_STATUS_T ExecuteMoveDramCDelay(DRAMC_CTX_T *p, + REG_TRANSFER_T ui_reg, + REG_TRANSFER_T mck_reg, + S8 iShiftUI) +{ + S32 s4HighLevelDelay, s4DelaySum; + U32 u4TmpUI, u4TmpMCK; + U8 ucDataRateDivShift = 0; + DRAM_STATUS_T MoveResult; + + ucDataRateDivShift = u1MCK2UI_DivShift(p); + + u4TmpUI = u4IO32ReadFldAlign(DRAMC_REG_ADDR(ui_reg.u4Addr), ui_reg.u4Fld) & (~(1 << ucDataRateDivShift)); + u4TmpMCK = u4IO32ReadFldAlign(DRAMC_REG_ADDR(mck_reg.u4Addr), mck_reg.u4Fld); + //mcSHOW_DBG_MSG(("Base: u4TmpMCK:%d, u4TmpUI: %d,\n", u4TmpMCK, u4TmpUI)); + + s4HighLevelDelay = (u4TmpMCK << ucDataRateDivShift) + u4TmpUI; + s4DelaySum = (s4HighLevelDelay + iShiftUI); + + if (s4DelaySum < 0) + { + u4TmpUI = 0; + u4TmpMCK = 0; + MoveResult = DRAM_FAIL; + } + else + { + u4TmpMCK = s4DelaySum >> ucDataRateDivShift; + u4TmpUI = s4DelaySum - (u4TmpMCK << ucDataRateDivShift); + MoveResult = DRAM_OK; + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(ui_reg.u4Addr), u4TmpUI, ui_reg.u4Fld); + vIO32WriteFldAlign(DRAMC_REG_ADDR(mck_reg.u4Addr), u4TmpMCK, mck_reg.u4Fld); + //mcSHOW_DBG_MSG(("[%d] Final ==> u4TmpMCK:%d, u4TmpUI: %d,\n", iShiftUI, u4TmpMCK, u4TmpUI)); + + return MoveResult; +} + +static void _LoopAryToDelay(DRAMC_CTX_T *p, + REG_TRANSFER_T *ui_reg, + REG_TRANSFER_T *mck_reg, + U8 u8RG_num, + S8 iShiftUI, + BYTES_T eByteIdx) +{ + U8 idx = 0, step = 1; + if (eByteIdx == BYTE_0) + { + idx = 0; + step = 2; + } + else if (eByteIdx == BYTE_1) + { + idx = 1; + step = 2; + } + + for (; idx < u8RG_num; idx += step) + { + ExecuteMoveDramCDelay(p, ui_reg[idx], mck_reg[idx], iShiftUI); + } +} + +static void LP4_ShiftDQSUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) +{ + // DQS / DQS_OEN + REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS0}, // Byte0 + {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS1}}; // Byte1 + REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_DQS0}, + {DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_DQS1}}; + + _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs, + sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T), + iShiftUI, eByteIdx); +} + +void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) +{ + // DQS / DQS_OEN + REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS0}, // Byte0 + {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS1}}; // Byte1 + REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_OEN_DQS0}, + {DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_OEN_DQS1}}; + + _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs, + sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T), + iShiftUI, eByteIdx); +} + +static void ShiftDQUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) +{ + // Shift DQ / DQM / DQ_OEN / DQM_OEN + REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM0}, // Byte0 + {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM1}, // Byte1 + {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ0}, // Byte0 + {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ1}}; // Byte1 + REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_DQM0}, + {DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_DQM1}, + {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_DQ0}, + {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_DQ1}}; + + _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs, + sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T), + iShiftUI, eByteIdx); +} + +static void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) +{ + U8 backup_rank, rk_i; + backup_rank = u1GetRank(p); + + // Shift DQ / DQM / DQ_OEN / DQM_OEN + for (rk_i = RANK_0; rk_i < p->support_rank_num; rk_i++) + { + vSetRank(p, rk_i); + ShiftDQUI(p, iShiftUI, eByteIdx); + } + vSetRank(p, backup_rank); +} + +static void ShiftDQ_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) +{ + REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM0}, // Byte0 + {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM1}, // Byte1 + {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ0}, // Byte0 + {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ1}}; // Byte1 + REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0}, + {DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1}, + {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0}, + {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1}}; + + _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs, + sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T), + iShiftUI, eByteIdx); +} + +void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) +{ + U8 backup_rank, rk_i; + backup_rank = u1GetRank(p); + + // Shift DQ / DQM / DQ_OEN / DQM_OEN + for (rk_i = RANK_0; rk_i < p->support_rank_num; rk_i++) + { + vSetRank(p, rk_i); + ShiftDQ_OENUI(p, iShiftUI, eByteIdx); + } + vSetRank(p, backup_rank); +} + +static void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) +{ +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + LP5_ShiftWCKUI(p, iShiftUI, eByteIdx); + else +#endif + { + LP4_ShiftDQSUI(p, iShiftUI, eByteIdx); + LP4_ShiftDQS_OENUI(p, iShiftUI, eByteIdx); + } +} + +U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p) +{ + if ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400)) + return TRUE; + else + return FALSE; +} + +//static void vSetDramMRWriteLevelingOnOff(DRAMC_CTX_T *p, U8 u1OnOff) +static void vSetDramMRWriteLevelingOnOff(DRAMC_CTX_T *p, U8 u1OnOff) +{ + // MR2 OP[7] to enable/disable write leveling + if (u1OnOff) + u1MR02Value[p->dram_fsp] |= 0x80; // OP[7] WR LEV =1 + else + u1MR02Value[p->dram_fsp] &= 0x7f; // OP[7] WR LEV =0 + + DramcModeRegWriteByRank(p, p->rank, 2, u1MR02Value[p->dram_fsp]); +} + +U8 u1IsPhaseMode(DRAMC_CTX_T *p) +{ + if ((vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) || (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)) + return TRUE; + else // DDR800_CLOSE_LOOP and NORMAL_CLOSE_LOOP + return FALSE; +} + +static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerReg, REG_TRANSFER_T RepondsReg) +{ +// U32 u4TimeCnt = TIME_OUT_CNT; + // @Darren, Rx HW AutoK simulation time + U32 u4TimeCnt = DDR_HW_AUTOK_POLLING_CNT; + DRAM_STATUS_T u4RespFlag = 0; + + vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); // Init EN status + vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 1, TriggerReg.u4Fld); + do + { + u4RespFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(RepondsReg.u4Addr), RepondsReg.u4Fld); + u4TimeCnt --; + mcDELAY_US(1); + }while ((u4RespFlag == 0) && (u4TimeCnt > 0)); + + if (u4TimeCnt == 0)//time out + { + mcSHOW_DBG_MSG(("[DramcTriggerAndWait] Wait 0x%x respond fail (time out)\n", RepondsReg.u4Addr)); + return DRAM_FAIL; + } + + return DRAM_OK; +} + +#if (SIMULATION_WRITE_LEVELING == 1) +#if !__ETT__ +#undef ASSERT +#define ASSERT(x) \ + if (!(x)) \ + while (1)\ + mcSHOW_ERR_MSG(("ASSERT FAIL at %s[%d]!\n", __FUNCTION__, __LINE__)); +#endif + + +#define DQPI_PER_UI (32) +#define STORAGED_DLY_UNIT (24) +static void WriteLevelingScanRange_PI(DRAMC_CTX_T *p, S32 *ps4DlyBegin, S32 *ps4DlyEnd, U8 *pu1PIStep, S16 *pPI_bound, WLEV_DELAY_BASED_T stDelayBase) +{ + S32 s4DlyBegin = 0, s4DlyEnd; + U8 u1PIStep; + S16 PI_bound; + + if (stDelayBase == PI_BASED) + { + // Giving PI scan range + s4DlyBegin = WRITE_LEVELING_MOVD_DQS * 32 - MAX_CLK_PI_DELAY - 1; + s4DlyEnd = s4DlyBegin + 64 - 1; + + if ((vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)) + { + u1PIStep = 16; + PI_bound = 32; + } + else if ((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)) + { + u1PIStep = 8; + PI_bound = 32; + } + else + { + u1PIStep = 1; + PI_bound = 64; + } + } + else // stDelayBase == DLY_BASED + { + // Giving delay cell scan range + s4DlyBegin = 0; + s4DlyEnd = 2 * STORAGED_DLY_UNIT; + + u1PIStep = 1; // One step is 1/4 delay cell + PI_bound = 1024; // No bounadary as delay cell based + } + mcSHOW_DBG_MSG2(("Begin: %d, End: %d, Step: %d, Bound: %d\n", s4DlyBegin, s4DlyEnd, u1PIStep, PI_bound)); + + *ps4DlyBegin = s4DlyBegin; + *ps4DlyEnd = s4DlyEnd; + *pu1PIStep = u1PIStep; + *pPI_bound = PI_bound; + +} + +#if ENABLE_WDQS_MODE_2 +DRAM_STATUS_T WriteLevelingPosCal(DRAMC_CTX_T *p, WLEV_DELAY_BASED_T stDelayBase) +{ + DRAM_RANK_T backup_rank = u1GetRank(p); + U8 wrlevel_dqs_delay[DQS_NUMBER] = {0}; + U8 rank_i = 0; + + if((wrlevel_dqs_final_delay[RANK_0][0] - wrlevel_dqs_final_delay[RANK_1][0])>=9 || + (wrlevel_dqs_final_delay[RANK_0][0] - wrlevel_dqs_final_delay[RANK_1][0])<=-9 || + (wrlevel_dqs_final_delay[RANK_0][1] - wrlevel_dqs_final_delay[RANK_1][1])>=9 || + (wrlevel_dqs_final_delay[RANK_0][1] - wrlevel_dqs_final_delay[RANK_1][1])<=-9 ) + { + mcSHOW_ERR_MSG(("[WARNING] Larger WL R2R !!\n")); + #if CHECK_HQA_CRITERIA + while(1); + #endif + } + + wrlevel_dqs_delay[0] = (wrlevel_dqs_final_delay[RANK_0][0] + wrlevel_dqs_final_delay[RANK_1][0]) >> 1; + wrlevel_dqs_delay[1] = (wrlevel_dqs_final_delay[RANK_0][1] + wrlevel_dqs_final_delay[RANK_1][1]) >> 1; + + wrlevel_dqs_final_delay[RANK_0][0] = wrlevel_dqs_final_delay[RANK_1][0] = wrlevel_dqs_delay[0]; + wrlevel_dqs_final_delay[RANK_0][1] = wrlevel_dqs_final_delay[RANK_1][1] = wrlevel_dqs_delay[1]; + + for (rank_i = p->rank; rank_i < p->support_rank_num; rank_i++) + { + vSetRank(p, rank_i); + + // set to best values for DQS + if (stDelayBase == PI_BASED) + { + // Adjust DQS output delay. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), wrlevel_dqs_delay[0], SHU_R0_B0_DQ0_ARPI_PBYTE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), wrlevel_dqs_delay[1], SHU_R0_B1_DQ0_ARPI_PBYTE_B1); + } + else // stDelayBase == DLY_BASED + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1); + } + } + + vSetRank(p, backup_rank); + + mcSHOW_DBG_MSG(("[WriteLevelingPosCal] DQS PI B0/B1 = %d/%d\n", wrlevel_dqs_delay[0], wrlevel_dqs_delay[1])); +} +#endif + +#define SET_PATTERN_MANUALLY_FOR_DEBUG 1 +DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase) +{ +// Note that below procedure is based on "ODT off" + DRAM_STATUS_T KResult = DRAM_FAIL; + + U8 byte_i, rank_i, ucDoneFlg; + DRAM_RANK_T backup_rank; + + S32 wrlevel_dqs_delay[DQS_NUMBER]; // 3 is channel number + + S32 s4DlyBegin, s4DlyEnd; + U8 u1PIStep; + U8 u1OverBoundCnt = 0; + S16 PI_bound = 64; + + //When doing WriteLeveling, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); + + // error handling + if (!p) + { + mcSHOW_ERR_MSG(("context NULL\n")); + return DRAM_FAIL; + } + +#if VENDER_JV_LOG + vPrintCalibrationBasicInfo_ForJV(p); +#else + vPrintCalibrationBasicInfo(p); +#endif + + + fgwrlevel_done = 0; + backup_rank = u1GetRank(p); + + //DramcRankSwap(p, p->rank); + //tx_rank_sel is selected by SW //Lewis@20180604: tx_rank_sel is selected by SW in WL if TMRRI design has changed. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), p->rank, TX_SET0_TXRANK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK + + // backup mode settings + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3)), + (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)) + }; + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + + //default set DRAM FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, DRAM_FAIL); + +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + + if (p->isWLevInitShift[p->channel] == FALSE) + { + // It must be PI_BASED or FAIL!! + ASSERT(stDelayBase == PI_BASED); + + p->isWLevInitShift[p->channel] = TRUE; + + // This flow would be excuted just one time, so all ranks(maybe rank0/1) should be adjusted at once. + ShiftDQUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); + ShiftDQ_OENUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); + ShiftDQSWCK_UI(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + // For DLY based WCK leveling + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), 0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), 0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1); + + // Set DQS DLY-based delay to 16 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1); + } +#endif + // Set DQS PI-based delay to 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay + + } + + // decide algorithm parameters according to freq.(PI mode/ phase mode) + WriteLevelingScanRange_PI(p, &s4DlyBegin, &s4DlyEnd, &u1PIStep, &PI_bound, stDelayBase); + + // Not support autok to delay cell based mode. + if (stDelayBase == DLY_BASED) + isAutoK = FALSE; + + +#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_WRITELEVELING) + if (p->femmc_Ready == 1) + { + wrlevel_dqs_final_delay[p->rank][0] = p->pSavetimeData->u1WriteLeveling_bypass_Save[p->channel][p->rank][0]; + wrlevel_dqs_final_delay[p->rank][1] = p->pSavetimeData->u1WriteLeveling_bypass_Save[p->channel][p->rank][1]; + + ucDoneFlg = 0xff; + KResult = DRAM_OK; + vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, DRAM_FAST_K); + } +#endif + + if (u1OverBoundCnt > 0) + ShiftDQSWCK_UI(p, -u1OverBoundCnt * (PI_bound / DQPI_PER_UI), ALL_BYTES); + + if (ucDoneFlg == 0xff) + { + // all bytes are done + fgwrlevel_done = 1; + KResult = DRAM_OK; + } + else + { + KResult = DRAM_FAIL; + #if __FLASH_TOOL_DA__ + PINInfo_flashtool.WL_ERR_FLAG|=(0x1<<(p->channel*2+p->rank)); + #endif + } + vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, KResult); + mcSHOW_DBG_MSG2(("pass bytecount = 0x%x (0xff: all bytes pass) \n\n", ucDoneFlg)); + +#if defined(FOR_HQA_TEST_USED) && defined(FOR_HQA_REPORT_USED) + if (gHQALog_flag == 1) + { + for (byte_i = 0; byte_i < (p->data_width / DQS_BIT_NUMBER); byte_i++) + { + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_DQS", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i], NULL); + } + } +#endif + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + + vSetLP5Dram_WCK2CK_WlevOnOff(p, DISABLE); + else +#endif + vSetDramMRWriteLevelingOnOff(p, DISABLE); // Disable DDR write leveling mode: issue MR2[7] to enable write leveling + + + // Write leveling enable OFF + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); + + //Disable DQ_O1, SELO1ASO=0 for power saving + O1PathOnOff(p, OFF); + + //tx_rank_sel is selected by HW + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK + + //restore registers. + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + // Calculate DQS "PI" delay, nothing to do with delay cell + for (byte_i = 0; byte_i < (p->data_width / DQS_BIT_NUMBER); byte_i++) + { + mcSHOW_DBG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i])); + mcDUMP_REG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i])); + if (wrlevel_dqs_final_delay[p->rank][byte_i] >= PI_bound) + { + ShiftDQSWCK_UI(p, (wrlevel_dqs_final_delay[p->rank][byte_i] / PI_bound) * (PI_bound / DQPI_PER_UI), byte_i); + + wrlevel_dqs_final_delay[p->rank][byte_i] %= PI_bound; + } + + wrlevel_dqs_delay[byte_i] = wrlevel_dqs_final_delay[p->rank][byte_i]; + mcSHOW_DBG_MSG((" => %d\n", wrlevel_dqs_delay[byte_i])); + mcDUMP_REG_MSG((" => %d\n", wrlevel_dqs_delay[byte_i])); + } + + for (rank_i = p->rank; rank_i < RANK_MAX; rank_i++) + { + vSetRank(p, rank_i); + + // set to best values for DQS + if (stDelayBase == PI_BASED) + { + // Adjust DQS output delay. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), wrlevel_dqs_delay[0], SHU_R0_B0_DQ0_ARPI_PBYTE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), wrlevel_dqs_delay[1], SHU_R0_B1_DQ0_ARPI_PBYTE_B1); + } + else // stDelayBase == DLY_BASED + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1); + } + } + + vSetRank(p, backup_rank); + + mcSHOW_DBG_MSG3(("[DramcWriteLeveling] Done\n\n")); + + return KResult; +} +#endif //SIMULATION_WRITE_LEVELING + +#if (SIMULATION_DUTY_CYC_MONITOR == 1) +static U8 FetchRGSettingVal(int step_val) +{ + if (step_val <= 0) + return (U8)(-step_val); + else + return ((U8)step_val | 0x08); +} + +DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p) +{ + U8 backup_rank; +// U8 u8ResultDutyCycMonitor[WHOLE_STEPS_NUM] = {0}; + + // error handling + if (!p) + { + mcSHOW_ERR_MSG(("context NULL\n")); + return DRAM_FAIL; + } + + vAutoRefreshSwitch(p, DISABLE); + //CKEFixOnOff(p, p->rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + backup_rank = u1GetRank(p); + + RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_FS); + + int i = -7; + for (i = -7; i <= 7; i++) + { + // MRW MR30 OP[7:4] = i(Set DCAU) and OP[3:0] = i(Set DCAL) + U8 u8RGSettingVal = FetchRGSettingVal(i); + mcSHOW_ERR_MSG(("Set value %d into MR30\n", u8RGSettingVal)); + MRWriteFldMulti(p, 30, P_Fld(u8RGSettingVal, MR30_DCAU) | + P_Fld(u8RGSettingVal, MR30_DCAL), + TO_MR); + + // Start duty cycle monitor + DramcMRWriteFldAlign(p, 26, 1, MR26_DCM_START_STOP, TO_MR); + + // Delay tDCMM(2us) + mcDELAY_US(2); + + // Duty cycle monitor Flip 0 -> 1, and store result of flip = 0 + DramcMRWriteFldAlign(p, 26, 1, MR26_DCM_FLIP, TO_MR); + + // Delay tDCMM(2us) + mcDELAY_US(2); + + // Duty cycle monitor Flip 1 -> 0, and store result of flip = 1 + DramcMRWriteFldAlign(p, 26, 0, MR26_DCM_FLIP, TO_MR); + + // Delay tDCMM(2us) + mcDELAY_US(2); + + // Stop Duty cycle monitor + DramcMRWriteFldAlign(p, 26, 0, MR26_DCM_START_STOP, TO_MR); + + // Delay tMRD + mcDELAY_US(2); + + mcSHOW_ERR_MSG(("Wait tMRD and MRR MR26\n")); + + ///TODO: Read back result MR25[5:2] + // Store result into u8ResultDutyCycMonitor[] + + } + ///TODO: Find and set a best MR30 variables + + RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_OFF); + + vAutoRefreshSwitch(p, ENABLE); + //CKEFixOnOff(p, p->rank, CKE_DYNAMIC, CKE_WRITE_TO_ONE_CHANNEL); + + vSetRank(p, backup_rank); +} +#endif // SIMULATION_DUTY_CYC_MONITOR + +void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p) +{ + U8 u1RankIdx, u1RankIdxBak; + U32 u4WbrBackup = GetDramcBroadcast(); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + u1RankIdxBak = u1GetRank(p); + + for(u1RankIdx=RANK_0; u1RankIdx<RANK_MAX; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_CA_TXDLY0, + P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA0_DLY) | + P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA1_DLY) | + P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA2_DLY) | + P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA3_DLY)); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_CA_TXDLY1, + P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA4_DLY) | + P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA5_DLY) | + P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA6_DLY) | + P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA7_DLY)); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) + | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) + | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) + | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) + | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) + | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) + | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) + | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) + | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) + | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) + | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) + | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) + | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_R0_B0_TXDLY3, 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_R0_B1_TXDLY3, 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1); + } + + vSetRank(p, u1RankIdxBak); + DramcBroadcastOnOff(u4WbrBackup); +} + + +//Reset PHY to prevent glitch when change DQS gating delay or RX DQS input delay +// [Lynx] Evere_st : cannot reset single channel. All DramC and All Phy have to reset together. +void DramPhyReset(DRAMC_CTX_T *p) +{ + // Evere_st change reset order : reset DQS before DQ, move PHY reset to final. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 1, RX_SET0_RDATRST);// read data counter reset + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMPHYRST); + + //RG_ARCMD_RESETB & RG_ARDQ_RESETB_B0/1 only reset once at init, Justin Chan. + ///TODO: need to confirm RG_ARCMD_RESETB & RG_ARDQ_RESETB_B0/1 is reset at mem.c + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), + P_Fld(0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | + P_Fld(0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), + P_Fld(0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | + P_Fld(0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1)); + mcDELAY_US(1);//delay 10ns + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), + P_Fld(1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | + P_Fld(1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), + P_Fld(1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | + P_Fld(1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMPHYRST); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0, RX_SET0_RDATRST);// read data counter reset +} + +#if SIMULATION_LP4_ZQ +//------------------------------------------------------------------------- +/** DramcZQCalibration + * start Dram ZQ calibration. + * @param p Pointer of context created by DramcCtxCreate. + * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL + */ +//------------------------------------------------------------------------- +#if ZQ_SWCMD_MODE +static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) +{ + U32 u4Response; + U32 u4TimeCnt = TIME_OUT_CNT; + U32 u4SWCMDEN, u4SWCMDCTRL, u4SPDCTRL, u4CKECTRL; + + // Backup rank, CKE fix on/off, HW MIOCK control settings + u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); + u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)); + u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); + u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); + + mcSHOW_DBG_MSG3(("[ZQCalibration]\n")); + //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); + + // Disable HW MIOCK control to make CLK always on + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON); + mcDELAY_US(1); + + //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank. + CKEFixOnOff(p, rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + //select rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_SWTRIG_ZQ_RK); + + //ZQCAL Start + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQCEN_SWTRIG); + + do + { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_ZQC_SWTRIG_RESPONSE); + u4TimeCnt --; + mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + + mcSHOW_DBG_MSG3(("%d- ", u4TimeCnt)); + //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); + }while((u4Response==0) &&(u4TimeCnt>0)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN_SWTRIG); + + if(u4TimeCnt==0)//time out + { + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); + mcSHOW_DBG_MSG(("ZQCAL Start fail (time out)\n")); + //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n")); + return DRAM_FAIL; + } + + // [JC] delay tZQCAL + mcDELAY_US(1); + u4TimeCnt = TIME_OUT_CNT; + + //ZQCAL Latch + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQLATEN_SWTRIG); + do + { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE); + u4TimeCnt --; + mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling + + mcSHOW_DBG_MSG3(("%d=", u4TimeCnt)); + //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); + }while((u4Response==0) &&(u4TimeCnt>0)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN_SWTRIG); + + if(u4TimeCnt==0)//time out + { + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); + mcSHOW_DBG_MSG(("ZQCAL Latch fail (time out)\n")); + //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n")); + return DRAM_FAIL; + } + + // [JC] delay tZQLAT + mcDELAY_US(1); + + // Restore rank, CKE fix on, HW MIOCK control settings + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4SWCMDCTRL); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL); + + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK); + mcSHOW_DBG_MSG3(("\n[DramcZQCalibration] Done\n\n")); + //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n")); + + return DRAM_OK; +} +#endif +#if ZQ_RTSWCMD_MODE +DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) +{ + U32 u4Response; + U32 u4TimeCnt = TIME_OUT_CNT; + U32 u4SWCMDEN, u4SWCMDCTRL, u4MPCCTRL, u4RTSWCMD, u4SPDCTRL, u4CKECTRL; + + // Backup rank, CKE fix on/off, HW MIOCK control settings + u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); + u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2)); + u4MPCCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL)); + u4RTSWCMD = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT)); + u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); + u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); + + mcSHOW_DBG_MSG3(("[ZQCalibration]\n")); + //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); + + // Disable HW MIOCK control to make CLK always on + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON); + mcDELAY_US(1); + + //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank. + //CKEFixOnOff(p, rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + //select rank + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), + P_Fld(rank, SWCMD_CTRL2_RTSWCMD_RK) | + P_Fld(0x20, SWCMD_CTRL2_RTSWCMD_AGE)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0x1, MPC_CTRL_RTSWCMD_HPRI_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x2a, RTSWCMD_CNT_RTSWCMD_CNT); + + //ZQCAL Start + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x5, SWCMD_EN_RTSWCMD_SEL); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); + + do + { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE); + u4TimeCnt --; + mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + + mcSHOW_DBG_MSG3(("%d- ", u4TimeCnt)); + //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); + }while((u4Response==0) &&(u4TimeCnt>0)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); + + if(u4TimeCnt==0)//time out + { + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); + mcSHOW_DBG_MSG(("ZQCAL Start fail (time out)\n")); + //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n")); + return DRAM_FAIL; + } + + // [JC] delay tZQCAL + mcDELAY_US(1); + u4TimeCnt = TIME_OUT_CNT; + + //ZQCAL Latch + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x6, SWCMD_EN_RTSWCMD_SEL); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); + + do + { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE); + u4TimeCnt --; + mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling + + mcSHOW_DBG_MSG3(("%d=", u4TimeCnt)); + //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); + }while((u4Response==0) &&(u4TimeCnt>0)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); + + if(u4TimeCnt==0)//time out + { + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); + mcSHOW_DBG_MSG(("ZQCAL Latch fail (time out)\n")); + //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n")); + return DRAM_FAIL; + } + + // [JC] delay tZQLAT + mcDELAY_US(1); + + // Restore rank, CKE fix on, HW MIOCK control settings + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), u4SWCMDCTRL); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), u4MPCCTRL); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), u4RTSWCMD); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL); + + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK); + mcSHOW_DBG_MSG3(("\n[DramcZQCalibration] Done\n\n")); + //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n")); + + return DRAM_OK; +} +#endif +#if ZQ_SCSM_MODE +DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank) +{ + U32 u4Response; + U32 u4TimeCnt = TIME_OUT_CNT; + U32 u4SWCMDEN, u4MPCCTRL, u4SWCMDCTRL, u4SPDCTRL, u4CKECTRL; + + // Backup rank, CKE fix on/off, HW MIOCK control settings + u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); + u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)); + u4MPCCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION)); + u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); + u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); + + mcSHOW_DBG_MSG3(("[ZQCalibration]\n")); + //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); + + // Disable HW MIOCK control to make CLK always on + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON); + mcDELAY_US(1); + + //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank. + CKEFixOnOff(p, rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + //Use rank swap or MRSRK to select rank + //DramcRankSwap(p, p->rank); + //!!R_DMMRSRK(R_DMMPCRKEN=1) specify rank0 or rank1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_MRSRK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN); + + //ZQCAL Start + //R_DMZQCEN, 0x1E4[4]=1 for ZQCal Start + //Wait zqc_response=1 (dramc_conf_nao, 0x3b8[4]) + //R_DMZQCEN, 0x1E4[4]=0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQCEN); + do + { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_ZQC_RESPONSE); + u4TimeCnt --; + mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + + mcSHOW_DBG_MSG3(("%d- ", u4TimeCnt)); + //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); + }while((u4Response==0) &&(u4TimeCnt>0)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN); + + if(u4TimeCnt==0)//time out + { + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); + mcSHOW_DBG_MSG(("ZQCAL Start fail (time out)\n")); + //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n")); + return DRAM_FAIL; + } + + // [JC] delay tZQCAL + mcDELAY_US(1); + u4TimeCnt = TIME_OUT_CNT; + + //ZQCAL Latch + //R_DMZQLATEN, 0x1E4[6]=1 for ZQCal latch + //Wait zqlat_response=1 (dramc_conf_nao, 0x3b8[28]) + //R_DMZQLATEN, 0x1E4[6]=0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQLATEN); + do + { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_ZQLAT_RESPONSE); + u4TimeCnt --; + mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling + + mcSHOW_DBG_MSG3(("%d=", u4TimeCnt)); + //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); + }while((u4Response==0) &&(u4TimeCnt>0)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN); + + if(u4TimeCnt==0)//time out + { + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); + mcSHOW_DBG_MSG(("ZQCAL Latch fail (time out)\n")); + //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n")); + return DRAM_FAIL; + } + + // [JC] delay tZQLAT + mcDELAY_US(1); + + // Restore rank, CKE fix on, HW MIOCK control settings + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), u4SWCMDCTRL); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), u4MPCCTRL); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL); + + vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK); + mcSHOW_DBG_MSG3(("\n[DramcZQCalibration] Done\n\n")); + //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n")); + + return DRAM_OK; +} +#endif + +DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank) +{ + #if ZQ_SWCMD_MODE + return ZQ_SWCMD_MODE_Cal(p, rank); + #elif ZQ_RTSWCMD_MODE + return ZQ_RTSWCMD_MODE_Cal(p, rank); + #else //ZQ_SCSM_MODE + return ZQ_SCSM_MODE_Cal(p, rank); + #endif +} +#endif + +#if (SIMULATION_GATING == 1) +#define GATING_PATTERN_NUM_LP5 0x23 +#define GATING_GOLDEND_DQSCNT_LP5 0x4646 +#define RXDQS_GATING_AUTO_DBG_REG_NUM 6 +/* Preamble & Postamble setting. Currently use macro to define. + * Later may use speed or MR setting to decide + * !!! REVIEW !!! + */ + +#if GATING_ADJUST_TXDLY_FOR_TRACKING +U8 u1TXDLY_Cal_min =0xff, u1TXDLY_Cal_max=0; +U8 ucbest_coarse_mck_backup[RANK_MAX][DQS_NUMBER]; +U8 ucbest_coarse_ui_backup[RANK_MAX][DQS_NUMBER]; +U8 ucbest_coarse_mck_P1_backup[RANK_MAX][DQS_NUMBER]; +U8 ucbest_coarse_ui_P1_backup[RANK_MAX][DQS_NUMBER]; +#endif + + +struct rxdqs_gating_cal { + U8 dqsien_dly_mck; + U8 dqsien_dly_ui; + U8 dqsien_dly_pi; + + U8 dqsien_dly_mck_p1; + U8 dqsien_dly_ui_p1; + + U8 dqsien_pi_adj_step; + + U8 dqsien_pi_per_ui; + U8 dqsien_ui_per_mck; + U8 dqsien_freq_div; +}; + +struct rxdqs_gating_trans { + U8 dqs_lead[DQS_NUMBER]; + U8 dqs_lag[DQS_NUMBER]; + U8 dqs_high[DQS_NUMBER]; +#if GATING_LEADLAG_LOW_LEVEL_CHECK + U8 dqs_low[DQS_NUMBER]; +#endif + U8 dqs_transition[DQS_NUMBER]; + U8 dqs_transitioned[DQS_NUMBER]; + U8 dqsien_dly_mck_leadlag[DQS_NUMBER]; + U8 dqsien_dly_ui_leadlag[DQS_NUMBER]; + U8 dqsien_dly_pi_leadlag[DQS_NUMBER]; +}; + +struct rxdqs_gating_best_win { + U8 best_dqsien_dly_mck[DQS_NUMBER]; + U8 best_dqsien_dly_ui[DQS_NUMBER]; + U8 best_dqsien_dly_pi[DQS_NUMBER]; + U8 best_dqsien_dly_mck_p1[DQS_NUMBER]; + U8 best_dqsien_dly_ui_p1[DQS_NUMBER]; + U8 best_dqsien_dly_pi_p1[DQS_NUMBER]; +}; + +struct rxdqs_gating_auto_param { + U8 early_break; + U8 dbg_mode; + + U8 init_mck; + U8 init_ui; + U8 end_mck; + U8 end_ui; + U8 pi_offset; + + U8 burst_len; +}; + +#define ENABLE_GATING_AUTOK_WA 1 + +#if ENABLE_GATING_AUTOK_WA +U8 __wa__gating_swk_for_autok = 0; +U8 __wa__gating_autok_init_ui[RANK_MAX] = { 0 }; +#endif + +#if (__LP5_COMBO__) +static U8 u1GetLp5ReadLatency(DRAMC_CTX_T *p) +{ + U8 read_latency; + U8 rl, ckr, dvfsc; + + const U8 au1MR2MappingToRL_wo_dvfsc[2][12] = { + {3, 4, 5, 6, 8, 9, 10, 12, 13, 14, 15, 17}, /* CKR = 4:1 */ + {6, 8, 10, 12, 16, 18}, /* CKR = 2:1 */ + }; + + ///TODO: Spec has not specify these values + const U8 au1MR2MappingToRL_wi_dvfsc[2][6] = { + {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, /* CKR = 4:1 */ + {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, /* CKR = 2:1 */ + }; + + ckr = (u1MR18Value[p->dram_fsp] >> 7) & 0x1; + dvfsc = !!(u1MR19Value[p->dram_fsp] & 0x3); + rl = (u1MR02Value[p->dram_fsp] & 0xf); + + if (dvfsc) + read_latency = au1MR2MappingToRL_wi_dvfsc[ckr][rl]; + else + read_latency = au1MR2MappingToRL_wo_dvfsc[ckr][rl]; + + /* note that the uint of RL is nCK, convert to nWCK */ + if (ckr == 0) + read_latency *= 4; + else + read_latency *= 2; + + mcSHOW_DBG_MSG(("ckr = %d, dvfsc = %d, rl = %d, read_latency = %d\n", + ckr, dvfsc, rl, read_latency)); + + return read_latency; +} +#endif + +static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK) +{ + const U8 au1MR2MappingToRL[2][8] = {{6, 10, 14, 20, 24, 28, 32, 36}, //normal mode + {6, 10, 16, 22, 26, 32, 36, 40}}; //byte mode + U8 u1MR0_LatencyMode; + U8 u1MR2RLValue; + + u1MR2RLValue = u1MR02Value[p->dram_fsp] & 0x7; //MR2 Op[2:0] + U8 u1RX_Path_delay_UI, u1RealRL,u1StartUI, u1ExtraMCKfor1_4mode; + U8 u1MCK2CK_UI, u1ReadDQSINCTL, u1DQSINCTL_UI; + U8 u4TDQSCK_UI_min; + U8 u1GatingAheadDQS_UI; + + /* LPDDR5 uses same bit */ + if(gu2MR0_Value[p->rank] == 0xffff) //MR0 is not ready + { + u1MR0_LatencyMode = CBT_NORMAL_MODE; + } + else + { + u1MR0_LatencyMode = (gu2MR0_Value[p->rank]>>1) & 0x1; //MR0 OP[1], 0:normal mode, 1:byte mode + } + +#if (__LP5_COMBO__) + if (is_lp5_family(p)) { + u4TDQSCK_UI_min = 500 * p->frequency *2/ 1000000; + u1RealRL = u1GetLp5ReadLatency(p); + } else +#endif + { + u4TDQSCK_UI_min = 1500 * p->frequency *2/ 1000000; + u1RealRL = au1MR2MappingToRL[u1MR0_LatencyMode][u1MR2RLValue]; + } + + ///TODO: A60868 does not support LP5 DIV4, current setting is not provided for LP5 + if(vGet_Div_Mode(p) == DIV4_MODE) + { + u1MCK2CK_UI = 4; + u1ExtraMCKfor1_4mode = 1; + u1GatingAheadDQS_UI = 3; + } + else if (vGet_Div_Mode(p) == DIV8_MODE) + { + u1MCK2CK_UI = 8; + u1ExtraMCKfor1_4mode = 0; +#if (__LP5_COMBO__) + if (is_lp5_family(p)) { + if (p->frequency <= 1600) + u1GatingAheadDQS_UI = 1 * u1MCK2CK_UI; + else if (p->frequency == 1866) + u1GatingAheadDQS_UI = 4; + else + u1GatingAheadDQS_UI = 8; + } else +#endif + u1GatingAheadDQS_UI = 5; + } + else + { + /* DIV16, only for LP5 */ + u1MCK2CK_UI = 16; + u1ExtraMCKfor1_4mode = 0; + u1GatingAheadDQS_UI = 8; + } + + // RX_Path_delay_UI = RL*2 + tDQSCK_UI<1500~3500ps> - PHY_interanl<skip 30ps> - GatingAheadDQS<2UI> + if(1:4 mod)+1MCK + u1RX_Path_delay_UI = (u1RealRL<<1) + u4TDQSCK_UI_min - u1GatingAheadDQS_UI + (u1MCK2CK_UI*u1ExtraMCKfor1_4mode); + + u1ReadDQSINCTL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), MISC_SHU_RK_DQSCTL_DQSINCTL); + u1DQSINCTL_UI = u1ReadDQSINCTL * u1MCK2CK_UI; + + if(u1AutoK) + u1RX_Path_delay_UI += 0; //HW K start position = gating min position(1500ns) + else + u1RX_Path_delay_UI -= 3; //SW K start position = gating min position(1500ns) -3UI + + if(u1RX_Path_delay_UI >= u1DQSINCTL_UI) + u1StartUI = u1RX_Path_delay_UI - u1DQSINCTL_UI; + else + { + u1StartUI =0; + mcSHOW_ERR_MSG(("GatingStartPos err! Need to fine-tune default DQSINCTL value.\n(RX_Path_delay_UI %d) < DQSINCTL_UI %d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI)); + #if __ETT__ + while(1); + #endif + } + + mcSHOW_DBG_MSG(("[GatingStartPos] MR0_LatencyMode %d, u1RealRL %d , u4TDQSCK_UI_min %d, 1:4ExtraMCK %d\n", u1MR0_LatencyMode, u1RealRL, u4TDQSCK_UI_min, u1ExtraMCKfor1_4mode)); + mcDUMP_REG_MSG(("[GatingStartPos] MR0_LatencyMode %d, u1RealRL %d , u4TDQSCK_UI_min %d, 1:4ExtraMCK %d\n", u1MR0_LatencyMode, u1RealRL, u4TDQSCK_UI_min, u1ExtraMCKfor1_4mode)); + + if(u1AutoK) + { + mcSHOW_DBG_MSG(("RX_Path_delay_UI(%d) - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI)); + mcDUMP_REG_MSG(("RX_Path_delay_UI(%d) - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI)); + } + else + { + mcSHOW_DBG_MSG(("RX_Path_delay_UI(%d) -3 - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI)); + mcDUMP_REG_MSG(("RX_Path_delay_UI(%d) -3 - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI)); + } + + return u1StartUI; +} + +#if GATING_RODT_LATANCY_EN +U8 get_rodt_mck2ui(DRAMC_CTX_T *p) +{ + if (vGet_Div_Mode(p) == DIV16_MODE) + return 8; + else if (vGet_Div_Mode(p) == DIV8_MODE) + return 4; + else + return 2; +} +#endif + +static u8 rxdqs_gating_bypass(DRAMC_CTX_T *p) +{ +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_GatingCal + if (p->femmc_Ready == 1) { + mcSHOW_DBG_MSG(("[FAST_K] Bypass Gating Calibration\n")); + return 1; + } +#endif + + return 0; +} + +static void rxdqs_gating_fastk_save_restore(DRAMC_CTX_T *p, + struct rxdqs_gating_best_win *best_win, + struct rxdqs_gating_cal *gating_cal) +{ +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + u8 ui_per_mck = gating_cal->dqsien_ui_per_mck; + u8 freq_div = gating_cal->dqsien_freq_div; + u8 ch = p->channel; + u8 rk = p->rank; + u8 dqs_i; + + if (p->femmc_Ready == 1) { + for (dqs_i = 0; dqs_i < p->data_width/DQS_BIT_NUMBER; dqs_i++) { + best_win->best_dqsien_dly_mck[dqs_i] = + p->pSavetimeData->u1Gating_MCK_Save[ch][rk][dqs_i]; + best_win->best_dqsien_dly_ui[dqs_i] = + p->pSavetimeData->u1Gating_UI_Save[ch][rk][dqs_i]; + best_win->best_dqsien_dly_pi[dqs_i] = + p->pSavetimeData->u1Gating_PI_Save[ch][rk][dqs_i]; + + /* Calculate P1 */ + best_win->best_dqsien_dly_ui_p1[dqs_i] = + best_win->best_dqsien_dly_mck[dqs_i] * ui_per_mck + + best_win->best_dqsien_dly_ui[dqs_i] + freq_div; /* Total UI for Phase1 */ + best_win->best_dqsien_dly_mck_p1[dqs_i] = + best_win->best_dqsien_dly_ui_p1[dqs_i] / ui_per_mck; + best_win->best_dqsien_dly_ui_p1[dqs_i] = + best_win->best_dqsien_dly_ui_p1[dqs_i] % ui_per_mck; + + vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAST_K); + + mcSHOW_DBG_MSG(("[FAST_K] CH%d RK%d best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", + ch, rk, dqs_i, best_win->best_dqsien_dly_mck[dqs_i], + best_win->best_dqsien_dly_ui[dqs_i], + best_win->best_dqsien_dly_pi[dqs_i])); + mcSHOW_DBG_MSG(("[FAST_K] CH%d RK%d best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", + ch, rk, dqs_i, best_win->best_dqsien_dly_mck_p1[dqs_i], + best_win->best_dqsien_dly_ui_p1[dqs_i], + best_win->best_dqsien_dly_pi_p1[dqs_i])); + + } + } +#endif +} + +static void rxdqs_gating_misc_process(DRAMC_CTX_T *p, + struct rxdqs_gating_best_win *rxdqs_best_win) +{ +#if GATING_ADJUST_TXDLY_FOR_TRACKING + U8 u1TX_dly_DQSgated = 0; +#endif + U8 dqs_i; + + /* Set result of useless bytes (if any) as 0. */ + for (dqs_i = (p->data_width/DQS_BIT_NUMBER); dqs_i < DQS_NUMBER; dqs_i++) { + rxdqs_best_win->best_dqsien_dly_mck[dqs_i] = + rxdqs_best_win->best_dqsien_dly_ui[dqs_i] = + rxdqs_best_win->best_dqsien_dly_pi[dqs_i]= 0; + rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i] = + rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i] = + rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i]= 0; + +#if GATING_ADJUST_TXDLY_FOR_TRACKING + ucbest_coarse_mck_backup[p->rank][dqs_i] = + ucbest_coarse_ui_backup[p->rank][dqs_i] = 0; + ucbest_coarse_mck_P1_backup[p->rank][dqs_i] = + ucbest_coarse_ui_P1_backup[p->rank][dqs_i] = 0; +#endif + } + + for (dqs_i=0; dqs_i<(p->data_width/DQS_BIT_NUMBER); dqs_i++) { +#ifdef FOR_HQA_REPORT_USED + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "DQSINCTL ", "", 0, + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), MISC_SHU_RK_DQSCTL_DQSINCTL), NULL); + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, + "Gating_Center_", "2T", dqs_i, rxdqs_best_win->best_dqsien_dly_mck[dqs_i], NULL); + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, + "Gating_Center_", "05T", dqs_i, rxdqs_best_win->best_dqsien_dly_ui[dqs_i], NULL); + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, + "Gating_Center_", "PI", dqs_i, rxdqs_best_win->best_dqsien_dly_pi[dqs_i], NULL); +#endif + + /*TINFO="best DQS%d delay(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win.best_dqsien_dly_mck[dqs_i], rxdqs_best_win.best_dqsien_dly_ui[dqs_i], rxdqs_best_win.best_dqsien_dly_pi[dqs_i])); */ + mcSHOW_DBG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, + rxdqs_best_win->best_dqsien_dly_mck[dqs_i], + rxdqs_best_win->best_dqsien_dly_ui[dqs_i], + rxdqs_best_win->best_dqsien_dly_pi[dqs_i])); + mcDUMP_REG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, + rxdqs_best_win->best_dqsien_dly_mck[dqs_i], + rxdqs_best_win->best_dqsien_dly_ui[dqs_i], + rxdqs_best_win->best_dqsien_dly_pi[dqs_i])); + /* cc mark mcFPRINTF((fp_A60501,"best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, + rxdqs_best_win.best_dqsien_dly_mck[dqs_i], + rxdqs_best_win.best_dqsien_dly_ui[dqs_i], + rxdqs_best_win.best_dqsien_dly_pi[dqs_i])); + */ + +#if GATING_ADJUST_TXDLY_FOR_TRACKING + u1TX_dly_DQSgated = (rxdqs_best_win->best_dqsien_dly_mck[dqs_i] << 4) + + rxdqs_best_win->best_dqsien_dly_ui[dqs_i]; + + if (vGet_Div_Mode(p) == DIV16_MODE) + u1TX_dly_DQSgated >>= 4; + else if (vGet_Div_Mode(p) == DIV8_MODE) + u1TX_dly_DQSgated >>= 3; + else + u1TX_dly_DQSgated >>= 2; + + if (u1TX_dly_DQSgated < u1TXDLY_Cal_min) + u1TXDLY_Cal_min = u1TX_dly_DQSgated; + + ucbest_coarse_ui_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_ui[dqs_i]; + ucbest_coarse_mck_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_mck[dqs_i]; +#endif + } + + mcSHOW_DBG_MSG(("\n")); + //cc mark mcFPRINTF((fp_A60501,"\n")); + + for (dqs_i=0; dqs_i<(p->data_width/DQS_BIT_NUMBER); dqs_i++) { + /*TINFO="best DQS%d P1 delay(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win.best_dqsien_dly_mck_p1[dqs_i], rxdqs_best_win.best_dqsien_dly_ui_p1[dqs_i], rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i]*/ + mcSHOW_DBG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, + rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i], + rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i], + rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i])); + mcDUMP_REG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, + rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i], + rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i], + rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i])); + /* cc mark mcFPRINTF((fp_A60501,"best DQS%d P1 dly(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, + rxdqs_best_win.best_dqsien_dly_mck_p1[dqs_i], + rxdqs_best_win.best_dqsien_dly_ui_p1[dqs_i], + rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i])); + */ + +#if GATING_ADJUST_TXDLY_FOR_TRACKING + // find max gating TXDLY (should be in P1) + u1TX_dly_DQSgated = (rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i] << 4) + + rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i]; + + if (vGet_Div_Mode(p) == DIV16_MODE) + u1TX_dly_DQSgated >>= 4; + else if (vGet_Div_Mode(p) == DIV8_MODE) + u1TX_dly_DQSgated >>= 3; + else + u1TX_dly_DQSgated >>= 2; + + if(u1TX_dly_DQSgated > u1TXDLY_Cal_max) + u1TXDLY_Cal_max = u1TX_dly_DQSgated; + + ucbest_coarse_ui_P1_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i]; + ucbest_coarse_mck_P1_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i]; +#endif + } + +#if RDSEL_TRACKING_EN + //Byte 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), + (ucbest_coarse_mck_backup[p->rank][0] << 4) | (ucbest_coarse_ui_backup[p->rank][0]), + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), rxdqs_best_win->best_dqsien_dly_pi[0], + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); //PI + //Byte 1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), + (ucbest_coarse_mck_backup[p->rank][1] << 4) | (ucbest_coarse_ui_backup[p->rank][1]), + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1);//UI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), + rxdqs_best_win->best_dqsien_dly_pi[1], SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); //PI +#endif + +} + +static void rxdqs_gating_auto_cal_reset(DRAMC_CTX_T *p) +{ + /* Reset internal autok status and logic */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), + P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST) | + P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST) | + P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST)); + + mcDELAY_US(1); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), + P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST) | + P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST) | + P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST)); +} +static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, + struct rxdqs_gating_auto_param *auto_param) +{ + /* Before start calibration, reset all state machine and all rank's state */ + rxdqs_gating_auto_cal_reset(p); + + + /*----------- + * Normal Setting, Same as SW calibration + *---------------*/ + if (p->frequency == 800) { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), + 0x1, MISC_STBCAL1_STBCNT_SW_RST); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), + 0x1, MISC_STBCAL1_STBCNT_SHU_RST_EN); + + /* SELPH_MODE = BY RANK */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + 0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); + + if (p->dram_type == TYPE_LPDDR5) { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), + 0x1, MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD); + + /* PICG_EARLY_EN */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), + 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), + 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); + + /* BURST_MODE */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + 0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE); + +#if (__LP5_COMBO__) + if (is_lp5_family(p)) { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), + 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), + 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1); + } else +#endif + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), + 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), + 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), + 0x2, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), + 0x2, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), + 0x1, MISC_STBCAL_DQSIENMODE); + + /* New Rank Mode */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST) | + P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) | + P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), + 0x1, B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), + 0x1, B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1); + + /* dummy read */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), + 0x1, DUMMY_RD_DUMMY_RD_PA_OPT); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), + 0x1, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE); + + //Yulia add workaround for auto K pattern length. : Apply for all project before IPM_V2 + //Dummy read BL should be controlled by DQSIEN_AUTOK_BURST_LENGTH, but now we can only use dummy read length(DMY_RD_LEN) + //DMY_RD_LEN (0 for BL8, 1 for BL16, 3 for BL32) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), 3/*auto_param->burst_len*/, RK_DUMMY_RD_ADR_DMY_RD_LEN); + + /* Decide by HW Although Dummy read used, but TA2 has higher priority */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + 0x4, TEST2_A4_TESTAGENTRKSEL); + + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, + // MISC_STBCAL2_STBENCMPEN); + + /*----------- + * Auto calibration setting + *-------------------*/ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), + P_Fld(auto_param->init_mck, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI_MCK) | + P_Fld(auto_param->init_ui, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI__UI) | + P_Fld(auto_param->end_mck, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END_MCK) | + P_Fld(auto_param->end_ui, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END__UI) | + P_Fld(auto_param->pi_offset, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_PI_OFFSET) | + P_Fld(p->rank, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CUR_RANK) | + P_Fld(auto_param->burst_len, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_BURST_LENGTH) | + P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B0_EN) | + P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B1_EN)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), + auto_param->dbg_mode, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_DEBUG_MODE_EN); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), + auto_param->early_break, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_EARLY_BREAK_EN); + + /*--------- + * DV settings + *-------------------*/ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), + 0x0, MISC_STBCAL_PICGEN); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN)); + + mcSHOW_DBG_MSG(("[Gating] AUTO K with param:\n")); + mcSHOW_DBG_MSG(("\tinit_mck: %d, init_ui: %d, end_mck: %d, end_ui: %d\n", + auto_param->init_mck, auto_param->init_ui, + auto_param->end_mck, auto_param->end_ui)); + mcSHOW_DBG_MSG(("\tpi_offset: %d, early_break: %s\n", auto_param->pi_offset, + (auto_param->early_break)? "ENABLE" : "DISABLE")); +} + +static void rxdqs_gating_auto_cal_trigger(DRAMC_CTX_T *p) +{ + mcSHOW_DBG_MSG(("[Gating] AUTO K start...\n")); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), + 0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO); +} + +static void rxdqs_gating_auto_cal_stop(DRAMC_CTX_T *p) +{ + mcSHOW_DBG_MSG(("[Gating] AUTO K stop...\n")); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), + 0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO); + + rxdqs_gating_auto_cal_reset(p); +} + + +static void rxdqs_gating_set_final_result(DRAMC_CTX_T *p, U8 mck2ui, + struct rxdqs_gating_best_win *best_win) +{ +#if GATING_RODT_LATANCY_EN + U8 reg_mck, reg_ui; + U8 value; + U8 reg_mck_rodt[DQS_NUMBER], reg_ui_rodt[DQS_NUMBER]; + U8 reg_mck_rodt_p1[DQS_NUMBER], reg_ui_rodt_p1[DQS_NUMBER]; + U8 dqs_i; +#endif + +#if GATING_RODT_LATANCY_EN + for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) { + reg_mck = best_win->best_dqsien_dly_mck[dqs_i]; + reg_ui = best_win->best_dqsien_dly_ui[dqs_i]; + + value = (reg_mck * mck2ui) + reg_ui; + + if (value >= 11) { + U8 rodt_mck2ui = get_rodt_mck2ui(p); + + value -= 11; + reg_mck_rodt[dqs_i] = value / rodt_mck2ui; + reg_ui_rodt[dqs_i] = value % rodt_mck2ui; + + reg_mck_rodt_p1[dqs_i] = reg_mck_rodt[dqs_i]; + reg_ui_rodt_p1[dqs_i] = reg_ui_rodt[dqs_i]; + } else { + + reg_mck_rodt[dqs_i] = 0; + reg_ui_rodt[dqs_i] = 0; + reg_mck_rodt_p1[dqs_i] = 4; + reg_ui_rodt_p1[dqs_i] = 4; + mcSHOW_DBG_MSG(("[Warning] RODT cannot be -11UI for B%d\n", + dqs_i)); + } + + mcSHOW_DBG_MSG(("DQS%d Final RODTEN: (%2d, %2d)\n", + dqs_i, reg_mck_rodt[dqs_i], reg_ui_rodt[dqs_i])); + mcSHOW_DBG_MSG(("DQS%d Final RODTEN_P1: (%2d, %2d)\n", + dqs_i, reg_mck_rodt_p1[dqs_i], reg_ui_rodt_p1[dqs_i])); + } +#endif + + /* Set DQSIEN delay in MCK and UI */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(best_win->best_dqsien_dly_mck[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(best_win->best_dqsien_dly_ui[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(best_win->best_dqsien_dly_mck_p1[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(best_win->best_dqsien_dly_ui_p1[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(best_win->best_dqsien_dly_mck[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(best_win->best_dqsien_dly_ui[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(best_win->best_dqsien_dly_mck_p1[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(best_win->best_dqsien_dly_ui_p1[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + +#if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(reg_mck_rodt[0], + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(reg_ui_rodt[0], + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(reg_mck_rodt_p1[0], + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(reg_ui_rodt_p1[0], + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(reg_mck_rodt[1], + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(reg_ui_rodt[1], + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(reg_mck_rodt_p1[1], + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(reg_ui_rodt_p1[1], + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); +#endif + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), + best_win->best_dqsien_dly_pi[0], + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), + best_win->best_dqsien_dly_pi[1], + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + +} + + +/* By autoK: Set the result calibrated by HW to RG */ +static void rxdqs_gating_auto_xlate(DRAMC_CTX_T *p, + struct rxdqs_gating_best_win *best_win, + struct rxdqs_gating_cal *rxdqs_cal) +{ + u8 mck, ui, pi; + U8 mck_p1, ui_p1; + u8 mck2ui, freq_div; + U8 total_ui; +#if GATING_RODT_LATANCY_EN + U8 mck_rodt, ui_rodt; + U8 mck_rodt_p1, ui_rodt_p1; +#endif + U16 value; + u8 dqs_i; + + /* Transfer HW unit to RG unit */ + for (dqs_i = 0; dqs_i < p->data_width/DQS_BIT_NUMBER; dqs_i++) { + mck = best_win->best_dqsien_dly_mck[dqs_i]; + ui = best_win->best_dqsien_dly_ui[dqs_i]; + pi = best_win->best_dqsien_dly_pi[dqs_i]; + mck2ui = rxdqs_cal->dqsien_ui_per_mck; + freq_div = rxdqs_cal->dqsien_freq_div; + + if (vGet_Div_Mode(p) == DIV16_MODE) + total_ui = (mck << 4) + ui; /* 1:16 mode */ + else if (vGet_Div_Mode(p) == DIV8_MODE) + total_ui = (mck << 3) + ui; /* 1: 8 mode */ + else + total_ui = (mck << 2) + ui; /* 1: 4 mode */ + + /* RG is always 1:16 mode */ + mck = (total_ui >> 4); + ui = (total_ui & 0xf); + + value = mck * mck2ui + ui; /* Total UI number */ + mck_p1 = (value + freq_div) / mck2ui; + ui_p1 = (value + freq_div) % mck2ui; + + mcSHOW_DBG_MSG(("[Gating][RG] DQS%d Final result: (%d, %d, %d)\n", dqs_i, mck, ui, pi)); + mcSHOW_DBG_MSG(("[Gating][RG] DQS%d Final result P1: (%d, %d)\n", dqs_i, mck_p1, ui_p1)); + + best_win->best_dqsien_dly_mck[dqs_i] = mck; + best_win->best_dqsien_dly_ui[dqs_i] = ui; + best_win->best_dqsien_dly_pi[dqs_i] = pi; + + best_win->best_dqsien_dly_mck_p1[dqs_i] = mck_p1; + best_win->best_dqsien_dly_ui_p1[dqs_i] = ui_p1; + best_win->best_dqsien_dly_pi_p1[dqs_i] = pi; + } +} + +#define RXDQS_GATING_AUTO_CAL_STATUS_BYTE_OFFSET 0x40 + +static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p, + struct rxdqs_gating_auto_param *auto_param, + struct rxdqs_gating_best_win *best_win) +{ + U8 mck_center[DQS_NUMBER], ui_center[DQS_NUMBER], pi_center[DQS_NUMBER]; + U8 mck_left[DQS_NUMBER], ui_left[DQS_NUMBER], pi_left[DQS_NUMBER]; + U8 mck_right[DQS_NUMBER], ui_right[DQS_NUMBER], pi_right[DQS_NUMBER]; + U8 done[DQS_NUMBER] = { 0 }, error[DQS_NUMBER] = { 0 }; + DRAM_STATUS_T ret; + U8 done_bytes, total_bytes; + U8 byte_ofst; + U8 dqs_i; + + total_bytes = p->data_width / DQS_BIT_NUMBER; + done_bytes = 0; + ret = DRAM_OK; + + while (done_bytes < total_bytes) { + for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) { + /* If already done, skip this byte */ + if (done[dqs_i]) + continue; + + byte_ofst = dqs_i * RXDQS_GATING_AUTO_CAL_STATUS_BYTE_OFFSET; + + done[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_DONE_B0_RK0); + error[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_ERR_B0_RK0); + + /* If autok fail, done flag will not be asserted. */ + if (done[dqs_i] || error[dqs_i]) { + /* Done and Pass */ + if (error[dqs_i] == 0) { + mck_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK0); + ui_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK0); + pi_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK0); + + mck_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK0); + ui_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK0); + pi_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK0); + + /* If early break mode not enabled, right boundary could be found */ + if (auto_param->early_break == DISABLE) { + mck_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK0); + ui_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK0); + pi_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), + DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK0); + } + } + else + { + /* If error occurred for this byte, it will be treated as a DONE condition */ + done[dqs_i] = 1; + } + + if (auto_param->dbg_mode == ENABLE) { + U32 dbg_reg_addr; + U32 dbg_reg_idx; + U32 dbg_reg_val; + + dbg_reg_addr = DRAMC_REG_ADDR( + DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS0 + byte_ofst); + for (dbg_reg_idx = 0; + dbg_reg_idx < RXDQS_GATING_AUTO_DBG_REG_NUM; + dbg_reg_idx++, dbg_reg_addr += 4) { + dbg_reg_val = u4IO32Read4B(dbg_reg_addr); + + mcSHOW_ERR_MSG(("B%d Gating AUTOK DBG Status-%d: [0x%08x]\n", + dqs_i, dbg_reg_idx, dbg_reg_val)); + } + } + done_bytes++; + } + } + + mcDELAY_MS(1); + } + + /* Log it */ + for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) { + mcSHOW_DBG_MSG(("[Gating][%s] AUTOK of CH-%d, Rk-%d, Byte-%d:\n", + error[dqs_i]? "Fail" : "Pass", p->channel, p->rank, dqs_i)); + + if (done[dqs_i]) { + if (error[dqs_i] == 0) { + mcSHOW_DBG_MSG(("\tcenter(%2d, %2d, %2d)\n", + mck_center[dqs_i], ui_center[dqs_i], pi_center[dqs_i])); + mcSHOW_DBG_MSG(("\tleft(%2d, %2d, %2d)\n", + mck_left[dqs_i], ui_left[dqs_i], pi_left[dqs_i])); + + if (auto_param->early_break == DISABLE) { + mcSHOW_DBG_MSG(("\tright(%2d, %2d, %2d)\n", + mck_right[dqs_i], ui_right[dqs_i], pi_right[dqs_i])); + } + } + if (error[dqs_i]) { + ret = DRAM_FAIL; + } else { + /* If passed, shall set the result to RG */ + best_win->best_dqsien_dly_mck[dqs_i] = mck_center[dqs_i]; + best_win->best_dqsien_dly_ui[dqs_i] = ui_center[dqs_i]; + best_win->best_dqsien_dly_pi[dqs_i] = pi_center[dqs_i]; + } + } + } + + rxdqs_gating_auto_cal_stop(p); + + return ret; +} + +static DRAM_STATUS_T dramc_rx_dqs_gating_auto_cal(DRAMC_CTX_T *p) +{ + struct rxdqs_gating_auto_param auto_param; + struct rxdqs_gating_best_win rxdqs_best_win; + struct rxdqs_gating_cal rxdqs_cal; + DRAM_STATUS_T ret; + U8 start_ui, end_ui; + U8 mck2ui_hw; + + U32 reg_backup_address[ ] = { + (DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)), + (DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4)), + (DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR)) + }; + + DramcBackupRegisters(p, reg_backup_address, + sizeof (reg_backup_address) / sizeof (U32)); + + ret = DRAM_OK; + + memset((void *)&auto_param, 0, sizeof auto_param); + memset((void *)&rxdqs_best_win, 0, sizeof rxdqs_best_win); + memset((void *)&rxdqs_cal, 0, sizeof rxdqs_cal); + + if (vGet_Div_Mode(p) == DIV4_MODE) + rxdqs_cal.dqsien_freq_div = 2; + else + rxdqs_cal.dqsien_freq_div = 4; + rxdqs_cal.dqsien_ui_per_mck = DQS_GW_UI_PER_MCK; + + if (!rxdqs_gating_bypass(p)) { + /* 60868 has different mck2ui relations for HW and RG */ + if (vGet_Div_Mode(p) == DIV16_MODE) + mck2ui_hw = 16; + else if (vGet_Div_Mode(p) == DIV8_MODE) + mck2ui_hw = 8; + else + mck2ui_hw = 4; + +#if ENABLE_GATING_AUTOK_WA + if (__wa__gating_autok_init_ui[p->rank] > 3) + start_ui = __wa__gating_autok_init_ui[p->rank] - 3; + else +#endif + start_ui = u1GetGatingStartPos(p, AUTOK_ON); + end_ui = start_ui + 32; + + /* Set auto calibration params */ + auto_param.early_break = ENABLE; + auto_param.dbg_mode = ENABLE; + auto_param.init_mck = start_ui / mck2ui_hw; + auto_param.init_ui = start_ui % mck2ui_hw; + auto_param.end_mck = end_ui / mck2ui_hw; + auto_param.end_ui = end_ui % mck2ui_hw; + auto_param.pi_offset = 2; /* 2 ^ 2 = 4 */ + auto_param.burst_len = RXDQS_BURST_LEN_8; + +#if FOR_DV_SIMULATION_USED == 1 + cal_sv_rand_args_t *psra = get_psra(); + + if (psra) { + auto_param.early_break = + psra->dqsien_autok_early_break_en? ENABLE: DISABLE; + auto_param.dbg_mode = + psra->dqsien_autok_dbg_mode_en? ENABLE: DISABLE; + auto_param.pi_offset = + psra->dqsien_autok_pi_offset? ENABLE: DISABLE; + } +#endif /* FOR_DV_SIMULATION_USED == 1 */ + + rxdqs_gating_auto_cal_cfg(p, &auto_param); + + /* Trigger HW auto k */ + rxdqs_gating_auto_cal_trigger(p); + + ret = rxdqs_gating_auto_cal_status(p, &auto_param, &rxdqs_best_win); + if (ret == DRAM_OK) + vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_OK); + + rxdqs_gating_auto_xlate(p, &rxdqs_best_win, &rxdqs_cal); + } + + rxdqs_gating_fastk_save_restore(p, &rxdqs_best_win, &rxdqs_cal); + rxdqs_gating_set_final_result(p, rxdqs_cal.dqsien_ui_per_mck, &rxdqs_best_win); + + rxdqs_gating_misc_process(p, &rxdqs_best_win); + DramcRestoreRegisters(p, reg_backup_address, + sizeof (reg_backup_address) / sizeof (U32)); + + DramPhyReset(p); + + return ret; +} + +static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) +{ + + /* Disable Per-Bank ref */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0), 0, SHU_CONF0_PBREFEN); + + /*---------------- + * From DV + *------------------------*/ + if (p->frequency == 800) { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), + 0x1, MISC_STBCAL1_STBCNT_SW_RST); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), + 0x1, MISC_STBCAL1_STBCNT_SHU_RST_EN); + + /* SELPH_MODE = BY RANK */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + 0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); + + if (p->dram_type == TYPE_LPDDR5) { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), + 0x1, MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD); + + /* PICG_EARLY_EN */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), + 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), + 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); + + /* BURST_MODE */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + 0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE); + +#if (__LP5_COMBO__) + if (is_lp5_family(p)) { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), + 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), + 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1); + } else +#endif + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), + 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), + 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), + 0x2, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), + 0x2, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), + 0x1, MISC_STBCAL_DQSIENMODE); + + /* New Rank Mode */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST) | + P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) | + P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), + 0x1, B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), + 0x1, B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1); + + //DramcHWGatingOnOff(p, 0); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, + MISC_STBCAL2_STBENCMPEN); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0, + RX_SET0_DM4TO1MODE); + + /* enable &reset DQS counter */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, + MISC_STBCAL2_DQSG_CNT_EN); + mcDELAY_US(4); /* wait 1 auto refresh after DQS Counter enable */ + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, + MISC_STBCAL2_DQSG_CNT_RST); + mcDELAY_US(1); /* delay 2T */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, + MISC_STBCAL2_DQSG_CNT_RST); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), + u1GetRank(p), MISC_CTRL1_R_DMSTBENCMP_RK_OPT); + DramcEngine2Init(p, 0x55000000, + 0xaa000000 | GATING_PATTERN_NUM_LP5, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT); + + if (use_enhanced_rdqs) { + /* TBD. Enter Enhanced RDQS training mode */ + } +} + +static void rxdqs_gating_set_dqsien_dly(DRAMC_CTX_T *p, U8 dly_ui, + struct rxdqs_gating_cal *rxdqs_cal) +{ + U32 reg_mck, reg_ui; + U32 reg_mck_p1, reg_ui_p1; +#if GATING_RODT_LATANCY_EN + U32 reg_mck_rodt, reg_ui_rodt; + U32 reg_mck_rodt_p1, reg_ui_rodt_p1; +#endif + U8 mck2ui = rxdqs_cal->dqsien_ui_per_mck; + + rxdqs_cal->dqsien_dly_mck = dly_ui / rxdqs_cal->dqsien_ui_per_mck; + rxdqs_cal->dqsien_dly_ui = dly_ui % rxdqs_cal->dqsien_ui_per_mck; + rxdqs_cal->dqsien_dly_mck_p1 = (dly_ui + rxdqs_cal->dqsien_freq_div) / mck2ui; + rxdqs_cal->dqsien_dly_ui_p1 = (dly_ui + rxdqs_cal->dqsien_freq_div) % mck2ui; + + reg_mck = rxdqs_cal->dqsien_dly_mck; + reg_ui = rxdqs_cal->dqsien_dly_ui; + reg_mck_p1 = rxdqs_cal->dqsien_dly_mck_p1; + reg_ui_p1 = rxdqs_cal->dqsien_dly_ui_p1; + +#if GATING_RODT_LATANCY_EN + value = (reg_mck * mck2ui) + reg_ui; + + if (value >= 11) { + /* For RODT, MCK2UI is different from Gating */ + U8 rodt_mck2ui = get_rodt_mck2ui(p); + + value -= 11; + reg_mck_rodt = value / rodt_mck2ui; + reg_ui_rodt = value % rodt_mck2ui; + + reg_mck_rodt_p1 = reg_mck_rodt; + reg_ui_rodt_p1 = reg_ui_rodt; + } else { + + reg_mck_rodt = 0; + reg_ui_rodt = 0; + reg_mck_rodt_p1 = 4; + reg_ui_rodt_p1 = 4; + mcSHOW_DBG_MSG(("[Warning] RODT cannot be -11UI\n")); + } +#endif + + /* Set DQSIEN delay in MCK and UI */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(reg_mck, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(reg_ui, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(reg_mck_p1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(reg_ui_p1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(reg_mck, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(reg_ui, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(reg_mck_p1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(reg_ui_p1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + +#if GATING_RODT_LATANCY_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), + P_Fld(reg_mck_rodt, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | + P_Fld(reg_ui_rodt, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | + P_Fld(reg_mck_rodt_p1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | + P_Fld(reg_ui_rodt_p1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), + P_Fld(reg_mck_rodt, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | + P_Fld(reg_ui_rodt, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | + P_Fld(reg_mck_rodt_p1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | + P_Fld(reg_ui_rodt_p1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); +#endif +} + +static void rxdqs_gating_sw_cal_trigger(DRAMC_CTX_T *p, + struct rxdqs_gating_cal *rxdqs_cal) +{ +#if 0//ENABLE_DDR800_OPEN_LOOP_MODE_OPTION -> No 0.5UI after A60868 + if (u1IsPhaseMode(p) == TRUE) { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), + rxdqs_cal->dqsien_dly_pi >> 4, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), + rxdqs_cal->dqsien_dly_pi >> 4, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1); + } else +#endif + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), + rxdqs_cal->dqsien_dly_pi, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), + rxdqs_cal->dqsien_dly_pi, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + } + DramPhyReset(p); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, + MISC_STBCAL2_DQSG_CNT_RST); + mcDELAY_US(1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, + MISC_STBCAL2_DQSG_CNT_RST); + + /* enable TE2, audio pattern */ + DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN); +} + +static void rxdqs_gating_get_leadlag(DRAMC_CTX_T *p, + struct rxdqs_gating_trans *rxdqs_trans, + struct rxdqs_gating_cal *rxdqs_cal) +{ + U8 dqs_i; + U8 debounce_thrd_PI = 16; + + for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) { + if (dqs_i == 0) { + rxdqs_trans->dqs_lead[0] = u4IO32ReadFldAlign( + DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B0), + MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0); + rxdqs_trans->dqs_lag[0] = u4IO32ReadFldAlign( + DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B0), + MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0); + } else { + rxdqs_trans->dqs_lead[1] = u4IO32ReadFldAlign( + DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B1), + MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1); + rxdqs_trans->dqs_lag[1] = u4IO32ReadFldAlign( + DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B1), + MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1); + } + + if ((rxdqs_trans->dqs_lead[dqs_i] == 1) && + (rxdqs_trans->dqs_lag[dqs_i] == 1)) { + rxdqs_trans->dqs_high[dqs_i]++; + rxdqs_trans->dqs_transition[dqs_i] = 1; + + /* Record the latest value that causes (lead, lag) = (1, 1) */ + rxdqs_trans->dqsien_dly_mck_leadlag[dqs_i] = + rxdqs_cal->dqsien_dly_mck; + rxdqs_trans->dqsien_dly_ui_leadlag[dqs_i] = + rxdqs_cal->dqsien_dly_ui; + rxdqs_trans->dqsien_dly_pi_leadlag[dqs_i] = + rxdqs_cal->dqsien_dly_pi; + } else if ((rxdqs_trans->dqs_high[dqs_i] * + rxdqs_cal->dqsien_pi_adj_step) >= debounce_thrd_PI) { + /* Consecutive 16 PI DQS high for de-glitch */ + if (((rxdqs_trans->dqs_lead[dqs_i] == 1) && + (rxdqs_trans->dqs_lag[dqs_i] == 0)) || + ((rxdqs_trans->dqs_lead[dqs_i] == 0) && + (rxdqs_trans->dqs_lag[dqs_i] == 1))) { + rxdqs_trans->dqs_transition[dqs_i]++; + } + #if GATING_LEADLAG_LOW_LEVEL_CHECK + else if ((rxdqs_trans->dqs_lead[dqs_i] == 0) && + (rxdqs_trans->dqs_lag[dqs_i] == 0)){ + if ((rxdqs_trans->dqs_low[dqs_i] * + rxdqs_cal->dqsien_pi_adj_step) >= debounce_thrd_PI) { + /* (lead, lag) = (0, 0), transition done */ + rxdqs_trans->dqs_transitioned[dqs_i] = 1; + } + rxdqs_trans->dqs_low[dqs_i]++; + }else { + rxdqs_trans->dqs_high[dqs_i] = 0; + rxdqs_trans->dqs_low[dqs_i] = 0; + } + #else + else { + /* (lead, lag) = (0, 0), transition done */ + rxdqs_trans->dqs_transitioned[dqs_i] = 1; + } + #endif + } else { + /* Lead/lag = (1, 1) number is too few. Reset dqs_high */ + rxdqs_trans->dqs_high[dqs_i] = 0; + #if GATING_LEADLAG_LOW_LEVEL_CHECK + rxdqs_trans->dqs_low[dqs_i] = 0; + #endif + } + } +} + +static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p, + struct rxdqs_gating_trans *rxdqs_trans, + struct rxdqs_gating_cal *rxdqs_cal, U8 *pass_byte_count, + struct rxdqs_gating_best_win *best_win, U8 dly_ui, U8 dly_ui_end) +{ + U8 gating_error[DQS_NUMBER]; + U32 debug_cnt[DQS_NUMBER]; + U32 debug_pass_cnt; + U8 dqs_i; + U8 passed_bytes; + + memset(debug_cnt, 0, sizeof(debug_cnt)); + passed_bytes = *pass_byte_count; + + rxdqs_gating_sw_cal_trigger(p, rxdqs_cal); + + if (p->rank == RANK_0) { + gating_error[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_MISC_STBERR_ALL), + MISC_STBERR_ALL_GATING_ERROR_B0_RK0); + gating_error[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_MISC_STBERR_ALL), + MISC_STBERR_ALL_GATING_ERROR_B1_RK0); + } else { + gating_error[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_MISC_STBERR_ALL), + MISC_STBERR_ALL_GATING_ERROR_B0_RK1); + gating_error[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( + DDRPHY_REG_MISC_STBERR_ALL), + MISC_STBERR_ALL_GATING_ERROR_B1_RK1); + } + + /* read DQS counter + * Note: DQS counter is no longer used as pass condition. Here + * Read it and log it is just as debug method. Any way, DQS counter + * can still be used as a clue: it will be n*0x23 when gating is correct + */ + debug_cnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B0)); + debug_cnt[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B1)); + + /* read (lead, lag) */ + rxdqs_gating_get_leadlag(p, rxdqs_trans, rxdqs_cal); + + mcSHOW_DBG_MSG(("%2d %2d %2d | ", + rxdqs_cal->dqsien_dly_mck, rxdqs_cal->dqsien_dly_ui, + rxdqs_cal->dqsien_dly_pi)); + mcSHOW_DBG_MSG(("B1->B0 | %x %x | %x %x | (%d %d) (%d %d)\n", + debug_cnt[1], debug_cnt[0], + gating_error[1], gating_error[0], + rxdqs_trans->dqs_lead[1], rxdqs_trans->dqs_lag[1], + rxdqs_trans->dqs_lead[0], rxdqs_trans->dqs_lag[0])); + +#if (__LP5_COMBO__) + if((is_lp5_family(p)) && (vGet_Div_Mode(p) == DIV16_MODE)) + debug_pass_cnt = (GATING_GOLDEND_DQSCNT_LP5 >> 1); + else +#endif + debug_pass_cnt = GATING_GOLDEND_DQSCNT_LP5; + + /* Decide the window center */ + for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) { + if (passed_bytes & (1 << dqs_i)) + continue; + + if ((gating_error[dqs_i] == 0) && (debug_cnt[dqs_i] == debug_pass_cnt)) { + /* Calcuate DQSIEN position */ + if (rxdqs_trans->dqs_transitioned[dqs_i] != 0) { + U8 pass_count = rxdqs_trans->dqs_transition[dqs_i]; + U8 offset = (pass_count * rxdqs_cal->dqsien_pi_adj_step) / 2; + U8 mck2ui, ui2pi, freq_div; + U8 tmp; + + mck2ui = rxdqs_cal->dqsien_ui_per_mck; + ui2pi = rxdqs_cal->dqsien_pi_per_ui; + freq_div = rxdqs_cal->dqsien_freq_div; + + /* PI */ + tmp = rxdqs_trans->dqsien_dly_pi_leadlag[dqs_i] + offset; + best_win->best_dqsien_dly_pi[dqs_i] = tmp % ui2pi; + best_win->best_dqsien_dly_pi_p1[dqs_i] = + best_win->best_dqsien_dly_pi[dqs_i]; + + /* UI & MCK - P0 */ + tmp /= ui2pi; + tmp = rxdqs_trans->dqsien_dly_ui_leadlag[dqs_i] + tmp; + best_win->best_dqsien_dly_ui[dqs_i] = tmp % mck2ui; + best_win->best_dqsien_dly_mck[dqs_i] = + rxdqs_trans->dqsien_dly_mck_leadlag[dqs_i] + (tmp / mck2ui); + + /* UI & MCK - P1 */ + best_win->best_dqsien_dly_ui_p1[dqs_i] = + best_win->best_dqsien_dly_mck[dqs_i] * mck2ui + + best_win->best_dqsien_dly_ui[dqs_i] + freq_div; /* Total UI for Phase1 */ + mcSHOW_DBG_MSG(("Total UI for P1: %d, mck2ui %d\n", + best_win->best_dqsien_dly_mck_p1[dqs_i], mck2ui)); + best_win->best_dqsien_dly_mck_p1[dqs_i] = + best_win->best_dqsien_dly_ui_p1[dqs_i] / mck2ui; + best_win->best_dqsien_dly_ui_p1[dqs_i] = + best_win->best_dqsien_dly_ui_p1[dqs_i] % mck2ui; + + mcSHOW_DBG_MSG(("best dqsien dly found for B%d: " + "(%2d, %2d, %2d)\n", dqs_i, + best_win->best_dqsien_dly_mck[dqs_i], + best_win->best_dqsien_dly_ui[dqs_i], + best_win->best_dqsien_dly_pi[dqs_i])); + passed_bytes |= 1 << dqs_i; + + if (((p->data_width == DATA_WIDTH_16BIT) && + (passed_bytes == 0x3)) || + ((p->data_width == DATA_WIDTH_32BIT) && + (passed_bytes == 0xf))) { + dly_ui = dly_ui_end; + break; + } + } + } else { + /* Clear lead lag info in case lead/lag flag toggled + * while gating counter & gating error still incorrect + */ + rxdqs_trans->dqs_high[dqs_i] = 0; + rxdqs_trans->dqs_transition[dqs_i] = 0; + rxdqs_trans->dqs_transitioned[dqs_i] = 0; + } + } + + *pass_byte_count = passed_bytes; + return dly_ui; +} + +static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, + U8 use_enhance_rdqs) +{ + struct rxdqs_gating_cal rxdqs_cal; + struct rxdqs_gating_trans rxdqs_trans; + struct rxdqs_gating_best_win rxdqs_best_win; + U8 dly_ui, dly_ui_start, dly_ui_end; + U8 pi_per_ui, ui_per_mck, freq_div; + U8 pass_byte_count; + U8 dqs_i; + U8 u1GatingErrorFlag=0; + + if (p == NULL) { + mcSHOW_ERR_MSG(("[Error] Context NULL\n")); + return DRAM_FAIL; + } + + memset(&rxdqs_cal, 0, sizeof(struct rxdqs_gating_cal)); + memset(&rxdqs_trans, 0, sizeof(struct rxdqs_gating_trans)); + memset(&rxdqs_best_win, 0, sizeof(struct rxdqs_gating_best_win)); + + pi_per_ui = DQS_GW_PI_PER_UI; /* 1 UI = ? PI. Sams as CBT, differ according to data rate?? */ + ui_per_mck = DQS_GW_UI_PER_MCK; /* 1 mck = ? UI. Decided by (Tmck/Tck) * (Tck/Twck) */ + if (vGet_Div_Mode(p) == DIV4_MODE) + freq_div = 2; + else + freq_div = 4; + +#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION + if (u1IsPhaseMode(p) == TRUE) + rxdqs_cal.dqsien_pi_adj_step = (0x1 << 4); // Divide by 16 (90 degree) + else +#endif + rxdqs_cal.dqsien_pi_adj_step = DQS_GW_FINE_STEP; +#if ENABLE_GATING_AUTOK_WA + if (__wa__gating_swk_for_autok) + rxdqs_cal.dqsien_pi_adj_step = pi_per_ui; +#endif + rxdqs_cal.dqsien_pi_per_ui = pi_per_ui; + rxdqs_cal.dqsien_ui_per_mck = ui_per_mck; + rxdqs_cal.dqsien_freq_div = freq_div; + + U32 reg_backup_address[ ] = { + (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), + }; + + /* Register backup */ + DramcBackupRegisters(p, reg_backup_address, + sizeof (reg_backup_address) / sizeof (U32)); + + if (!rxdqs_gating_bypass(p)) { + rxdqs_gating_sw_cal_init(p, use_enhance_rdqs); + +#if 1 + #if (LP5_DDR4266_RDBI_WORKAROUND) + if((is_lp5_family(p)) && (p->frequency == 2133)) + dly_ui_start = 15; + else if((is_lp5_family(p)) && (p->frequency == 2750)) + dly_ui_start = 12; + else + dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF);//7; //12;ly_ui_start + 32; + #else + if((is_lp5_family(p)) && ((p->frequency == 2133) || (p->frequency == 2750))) + dly_ui_start = 5; + else + dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF);//7; //12;ly_ui_start + 32; + #endif + + dly_ui_end = dly_ui_start+ 32; + pass_byte_count = 0; +#else + #if __LP5_COMBO__ + if (is_lp5_family(p)) + { + if (p->frequency == 1600) + dly_ui_start = 7; //12; + else + dly_ui_start = 8; //12; + + dly_ui_end = dly_ui_start + 32; + pass_byte_count = 0; + } + else + #endif + { + dly_ui_start = 9; //12; Eddie change to 9 for Hynix Normal Mode + if(p->freq_sel==LP4_DDR4266) + { + dly_ui_start = 16; + } + dly_ui_end = dly_ui_start + 32; + pass_byte_count = 0; + } +#endif + + + for (dly_ui = dly_ui_start; dly_ui < dly_ui_end; + dly_ui += DQS_GW_COARSE_STEP) { + rxdqs_gating_set_dqsien_dly(p, dly_ui, &rxdqs_cal); + + for (rxdqs_cal.dqsien_dly_pi = 0; rxdqs_cal.dqsien_dly_pi < + pi_per_ui; rxdqs_cal.dqsien_dly_pi += + rxdqs_cal.dqsien_pi_adj_step) { + dly_ui = rxdqs_gating_sw_cal(p, &rxdqs_trans, &rxdqs_cal, + &pass_byte_count, &rxdqs_best_win, dly_ui, dly_ui_end); + + if (dly_ui == dly_ui_end) + break; + } + } + + DramcEngine2End(p); + + //check if there is no pass taps for each DQS + for (dqs_i=0; dqs_i<(p->data_width/DQS_BIT_NUMBER); dqs_i++) + { + if ((pass_byte_count<< dqs_i)==0) + { + u1GatingErrorFlag=1; + /*TINFO="error, no pass taps in DQS_%d !!!\n", dqs_i*/ + mcSHOW_ERR_MSG(("error, no pass taps in DQS_%d!\n", dqs_i)); + } + } + if (u1GatingErrorFlag==0) + vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_OK); + +#if (ENABLE_GATING_AUTOK_WA) + if (!u1GatingErrorFlag && __wa__gating_swk_for_autok) { + U8 ui[DQS_NUMBER], ui_min = 0xff; + U8 dqs_index; + for (dqs_index = 0; dqs_index < (p->data_width/DQS_BIT_NUMBER); dqs_index++){ + ui[dqs_index] = rxdqs_best_win.best_dqsien_dly_mck[dqs_index] * ui_per_mck + + rxdqs_best_win.best_dqsien_dly_ui[dqs_index]; + + if (ui[dqs_index] < ui_min) + ui_min = ui[dqs_index]; + } + __wa__gating_autok_init_ui[p->rank] = ui_min; + + DramcRestoreRegisters(p, reg_backup_address, + sizeof (reg_backup_address) / sizeof (U32)); + return DRAM_OK; + } +#endif + } + + rxdqs_gating_fastk_save_restore(p, &rxdqs_best_win, &rxdqs_cal); + rxdqs_gating_misc_process(p, &rxdqs_best_win); + + mcSHOW_DBG_MSG(("[Gating] SW calibration Done\n")); + + /* Set MCK & UI */ + rxdqs_gating_set_final_result(p, ui_per_mck, &rxdqs_best_win); + + DramcRestoreRegisters(p, reg_backup_address, + sizeof (reg_backup_address) / sizeof (U32)); + + DramPhyReset(p); + + return DRAM_OK; +} + +/* LPDDR5 Rx DQS Gating */ +DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, + u8 autok, U8 use_enhanced_rdqs) +{ + DRAM_STATUS_T ret; + + vPrintCalibrationBasicInfo(p); + +#if ENABLE_GATING_AUTOK_WA + if (autok) { + __wa__gating_swk_for_autok = 1; + dramc_rx_dqs_gating_sw_cal(p, use_enhanced_rdqs); + __wa__gating_swk_for_autok = 0; + } +#endif + + // default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAIL); + + /* Try HW auto calibration first. If failed, + * will try SW mode. + */ + if (autok) { +#if ENABLE_GATING_AUTOK_WA + if (rxdqs_gating_bypass(p)) /* Already done by SWK */ + return DRAM_OK; +#endif + ret = dramc_rx_dqs_gating_auto_cal(p); + if (ret == DRAM_OK) { + vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_OK); + return DRAM_OK; + } + + mcSHOW_ERR_MSG(("[Error] Gating auto calibration fail!!\n")); + } + + mcSHOW_DBG_MSG(("[Gating] SW mode calibration\n")); + + return dramc_rx_dqs_gating_sw_cal(p, use_enhanced_rdqs); +} + +///TODO: wait for porting +++ +#if GATING_ADJUST_TXDLY_FOR_TRACKING +void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) +{ + U8 dqs_i; + U8 u1RankIdx, u1RankMax; + S8 s1ChangeDQSINCTL; +#if XRTRTR_NEW_CROSS_RK_MODE + U16 u2PHSINCTL = 0; + U32 u4Rank_Sel_MCK_P0[2], u4Rank_Sel_MCK_P1[2], u4RANKINCTL_STB; +#endif +#if RDSEL_TRACKING_EN + U32 u4PI_value[2] = {0}; +#endif + U32 backup_rank; + U32 u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R, reg_TX_dly_DQSgated_min = 0; + U8 mck2ui_shift; + + backup_rank = u1GetRank(p); + +#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + if (vGet_Div_Mode(p) == DIV8_MODE) + { + // wei-jen: DQSgated_min should be 2 when freq >= 1333, 1 when freq < 1333 + if (p->frequency >= 1333) + { + reg_TX_dly_DQSgated_min = 2; + } + else + { + reg_TX_dly_DQSgated_min = 1; + } + } + else // for LPDDR4 1:4 mode + { + // 1866,1600,1333,1200 : reg_TX_dly_DQSgated (min) =2 + reg_TX_dly_DQSgated_min = 2; + } +#else + // wei-jen: DQSgated_min should be 3 when freq >= 1333, 2 when freq < 1333 + if (p->frequency >= 1333) + { + reg_TX_dly_DQSgated_min = 3; + } + else + { + reg_TX_dly_DQSgated_min = 2; + } +#endif + + //Sylv_ia MP setting is switched to new mode, so RANKRXDVS can be set as 0 (review by HJ Huang) +#if 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ7), u1RankRxDVS, SHU_B0_DQ7_R_DMRANKRXDVS_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B1_DQ7), u1RankRxDVS, SHU_B1_DQ7_R_DMRANKRXDVS_B1); +#endif + // === End of DVS setting ===== + + s1ChangeDQSINCTL = reg_TX_dly_DQSgated_min - u1TXDLY_Cal_min; + + mcSHOW_DBG_MSG(("[RxdqsGatingPostProcess] freq %d\n" + "ChangeDQSINCTL %d, reg_TX_dly_DQSgated_min %d, u1TXDLY_Cal_min %d\n", + p->frequency, + s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min)); + mcDUMP_REG_MSG(("[RxdqsGatingPostProcess] freq %d\n" + "ChangeDQSINCTL %d, reg_TX_dly_DQSgated_min %d, u1TXDLY_Cal_min %d\n", + p->frequency, + s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min)); + + if (vGet_Div_Mode(p) == DIV16_MODE) + mck2ui_shift = 4; + else if (vGet_Div_Mode(p) == DIV8_MODE) + mck2ui_shift = 3; + else + mck2ui_shift = 2; + + if (s1ChangeDQSINCTL != 0) // need to change DQSINCTL and TXDLY of each byte + { + u1TXDLY_Cal_min += s1ChangeDQSINCTL; + u1TXDLY_Cal_max += s1ChangeDQSINCTL; + + if (p->support_rank_num == RANK_DUAL) + u1RankMax = RANK_MAX; + else + u1RankMax = RANK_1; + + for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) + { + mcSHOW_DBG_MSG2(("Rank: %d\n", u1RankIdx)); + mcDUMP_REG_MSG(("Rank: %d\n", u1RankIdx)); + + for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) + { +#if 1 + U8 total_ui, total_ui_P1; + total_ui = (ucbest_coarse_mck_backup[u1RankIdx][dqs_i] << 4) + ucbest_coarse_ui_backup[u1RankIdx][dqs_i]; + total_ui_P1 = (ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] << 4) + ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i]; + + total_ui += (s1ChangeDQSINCTL << mck2ui_shift); + total_ui_P1 += (s1ChangeDQSINCTL << mck2ui_shift); + + ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = (total_ui >> 4); + ucbest_coarse_ui_backup[u1RankIdx][dqs_i] = total_ui & 0xf; + + ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = (total_ui_P1 >> 4); + ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] = total_ui_P1 & 0xf; +#else + if (vGet_Div_Mode(p) == DIV8_MODE) + { + u4ReadTXDLY[u1RankIdx][dqs_i] = ucbest_coarse_mck_backup[u1RankIdx][dqs_i]; + u4ReadTXDLY_P1[u1RankIdx][dqs_i] = ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i]; + + u4ReadTXDLY[u1RankIdx][dqs_i] += s1ChangeDQSINCTL; + u4ReadTXDLY_P1[u1RankIdx][dqs_i] += s1ChangeDQSINCTL; + + ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = u4ReadTXDLY[u1RankIdx][dqs_i]; + ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = u4ReadTXDLY_P1[u1RankIdx][dqs_i]; + } + else // LP3 or LP4 1:4 mode + { + u4ReadTXDLY[u1RankIdx][dqs_i] = ((ucbest_coarse_mck_backup[u1RankIdx][dqs_i] << 1) + ((ucbest_coarse_ui_backup[u1RankIdx][dqs_i] >> 2) & 0x1)); + u4ReadTXDLY_P1[u1RankIdx][dqs_i] = ((ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] << 1) + ((ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] >> 2) & 0x1)); + + u4ReadTXDLY[u1RankIdx][dqs_i] += s1ChangeDQSINCTL; + u4ReadTXDLY_P1[u1RankIdx][dqs_i] += s1ChangeDQSINCTL; + + ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = (u4ReadTXDLY[u1RankIdx][dqs_i] >> 1); + ucbest_coarse_ui_backup[u1RankIdx][dqs_i] = ((u4ReadTXDLY[u1RankIdx][dqs_i] & 0x1) << 2) + (ucbest_coarse_ui_backup[u1RankIdx][dqs_i] & 0x3); + + ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = (u4ReadTXDLY_P1[u1RankIdx][dqs_i] >> 1); + ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] = ((u4ReadTXDLY_P1[u1RankIdx][dqs_i] & 0x1) << 2) + (ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] & 0x3); + } +#endif + mcSHOW_DBG_MSG(("best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i])); + mcDUMP_REG_MSG(("PostProcess best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i])); + } + for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) + { + mcSHOW_DBG_MSG(("best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i])); + mcDUMP_REG_MSG(("PostProcess best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i])); + } + } + + for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + // 4T or 2T coarse tune + /* Set DQSIEN delay in MCK and UI */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + P_Fld(ucbest_coarse_mck_backup[u1RankIdx][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | + P_Fld(ucbest_coarse_ui_backup[u1RankIdx][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | + P_Fld(ucbest_coarse_mck_P1_backup[u1RankIdx][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | + P_Fld(ucbest_coarse_ui_P1_backup[u1RankIdx][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + P_Fld(ucbest_coarse_mck_backup[u1RankIdx][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | + P_Fld(ucbest_coarse_ui_backup[u1RankIdx][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | + P_Fld(ucbest_coarse_mck_P1_backup[u1RankIdx][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | + P_Fld(ucbest_coarse_ui_P1_backup[u1RankIdx][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); + #if RDSEL_TRACKING_EN + //Byte 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), + (ucbest_coarse_mck_backup[u1RankIdx][0] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][0]), + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI + //Byte 1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), + (ucbest_coarse_mck_backup[u1RankIdx][1] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][1]), + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1);//UI + #endif + } + } + vSetRank(p, backup_rank); + + u4ReadDQSINCTL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), + MISC_SHU_RK_DQSCTL_DQSINCTL); + mcDUMP_REG_MSG(("u4ReadDQSINCTL=%d\n", u4ReadDQSINCTL)); + u4ReadDQSINCTL -= s1ChangeDQSINCTL; + + #if ENABLE_READ_DBI + if (p->DBI_R_onoff[p->dram_fsp]) + { + u4ReadDQSINCTL++; + #if 0//cc mark for reg not found + u4ReadRODT = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_RODT); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), u4ReadRODT + 1, SHU_ODTCTRL_RODT); //update RODT value when READ_DBI is on + #endif + } + #endif + +#if XRTRTR_NEW_CROSS_RK_MODE + for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) + { + if (ucbest_coarse_mck_backup[RANK_0][dqs_i] > ucbest_coarse_mck_backup[RANK_1][dqs_i]) + { + u4Rank_Sel_MCK_P0[dqs_i] = (ucbest_coarse_mck_backup[RANK_0][dqs_i] > 0)? (ucbest_coarse_mck_backup[RANK_0][dqs_i] - 1): 0; + u4Rank_Sel_MCK_P1[dqs_i] = (ucbest_coarse_mck_P1_backup[RANK_0][dqs_i] > 0)? (ucbest_coarse_mck_P1_backup[RANK_0][dqs_i] - 1): 0; + } + else + { + u4Rank_Sel_MCK_P0[dqs_i] = (ucbest_coarse_mck_backup[RANK_1][dqs_i] > 0)? (ucbest_coarse_mck_backup[RANK_1][dqs_i] - 1): 0; + u4Rank_Sel_MCK_P1[dqs_i] = (ucbest_coarse_mck_P1_backup[RANK_1][dqs_i] > 0)? (ucbest_coarse_mck_P1_backup[RANK_1][dqs_i] - 1): 0; + } + } + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY), + P_Fld(u4Rank_Sel_MCK_P0[0], SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0) | + P_Fld(u4Rank_Sel_MCK_P1[0], SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY), + P_Fld(u4Rank_Sel_MCK_P0[1], SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1) | + P_Fld(u4Rank_Sel_MCK_P1[1], SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1)); + + u4RANKINCTL_STB = (u4ReadDQSINCTL > 2)? (u4ReadDQSINCTL - 2): 0; + u2PHSINCTL = (u4ReadDQSINCTL == 0)? 0: (u4ReadDQSINCTL - 1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), u4RANKINCTL_STB, MISC_SHU_RANKCTL_RANKINCTL_STB); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RANK_SEL_STB), u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL); +#endif + +#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + // Wei-Jen: RANKINCTL_RXDLY = RANKINCTL = RankINCTL_ROOT = u4ReadDQSINCTL-2, if XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY enable + // Wei-Jen: New algorithm : u4ReadDQSINCTL-2 >= 0 + if (u4ReadDQSINCTL >= 2) + { + u4RankINCTL_ROOT = u4ReadDQSINCTL - 2; + } + else + { + u4RankINCTL_ROOT = 0; + mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n")); +#if (__ETT__) + while (1); +#endif + } +#else + //Modify for corner IC failed at HQA test XTLV + if (u4ReadDQSINCTL >= 3) + { + u4RankINCTL_ROOT = u4ReadDQSINCTL - 3; + } + else + { + u4RankINCTL_ROOT = 0; + mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <3, Risk for supporting 1066/RL8\n")); + } +#endif + + //DQSINCTL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), + u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL); //Rank0 DQSINCTL + vSetRank(p, RANK_1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), + u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL); //Rank1 DQSINCTL + vSetRank(p, backup_rank); + + //No need to update RODT. If we update RODT, also need to update SELPH_ODTEN0_TXDLY + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), u4ReadDQSINCTL, SHU_ODTCTRL_RODT); //RODT = DQSINCTL + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), + u4ReadDQSINCTL, MISC_SHU_RANKCTL_RANKINCTL_PHY); //RANKINCTL_PHY = DQSINCTL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), + u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL); //RANKINCTL= DQSINCTL -3 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), + u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1); //RANKINCTL_ROOT1= DQSINCTL -3 + +#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), + u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_RXDLY); + + u4XRTR2R = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIM_XRT), SHU_ACTIM_XRT_XRTR2R); + + mcSHOW_DBG_MSG2(("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL)); + mcSHOW_DBG_MSG2(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); + mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); +#else + //XRTR2R=A-phy forbidden margin(6T) + reg_TX_dly_DQSgated (max) +Roundup(tDQSCKdiff/MCK+0.25MCK)+1(05T sel_ph margin)-1(forbidden margin overlap part) + //Roundup(tDQSCKdiff/MCK+1UI) =1~2 all LP3 and LP4 timing + //u4XRTR2R= 8 + u1TXDLY_Cal_max; // 6+ u1TXDLY_Cal_max +2 + + //Modify for corner IC failed at HQA test XTLV @ 3200MHz + u4XRTR2R = 8 + u1TXDLY_Cal_max + 1; // 6+ u1TXDLY_Cal_max +2 + if (u4XRTR2R > 12) + { + u4XRTR2R = 12; + mcSHOW_ERR_MSG(("XRTR2R > 12, Max value is 12\n")); + } + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIM_XRT), u4XRTR2R, SHU_ACTIM_XRT_XRTR2R); + + mcSHOW_DBG_MSG2(("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL)); + mcSHOW_DBG_MSG2(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); + mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); +#endif + +#if 0//ENABLE_RODT_TRACKING + //Because Ki_bo+,WE2,Bi_anco,Vin_son...or behind project support WDQS, they need to apply the correct new setting + //The following 2 items are indepentent + //1. if TX_WDQS on(by vendor_id) or p->odt_onoff = 1, ROEN/RODTE/RODTE2 = 1 + //2. if ENABLE_RODT_TRACKING on, apply new setting and RODTENSTB_TRACK_EN = ROEN + // LP4 support only + U8 u1ReadROEN; + u1ReadROEN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_ROEN); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RODTENSTB), P_Fld(0xff, SHU_RODTENSTB_RODTENSTB_EXT) | \ + P_Fld(u1ReadROEN, SHU_RODTENSTB_RODTENSTB_TRACK_EN)); +#endif + +#ifdef XRTR2W_PERFORM_ENHANCE_RODTEN + // LP4 support only + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), + P_Fld(0x0fff, MISC_SHU_RODTENSTB_RODTENSTB_EXT) | + P_Fld(1, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | + P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN)); +#endif + + vSetRank(p, backup_rank); + + +} +#endif + +#if GATING_ADJUST_TXDLY_FOR_TRACKING +void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p) +{ + u1TXDLY_Cal_min = 0xff; + u1TXDLY_Cal_max = 0; +} +#endif +///TODO: wait for porting --- + +#endif + +#if RDSEL_TRACKING_EN +void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p) +{ + U8 u1RankIdx; + S32 s4PosVH, s4NegVH; + U32 u4Gating_shift=0, u4Gating_origin_B0=0, u4Gating_origin_B1=0; + U32 u4Gating_origin_final=0xff; + + s4NegVH = divRoundClosest(400, ((1000000 / p->frequency) / 64)); + + for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + u4Gating_origin_B0 = ((ucbest_coarse_mck_backup[u1RankIdx][0] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][0])); + u4Gating_origin_B1 = ((ucbest_coarse_mck_backup[u1RankIdx][1] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][1])); + + if (u4Gating_origin_B0 < u4Gating_origin_B1) + { + u4Gating_origin_final = (u4Gating_origin_B0 < u4Gating_origin_final) ? u4Gating_origin_B0 : u4Gating_origin_final; + } + else + { + u4Gating_origin_final = (u4Gating_origin_B1 < u4Gating_origin_final) ? u4Gating_origin_B1 : u4Gating_origin_final; + } + } + + u4Gating_shift = ((((u4Gating_origin_final >> 3) & 0x1f) << 4) | (u4Gating_origin_final & 7)) - u4Gating_origin_B0; + + s4PosVH = s4NegVH + (u4Gating_shift << 5); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RDSEL_TRACK), P_Fld(s4PosVH, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS) + | P_Fld(-s4NegVH, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG)); +} +#endif + +#if RDDQC_PINMUX_WORKAROUND +static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p) +{ + U8 *uiLPDDR_RDDQC_Mapping; +#if (__LP5_COMBO__) + const U8 uiLPDDR5_RDDQC_Mapping_POP[CHANNEL_NUM][16] = + { + { + 8, 9, 10, 11, 12, 15, 14, 13, + 0, 1, 2, 3, 4, 7, 6, 5, + }, + #if (CHANNEL_NUM>1) + { + 8, 9, 10, 11, 12, 15, 14, 13, + 0, 1, 2, 3, 4, 7, 6, 5, + }, + #endif + }; + +#endif + const U8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_NUM][16] = + { + { + // for DSC + //CH-A + { + 0, 1, 6, 7, 4, 5, 3, 2, + 9, 8, 11, 10, 15, 14, 12, 13 + }, + #if (CHANNEL_NUM>1) + //CH-B + { + 1, 0, 5, 4, 7, 2, 3, 6, + 8, 9, 11, 10, 12, 14, 13, 15 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 0, 1, 6, 7, 4, 5, 3, 2, + 9, 8, 11, 10, 15, 14, 12, 13 + }, + //CH-D + { + 1, 0, 5, 4, 7, 2, 3, 6, + 8, 9, 11, 10, 12, 14, 13, 15 + }, + #endif + }, + { + // for LPBK + // TODO: need porting + }, + { + // for EMCP + //CH-A + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 12, 15, 14, 11, 13 + }, + #if (CHANNEL_NUM>1) + //CH-B + { + 0, 1, 7, 4, 2, 5, 6, 3, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif + #if (CHANNEL_NUM>2) + //CH-C + { + 1, 0, 3, 2, 4, 7, 6, 5, + 8, 9, 10, 12, 15, 14, 11, 13 + }, + //CH-D + { + 0, 1, 7, 4, 2, 5, 6, 3, + 9, 8, 10, 12, 11, 14, 13, 15 + }, + #endif + } + }; + + #if (__LP5_COMBO__) + if (is_lp5_family(p)) + { + uiLPDDR_RDDQC_Mapping = (U8 *)uiLPDDR5_RDDQC_Mapping_POP[p->channel]; + } + else + #endif + { + uiLPDDR_RDDQC_Mapping = (U8 *)uiLPDDR4_RDDQC_Mapping_POP[p->DRAMPinmux][p->channel]; + } + + + //Set RDDQC pinmux + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1), P_Fld(uiLPDDR_RDDQC_Mapping[0], MRR_BIT_MUX1_MRR_BIT0_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[1], MRR_BIT_MUX1_MRR_BIT1_SEL) | + P_Fld(uiLPDDR_RDDQC_Mapping[2], MRR_BIT_MUX1_MRR_BIT2_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[3], MRR_BIT_MUX1_MRR_BIT3_SEL)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2), P_Fld(uiLPDDR_RDDQC_Mapping[4], MRR_BIT_MUX2_MRR_BIT4_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[5], MRR_BIT_MUX2_MRR_BIT5_SEL) | + P_Fld(uiLPDDR_RDDQC_Mapping[6], MRR_BIT_MUX2_MRR_BIT6_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[7], MRR_BIT_MUX2_MRR_BIT7_SEL)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3), P_Fld(uiLPDDR_RDDQC_Mapping[8], MRR_BIT_MUX3_MRR_BIT8_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[9], MRR_BIT_MUX3_MRR_BIT9_SEL) | + P_Fld(uiLPDDR_RDDQC_Mapping[10], MRR_BIT_MUX3_MRR_BIT10_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[11], MRR_BIT_MUX3_MRR_BIT11_SEL)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4), P_Fld(uiLPDDR_RDDQC_Mapping[12], MRR_BIT_MUX4_MRR_BIT12_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[13], MRR_BIT_MUX4_MRR_BIT13_SEL) | + P_Fld(uiLPDDR_RDDQC_Mapping[14], MRR_BIT_MUX4_MRR_BIT14_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[15], MRR_BIT_MUX4_MRR_BIT15_SEL)); + +} +#endif + +#define RDDQCGOLDEN_LP5_MR30_BIT_CTRL_LOWER RDDQCGOLDEN_MR15_GOLDEN +#define RDDQCGOLDEN_LP5_MR31_BIT_CTRL_UPPER RDDQCGOLDEN_MR20_GOLDEN +#define RDDQCGOLDEN_LP5_MR32_PATTERN_A RDDQCGOLDEN_MR32_GOLDEN +#define RDDQCGOLDEN_LP5_MR33_PATTERN_B RDDQCGOLDEN_MR40_GOLDEN +U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p) +{ + U8 RDDQC_Bit_Ctrl_Lower = 0x55; + U8 RDDQC_Bit_Ctrl_Upper = 0x55; + U8 RDDQC_Pattern_A = 0x5A; + U8 RDDQC_Pattern_B = 0x3C; + +#if FOR_DV_SIMULATION_USED == 1 + cal_sv_rand_args_t *psra = get_psra(); + + if (psra) { + RDDQC_Bit_Ctrl_Lower = psra->low_byte_invert_golden & 0xFF; + RDDQC_Bit_Ctrl_Upper = psra->upper_byte_invert_golden & 0xFF; + RDDQC_Pattern_A = psra->mr_dq_a_golden; + RDDQC_Pattern_B = psra->mr_dq_b_golden; + + /* + * TODO + * + * sv also passes mr20_6 and mr20_7 to sa. + * currently, sa does NOT use these two random arguments. + */ + } +#endif /* FOR_DV_SIMULATION_USED == 1 */ + + // Disable Read DBI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), 0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), 0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK); + +#if RDDQC_PINMUX_WORKAROUND + // Translate pin order by MRR bit sel + RDDQCPinmuxWorkaround(p); +#endif + + // Set golden values into dram MR +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + DramcModeRegWriteByRank(p, p->rank, 31, RDDQC_Bit_Ctrl_Lower); + DramcModeRegWriteByRank(p, p->rank, 32, RDDQC_Bit_Ctrl_Upper); + DramcModeRegWriteByRank(p, p->rank, 33, RDDQC_Pattern_A); + DramcModeRegWriteByRank(p, p->rank, 34, RDDQC_Pattern_B); + } + else +#endif + { + DramcModeRegWriteByRank(p, p->rank, 15, RDDQC_Bit_Ctrl_Lower); + DramcModeRegWriteByRank(p, p->rank, 20, RDDQC_Bit_Ctrl_Upper); + DramcModeRegWriteByRank(p, p->rank, 32, RDDQC_Pattern_A); + DramcModeRegWriteByRank(p, p->rank, 40, RDDQC_Pattern_B); + } + + //Set golden values into RG, watch out the MR_index of RGs are reference LP4 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RDDQCGOLDEN), + P_Fld(RDDQC_Bit_Ctrl_Lower, RDDQCGOLDEN_LP5_MR30_BIT_CTRL_LOWER) | + P_Fld(RDDQC_Bit_Ctrl_Upper, RDDQCGOLDEN_LP5_MR31_BIT_CTRL_UPPER) | + P_Fld(RDDQC_Pattern_A, RDDQCGOLDEN_LP5_MR32_PATTERN_A) | + P_Fld(RDDQC_Pattern_B, RDDQCGOLDEN_LP5_MR33_PATTERN_B)); + + // Open gated clock, by KaiHsin (DCM) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8), + P_Fld(1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8), + P_Fld(1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1)); + +#if (__LP5_COMBO__ == TRUE) + if (is_lp5_family(p)) + { + // Set function mode applied to DQ & DMI +// U8 RDDQC_RDC_DQ_mode = 0; +// U8 RDDQC_RDC_DMI_mode = 0; + +// vSetLP5DramRDDQC_DQandDMI(p, RDDQC_RDC_DQ_mode, RDDQC_RDC_DMI_mode); + +// vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RDDQCGOLDEN1), +// P_Fld(RDDQC_RDC_DQ_mode, RDDQCGOLDEN1_LP5_MR20_7_GOLDEN) | +// P_Fld(RDDQC_RDC_DMI_mode, RDDQCGOLDEN1_LP5_MR20_6_GOLDEN)); + + if (is_heff_mode(p) == FALSE) + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), 1, SHU_COMMON0_LP5WCKON); + + // Enable MR18 "WCK always ON mode" + vSetLP5Dram_WCKON_OnOff(p, ON); + } + + RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_FS); + } +#endif + return 0; +} + +U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p) +{ + // Recover MPC Rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 0, SWCMD_CTRL0_MRSRK); + +#if (__LP5_COMBO__ == TRUE) + if (is_lp5_family(p)) + { + RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_OFF); + + if (is_heff_mode(p) == FALSE) + { + // Disable MR18 "WCK always ON mode" + vSetLP5Dram_WCKON_OnOff(p, OFF); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), 0, SHU_COMMON0_LP5WCKON); + } + } +#endif + return 0; +} + +/* Issue "RD DQ Calibration" + * 1. SWCMD_CTRL1_RDDQC_LP_ENB = 1 to stop RDDQC burst + * 2. RDDQCEN = 1 for RDDQC + * 3. Wait rddqc_response = 1 + * 4. Read compare result + * 5. RDDQCEN = 0 + */ + U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p) +{ + U32 u4Result = 0, u4TmpResult; + DRAM_STATUS_T u4Response = DRAM_FAIL; + + //Issue RD DQ calibration + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1), 1, SWCMD_CTRL1_RDDQC_LP_ENB); + + // Trigger and wait + REG_TRANSFER_T TriggerReg = {DRAMC_REG_SWCMD_EN, SWCMD_EN_RDDQCEN}; + REG_TRANSFER_T RepondsReg = {DRAMC_REG_SPCMDRESP, SPCMDRESP_RDDQC_RESPONSE}; + u4Response = DramcTriggerAndWait(p, TriggerReg, RepondsReg); + + // Read RDDQC compare result + u4TmpResult = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RDQC_CMP)); + u4Result = (0xFFFF) & ((u4TmpResult) | (u4TmpResult >> 16)); // (BL0~7) | (BL8~15) + +#if (FEATURE_RDDQC_K_DMI == TRUE) + // Read DQM compare result + u4TmpResult = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RDQC_DQM_CMP), RDQC_DQM_CMP_RDDQC_DQM_CMP0_ERR); + u4TmpResult |= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RDQC_DQM_CMP), RDQC_DQM_CMP_RDDQC_DQM_CMP1_ERR); + u4Result |= (u4TmpResult << 16); +#endif + + //R_DMRDDQCEN -> 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RDDQCEN); + + return u4Result; +} + +DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, + RX_PATTERN_OPTION_T u1UseTestEngine, + U8 *u1AssignedVref, + u8 isAutoK) +{ + U8 u1BitIdx, u1ByteIdx; + U16 u16DelayStep = 1; + PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM]; + S32 iDQSDlyPerbyte[DQS_NUMBER], iDQMDlyPerbyte[DQS_NUMBER];//, iFinalDQSDly[DQS_NUMBER]; + U8 u1VrefScanEnable = FALSE; + U16 u2FinalVref [DQS_NUMBER]= {0xe, 0xe}; + U16 u2VrefBegin, u2VrefEnd, u2VrefStep; + U8 u1RXEyeScanEnable=0,u1PrintCalibrationProc; + U8 u1CalDQMNum = 0; + +#if ENABLE_EYESCAN_GRAPH + U8 EyeScan_index[DQ_DATA_WIDTH_LP4 + RDDQC_ADD_DMI_NUM] = {0}; + U8 u1pass_in_this_vref_flag[DQ_DATA_WIDTH_LP4 + RDDQC_ADD_DMI_NUM]; +#endif + + U8 backup_rank, rank_i, u1KnownVref[2]={0xff, 0xff}; + + // error handling + if (!p) + { + mcSHOW_ERR_MSG(("context NULL\n")); + return DRAM_FAIL; + } + +#if RDDQC_PINMUX_WORKAROUND + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1)), + (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2)), + (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3)), + (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4)), + }; + + //Back up dramC register + DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); +#endif + + if (u1UseTestEngine == PATTERN_TEST_ENGINE) + u1RXEyeScanEnable = GetEyeScanEnable(p, 1); + +#if (FEATURE_RDDQC_K_DMI == TRUE) + if (u1UseTestEngine == PATTERN_RDDQC) + { + u1CalDQMNum = 2; + iDQMDlyPerbyte[0] = -0xFFFFFF; + iDQMDlyPerbyte[1] = -0xFFFFFF; + } + else +#endif + { + u1CalDQMNum = 0; + iDQMDlyPerbyte[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0); + iDQMDlyPerbyte[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1); + + } + +#if ENABLE_EYESCAN_GRAPH + if (u1UseTestEngine == PATTERN_TEST_ENGINE) + { + for(u1vrefidx=0; u1vrefidx<EYESCAN_RX_VREF_RANGE_END;u1vrefidx++) + { + for (u1BitIdx = 0; u1BitIdx < DQ_DATA_WIDTH_LP4; u1BitIdx++) + { + for(ii=0; ii<EYESCAN_BROKEN_NUM; ii++) + { + gEyeScan_Min[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID; + gEyeScan_Max[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID; + + gEyeScan_ContinueVrefHeight[u1BitIdx] = 0; + gEyeScan_TotalPassCount[u1BitIdx] = 0; + } + } + } + } +#endif + + + //When doing RxWindowPerbitCal, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); + //CKEFixOnOff(p, p->rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + backup_rank = u1GetRank(p); + + //defult set result fail. When window found, update the result as oK + if (u1UseTestEngine == PATTERN_TEST_ENGINE) + { + vSetCalibrationResult(p, DRAM_CALIBRATION_RX_PERBIT, DRAM_FAIL); + + // Something wrong with TA2 pattern -- SI, which causes RX autoK fail. + if (isAutoK == TRUE) + { + DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); + } + else + { +#if ENABLE_K_WITH_WORST_SI_UI_SHIFT + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 +#else + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern, 0, TE_NO_UI_SHIFT); +#endif + } + } + else + { + vSetCalibrationResult(p, DRAM_CALIBRATION_RX_RDDQC, DRAM_FAIL); + DramcRxWinRDDQCInit(p); + } + + // Intialize, diable RX Vref + u2VrefBegin = 0; + u2VrefEnd = 0; + u2VrefStep = 1; + + if ((u1UseTestEngine == PATTERN_TEST_ENGINE)) + { + #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) + if ((p->rank==RANK_0) || (p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) || (u1RXEyeScanEnable==1)) + u1VrefScanEnable =1; + #else + u1VrefScanEnable =0; + #endif + } + + u1PrintCalibrationProc = ((u1VrefScanEnable == 0) || (u1RXEyeScanEnable == 1) || (u1AssignedVref != NULL)); + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) + { + mcSHOW_DBG_MSG(("[FAST_K] Bypass RX Calibration\n")); + } + else +#endif + { +#if VENDER_JV_LOG +#if 0 //BU don't want customer knows our RX's ability + if (u1UseTestEngine == 1) + vPrintCalibrationBasicInfo_ForJV(p); +#endif +#else + vPrintCalibrationBasicInfo(p); +#endif + mcSHOW_DBG_MSG2(("Start DQ dly to find pass range UseTestEngine =%d\n", u1UseTestEngine)); + } + + mcSHOW_DBG_MSG2(("UseTestEngine: %d\n", u1UseTestEngine)); + mcSHOW_DBG_MSG(("RX Vref Scan: %d\n", u1VrefScanEnable)); + + if (u1VrefScanEnable) + { + if ((Get_Vref_Calibration_OnOff(p) == VREF_CALI_OFF) && (u1RXEyeScanEnable == 0)) + { + u2VrefBegin = 0; + u2VrefEnd = 0; + u1KnownVref[0] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][0];// byte 0 + u1KnownVref[1] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][1];// byte 1 + + if (u1UseTestEngine == PATTERN_TEST_ENGINE && ((u1KnownVref[0] == 0) || (u1KnownVref[1] == 0))) + { +// mcSHOW_ERR_MSG(("\nWrong frequency K order= %d\n")); + #if __ETT__ + while (1); + #endif + } + } + else if (u1AssignedVref != NULL) // need to specify RX Vref and don't scan RX Vref. + { + u2VrefBegin = 0; + u2VrefEnd = 0; + u1KnownVref[0] = u1AssignedVref[0]; // byte 0 + u1KnownVref[1] = u1AssignedVref[1]; // byte 1 + } + else + { + #if (SW_CHANGE_FOR_SIMULATION || FOR_DV_SIMULATION_USED) + u2VrefBegin = RX_VREF_RANGE_BEGIN; + #else + if (u1RXEyeScanEnable == 0) + { + if (p->odt_onoff) + { + u2VrefBegin = RX_VREF_RANGE_BEGIN_ODT_ON; + } + else + { + u2VrefBegin = RX_VREF_RANGE_BEGIN_ODT_OFF; + } + u2VrefEnd = RX_VREF_RANGE_END-1; + mcSHOW_DBG_MSG(("\nSet Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd)); + } + else + { + u2VrefBegin = 0;//Lewis@20160817: Enlarge RX Vref range for eye scan + u2VrefEnd = EYESCAN_RX_VREF_RANGE_END-1; + mcSHOW_DBG_MSG(("\nSet Eyescan Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd)); + } + #endif + } + + if (u1RXEyeScanEnable == 0) + { + u2VrefStep = RX_VREF_RANGE_STEP; + } + else + { + u2VrefStep = EYESCAN_GRAPH_RX_VREF_STEP; + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); + } + else // Disable RX Vref + { + u2VrefBegin = 0; + u2VrefEnd = 0; + u2VrefStep = 1; + } + + //if RDDQD, roughly calibration + if (u1UseTestEngine == PATTERN_RDDQC) + u16DelayStep <<= 1; + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) + { + // load RX DQS and DQM delay from eMMC + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + if (u1VrefScanEnable) + { + // load RX Vref from eMMC + #if ( SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL) + u2FinalVref[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbitVref_Save[p->channel][p->rank][u1ByteIdx]; + #endif + } + + iDQSDlyPerbyte[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbit_DQS[p->channel][p->rank][u1ByteIdx]; + iDQMDlyPerbyte[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbit_DQM[p->channel][p->rank][u1ByteIdx]; + } + + // load RX DQ delay from eMMC + for (u1BitIdx = 0; u1BitIdx < 16; u1BitIdx++) + { + FinalWinPerBit[u1BitIdx].best_dqdly = p->pSavetimeData->u1RxWinPerbit_DQ[p->channel][p->rank][u1BitIdx]; + } + + if (u1UseTestEngine == PATTERN_TEST_ENGINE) + vSetCalibrationResult(p, DRAM_CALIBRATION_RX_PERBIT, DRAM_FAST_K); + else + vSetCalibrationResult(p, DRAM_CALIBRATION_RX_RDDQC, DRAM_FAST_K); + } +#endif + + if (u1VrefScanEnable == TRUE) + { + // When only calibrate RX Vref for Rank 0, apply the same value for Rank 1. + for (rank_i = p->rank; rank_i < p->support_rank_num; rank_i++) + { + vSetRank(p, rank_i); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), + P_Fld(u2FinalVref[0], SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | + P_Fld(u2FinalVref[0], SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL), + P_Fld(u2FinalVref[1], SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) | + P_Fld(u2FinalVref[1], SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1)); + + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + mcSHOW_DBG_MSG(("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i)); + mcDUMP_REG_MSG(("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i)); + + gFinalRXVrefDQ[p->channel][rank_i][u1ByteIdx] = (U8) u2FinalVref[u1ByteIdx]; + gFinalRXVrefDQForSpeedUp[p->channel][rank_i][p->odt_onoff][u1ByteIdx] = (U8) u2FinalVref[u1ByteIdx]; + } + } + vSetRank(p, backup_rank); + } + +#if DUMP_TA2_WINDOW_SIZE_RX_TX + //RX + if (u1UseTestEngine == PATTERN_TEST_ENGINE) + { + U32 u4B0Tatal =0; + U32 u4B1Tatal =0; + mcSHOW_DBG_MSG(("RX window per bit CH[%d] Rank[%d] window size\n", p->channel, p->rank)); + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + mcSHOW_DBG_MSG(("DQ[%d] size = %d\n", u1BitIdx, gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx])); + if(u1BitIdx < 8) + { + u4B0Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]; + } + else + { + u4B1Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]; + } + } + mcSHOW_DBG_MSG(("total rx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal)); + } +#endif + + // set dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), + P_Fld((U32)iDQSDlyPerbyte[0], SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), + P_Fld((U32)iDQMDlyPerbyte[0], SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), + P_Fld((U32)iDQSDlyPerbyte[1], SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), + P_Fld((U32)iDQMDlyPerbyte[1], SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1)); + + // set dq delay + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), + P_Fld(((U32)FinalWinPerBit[u1BitIdx].best_dqdly), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | + P_Fld(((U32)FinalWinPerBit[u1BitIdx + 1].best_dqdly), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), + P_Fld((U32)FinalWinPerBit[u1BitIdx + 8].best_dqdly, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | + P_Fld((U32)FinalWinPerBit[u1BitIdx + 9].best_dqdly, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); + + //mcSHOW_DBG_MSG(("u1BitId %d Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2, + // FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly, FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly)); + } + + DramPhyReset(p); + +#if RDDQC_PINMUX_WORKAROUND + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); +#endif + + vSetRank(p, backup_rank); + + vPrintCalibrationBasicInfo(p); + +#ifdef ETT_PRINT_FORMAT + mcSHOW_DBG_MSG(("DQS Delay:\nDQS0 = %d, DQS1 = %d\n" + "DQM Delay:\nDQM0 = %d, DQM1 = %d\n", + iDQSDlyPerbyte[0], iDQSDlyPerbyte[1], + iDQMDlyPerbyte[0], iDQMDlyPerbyte[1])); + mcDUMP_REG_MSG(("DQS Delay:\nDQS0 = %d, DQS1 = %d\n" + "DQM Delay:\nDQM0 = %d, DQM1 = %d\n", + iDQSDlyPerbyte[0], iDQSDlyPerbyte[1], + iDQMDlyPerbyte[0], iDQMDlyPerbyte[1])); +#else + mcSHOW_DBG_MSG(("DQS Delay:\nDQS0 = %2d, DQS1 = %2d\n" + "DQM Delay:\nDQM0 = %2d, DQM1 = %2d\n", + iDQSDlyPerbyte[0], iDQSDlyPerbyte[1], + iDQMDlyPerbyte[0], iDQMDlyPerbyte[1])); + mcDUMP_REG_MSG(("DQS Delay:\nDQS0 = %2d, DQS1 = %2d\n" + "DQM Delay:\nDQM0 = %2d, DQM1 = %2d\n", + iDQSDlyPerbyte[0], iDQSDlyPerbyte[1], + iDQMDlyPerbyte[0], iDQMDlyPerbyte[1])); +#endif + mcSHOW_DBG_MSG(("DQ Delay:\n")); + mcDUMP_REG_MSG(("DQ Delay:\n")); + + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx = u1BitIdx + 4) + { +#ifdef ETT_PRINT_FORMAT + mcSHOW_DBG_MSG(("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly)); + mcDUMP_REG_MSG(("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly)); +#else + mcSHOW_DBG_MSG(("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly)); + mcDUMP_REG_MSG(("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly)); +#endif + } + mcSHOW_DBG_MSG(("\n\n")); + mcSHOW_DBG_MSG3(("[DramcRxWindowPerbitCal] Done\n")); + + #if LP5_DDR4266_RDBI_WORKAROUND + if((is_lp5_family(p)) && (p->frequency >= 2133)) + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), 1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), 1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1); + } + #endif + +return DRAM_OK; + + // Log example ==> Neec to update + /* +------------------------------------------------------ +Start calculate dq time and dqs time / +Find max DQS delay per byte / Adjust DQ delay to align DQS... +------------------------------------------------------ +bit# 0 : dq time=11 dqs time= 8 +bit# 1 : dq time=11 dqs time= 8 +bit# 2 : dq time=11 dqs time= 6 +bit# 3 : dq time=10 dqs time= 8 +bit# 4 : dq time=11 dqs time= 8 +bit# 5 : dq time=10 dqs time= 8 +bit# 6 : dq time=11 dqs time= 8 +bit# 7 : dq time= 9 dqs time= 6 +----seperate line---- +bit# 8 : dq time=12 dqs time= 7 +bit# 9 : dq time=10 dqs time= 8 +bit#10 : dq time=11 dqs time= 8 +bit#11 : dq time=10 dqs time= 8 +bit#12 : dq time=11 dqs time= 8 +bit#13 : dq time=11 dqs time= 8 +bit#14 : dq time=11 dqs time= 8 +bit#15 : dq time=12 dqs time= 8 +----seperate line---- +bit#16 : dq time=11 dqs time= 7 +bit#17 : dq time=10 dqs time= 8 +bit#18 : dq time=11 dqs time= 7 +bit#19 : dq time=11 dqs time= 6 +bit#20 : dq time=10 dqs time= 9 +bit#21 : dq time=11 dqs time=10 +bit#22 : dq time=11 dqs time=10 +bit#23 : dq time= 9 dqs time= 9 +----seperate line---- +bit#24 : dq time=12 dqs time= 6 +bit#25 : dq time=13 dqs time= 6 +bit#26 : dq time=13 dqs time= 7 +bit#27 : dq time=11 dqs time= 7 +bit#28 : dq time=12 dqs time= 8 +bit#29 : dq time=10 dqs time= 8 +bit#30 : dq time=13 dqs time= 7 +bit#31 : dq time=11 dqs time= 8 +----seperate line---- +================================================== + dramc_rxdqs_perbit_swcal_v2 + channel=2(2:cha, 3:chb) apply = 1 +================================================== +DQS Delay : + DQS0 = 0 DQS1 = 0 DQS2 = 0 DQS3 = 0 +DQ Delay : +DQ 0 = 1 DQ 1 = 1 DQ 2 = 2 DQ 3 = 1 +DQ 4 = 1 DQ 5 = 1 DQ 6 = 1 DQ 7 = 1 +DQ 8 = 2 DQ 9 = 1 DQ10 = 1 DQ11 = 1 +DQ12 = 1 DQ13 = 1 DQ14 = 1 DQ15 = 2 +DQ16 = 2 DQ17 = 1 DQ18 = 2 DQ19 = 2 +DQ20 = 0 DQ21 = 0 DQ22 = 0 DQ23 = 0 +DQ24 = 3 DQ25 = 3 DQ26 = 3 DQ27 = 2 +DQ28 = 2 DQ29 = 1 DQ30 = 3 DQ31 = 1 +_______________________________________________________________ + */ +} + +#if SIMULATION_RX_DVS +static U8 DramcRxDVSCal(DRAMC_CTX_T *p, U8 u1byte) +{ + U8 u1rising_lead, u1falling_lead, u1rising_lag, u1falling_lag, u1lead_lag; + + if (u1byte == 0) + { + u1rising_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B0); + u1falling_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B0); + u1rising_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B0); + u1falling_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B0); + } + else //byte1 + { + u1rising_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1); + u1falling_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B1); + u1rising_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1); + u1falling_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B1); + } + + mcSHOW_DBG_MSG2(("Byte%d | LEAD(%d %d) | LAG(%d %d)\n", u1byte, u1rising_lead, u1falling_lead, u1rising_lag, u1falling_lag)); + + u1lead_lag = (u1rising_lead | u1falling_lead | u1rising_lag | u1falling_lag); + + return u1lead_lag; +} + +DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p) +{ + U8 ii, u1ByteIdx; + S16 iDelay = 0, S16DelayBegin = 0; + U16 u16DelayEnd = 0, u16DelayStep = 1; + U32 u4err_value; + + U8 u1lead_lag, u1DVS_first_flag[DQS_NUMBER_LP4]={0}, u1DVS_first_pass[DQS_NUMBER_LP4]={0}, u1DVS_pass_window[DQS_NUMBER_LP4]={0}, u1finish_flag[DQS_NUMBER_LP4]={0}; + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4)), + }; + + // error handling + if (!p) + { + mcSHOW_ERR_MSG(("context NULL\n")); + return DRAM_FAIL; + } + + mcSHOW_DBG_MSG(("\\\RX DVS calibration\\\\n")); + + //When doing RxWindowPerbitCal, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); + //CKEFixOnOff(p, p->rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1); + + //defult set result fail. When window found, update the result as oK +#if ENABLE_K_WITH_WORST_SI_UI_SHIFT + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//PIC Need to check if need to use UI_SHIFT;//UI_SHIFT + LEN1 +#else + DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); +#endif + + +#if (__LP5_COMBO__ == TRUE) + if (is_lp5_family(p)) + { + // 1 step = 1/4 delay cell + // Adjust step = 1/2/4(precision adjustment) by data-rate + if (p->frequency <= GetFreqBySel(p,LP5_DDR3200)) + u16DelayStep = 4; + else if (p->frequency <= GetFreqBySel(p,LP5_DDR4800)) // 3733, 4266, 4800 + u16DelayStep = 2; + else // 5500, 6000, 6400 + u16DelayStep = 1; + } +#endif + else + { + u16DelayStep = 4; + } + // Just for DV SIM test + S16DelayBegin = -80; + u16DelayEnd = 100; + + mcSHOW_DBG_MSG(("\nRX Delay %d -> %d, step: %d\n", S16DelayBegin, u16DelayEnd, u16DelayStep)); + + { + // Adjust DQM output delay to 0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), + P_Fld(0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | + P_Fld(0, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), + P_Fld(0, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | + P_Fld(0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); + + // Adjust DQ output delay to 0 + //every 2bit dq have the same delay register address + for (ii = 0; ii < 4; ii++) + SetRxDqDelay(p, ii, 0); + { + // non-autok flow + for (iDelay = S16DelayBegin; iDelay <= u16DelayEnd; iDelay += u16DelayStep) + { + SetRxDqDqsDelay(p, iDelay); + + u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern); + + mcSHOW_DBG_MSG2(("iDelay= %4d, err_value: 0x%x", iDelay, u4err_value)); + + for(u1ByteIdx=0; u1ByteIdx<(p->data_width/DQS_BIT_NUMBER); u1ByteIdx++) + { + u1lead_lag = DramcRxDVSCal(p, u1ByteIdx); + + if ((u1lead_lag == 0) && (u1DVS_first_flag[u1ByteIdx] == 0) && (((u4err_value >> (u1ByteIdx<<3)) & 0xff) == 0)) + { + u1DVS_first_pass[u1ByteIdx] = iDelay; + u1DVS_first_flag[u1ByteIdx] = 1; + mcSHOW_DBG_MSG(("Byte%d find first pass delay\n")) + } + else if (((u1lead_lag == 1) || (((u4err_value >> (u1ByteIdx<<3)) & 0xff) != 0)) && (u1DVS_first_flag[u1ByteIdx] == 1) && (u1finish_flag[u1ByteIdx] == 0)) + { + u1DVS_pass_window[u1ByteIdx] = iDelay - u1DVS_first_pass[u1ByteIdx] - u16DelayStep; + + if (u1DVS_pass_window[u1ByteIdx] < 7) //if window size bigger than 7, consider as real pass window. + { + u1DVS_pass_window[u1ByteIdx] = 0; + u1DVS_first_flag[u1ByteIdx] = 0; + mcSHOW_DBG_MSG(("Byte%d find fake window\n")) + } + else + { + u1finish_flag[u1ByteIdx] = 1; + mcSHOW_DBG_MSG(("Byte%d find pass window\n")) + } + } + } + + if ((u1finish_flag[0]==1) && (u1finish_flag[1]==1)) + { + mcSHOW_DBG_MSG(("Two byte DVS window find, early break!\n")); + break; + } + } + } + } + + DramcEngine2End(p); + + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + u1DVS_increase[p->rank][u1ByteIdx] = (u1DVS_pass_window[u1ByteIdx] > 8)? ((u1DVS_pass_window[u1ByteIdx] - 8) >> 3): 0; + mcSHOW_DBG_MSG(("\nByte %d final DVS window size(M) %d, DVS increase %d\n", u1ByteIdx, u1DVS_pass_window[u1ByteIdx], u1DVS_increase[p->rank][u1ByteIdx])); + } + + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + vAutoRefreshSwitch(p, ENABLE); + + DramPhyReset(p); + + vPrintCalibrationBasicInfo(p); + + mcSHOW_DBG_MSG(("\n\n")); + mcSHOW_DBG_MSG3(("[DramcRxDVSWindowCal] Done\n")); + +return DRAM_OK; +} + +void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p) +{ + U8 rank_i, u1ByteIdx, u1DVS_increase_final, u1DVS_dly_final[DQS_NUMBER_LP4]={0}; + U8 backup_rank = p->rank; + + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + if (p->support_rank_num == RANK_DUAL) + u1DVS_increase_final = (u1DVS_increase[RANK_0][u1ByteIdx] < u1DVS_increase[RANK_1][u1ByteIdx])? u1DVS_increase[RANK_0][u1ByteIdx] : u1DVS_increase[RANK_1][u1ByteIdx]; + else + u1DVS_increase_final = u1DVS_increase[p->rank][u1ByteIdx]; + + if (u1ByteIdx == 0) + { + u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0); + } + else //byte1 + { + u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1); + } + mcSHOW_DBG_MSG(("Byte%d final DVS delay: %d\n", u1ByteIdx, u1DVS_dly_final[u1ByteIdx])); + } + + for(rank_i=RANK_0; rank_i< p->support_rank_num; rank_i++) + { + vSetRank(p, rank_i); + DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, DVS_CAL_KEEP_VREF, AUTOK_OFF); + } + + if ((DramcRxDVSCal(p, 0) == 1) || (DramcRxDVSCal(p, 1) == 1)) //Prevent set wrong DV dly + { + mcSHOW_ERR_MSG(("Final DVS delay is out of RX window\n")); + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + if (u1DVS_dly_final[u1ByteIdx] > 0) + { + u1DVS_dly_final[u1ByteIdx] -= 1; + if (u1ByteIdx == 0) + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0); + } + else //byte1 + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1); + } + } + for(rank_i=RANK_0; rank_i< p->support_rank_num; rank_i++) + { + vSetRank(p, rank_i); + DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, DVS_CAL_KEEP_VREF, AUTOK_OFF); + } + } + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1); + + vSetRank(p, backup_rank); +} +#endif + +#if SIMULATION_DATLAT +static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val) +{ + U8 u1DATLAT_DSEL = 0; + U8 u1DLECG_OptionEXT1 = 0; + U8 u1DLECG_OptionEXT2 = 0; + U8 u1DLECG_OptionEXT3 = 0; + + // If (RX_PIPE_BYPASS_ENABLE == 1) bypass RX PIPE, so RG_DATLAT_DSEL = RG_DATLAT + // else RG_DATLAT_DSEL = RG_DATLAT - 1 + if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + { + u1DATLAT_DSEL = curr_val; + } + else + { + if (curr_val < 1) + u1DATLAT_DSEL = curr_val; + else + u1DATLAT_DSEL = curr_val - 1; + } + +// mcSHOW_DBG_MSG(("DATLAT: %d, u1DATLAT_DSEL: %d\n", curr_val, u1DATLAT_DSEL)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT), + P_Fld(curr_val, MISC_SHU_RDAT_DATLAT) | + P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL) | + P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); + + // Had been adjusted for 868 already. + //(>=8 & <14) set EXT1 =1, EXT2=0, EXT3=0 + //(>= 14 & <19) set EXT1=1, EXT2=1, EXT3=0 + //(>=19) set EXT1=1, EXT2=1, EXT3=1 + u1DLECG_OptionEXT1 = (curr_val >= 8)? (1): (0); + u1DLECG_OptionEXT2 = (curr_val >= 14)? (1): (0); + u1DLECG_OptionEXT3 = (curr_val >= 19)? (1): (0); +// mcSHOW_DBG_MSG(("u1DLECG_OptionEXT1: %d, 2 for %d, 3 for %d\n", u1DLECG_OptionEXT1, u1DLECG_OptionEXT2, u1DLECG_OptionEXT3)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RX_CG_SET0), + P_Fld(u1DLECG_OptionEXT1, SHU_RX_CG_SET0_READ_START_EXTEND1) | + P_Fld(u1DLECG_OptionEXT1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | + P_Fld((u1DLECG_OptionEXT2), SHU_RX_CG_SET0_READ_START_EXTEND2) | + P_Fld((u1DLECG_OptionEXT2), SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | + P_Fld((u1DLECG_OptionEXT3), SHU_RX_CG_SET0_READ_START_EXTEND3) | + P_Fld((u1DLECG_OptionEXT3), SHU_RX_CG_SET0_DLE_LAST_EXTEND3)); + + DramPhyReset(p); + +} + +static U8 aru1RxDatlatResult[RANK_MAX]; +DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) +{ + U32 u4prv_register_080; + U8 ucfirst, ucbegin, ucsum, ucbest_step; + U16 u2DatlatBegin; + + // error handling + if (!p) + { + mcSHOW_ERR_MSG(("context NULL\n")); + return DRAM_FAIL; + } + + mcSHOW_DBG_MSG(("\n[DATLAT]\n" + "Freq=%d, CH%d RK%d\n\n", p->frequency, p->channel, p->rank)); + + // pre-save + // 0x07c[6:4] DATLAT bit2-bit0 + u4prv_register_080 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT)); + + //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL); + + // init best_step to default + ucbest_step = (U8) u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT), MISC_SHU_RDAT_DATLAT); + mcSHOW_DBG_MSG(("DATLAT Default: 0x%x\n", ucbest_step)); + mcDUMP_REG_MSG(("DATLAT Default: 0x%x\n", ucbest_step)); + + // 1.set DATLAT 0-15 (0-21 for MT6595) + // 2.enable engine1 or engine2 + // 3.check result ,3~4 taps pass + // 4.set DATLAT 2nd value for optimal + + // Initialize + ucfirst = 0xff; + ucbegin = 0; + ucsum = 0; + + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 + u2DatlatBegin = 0; + +#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT) + if (p->femmc_Ready == 1) + { + ucbest_step = p->pSavetimeData->u1RxDatlat_Save[p->channel][p->rank]; + } +#endif + + aru1RxDatlatResult[p->rank] = ucbest_step; + + mcSHOW_DBG_MSG(("best_step = %d\n\n", ucbest_step)); + mcDUMP_REG_MSG(("best_step=%d\n\n", ucbest_step)); + +#if __A60868_TO_BE_PORTING__ +#if __ETT__ + U8 _init_Datlat_value = vDramcACTimingGetDatLat(p); + if ((_init_Datlat_value > (ucbest_step + 1)) || (_init_Datlat_value < (ucbest_step - 1))) + { + mcSHOW_DBG_MSG(("[WARNING!!] Datlat initial value(%d) = best_step(%d) %c %d, out of range!\n\n", + _init_Datlat_value, + ucbest_step, + (ucbest_step > _init_Datlat_value)? '-': '+', + abs(ucbest_step - _init_Datlat_value))); + while (1); + } +#endif +#endif + +#if defined(FOR_HQA_TEST_USED) && defined(FOR_HQA_REPORT_USED) + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, "DATLAT", "", 0, ucbest_step, NULL); +#endif + +#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT) + if (p->femmc_Ready == 1) + { + dle_factor_handler(p, ucbest_step); + vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAST_K); + } +#endif + + mcSHOW_DBG_MSG3(("[DramcRxdatlatCal] Done\n")); + return DRAM_OK; +} + +DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p) +{ + U8 u1FinalDatlat, u1Datlat0, u1Datlat1; + + u1Datlat0 = aru1RxDatlatResult[0]; + u1Datlat1 = aru1RxDatlatResult[1]; + + if (p->support_rank_num == RANK_DUAL) + { + if (u1Datlat0 > u1Datlat1) + { + u1FinalDatlat = u1Datlat0; + } + else + { + u1FinalDatlat = u1Datlat1; + } + } + else + { + u1FinalDatlat = u1Datlat0; + } + +#if ENABLE_READ_DBI + if (p->DBI_R_onoff[p->dram_fsp]) + { + u1FinalDatlat++; + } +#endif + + dle_factor_handler(p, u1FinalDatlat); + +#if RDSEL_TRACKING_EN + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RDSEL_TRACK), u1FinalDatlat, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); +#endif + + mcSHOW_DBG_MSG(("[DualRankRxdatlatCal] RK0: %d, RK1: %d, Final_Datlat %d\n", u1Datlat0, u1Datlat1, u1FinalDatlat)); + + return DRAM_OK; + +} +#endif // SIMULATION_DATLAT + +#if SIMULATION_TX_PERBIT + +//============================================================= +///// DramC TX perbi calibration ----------Begin-------------- +//============================================================= +//------------------------------------------------------------------------- +/** DramcTxWindowPerbitCal (v2) + * TX DQS per bit SW calibration. + * @param p Pointer of context created by DramcCtxCreate. + * @param apply (U8): 0 don't apply the register we set 1 apply the register we set ,default don't apply. + * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL + */ +//------------------------------------------------------------------------- +#if (SW_CHANGE_FOR_SIMULATION || FOR_DV_SIMULATION_USED) +#define TX_VREF_RANGE_BEGIN 0 +#define TX_VREF_RANGE_END 2 // binary 110010 +#define TX_VREF_RANGE_STEP 2 +#else +#define TX_VREF_RANGE_BEGIN 16 +#define TX_VREF_RANGE_END 50 // binary 110010 +#define TX_VREF_RANGE_STEP 2 +#endif + +#define TX_DQ_UI_TO_PI_TAP 64 // 1 PI = tCK/64, total 128 PI, 1UI = 32 PI +#define TX_PHASE_DQ_UI_TO_PI_TAP 32 // 1 PI = tCK/64, total 128 PI, 1UI = 32 PI for DDR800 semi open loop mode +#define LP4_TX_VREF_DATA_NUM 50 +#define LP4_TX_VREF_PASS_CONDITION 0 +#define TX_PASS_WIN_CRITERIA 7 +#define LP4_TX_VREF_BOUNDARY_NOT_READY 0xff + +typedef struct _PASS_WIN_DATA_BY_VREF_T +{ + U16 u2VrefUsed; + U16 u2WinSum_byVref; + U8 u1WorseBitWinSize_byVref; + U8 u1WorseBitIdx_byVref; +} PASS_WIN_DATA_BY_VREF_T; + +static void TxWinTransferDelayToUIPI(DRAMC_CTX_T *p, U16 uiDelay, U8 u1AdjustPIToCenter, U8* pu1UILarge_DQ, U8* pu1UISmall_DQ, U8* pu1PI, U8* pu1UILarge_DQOE, U8* pu1UISmall_DQOE) +{ + U8 u1Small_ui_to_large, u1PI = 0, u164PIto1UI, u1TxDQOEShift = 0; + U16 u2TmpValue, u2DQOE_shift; + DDR800_MODE_T eDdr800Mode = vGet_DDR_Loop_Mode(p); + U8 u1PiTap = (u1IsPhaseMode(p) == TRUE) ? TX_PHASE_DQ_UI_TO_PI_TAP : TX_DQ_UI_TO_PI_TAP; + + u1Small_ui_to_large = u1MCK2UI_DivShift(p); + + #if ENABLE_WDQS_MODE_2 + u1TxDQOEShift = WDQSMode2AcTxOEShift(p); + #else + u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4; + #endif + + if(pu1PI != NULL) + { + u1PI = uiDelay & (u1PiTap-1); + *pu1PI =u1PI; + } + + if (u1IsLP4Div4DDR800(p) /*DDR800 close loop mode*/ || u1IsPhaseMode(p)) + u164PIto1UI = 0; + else + u164PIto1UI = 1; + + u2TmpValue = (uiDelay /u1PiTap)<<u164PIto1UI; // 1:8 mode for 2UI carry, DDR800 1:4 mode for 1UI carry + + if (u1AdjustPIToCenter && (pu1PI != NULL) && (eDdr800Mode == CLOSE_LOOP_MODE)) + { + if (u1PI < 10) + { + u1PI += (u1PiTap) >> 1; + u2TmpValue --; + } + else if (u1PI > u1PiTap - 10) + { + u1PI -= (u1PiTap) >> 1; + u2TmpValue ++; + } + + *pu1PI = u1PI; + } + + #if 0 + *pu1UISmall_DQ = u2TmpValue % u1Small_ui_to_large; + *pu1UILarge_DQ = u2TmpValue / u1Small_ui_to_large; + #else + *pu1UISmall_DQ = u2TmpValue - ((u2TmpValue >> u1Small_ui_to_large) << u1Small_ui_to_large); + *pu1UILarge_DQ = (u2TmpValue >> u1Small_ui_to_large); + #endif + // calculate DQ OE according to DQ UI + #if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + u2TmpValue -= TX_DQ_OE_SHIFT_LP5; + } + else + #endif + { + u2TmpValue -= u1TxDQOEShift; + } + + if(((u1MR03Value[p->dram_fsp]&0x80)>>7)==1) //if WDBI is on, OE_DLY don't need to shift 1 MCK with DLY + { + if (vGet_Div_Mode(p) == DIV4_MODE) + u2DQOE_shift = 4; //OE_shift = OE_shift - 3(original OE position) + 4 (MCK) + else + u2DQOE_shift = 8; //OE_shift = OE_shift - 3(original OE position) + 8 (MCK) + + u2TmpValue += u2DQOE_shift; + } + + *pu1UISmall_DQOE = u2TmpValue - ((u2TmpValue >> u1Small_ui_to_large) << u1Small_ui_to_large); + *pu1UILarge_DQOE = (u2TmpValue >> u1Small_ui_to_large); +} + +static void TXPerbitCalibrationInit(DRAMC_CTX_T *p, U8 calType) +{ + //Set TX delay chain to 0 + if (calType != TX_DQ_DQS_MOVE_DQM_ONLY) + { + #if 1 + #if PINMUX_AUTO_TEST_PER_BIT_TX + if(gTX_check_per_bit_flag == 1) + { + //not reset delay cell + } + else + #endif + { + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0); + } + #else + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_R0_B0_DQ0), P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0) + | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0) + | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0) + | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0) + | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0) + | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0) + | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0) + | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_R0_B1_DQ0), P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1) + | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1) + | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1) + | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1) + | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1) + | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1) + | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1) + | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1)); + #endif + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1); + } + + + //Use HW TX tracking value + //R_DMARPIDQ_SW :drphy_conf (0x170[7])(default set 1) + // 0: DQS2DQ PI setting controlled by HW + //R_DMARUIDQ_SW : Dramc_conf(0x156[15])(default set 1) + // 0: DQS2DQ UI setting controlled by HW + ///TODO: need backup original setting? + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW); + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW); + +} + +#define TX_TDQS2DQ_PRE_CAL 0 +#if TX_TDQS2DQ_PRE_CAL +// (1) DDR800 1:4 mode +// (2) DDR1200/1600 1:4 mode +// (3) 1:8 mode +// The 3 condition have different MCK2UI/UI2PI. Therefore, TX DQS2DQ should be record separately. +// Here, we record (2) and (3). DDR800 1:4 skip recording DQS2DQ. +U16 u2DQS2DQ_Pre_Cal[CHANNEL_NUM][RANK_MAX][2/*DIV_Mode*/] = {0}; +#endif + +static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U16 *pu2Begin, U16 *pu2End) +{ + U8 u1MCK2UI, u1UI2PI, u1ByteIdx; + U32 u4RegValue_TXDLY, u4RegValue_dly; + U8 ucdq_ui_large_bak[DQS_NUMBER], ucdq_ui_small_bak[DQS_NUMBER]; + U16 u2TempVirtualDelay, u2SmallestVirtualDelay = 0xffff; + U16 u2DQDelayBegin = 0, u2DQDelayEnd = 0; + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + u4RegValue_TXDLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_MCK)); + u4RegValue_dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_UI)); + } + else +#endif + { + u4RegValue_TXDLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0)); + u4RegValue_dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1)); + } + + u1MCK2UI = u1MCK2UI_DivShift(p); + + if (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP) + u1UI2PI = 6; + else + u1UI2PI = 5; + + + // find smallest DQS delay + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + ucdq_ui_large_bak[u1ByteIdx] = (u4RegValue_TXDLY >> (u1ByteIdx << 2)) & 0x7;// MCK + ucdq_ui_small_bak[u1ByteIdx] = (u4RegValue_dly >> (u1ByteIdx << 2)) & 0x7;// UI + //wrlevel_dqs_final_delay[p->rank][u1ByteIdx] ==> PI + + //LP4 : Virtual Delay = 256 * MCK + 32*UI + PI; + //LP3 : Virtual Delay = 128 * MCK + 32*UI + PI; + u2TempVirtualDelay = (((ucdq_ui_large_bak[u1ByteIdx] << u1MCK2UI) + ucdq_ui_small_bak[u1ByteIdx]) << u1UI2PI) + wrlevel_dqs_final_delay[p->rank][u1ByteIdx]; + + if (u2TempVirtualDelay < u2SmallestVirtualDelay) + { + u2SmallestVirtualDelay = u2TempVirtualDelay; + } + } + + u2DQDelayBegin = u2SmallestVirtualDelay; + + #if TX_TDQS2DQ_PRE_CAL + if (u1IsLP4Div4DDR800(p) == FALSE) + { + if (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] > 0) + { + U16 u2TmpShift; + mcSHOW_DBG_MSG(("TX_TDQS2DQ_PRE_CAL : change DQ begin %d -->", u2DQDelayBegin)); + + u2TmpShift = (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)]* p->frequency) / 1000; + if (u2TmpShift >= 15) + u2TmpShift -= 15; + else + u2TmpShift = 0; + + u2DQDelayBegin += u2TmpShift; + mcSHOW_DBG_MSG(("%d (+%d)\n", u2DQDelayBegin, u2TmpShift)); + } + } + #endif + + #if (__LP5_COMBO__) + if (is_lp5_family(p)) { + /* For DDR3200, +1.5 MCK */ + if (p->frequency == 1600) + u2DQDelayBegin += (((1 << u1MCK2UI) + ((1 << u1MCK2UI) >> 1)) << u1UI2PI); + else if (p->frequency == 2133) + u2DQDelayBegin += ((1 << u1MCK2UI) << u1UI2PI); + else if (p->frequency == 2750) + u2DQDelayBegin += (9 << u1UI2PI); + } + #endif + + #if TX_K_DQM_WITH_WDBI + if (calType == TX_DQ_DQS_MOVE_DQM_ONLY) + { + // DBI on, calibration range -1MCK + u2DQDelayBegin -= (1 << (u1MCK2UI + 5)); + } + #endif + /* Scan range: 1MCK */ + u2DQDelayEnd = u2DQDelayBegin + ((1 << u1MCK2UI) << u1UI2PI); + + *pu2Begin = u2DQDelayBegin; + *pu2End = u2DQDelayEnd; + + #if 0//TX_TDQS2DQ_PRE_CAL + mcSHOW_DBG_MSG(("TXScanRange_PI %d~%d\n", u2DQDelayBegin, u2DQDelayEnd)); + #endif +} + + +static void TXScanRange_Vref(DRAMC_CTX_T *p, U8 u1VrefScanEnable, U16* pu2Range, U16 *pu2Begin, U16 *pu2End, U16 *pu2Setp) +{ + U16 u2VrefBegin = 0, u2VrefEnd = 0; + + if (u1VrefScanEnable) + { + #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL) + if (p->femmc_Ready == 1) + { + // if fast K, use TX Vref that saved. + u2VrefBegin = p->pSavetimeData->u1TxWindowPerbitVref_Save[p->channel][p->rank]; + u2VrefEnd = u2VrefBegin + 1; + } + #endif + } + else //LPDDR3, the for loop will only excute u2VrefLevel=TX_VREF_RANGE_END/2. + { + u2VrefBegin = 0; + u2VrefEnd = 0; + } + + *pu2Range = (!p->odt_onoff); + *pu2Begin = u2VrefBegin; + *pu2End = u2VrefEnd; + *pu2Setp = TX_VREF_RANGE_STEP; + +} + +static U16 TxChooseVref(DRAMC_CTX_T *p, PASS_WIN_DATA_BY_VREF_T pVrefInfo[], U8 u1VrefNum) +{ + U8 u1VrefIdx, u1WorseBitIdx = 0, u1WinSizeOfWorseBit = 0; + U16 u2MaxWinSum = 0; + U16 u2FinalVref = 0; + + for (u1VrefIdx = 0; u1VrefIdx < u1VrefNum; u1VrefIdx++) + { + mcSHOW_DBG_MSG(("TX Vref=%d, minBit %d, minWin=%d, winSum=%d\n", + pVrefInfo[u1VrefIdx].u2VrefUsed, + pVrefInfo[u1VrefIdx].u1WorseBitIdx_byVref, + pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref, + pVrefInfo[u1VrefIdx].u2WinSum_byVref)); + + #if LP4_TX_VREF_PASS_CONDITION + if ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref > LP4_TX_VREF_PASS_CONDITION)) + { + if (u1VrefPassBegin == LP4_TX_VREF_BOUNDARY_NOT_READY) + { + u1VrefPassBegin = pVrefInfo[u1VrefIdx].u2VrefUsed; + u1TempPassNum = 1; + } + else + u1TempPassNum ++; + + if (u1VrefIdx == u1VrefNum - 1) + { + u1VrefPassEnd = pVrefInfo[u1VrefIdx].u2VrefUsed; + if (u1TempPassNum > u1MaxVerfPassNum) + { + u1VrefPassBegin_Final = u1VrefPassBegin; + u1VrefPassEnd_Final = u1VrefPassEnd; + u1MaxVerfPassNum = u1TempPassNum; + } + } + } + else + { + if ((u1VrefPassBegin != LP4_TX_VREF_BOUNDARY_NOT_READY) && (u1VrefPassEnd == LP4_TX_VREF_BOUNDARY_NOT_READY)) + { + u1VrefPassEnd = pVrefInfo[u1VrefIdx].u2VrefUsed - TX_VREF_RANGE_STEP; + if (u1TempPassNum > u1MaxVerfPassNum) + { + u1VrefPassBegin_Final = u1VrefPassBegin; + u1VrefPassEnd_Final = u1VrefPassEnd; + u1MaxVerfPassNum = u1TempPassNum; + } + u1VrefPassBegin = 0xff; + u1VrefPassEnd = 0xff; + u1TempPassNum = 0; + } + } + #endif + } + + #if LP4_TX_VREF_PASS_CONDITION + //if((u1VrefPassBegin_Final !=LP4_TX_VREF_BOUNDARY_NOT_READY) && (u1VrefPassEnd_Final!=LP4_TX_VREF_BOUNDARY_NOT_READY)) + if (u1MaxVerfPassNum > 0) + { + // vref pass window found + u2FinalVref = (u1VrefPassBegin_Final + u1VrefPassEnd_Final) >> 1; + mcSHOW_DBG_MSG(("[TxChooseVref] Window > %d, Vref (%d~%d), Final Vref %d\n", LP4_TX_VREF_PASS_CONDITION, u1VrefPassBegin_Final, u1VrefPassEnd_Final, u2FinalVref)); + } + else + #endif + { + // not vref found + for (u1VrefIdx = 0; u1VrefIdx < u1VrefNum; u1VrefIdx++) + { + if ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref > u1WinSizeOfWorseBit) || + ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref == u1WinSizeOfWorseBit) && (pVrefInfo[u1VrefIdx].u2WinSum_byVref > u2MaxWinSum))) + { + u1WinSizeOfWorseBit = pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref; + u1WorseBitIdx = pVrefInfo[u1VrefIdx].u1WorseBitIdx_byVref; + u2MaxWinSum = pVrefInfo[u1VrefIdx].u2WinSum_byVref; + u2FinalVref = pVrefInfo[u1VrefIdx].u2VrefUsed; + } + } + + mcSHOW_DBG_MSG(("[TxChooseVref] Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", u1WorseBitIdx, u1WinSizeOfWorseBit, u2MaxWinSum, u2FinalVref)); + } + + return u2FinalVref; +} + + +static void DramcTXSetVref(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefValue) +{ + U8 u1TempOPValue; + +#ifdef __LP5_COMBO__ + if (is_lp5_family(p)) + u1TempOPValue = ((u1VrefValue & 0x7f)); + else +#endif + u1TempOPValue = ((u1VrefValue & 0x3f) | (u1VrefRange << 6)); + + u1MR14Value[p->channel][p->rank][p->dram_fsp] = u1TempOPValue; + //For TX VREF of different byte + + DramcModeRegWriteByRank(p, p->rank, 14, u1TempOPValue); +#ifdef __LP5_COMBO__ + if (is_lp5_family(p)) + DramcModeRegWriteByRank(p, p->rank, 15, u1TempOPValue); +#endif + + #if CALIBRATION_SPEED_UP_DEBUG + mcSHOW_DBG_MSG(("Yulia TX Vref : CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u1VrefRange, (u1VrefValue & 0x3f))); + #endif +} + + +static void TXSetFinalVref(DRAMC_CTX_T *p, U16 u2FinalRange, U16 u2FinalVref) +{ + DramcTXSetVref(p, u2FinalRange, u2FinalVref); + +#ifdef FOR_HQA_TEST_USED + gFinalTXVrefDQ[p->channel][p->rank] = (U8) u2FinalVref; +#endif + +#if VENDER_JV_LOG + mcSHOW_DBG_MSG5(("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref)); +#else + mcSHOW_DBG_MSG(("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref)); +#endif + + #if CALIBRATION_SPEED_UP_DEBUG + mcSHOW_DBG_MSG(("Yulia TX Vref Final: CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u2FinalRange, u2FinalVref)); + #endif +} + + +#if ENABLE_TX_TRACKING +#if !BYPASS_CALIBRATION +static +#endif +void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[]) +{ + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQM_ONLY) + { + //make a copy to dramc reg for TX DQ tracking used + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), + P_Fld(ucdq_pi[0], SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_pi[1], SHURK_PI_RK0_ARPI_DQ_B1)); + + // Source DQ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1), + P_Fld(ucdq_pi[1], SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1) | + P_Fld(ucdq_pi[0], SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0)); + // Target DQ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2), + P_Fld(ucdq_pi[1], SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1) | + P_Fld(ucdq_pi[0], SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0)); + } + + //if(calType ==TX_DQ_DQS_MOVE_DQM_ONLY || (calType ==TX_DQ_DQS_MOVE_DQ_ONLY)) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), + P_Fld(ucdqm_pi[0], SHURK_PI_RK0_ARPI_DQM_B0) | P_Fld(ucdqm_pi[1], SHURK_PI_RK0_ARPI_DQM_B1)); + + // Target DQM + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5), + P_Fld(ucdqm_pi[1], SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1) | + P_Fld(ucdqm_pi[0], SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0)); + } + } + + +#if 0// for LP3 , TX tracking will be disable, don't need to set DQ delay in DramC. + ///TODO: check LP3 byte mapping of dramC + vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI + (CHANNEL_A << POS_BANK_NUM), \ + P_Fld(ucdq_final_pi[0], SHURK0_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_final_pi[1], SHURK0_PI_RK0_ARPI_DQ_B1)); + + vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI + SHIFT_TO_CHB_ADDR, \ + P_Fld(ucdq_final_pi[2], SHURK0_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_final_pi[3], SHURK0_PI_RK0_ARPI_DQ_B1)); +#endif + +} +#endif //End ENABLE_TX_TRACKING + +#if !BYPASS_CALIBRATION +static +#endif +void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdq_ui_large[], U8 ucdq_oen_ui_large[], U8 ucdq_ui_small[], U8 ucdq_oen_ui_small[], U8 ucdql_pi[]) +{ + if (u1UpdateRegUI) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ + P_Fld(ucdq_ui_large[0], SHURK_SELPH_DQ0_TXDLY_DQ0) | + P_Fld(ucdq_ui_large[1], SHURK_SELPH_DQ0_TXDLY_DQ1) | + P_Fld(ucdq_ui_large[2], SHURK_SELPH_DQ0_TXDLY_DQ2) | + P_Fld(ucdq_ui_large[3], SHURK_SELPH_DQ0_TXDLY_DQ3) | + P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | + P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | + P_Fld(ucdq_oen_ui_large[2], SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | + P_Fld(ucdq_oen_ui_large[3], SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); + + // DLY_DQ[2:0] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ + P_Fld(ucdq_ui_small[0], SHURK_SELPH_DQ2_DLY_DQ0) | + P_Fld(ucdq_ui_small[1], SHURK_SELPH_DQ2_DLY_DQ1) | + P_Fld(ucdq_ui_small[2], SHURK_SELPH_DQ2_DLY_DQ2) | + P_Fld(ucdq_ui_small[3], SHURK_SELPH_DQ2_DLY_DQ3) | + P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ2_DLY_OEN_DQ0) | + P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ2_DLY_OEN_DQ1) | + P_Fld(ucdq_oen_ui_small[2], SHURK_SELPH_DQ2_DLY_OEN_DQ2) | + P_Fld(ucdq_oen_ui_small[3], SHURK_SELPH_DQ2_DLY_OEN_DQ3)); + } + + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdql_pi[0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdql_pi[1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1); +} + +#if !BYPASS_CALIBRATION +static +#endif +void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]) +{ + if (u1UpdateRegUI) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), + P_Fld(ucdqm_ui_large[0], SHURK_SELPH_DQ1_TXDLY_DQM0) | + P_Fld(ucdqm_ui_large[1], SHURK_SELPH_DQ1_TXDLY_DQM1) | + P_Fld(ucdqm_ui_large[2], SHURK_SELPH_DQ1_TXDLY_DQM2) | + P_Fld(ucdqm_ui_large[3], SHURK_SELPH_DQ1_TXDLY_DQM3) | + P_Fld(ucdqm_oen_ui_large[0], SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | + P_Fld(ucdqm_oen_ui_large[1], SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | + P_Fld(ucdqm_oen_ui_large[2], SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | + P_Fld(ucdqm_oen_ui_large[3], SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); + + // DLY_DQM[2:0] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), + P_Fld(ucdqm_ui_small[0], SHURK_SELPH_DQ3_DLY_DQM0) | + P_Fld(ucdqm_ui_small[1], SHURK_SELPH_DQ3_DLY_DQM1) | + P_Fld(ucdqm_ui_small[2], SHURK_SELPH_DQ3_DLY_DQM2) | + P_Fld(ucdqm_ui_small[3], SHURK_SELPH_DQ3_DLY_DQM3) | + P_Fld(ucdqm_oen_ui_small[0], SHURK_SELPH_DQ3_DLY_OEN_DQM0) | + P_Fld(ucdqm_oen_ui_small[1], SHURK_SELPH_DQ3_DLY_OEN_DQM1) | + P_Fld(ucdqm_oen_ui_small[2], SHURK_SELPH_DQ3_DLY_OEN_DQM2) | + P_Fld(ucdqm_oen_ui_small[3], SHURK_SELPH_DQ3_DLY_OEN_DQM3)); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdqm_pi[0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdqm_pi[1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1); +} + +#if TX_AUTO_K_ENABLE +static void Tx_Auto_K_Init(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi, U8 u1PI_Len) +{ + u8 pi_thrd = 0xa; + +#if FOR_DV_SIMULATION_USED == 1 + cal_sv_rand_args_t *psra = get_psra(); + + if (psra) { + pi_thrd = psra->tx_atk_pass_pi_thrd & 0xFF; + early_break = psra->tx_atk_early_break & 0xFF; + } +#endif + +#if ENABLE_PA_IMPRO_FOR_TX_AUTOK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 0x1, DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0), 0x1, TX_CG_SET0_TX_ATK_CLKRUN); +#endif + + if (calType == TX_DQ_DQS_MOVE_DQ_DQM) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), + P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQ_PI_EN) | //enable TX DQ auto K + P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQM_PI_EN)); //enable TX DQM auto K + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | //Set begin position of DQ B0 + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) | //Set begin position of DQ B1 + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | //Set begin position of DQM B0 + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); //Set begin position of DQM B1 + } + else if (calType == TX_DQ_DQS_MOVE_DQM_ONLY) + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DQM_PI_EN); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); + } + else + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DQ_PI_EN); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT)); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW); //Switch PI SW mode to HW mode (control by DRAMC not APHY) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), + P_Fld(u1PI_Len, TX_ATK_SET1_TX_ATK_PI_LEN) | //enable TX auto k len + P_Fld(pi_thrd, TX_ATK_SET1_TX_ATK_PASS_PI_THRD)); //Set threshold of PI pass window +#if (fcFOR_CHIP_ID == fcIPM) //Fix at Mar_gaux + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), early_break, TX_ATK_SET1_TX_ATK_EARLY_BREAK); //Enable early break +#endif + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), + P_Fld(0x5, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | + P_Fld(0x1, SHU_TX_SET0_TXOEN_AUTOSET_EN)); //Enable OE auto adjust + } + else +#endif + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), + P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | + P_Fld(0x1, SHU_TX_SET0_TXOEN_AUTOSET_EN)); //Enable OE auto adjust + } + +#if TX_AUTO_K_DEBUG_ENABLE + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DBG_EN); +#endif +} + +static void Tx_Auto_K_complete_check(DRAMC_CTX_T *p) +{ + U32 u4loop_count = 0; + + while ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_RESULT8), TX_ATK_RESULT8_TX_ATK_DONE) != 0x1)) + { + mcDELAY_US(1); + u4loop_count++; + //mcSHOW_DBG_MSG(("Wait! TX auto K is not done!\n")); + if (u4loop_count > 100000) + { + mcSHOW_ERR_MSG(("Error! TX auto K is not done!\n")); + break; + } + } + + if ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_RESULT8), TX_ATK_RESULT8_TX_ATK_FIND_PW) == 0x1)) + { + vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK); + mcSHOW_DBG_MSG(("Tx auto K, all bit find passs window\n")); + } + else + { + mcSHOW_ERR_MSG(("Error! TX auto K is fail!\n")); + } +} + +static void Tx_Auto_K_Clear(DRAMC_CTX_T *p) +{ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_TRIG); //Disable Tx auto K + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), 0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x1, MISC_CTRL1_R_DMARPIDQ_SW); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_DBG_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_CLR); //Clear state machine + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_CLR); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), + P_Fld(0x0, TX_ATK_SET1_TX_ATK_PI_LEN) | + P_Fld(0x0, TX_ATK_SET1_TX_ATK_DQ_PI_EN) | + P_Fld(0x0, TX_ATK_SET1_TX_ATK_DQM_PI_EN)); +#if ENABLE_PA_IMPRO_FOR_TX_AUTOK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0), 0x0, TX_CG_SET0_TX_ATK_CLKRUN); +#endif +} + +#if TX_AUTO_K_WORKAROUND +static void Tx_Auto_K_DQM_Workaround(DRAMC_CTX_T *p) +{ + //Set RK1 DQM DLY to RK0 + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), u4DQM_MCK_RK1_backup); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), u4DQM_UI_RK1_backup); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u4DQM_PI_RK1_backup[0]); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u4DQM_PI_RK1_backup[1]); +} +static void Tx_Auto_K_DQ_Workaround(DRAMC_CTX_T *p) +{ + //Set RK1 DQM DLY to RK0 + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), u4DQ_MCK_RK1_backup); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), u4DQ_UI_RK1_backup); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u4DQ_PI_RK1_backup[0]); + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u4DQ_PI_RK1_backup[1]); +} +#endif + +#if TX_AUTO_K_DEBUG_ENABLE +static void Tx_Auto_K_Debug_Message(DRAMC_CTX_T *p, U8 u1PI_Len) +{ + U8 u1bit_num = 0, u1BitIdx; + U16 u2Length = 0, u2Length_max = 0; + U32 u4status; + U32 u4status_bit[4][DQ_DATA_WIDTH_LP4]; + + if (u1PI_Len == 0) + u2Length_max = 48; + else + u2Length_max = 32 * (1 + u1PI_Len); + + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), u1BitIdx, TX_ATK_SET1_TX_ATK_DBG_BIT_SEL); + + u4status_bit[0][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS1)); + u4status_bit[1][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS2)); + u4status_bit[2][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS3)); + u4status_bit[3][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS4)); + } + + mcSHOW_DBG_MSG2(("Debug TX DQ PASS/FAIL status:\n")); + + for (u2Length = 0; u2Length < u2Length_max; u2Length++) + { + mcSHOW_DBG_MSG2(("Delay=%3d ", u2Length)); + + for (u1bit_num = 0; u1bit_num < p->data_width; u1bit_num++) + { + u4status = ((u4status_bit[u2Length / 32][u1bit_num] >> (u2Length % 32)) & 0x1); + + if (u4status == 0) + { + mcSHOW_DBG_MSG2(("x")); + } + else + { + mcSHOW_DBG_MSG2(("o")); + } + + if (u1bit_num == (p->data_width - 1)) + { + mcSHOW_DBG_MSG2((" \n")); + } + } + } + + //mcSHOW_DBG_MSG(("Debug DQ PASS(1)/FAIL(0) bit: %d, STATUS1: 0x%x, STATUS2: 0x%x, STATUS3: 0x%x, STATUS4: 0x%x,\n",u1BitIdx,u4status_bit[0][u1BitIdx],u4status_bit[1][u1BitIdx],u4status_bit[2][u1BitIdx],u4status_bit[3][u1BitIdx])); +} +#endif +#endif + +#if TX_K_DQM_WITH_WDBI +void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff) +{ + S8 u1TXShiftMCK; + + u1TXShiftMCK = (u1OnOff)? -1: 1; + DramcWriteShiftMCKForWriteDBI(p, u1TXShiftMCK); //Tx DQ/DQM -1 MCK for write DBI ON + + SetDramModeRegForWriteDBIOnOff(p, p->dram_fsp, u1OnOff); + DramcWriteDBIOnOff(p, u1OnOff); + + #if (TX_AUTO_K_ENABLE && TX_AUTO_K_WORKAROUND) + if (p->rank == RANK_1) + { + u4DQ_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)); + u4DQ_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)); + u4DQ_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)); + u4DQ_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)); + } + #endif +} +#endif + +PASS_WIN_DATA_T WinPerBit[DQ_DATA_WIDTH], VrefWinPerBit[DQ_DATA_WIDTH], FinalWinPerBit[DQ_DATA_WIDTH]; +DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK) +{ + U8 u1BitTemp, u1BitIdx, u1ByteIdx, u1RankIdx, backup_rank; + U32 uiFinishCount; + + U16 uiDelay, u2DQDelayBegin, u2DQDelayEnd, u2DQDelayStep = 1; + + U8 ucdq_pi, ucdq_ui_small, ucdq_ui_large, ucdq_oen_ui_small, ucdq_oen_ui_large; + U8 ucdq_ui_small_reg_value, u1UpdateRegUI; // for UI and TXDLY change check, if different , set reg. + + U8 ucdq_reg_pi[DQS_NUMBER], ucdq_reg_ui_large[DQS_NUMBER], ucdq_reg_ui_small[DQS_NUMBER]; + U8 ucdq_reg_oen_ui_large[DQS_NUMBER], ucdq_reg_oen_ui_small[DQS_NUMBER]; + + U8 ucdq_reg_dqm_pi[DQS_NUMBER] = {0}, ucdq_reg_dqm_ui_large[DQS_NUMBER] = {0}, ucdq_reg_dqm_ui_small[DQS_NUMBER] = {0}; + U8 ucdq_reg_dqm_oen_ui_large[DQS_NUMBER] = {0}, ucdq_reg_dqm_oen_ui_small[DQS_NUMBER] = {0}; + + #if 1//TX_DQM_CALC_MAX_MIN_CENTER + U16 u2DQM_Delay; // LP4 only + U16 u2Center_min[DQS_NUMBER] = {0}, u2Center_max[DQS_NUMBER] = {0}; + #endif + U8 u1EnableDelayCell = 0; + U16 u2DelayCellOfst[DQ_DATA_WIDTH] = {0}; + U32 u4err_value, u4fail_bit; + U16 u2FinalRange = 0, u2FinalVref; + U16 u2VrefLevel, u2VrefBegin = 0, u2VrefEnd = 0, u2VrefStep; + U16 u2TempWinSum, u2MaxWindowSum = 0;//, u2tx_window_sum[LP4_TX_VREF_DATA_NUM]={0}; + U8 u1min_bit, u1min_winsize = 0; + U8 u1VrefIdx = 0; + U8 u1PIDiff; + PASS_WIN_DATA_BY_VREF_T VrefInfo[LP4_TX_VREF_DATA_NUM]; + + if (!p) + { + mcSHOW_ERR_MSG(("context NULL\n")); + return DRAM_FAIL; + } + + #if TX_AUTO_K_ENABLE + U8 u1PI_Len, u1dq_shift; + U32 PwMaxInitReg[4] = {DRAMC_REG_TX_ATK_RESULT0, DRAMC_REG_TX_ATK_RESULT1, DRAMC_REG_TX_ATK_RESULT2, DRAMC_REG_TX_ATK_RESULT3}; + U32 PwMaxLenReg[4] = {DRAMC_REG_TX_ATK_RESULT4, DRAMC_REG_TX_ATK_RESULT5, DRAMC_REG_TX_ATK_RESULT6, DRAMC_REG_TX_ATK_RESULT7}; + U32 u4Length = 0; + #if TX_AUTO_K_WORKAROUND + U8 u1backup_Rank = 0; + #endif + #if TX_AUTO_K_WORKAROUND + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)), + }; + #endif + #endif + +#if VENDER_JV_LOG + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) + vPrintCalibrationBasicInfo_ForJV(p); +#else + vPrintCalibrationBasicInfo(p); +#endif + + backup_rank = u1GetRank(p); + + TXPerbitCalibrationInit(p, calType); + TXScanRange_PI(p, calType, &u2DQDelayBegin, &u2DQDelayEnd); + TXScanRange_Vref(p, u1VrefScanEnable, &u2FinalRange, &u2VrefBegin, &u2VrefEnd, &u2VrefStep); + + //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_FAIL); + + if (isAutoK) + { + #if TX_AUTO_K_ENABLE + //CKEFixOnOff(p, p->rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); //Let CLK always on + + //Set base address of TX MCK and UI + u1UpdateRegUI = 1; + uiDelay = u2DQDelayBegin; + u1PI_Len = 3; + TxWinTransferDelayToUIPI(p, uiDelay, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); + + for (u1ByteIdx = 0; u1ByteIdx < DQS_NUMBER; u1ByteIdx++) + { + if (u1UpdateRegUI) + { + ucdq_reg_ui_large[u1ByteIdx] = ucdq_ui_large; + ucdq_reg_ui_small[u1ByteIdx] = ucdq_ui_small; + ucdq_reg_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large; + ucdq_reg_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small; + + ucdq_reg_dqm_ui_large[u1ByteIdx] = ucdq_ui_large; + ucdq_reg_dqm_ui_small[u1ByteIdx] = ucdq_ui_small; + ucdq_reg_dqm_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large; + ucdq_reg_dqm_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small; + } + + ucdq_reg_pi[u1ByteIdx] = ucdq_pi; + ucdq_reg_dqm_pi[u1ByteIdx] = ucdq_pi; + } + + #if TX_AUTO_K_WORKAROUND + if (p->rank == 1) + { + u1backup_Rank = 1; + p->rank = 0; + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + } + #endif + + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) + { + TXSetDelayReg_DQ(p, u1UpdateRegUI, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi); + mcSHOW_DBG_MSG(("TX Auto-K set begin delay DQ MCK: %d, UI: %d, PI: %d\n", ucdq_reg_ui_large[0], ucdq_reg_ui_small[0], ucdq_reg_pi[0])); + + #if TX_AUTO_K_WORKAROUND + if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1backup_Rank == 1)) + Tx_Auto_K_DQM_Workaround(p); //Set best DLY value of RK1 DQM to RK0 DQM + #endif + } + if (calType == TX_DQ_DQS_MOVE_DQM_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) + { + TXSetDelayReg_DQM(p, u1UpdateRegUI, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi); + mcSHOW_DBG_MSG(("TX Auto-K set begin delay DQM MCK: %d, UI: %d, PI: %d\n", ucdq_reg_dqm_ui_large[0], ucdq_reg_dqm_ui_small[0], ucdq_reg_dqm_pi[0])); + + #if TX_AUTO_K_WORKAROUND + if ((calType == TX_DQ_DQS_MOVE_DQM_ONLY) && (u1backup_Rank == 1)) + Tx_Auto_K_DQ_Workaround(p); //Set best DLY value of RK1 DQ to RK0 DQ + #endif + } + + #if TX_AUTO_K_WORKAROUND + if (u1backup_Rank == 1) + p->rank = 1; + #endif + + //Tx_Auto_K_Init(p, calType, ucdq_pi, u1PI_Len); //u1PI_Len = 1 means that PI len is 64 PI + #endif + } + else + { + if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) + u2DQDelayStep = (1 << 3); + else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) + u2DQDelayStep = (1 << 4); + else if (calType == TX_DQ_DQS_MOVE_DQ_DQM) + u2DQDelayStep = 2; + else + u2DQDelayStep = 1; + if (is_lp5_family(p)) + u2DQDelayStep = 4; /* To speed up simulation */ + #if (FOR_DV_SIMULATION_USED == 1) + u2DQDelayStep = (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) ? 16 : 8; + #endif + } + +#if 0 + mcSHOW_DBG_MSG(("[TxWindowPerbitCal] calType=%d, VrefScanEnable %d (Range %d, VrefBegin %d, u2VrefEnd %d)\n" + "\nBegin, DQ Scan Range %d~%d\n", + calType, u1VrefScanEnable, u2FinalRange, u2VrefBegin, u2VrefEnd, u2DQDelayBegin, u2DQDelayEnd)); +#endif + + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if (p->femmc_Ready == 1 && (p->Bypass_TXWINDOW)) + { + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + u2Center_min[u1ByteIdx] = p->pSavetimeData->u1TxCenter_min_Save[p->channel][p->rank][u1ByteIdx]; + u2Center_max[u1ByteIdx] = p->pSavetimeData->u1TxCenter_max_Save[p->channel][p->rank][u1ByteIdx]; + + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) + { + u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; + FinalWinPerBit[u1BitTemp].win_center = p->pSavetimeData->u1Txwin_center_Save[p->channel][p->rank][u1BitTemp]; + } + } + vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_FAST_K); + } + else + #endif + { +#if ENABLE_K_WITH_WORST_SI_UI_SHIFT + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 +#else + DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); +#endif + + for (u2VrefLevel = u2VrefBegin; u2VrefLevel <= u2VrefEnd; u2VrefLevel += u2VrefStep) + { + // SET tx Vref (DQ) here, LP3 no need to set this. + if (u1VrefScanEnable) + { + #if (!REDUCE_LOG_FOR_PRELOADER) + mcSHOW_DBG_MSG(("\n\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel)); + #endif + + #if VENDER_JV_LOG + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) + { + mcSHOW_DBG_MSG5(("\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel)); + } + #endif + + DramcTXSetVref(p, u2FinalRange, u2VrefLevel); + } + else + { + mcSHOW_DBG_MSG(("\n\n\tTX Vref Scan disable\n")); + } + + // initialize parameters + uiFinishCount = 0; + u2TempWinSum = 0; + ucdq_ui_small_reg_value = 0xff; + + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + WinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA; + WinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA; + VrefWinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA; + VrefWinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA; + } + + if (isAutoK) + { + #if TX_AUTO_K_ENABLE + Tx_Auto_K_Init(p, calType, ucdq_pi, u1PI_Len); //u1PI_Len = 1 means that PI len is 64 PI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_TRIG); //TX Auto K start + #endif + } + else + { + //Move DQ delay , 1 PI = tCK/64, total 128 PI, 1UI = 32 PI + //For data rate 3200, max tDQS2DQ is 2.56UI (82 PI) + //For data rate 4266, max tDQS2DQ is 3.41UI (109 PI) + for (uiDelay = u2DQDelayBegin; uiDelay < u2DQDelayEnd; uiDelay += u2DQDelayStep) + { + TxWinTransferDelayToUIPI(p, uiDelay, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); + + // Check if TX UI changed, if not change , don't need to set reg again + if (ucdq_ui_small_reg_value != ucdq_ui_small) + { + u1UpdateRegUI = 1; + ucdq_ui_small_reg_value = ucdq_ui_small; + } + else + u1UpdateRegUI = 0; + + for (u1ByteIdx = 0; u1ByteIdx < DQS_NUMBER; u1ByteIdx++) + { + if (u1UpdateRegUI) + { + ucdq_reg_ui_large[u1ByteIdx] = ucdq_ui_large; + ucdq_reg_ui_small[u1ByteIdx] = ucdq_ui_small; + ucdq_reg_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large; + ucdq_reg_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small; + + ucdq_reg_dqm_ui_large[u1ByteIdx] = ucdq_ui_large; + ucdq_reg_dqm_ui_small[u1ByteIdx] = ucdq_ui_small; + ucdq_reg_dqm_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large; + ucdq_reg_dqm_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small; + } + + ucdq_reg_pi[u1ByteIdx] = ucdq_pi; + ucdq_reg_dqm_pi[u1ByteIdx] = ucdq_pi; + } + + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) + { + TXSetDelayReg_DQ(p, u1UpdateRegUI, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi); + } + + if (calType == TX_DQ_DQS_MOVE_DQM_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) + { + TXSetDelayReg_DQM(p, u1UpdateRegUI, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi); + } + + u4err_value = 0; +#if ENABLE_K_WITH_WORST_SI_UI_SHIFT + //DramcEngine2SetPat(p, p->test_pattern, 0, 0, TE_UI_SHIFT); + u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern); +#else + //audio + xtalk pattern + DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT); + u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); + DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT); + u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); +#endif + //audio + xtalk pattern + //u4err_value = 0; + //DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0); + //u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); + //DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1); + //u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); + + if (u1VrefScanEnable == 0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY)) + { + //mcSHOW_DBG_MSG(("Delay=%3d |%2d %2d %3d| %2d %2d| 0x%8x [0]",uiDelay, ucdq_ui_large,ucdq_ui_small, ucdq_pi, ucdq_oen_ui_large,ucdq_oen_ui_small, u4err_value)); + #ifdef ETT_PRINT_FORMAT + if (u4err_value != 0) + { + mcSHOW_DBG_MSG2(("%d |%d %d %d|[0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi)); + } + #else + mcSHOW_DBG_MSG2(("Delay=%3d |%2d %2d %3d| 0x%8x [0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi, u4err_value)); + #endif + } + + // check fail bit ,0 ok ,others fail + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + u4fail_bit = u4err_value & ((U32)1 << u1BitIdx); + + if (u1VrefScanEnable == 0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY)) + { + if(u4err_value != 0) + { + if (u1BitIdx % DQS_BIT_NUMBER == 0) + { + mcSHOW_DBG_MSG2((" ")); + } + + if (u4fail_bit == 0) + { + mcSHOW_DBG_MSG2(("o")); + } + else + { + mcSHOW_DBG_MSG2(("x")); + } + } + } + + if (WinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA) + { + if (u4fail_bit == 0) //compare correct: pass + { + WinPerBit[u1BitIdx].first_pass = uiDelay; + + #if TX_TDQS2DQ_PRE_CAL + if ((u1IsLP4Div4DDR800(p) == FALSE) && (calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1VrefScanEnable == FALSE)) + { + if (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] == 0) + { + u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] = ((uiDelay - u2DQDelayBegin)* 1000) / p->frequency; + } + + if (uiDelay == u2DQDelayBegin) + { + mcSHOW_ERR_MSG(("TX_TDQS2DQ_PRE_CAL: Warning, possible miss TX window boundary\n")); + #if __ETT__ + while (1); + #endif + } + } + #endif + } + } + else if (WinPerBit[u1BitIdx].last_pass == PASS_RANGE_NA) + { + if (u4fail_bit != 0) //compare error : fail + { + WinPerBit[u1BitIdx].last_pass = uiDelay - u2DQDelayStep; + } + else if (uiDelay > (u2DQDelayEnd - u2DQDelayStep)) + { + WinPerBit[u1BitIdx].last_pass = uiDelay; + } + + if (WinPerBit[u1BitIdx].last_pass != PASS_RANGE_NA) + { + if ((WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass) >= (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass)) + { + if ((VrefWinPerBit[u1BitIdx].last_pass != PASS_RANGE_NA) && (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass) > 0) + { + mcSHOW_DBG_MSG2(("Bit[%d] Bigger window update %d > %d, window broken?\n", u1BitIdx, \ + (WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass), (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass))); + } + + //if window size bigger than TX_PASS_WIN_CRITERIA, consider as real pass window. If not, don't update finish counte and won't do early break; + if ((WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass) > TX_PASS_WIN_CRITERIA) + uiFinishCount |= (1 << u1BitIdx); + + //update bigger window size + VrefWinPerBit[u1BitIdx].first_pass = WinPerBit[u1BitIdx].first_pass; + VrefWinPerBit[u1BitIdx].last_pass = WinPerBit[u1BitIdx].last_pass; + } + + //reset tmp window + WinPerBit[u1BitIdx].first_pass = PASS_RANGE_NA; + WinPerBit[u1BitIdx].last_pass = PASS_RANGE_NA; + } + } + } + + if(u1VrefScanEnable==0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY)) + { + if(u4err_value != 0) + { + mcSHOW_DBG_MSG2((" [MSB]\n")); + } + } + + //if all bits widnow found and all bits turns to fail again, early break; + if (uiFinishCount == 0xffff) + { + vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK); + #if !REDUCE_LOG_FOR_PRELOADER + #ifdef ETT_PRINT_FORMAT + mcSHOW_DBG_MSG2(("TX calibration finding left boundary early break. PI DQ delay=0x%B\n", uiDelay)); + #else + mcSHOW_DBG_MSG2(("TX calibration finding left boundary early break. PI DQ delay=0x%2x\n", uiDelay)); + #endif + #endif + break; //early break + } + } + } + + if (isAutoK) + { + #if TX_AUTO_K_ENABLE + Tx_Auto_K_complete_check(p); + #if TX_AUTO_K_DEBUG_ENABLE + Tx_Auto_K_Debug_Message(p, u1PI_Len); + #endif + #endif + } + + // (1) calculate per bit window size + // (2) find out min win of all DQ bits + // (3) calculate perbit window center + u1min_winsize = 0xff; + u1min_bit = 0xff; + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + if (isAutoK) + { + #if TX_AUTO_K_ENABLE + u1dq_shift = ((u1BitIdx % 4) * 8); + VrefWinPerBit[u1BitIdx].first_pass = u2DQDelayBegin - ucdq_pi + ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxInitReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift); + VrefWinPerBit[u1BitIdx].last_pass = ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxLenReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift) + VrefWinPerBit[u1BitIdx].first_pass; + VrefWinPerBit[u1BitIdx].win_size = ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxLenReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift); + + if (u1PI_Len == 0) + u4Length = 48; + else + u4Length = 32 * (1 + u1PI_Len); + + if ((VrefWinPerBit[u1BitIdx].first_pass == (int)(u2DQDelayBegin - ucdq_pi)) || (VrefWinPerBit[u1BitIdx].last_pass == (int)(u2DQDelayBegin + u4Length))) + { + mcSHOW_ERR_MSG(("Error! Probably miss pass window!\n")); + } + + mcSHOW_DBG_MSG(("TX DQ bit %d, first pass: %d, last pass: %d\n", u1BitIdx, VrefWinPerBit[u1BitIdx].first_pass, VrefWinPerBit[u1BitIdx].last_pass)); + #else + //if(VrefWinPerBit[u1BitIdx].last_pass == VrefWinPerBit[u1BitIdx].first_pass) + if (VrefWinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA) + VrefWinPerBit[u1BitIdx].win_size = 0; + else + VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass + u2DQDelayStep; + #endif + } + else + { + if (VrefWinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA) + VrefWinPerBit[u1BitIdx].win_size = 0; + else + VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass + u2DQDelayStep; + } + + if (VrefWinPerBit[u1BitIdx].win_size < u1min_winsize) + { + u1min_bit = u1BitIdx; + u1min_winsize = VrefWinPerBit[u1BitIdx].win_size; + } + + u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size; //Sum of CA Windows for vref selection + + #if VENDER_JV_LOG + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) + { + mcSHOW_DBG_MSG5(("TX Bit%d, %d%%\n", u1BitIdx, (VrefWinPerBit[u1BitIdx].win_size * 100 + 31) / 32)); + } + #endif + + + // calculate per bit window position and print + VrefWinPerBit[u1BitIdx].win_center = (VrefWinPerBit[u1BitIdx].first_pass + VrefWinPerBit[u1BitIdx].last_pass) >> 1; + #if PINMUX_AUTO_TEST_PER_BIT_TX + gFinalTXPerbitFirstPass[p->channel][u1BitIdx] = VrefWinPerBit[u1BitIdx].first_pass; + #endif + } + + + #if __ETT__ + if (u1VrefScanEnable == 0) + { + //mcSHOW_DBG_MSG(("\n\tCH=%d, VrefRange= %d, VrefLevel = %d\n", p->channel, u2FinalRange, u2VrefLevel)); + TxPrintWidnowInfo(p, VrefWinPerBit); + } + #endif + + if (u1VrefScanEnable == 1) + { + if (u2TempWinSum > u2MaxWindowSum) + u2MaxWindowSum = u2TempWinSum; + + VrefInfo[u1VrefIdx].u2VrefUsed = u2VrefLevel; + VrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref = u1min_winsize; + VrefInfo[u1VrefIdx].u1WorseBitIdx_byVref = u1min_bit; + VrefInfo[u1VrefIdx].u2WinSum_byVref = u2TempWinSum; + u1VrefIdx ++; + } + + #if TX_AUTO_K_ENABLE + if (isAutoK) + Tx_Auto_K_Clear(p); + #endif + + #if LP4_TX_VREF_PASS_CONDITION + if (u1VrefScanEnable && (u2TempWinSum < (u2MaxWindowSum * 95 / 100)) && (u1min_winsize < LP4_TX_VREF_PASS_CONDITION)) + #else + if (u1VrefScanEnable && (u2TempWinSum < (u2MaxWindowSum * 95 / 100)) && (u1min_winsize > TX_PASS_WIN_CRITERIA)) + #endif + { + mcSHOW_DBG_MSG(("\nTX Vref early break, caculate TX vref\n")); + break; + } + + #if TX_AUTO_K_ENABLE + Tx_Auto_K_Clear(p); + #endif + } + + DramcEngine2End(p); + + #if (TX_AUTO_K_ENABLE && TX_AUTO_K_WORKAROUND) + if ((isAutoK) && (p->rank == RANK_1)) + { + vSetRank(p, RANK_0); + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + vSetRank(p, backup_rank); + } + #endif + + if (u1VrefScanEnable == 0)// ..if time domain (not vref scan) , calculate window center of all bits. + { + // Calculate the center of DQ pass window + // Record center sum of each byte + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + #if 1//TX_DQM_CALC_MAX_MIN_CENTER + u2Center_min[u1ByteIdx] = 0xffff; + u2Center_max[u1ByteIdx] = 0; + #endif + + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) + { + u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; + memcpy(FinalWinPerBit, VrefWinPerBit, sizeof(PASS_WIN_DATA_T) * DQ_DATA_WIDTH); + + if (FinalWinPerBit[u1BitTemp].win_center < u2Center_min[u1ByteIdx]) + u2Center_min[u1ByteIdx] = FinalWinPerBit[u1BitTemp].win_center; + + if (FinalWinPerBit[u1BitTemp].win_center > u2Center_max[u1ByteIdx]) + u2Center_max[u1ByteIdx] = FinalWinPerBit[u1BitTemp].win_center; + + #ifdef FOR_HQA_TEST_USED + if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1VrefScanEnable == 0)) + { + gFinalTXPerbitWin[p->channel][p->rank][u1BitTemp] = FinalWinPerBit[u1BitTemp].win_size; + } + #endif + } + } + } + } + + // SET tx Vref (DQ) = u2FinalVref, LP3 no need to set this. + if (u1VrefScanEnable) + { + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL + if (p->femmc_Ready == 1 && (p->Bypass_TXWINDOW)) + { + u2FinalVref = p->pSavetimeData->u1TxWindowPerbitVref_Save[p->channel][p->rank]; + } + else + #endif + { + u2FinalVref = TxChooseVref(p, VrefInfo, u1VrefIdx); + } + + TXSetFinalVref(p, u2FinalRange, u2FinalVref); + return DRAM_OK; + } + +#ifdef FOR_HQA_TEST_USED + // LP4 DQ time domain || LP3 DQ_DQM time domain + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) + { + gFinalTXPerbitWin_min_max[p->channel][p->rank] = u1min_winsize; + if(u1min_winsize<16) + { + mcSHOW_ERR_MSG(("[WARNING] Smaller TX win !!\n")); + #if CHECK_HQA_CRITERIA + while(1); + #endif + } + } +#endif + + // LP3 only use "TX_DQ_DQS_MOVE_DQ_DQM" scan + // first freq 800(LP4-1600) doesn't support jitter meter(data < 1T), therefore, don't use delay cell + if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (p->frequency >= 1333) && (p->u2DelayCellTimex100 != 0)) + { + u1EnableDelayCell = 1; + mcSHOW_DBG_MSG(("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", p->u2DelayCellTimex100)); + } + + //Calculate the center of DQ pass window + //average the center delay + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + mcSHOW_DBG_MSG((" == TX Byte %d ==\n", u1ByteIdx)); + u2DQM_Delay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx]) >> 1); //(max +min)/2 + + if (u1EnableDelayCell == 0) + { + uiDelay = u2DQM_Delay; + } + else// if(calType == TX_DQ_DQS_MOVE_DQ_ONLY) + { + uiDelay = u2Center_min[u1ByteIdx]; // for DQ PI delay , will adjust with delay cell + + // calculate delay cell perbit + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) + { + u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; + u1PIDiff = FinalWinPerBit[u1BitTemp].win_center - u2Center_min[u1ByteIdx]; + if (p->u2DelayCellTimex100 != 0) + { + u2DelayCellOfst[u1BitTemp] = (u1PIDiff * 100000000 / (p->frequency << 6)) / p->u2DelayCellTimex100; + + mcSHOW_DBG_MSG(("u2DelayCellOfst[%d]=%d cells (%d PI)\n", u1BitTemp, u2DelayCellOfst[u1BitTemp], u1PIDiff)); + + if(u2DelayCellOfst[u1BitTemp]>255) + { + mcSHOW_DBG_MSG(("[WARNING] TX DQ%d delay cell %d >255, adjust to 255 cell\n", u1BitIdx, u2DelayCellOfst[u1BitTemp])); + u2DelayCellOfst[u1BitTemp] =255; + } + } + else + { + mcSHOW_ERR_MSG(("Error: Cell time (p->u2DelayCellTimex100) is 0 \n")); + break; + } + } + + } + + TxWinTransferDelayToUIPI(p, uiDelay, 1, &ucdq_reg_ui_large[u1ByteIdx], &ucdq_reg_ui_small[u1ByteIdx], &ucdq_reg_pi[u1ByteIdx], \ + &ucdq_reg_oen_ui_large[u1ByteIdx], &ucdq_reg_oen_ui_small[u1ByteIdx]); + + TxWinTransferDelayToUIPI(p, u2DQM_Delay, 1, &ucdq_reg_dqm_ui_large[u1ByteIdx], &ucdq_reg_dqm_ui_small[u1ByteIdx], &ucdq_reg_dqm_pi[u1ByteIdx], \ + &ucdq_reg_dqm_oen_ui_large[u1ByteIdx], &ucdq_reg_dqm_oen_ui_small[u1ByteIdx]); + + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) + { + mcSHOW_DBG_MSG(("Update DQ dly =%d (%d ,%d, %d) DQ OEN =(%d ,%d)\n", + uiDelay, ucdq_reg_ui_large[u1ByteIdx], ucdq_reg_ui_small[u1ByteIdx], ucdq_reg_pi[u1ByteIdx], \ + ucdq_reg_oen_ui_large[u1ByteIdx], ucdq_reg_oen_ui_small[u1ByteIdx])); + } + + //if(calType ==TX_DQ_DQS_MOVE_DQM_ONLY || calType== TX_DQ_DQS_MOVE_DQ_DQM) + { + mcSHOW_DBG_MSG(("Update DQM dly =%d (%d ,%d, %d) DQM OEN =(%d ,%d)", + u2DQM_Delay, ucdq_reg_dqm_ui_large[u1ByteIdx], ucdq_reg_dqm_ui_small[u1ByteIdx], ucdq_reg_dqm_pi[u1ByteIdx], \ + ucdq_reg_dqm_oen_ui_large[u1ByteIdx], ucdq_reg_dqm_oen_ui_small[u1ByteIdx])); + } + mcSHOW_DBG_MSG(("\n")); + +#ifdef FOR_HQA_REPORT_USED + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) + { + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "TX_Window_Center_", "DQ", u1BitIdx, FinalWinPerBit[u1BitIdx].win_center, NULL); + } + } + + if (calType == TX_DQ_DQS_MOVE_DQM_ONLY) + { + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "DQM", u1ByteIdx, u2DQM_Delay, NULL); + } +#if 0 + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "TX_Window_Center_", "LargeUI", u1ByteIdx, ucdq_reg_ui_large[u1ByteIdx], NULL); + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "SmallUI", u1ByteIdx, ucdq_reg_ui_small[u1ByteIdx], NULL); + HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "PI", u1ByteIdx, ucdq_reg_pi[u1ByteIdx], NULL); +#endif +#endif + + } + + +#if REG_ACCESS_PORTING_DGB + RegLogEnable = 1; +#endif + + /* p->rank = RANK_0, save to Reg Rank0 and Rank1, p->rank = RANK_1, save to Reg Rank1 */ + for (u1RankIdx = p->rank; u1RankIdx < RANK_MAX; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) + { + TXSetDelayReg_DQ(p, TRUE, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi); + } + + TXSetDelayReg_DQM(p, TRUE, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi); + + if (u1EnableDelayCell) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), + P_Fld(u2DelayCellOfst[3], SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0) + | P_Fld(u2DelayCellOfst[2], SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) + | P_Fld(u2DelayCellOfst[1], SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) + | P_Fld(u2DelayCellOfst[0], SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), + P_Fld(u2DelayCellOfst[7], SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0) + | P_Fld(u2DelayCellOfst[6], SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) + | P_Fld(u2DelayCellOfst[5], SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) + | P_Fld(u2DelayCellOfst[4], SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), + P_Fld(u2DelayCellOfst[11], SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1) + | P_Fld(u2DelayCellOfst[10], SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) + | P_Fld(u2DelayCellOfst[9], SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) + | P_Fld(u2DelayCellOfst[8], SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), + P_Fld(u2DelayCellOfst[15], SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1) + | P_Fld(u2DelayCellOfst[14], SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) + | P_Fld(u2DelayCellOfst[13], SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) + | P_Fld(u2DelayCellOfst[12], SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1)); + } + + #if ENABLE_TX_TRACKING + TXUpdateTXTracking(p, calType, ucdq_reg_pi, ucdq_reg_dqm_pi); + #endif + } + + vSetRank(p, backup_rank); + + if (isAutoK) + { + #if TX_AUTO_K_ENABLE + #if TX_AUTO_K_WORKAROUND + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), + P_Fld(ucdq_reg_pi[0], TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | + P_Fld(ucdq_reg_pi[1], TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) | + P_Fld(ucdq_reg_dqm_pi[0], TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | + P_Fld(ucdq_reg_dqm_pi[1], TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); //If TX auto-k is enable, TX_PI will be switch to PI_INIT + #endif + #endif + } + +#if REG_ACCESS_PORTING_DGB + RegLogEnable = 0; +#endif + +#if (TX_AUTO_K_ENABLE && TX_AUTO_K_WORKAROUND) + if ((isAutoK) && (p->rank == RANK_1) && (calType == TX_DQ_DQS_MOVE_DQ_DQM)) + { + u4DQM_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)); + u4DQM_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)); + u4DQM_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)); + u4DQM_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)); + u4DQ_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)); + u4DQ_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)); + u4DQ_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)); + u4DQ_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)); + } +#endif + + mcSHOW_DBG_MSG3(("[TxWindowPerbitCal] Done\n\n")); + + #if 0 + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_PADCTL4), 1, PADCTL4_CKEFIXON); // test only + #endif + + return DRAM_OK; +} + +#endif //SIMULATION_TX_PERBIT + +#if ENABLE_EYESCAN_GRAPH +void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) +{ + U8 ucindex, u1BitIdx, u1ByteIdx; + U8 ii, backup_rank, u1PrintWinData, u1vrefidx; + PASS_WIN_DATA_T WinPerBit[DQ_DATA_WIDTH], VrefWinPerBit[DQ_DATA_WIDTH], FinalWinPerBit[DQ_DATA_WIDTH]; + U16 tx_pi_delay[4], tx_dqm_pi_delay[4]; + U16 u2DQDelayBegin, uiDelay; + U16 u2VrefLevel, u2VrefBegin, u2VrefEnd, u2VrefStep, u2VrefRange; + U8 ucdq_pi, ucdq_ui_small, ucdq_ui_large,ucdq_oen_ui_small, ucdq_oen_ui_large; + U32 uiFinishCount; + U16 u2TempWinSum, u2tx_window_sum=0; + U32 u4err_value, u4fail_bit; + #if 1//TX_DQM_CALC_MAX_MIN_CENTER + U16 u2Center_min[DQS_NUMBER],u2Center_max[DQS_NUMBER]; + #endif + + U16 TXPerbitWin_min_max = 0; + U32 min_bit, min_winsize; + + U16 u2FinalVref=0xd; + U16 u2FinalRange=0; + + U8 EyeScan_index[DQ_DATA_WIDTH]; + + U16 backup_u1MR14Value; + U8 u1pass_in_this_vref_flag[DQ_DATA_WIDTH]; + + U8 u1MCK2UI, u1UI2PI; + + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)), + }; + + if (GetEyeScanEnable(p, 2)==DISABLE) return; + + //if (gTX_EYE_Scan_only_higheset_freq_flag==1 && p->frequency != u2DFSGetHighestFreq(p)) return; + + //backup register value + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); + + backup_u1MR14Value = u1MR14Value[p->channel][p->rank][p->dram_fsp]; + //Jimmy Temp + DramcModeRegReadByRank(p, p->rank, 14, &backup_u1MR14Value); + + if (gFinalTXVrefDQ[p->channel][p->rank] ==0) //Set final TX Vref as default value + gFinalTXVrefDQ[p->channel][p->rank] = u1MR14Value[p->channel][p->rank][p->dram_fsp]; + + //set initial values + for(u1vrefidx=0; u1vrefidx<=VREF_VOLTAGE_TABLE_NUM_LP5-1;u1vrefidx++) + { + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + for(ii=0; ii<EYESCAN_BROKEN_NUM; ii++) + { + gEyeScan_Min[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID; + gEyeScan_Max[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID; + } + gEyeScan_ContinueVrefHeight[u1BitIdx] = 0; + gEyeScan_TotalPassCount[u1BitIdx] = 0; + } + } + + + u1MCK2UI = u1MCK2UI_DivShift(p); + + //if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP) + // u1UI2PI = 6; + //else + u1UI2PI = 5; + + + for(u1ByteIdx=0; u1ByteIdx < p->data_width/DQS_BIT_NUMBER; u1ByteIdx++) + { + if (u1ByteIdx == 0) + { + tx_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ0)<<(u1MCK2UI+u1UI2PI)) + + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ0)<<u1UI2PI) + + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQ_B0)*(u1IsPhaseMode(p)==TRUE ? 8 : 1); + + tx_dqm_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM0)<<(u1MCK2UI+u1UI2PI)) + + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM0)<<u1UI2PI) + + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQM_B0)*(u1IsPhaseMode(p)==TRUE ? 8 : 1); + } + else + { + tx_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ1)<<(u1MCK2UI+u1UI2PI)) + + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ1)<<u1UI2PI) + + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQ_B1)*(u1IsPhaseMode(p)==TRUE ? 8 : 1); + + tx_dqm_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM1)<<(u1MCK2UI+u1UI2PI)) + + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM1)<<u1UI2PI) + + u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQM_B1)*(u1IsPhaseMode(p)==TRUE ? 8 : 1); + } + } + + if (tx_pi_delay[0] < tx_pi_delay[1]) + { + u2DQDelayBegin = tx_pi_delay[0]-32; + } + else + { + u2DQDelayBegin = tx_pi_delay[1]-32; + } + + u2VrefRange = 0; + u2VrefBegin = 0; + u2VrefEnd = (p->dram_type==TYPE_LPDDR5?VREF_VOLTAGE_TABLE_NUM_LP5:VREF_VOLTAGE_TABLE_NUM_LP4)-1; + u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP; + mcSHOW_DBG_MSG3(("\nTX Vref %d -> %d, step: %d\n", u2VrefBegin, u2VrefEnd, u2VrefStep)); + +#if ENABLE_K_WITH_WORST_SI_UI_SHIFT + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 +#else + DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); +#endif + + + for(u2VrefLevel = u2VrefBegin; u2VrefLevel <= u2VrefEnd; u2VrefLevel += u2VrefStep) + { + //set vref +//fra u1MR14Value[p->channel][p->rank][p->dram_fsp] = (u2VrefLevel | (u2VrefRange<<6)); + DramcTXSetVref(p, u2VrefRange, u2VrefLevel); + mcSHOW_DBG_MSG3(("\n\n Set TX VrefRange %d, VrefLevel=%d\n", u2VrefRange, u2VrefLevel)); + + // initialize parameters + uiFinishCount = 0; + u2TempWinSum =0; + + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + WinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA; + WinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA; + VrefWinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA; + VrefWinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA; + + gEyeScan_DelayCellPI[u1BitIdx] = 0; + + EyeScan_index[u1BitIdx] = 0; + u1pass_in_this_vref_flag[u1BitIdx] = 0; + } + + for (uiDelay=0; uiDelay<64; uiDelay+=(u1IsPhaseMode(p)==TRUE ? 8 : 1)) + { + TxWinTransferDelayToUIPI(p, tx_pi_delay[0]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ + P_Fld(ucdq_ui_large, SHURK_SELPH_DQ0_TXDLY_DQ0) | \ + P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ + P_Fld(ucdq_ui_small, SHURK_SELPH_DQ2_DLY_DQ0) | \ + P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ2_DLY_OEN_DQ0)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdq_pi, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0); + + TxWinTransferDelayToUIPI(p, tx_pi_delay[1]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ + P_Fld(ucdq_ui_large, SHURK_SELPH_DQ0_TXDLY_DQ1) | \ + P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ + P_Fld(ucdq_ui_small, SHURK_SELPH_DQ2_DLY_DQ1) | \ + P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ2_DLY_OEN_DQ1)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdq_pi, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1); + + TxWinTransferDelayToUIPI(p, tx_dqm_pi_delay[0]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \ + P_Fld(ucdq_ui_large, SHURK_SELPH_DQ1_TXDLY_DQM0) | \ + P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \ + P_Fld(ucdq_ui_small, SHURK_SELPH_DQ3_DLY_DQM0) | \ + P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ3_DLY_OEN_DQM0)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdq_pi, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0); + + TxWinTransferDelayToUIPI(p, tx_dqm_pi_delay[1]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \ + P_Fld(ucdq_ui_large, SHURK_SELPH_DQ1_TXDLY_DQM1) | \ + P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \ + P_Fld(ucdq_ui_small, SHURK_SELPH_DQ3_DLY_DQM1) | \ + P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ3_DLY_OEN_DQM1)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdq_pi, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1); + + u4err_value=0; +#if ENABLE_K_WITH_WORST_SI_UI_SHIFT + //DramcEngine2SetPat(p, p->test_pattern, 0, 0, TE_UI_SHIFT); + u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern); +#else + //audio + xtalk pattern + DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT); + u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); + DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT); + u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); +#endif + // audio + xtalk pattern + //u4err_value=0; + //DramcEngine2SetPat(p,TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT); + //u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); + //DramcEngine2SetPat(p,TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT); + //u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); + + // check fail bit ,0 ok ,others fail + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + u4fail_bit = u4err_value&((U32)1<<u1BitIdx); + + if (u4fail_bit == 0) + { + gEyeScan_TotalPassCount[u1BitIdx]+=EYESCAN_GRAPH_CATX_VREF_STEP; + } + + if(WinPerBit[u1BitIdx].first_pass== PASS_RANGE_NA) + { + if(u4fail_bit==0) //compare correct: pass + { + WinPerBit[u1BitIdx].first_pass = uiDelay; + u1pass_in_this_vref_flag[u1BitIdx] = 1; + } + } + else if(WinPerBit[u1BitIdx].last_pass == PASS_RANGE_NA) + { + if(u4fail_bit !=0) //compare error : fail + { + WinPerBit[u1BitIdx].last_pass = (uiDelay-1); + } + else if (uiDelay>=63) + { + WinPerBit[u1BitIdx].last_pass = 63; + } + + if(WinPerBit[u1BitIdx].last_pass !=PASS_RANGE_NA) + { + if((WinPerBit[u1BitIdx].last_pass -WinPerBit[u1BitIdx].first_pass) >= (VrefWinPerBit[u1BitIdx].last_pass -VrefWinPerBit[u1BitIdx].first_pass)) + { + //if window size bigger than 7, consider as real pass window. If not, don't update finish counte and won't do early break; + if((WinPerBit[u1BitIdx].last_pass -WinPerBit[u1BitIdx].first_pass) >7) + uiFinishCount |= (1<<u1BitIdx); + + //update bigger window size + VrefWinPerBit[u1BitIdx].first_pass = WinPerBit[u1BitIdx].first_pass; + VrefWinPerBit[u1BitIdx].last_pass = WinPerBit[u1BitIdx].last_pass; + } + + + if (EyeScan_index[u1BitIdx] < EYESCAN_BROKEN_NUM) + { +#if VENDER_JV_LOG || defined(RELEASE) + gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].first_pass; + gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].last_pass; +#else +//fra gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].first_pass + tx_pi_delay[u1BitIdx/8]-32; +//fra gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].last_pass + tx_pi_delay[u1BitIdx/8]-32; + gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].first_pass; + gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].last_pass; + mcSHOW_DBG_MSG3(("VrefRange %d, VrefLevel=%d, u1BitIdx=%d, index=%d (%d, %d)==\n",u2VrefRange,u2VrefLevel, u1BitIdx, EyeScan_index[u1BitIdx], gEyeScan_Min[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]], gEyeScan_Max[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]])); + gEyeScan_MinMax_store_delay[u1BitIdx/8] = tx_pi_delay[u1BitIdx/8]-32; /* save this information for HQA pass/fail judgement used */ +#endif + EyeScan_index[u1BitIdx]=EyeScan_index[u1BitIdx]+1; + } + + + //reset tmp window + WinPerBit[u1BitIdx].first_pass = PASS_RANGE_NA; + WinPerBit[u1BitIdx].last_pass = PASS_RANGE_NA; + } + } + } + } + + min_winsize = 0xffff; + min_bit = 0xff; + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass- VrefWinPerBit[u1BitIdx].first_pass +(VrefWinPerBit[u1BitIdx].last_pass==VrefWinPerBit[u1BitIdx].first_pass?0:1); + + if (VrefWinPerBit[u1BitIdx].win_size < min_winsize) + { + min_bit = u1BitIdx; + min_winsize = VrefWinPerBit[u1BitIdx].win_size; + } + + u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size; //Sum of CA Windows for vref selection + + gEyeScan_WinSize[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx] = VrefWinPerBit[u1BitIdx].win_size; + +#ifdef FOR_HQA_TEST_USED + if((((backup_u1MR14Value>>6)&1) == u2VrefRange) && ((backup_u1MR14Value&0x3f)==u2VrefLevel)) + { + gFinalTXPerbitWin[p->channel][p->rank][u1BitIdx] = VrefWinPerBit[u1BitIdx].win_size; + } +#endif + + } + + if ((min_winsize > TXPerbitWin_min_max) || ((min_winsize == TXPerbitWin_min_max) && (u2TempWinSum >u2tx_window_sum))) + { + TXPerbitWin_min_max = min_winsize; + u2tx_window_sum =u2TempWinSum; + u2FinalRange = u2VrefRange; + u2FinalVref = u2VrefLevel; + + //Calculate the center of DQ pass window + // Record center sum of each byte + for (u1ByteIdx=0; u1ByteIdx<(p->data_width/DQS_BIT_NUMBER); u1ByteIdx++) + { + #if 1//TX_DQM_CALC_MAX_MIN_CENTER + u2Center_min[u1ByteIdx] = 0xffff; + u2Center_max[u1ByteIdx] = 0; + #endif + + for (u1BitIdx=0; u1BitIdx<DQS_BIT_NUMBER; u1BitIdx++) + { + ucindex = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; + FinalWinPerBit[ucindex].first_pass = VrefWinPerBit[ucindex].first_pass; + FinalWinPerBit[ucindex].last_pass = VrefWinPerBit[ucindex].last_pass; + FinalWinPerBit[ucindex].win_size = VrefWinPerBit[ucindex].win_size; + FinalWinPerBit[ucindex].win_center = (FinalWinPerBit[ucindex].first_pass + FinalWinPerBit[ucindex].last_pass) >> 1; + + if(FinalWinPerBit[ucindex].win_center < u2Center_min[u1ByteIdx]) + u2Center_min[u1ByteIdx] = FinalWinPerBit[ucindex].win_center; + + if(FinalWinPerBit[ucindex].win_center > u2Center_max[u1ByteIdx]) + u2Center_max[u1ByteIdx] = FinalWinPerBit[ucindex].win_center; + } + } + } + + + if(u2VrefRange==0 && u2VrefLevel ==50 && p->dram_type!=TYPE_LPDDR5) + { + u2VrefRange = 1; + u2VrefLevel = 20; + } + + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) + { + if (u1pass_in_this_vref_flag[u1BitIdx]) gEyeScan_ContinueVrefHeight[u1BitIdx]+=EYESCAN_GRAPH_CATX_VREF_STEP; //count pass number of continue vref + } + } + + DramcEngine2End(p); + + //Calculate the center of DQ pass window + //average the center delay + for (u1ByteIdx=0; u1ByteIdx<(p->data_width/DQS_BIT_NUMBER); u1ByteIdx++) + { + uiDelay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx])>>1); //(max +min)/2 + +#if VENDER_JV_LOG || defined(RELEASE) + gEyeScan_CaliDelay[u1ByteIdx] = uiDelay; +#else + gEyeScan_CaliDelay[u1ByteIdx] = uiDelay + tx_pi_delay[u1ByteIdx]-32; +#endif + } + + + //restore to orignal value + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); + + //restore Vref + #ifdef __LP5_COMBO__ + if (is_lp5_family(p)) + { + u2VrefRange = 0; + u2VrefLevel = backup_u1MR14Value; + } + else + #endif + { + u2VrefRange = backup_u1MR14Value>>6; + u2VrefLevel = backup_u1MR14Value & 0x3f; + } + DramcTXSetVref(p, u2VrefRange, u2VrefLevel); + u1MR14Value[p->channel][p->rank][p->dram_fsp] = backup_u1MR14Value; + +} +#endif + +#if TX_OE_CALIBATION +#define TX_OE_PATTERN_USE_TA2 1 +#define TX_OE_SCAN_FULL_RANGE 0 + +void DramcTxOECalibration(DRAMC_CTX_T *p) +{ + U8 u1ByteIdx; + //U8 ucbegin=0xff, , ucfirst, ucsum, ucbest_step; + U8 ucdq_oen_ui_large[2] = {0}, ucdq_oen_ui_small[2] = {0}; + //U8 ucdq_ui_large_reg_value=0xff, ucdq_ui_small_reg_value=0xff; + U8 u1TxDQOEShift = 0; + + u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4; + + #if TX_OE_PATTERN_USE_TA2 + mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] TA2\n")); + #else + mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] DMA\n")); + #endif + + //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_TX_OE, DRAM_FAIL); + +#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION) + if (p->femmc_Ready == 1) + { + for (u1ByteIdx = 0; u1ByteIdx < DQS_NUMBER_LP4; u1ByteIdx++) + { + ucdq_oen_ui_large[u1ByteIdx] = p->pSavetimeData->u1TX_OE_DQ_MCK[p->channel][p->rank][u1ByteIdx]; + ucdq_oen_ui_small[u1ByteIdx] = p->pSavetimeData->u1TX_OE_DQ_UI[p->channel][p->rank][u1ByteIdx]; + } + vSetCalibrationResult(p, DRAM_CALIBRATION_TX_OE, DRAM_FAST_K); + } +#endif + + for (u1ByteIdx = 0; u1ByteIdx < DQS_NUMBER_LP4; u1ByteIdx++) + { + mcSHOW_DBG_MSG(("Byte%d TX OE(2T, 0.5T) = (%d, %d)\n", u1ByteIdx, ucdq_oen_ui_large[u1ByteIdx], ucdq_oen_ui_small[u1ByteIdx])); + } + mcSHOW_DBG_MSG(("\n\n")); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ + P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | \ + P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ0_TXDLY_OEN_DQ1)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \ + P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | \ + P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ1_TXDLY_OEN_DQM1)); + // DLY_DQ[2:0] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ + P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ2_DLY_OEN_DQ0) | \ + P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ2_DLY_OEN_DQ1) ); + // DLY_DQM[2:0] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \ + P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ3_DLY_OEN_DQM0) | \ + P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ3_DLY_OEN_DQM1)); +} +#endif + +//------------------------------------------------------------------------- +/** DramcMiockJmeter + * start MIOCK jitter meter. + * @param p Pointer of context created by DramcCtxCreate. + * @param block_no (U8): block 0 or 1. + * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL + */ +//------------------------------------------------------------------------- + +#ifdef ENABLE_MIOCK_JMETER +DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p) +{ + U16 ucsearch_state, fgcurrent_value, fginitial_value, ucstart_period = 0, ucmiddle_period = 0, ucend_period = 0; + U32 u4sample_cnt, u4ones_cnt[DQS_NUMBER]; + U16 u2real_freq, u2real_period, ucdqs_dly; + U16 u2Jm_dly_start = 0, u2Jm_dly_end = 512, u2Jm_dly_step = 4; + U8 u1ShuLevel; + U32 u4PLL3_ADDR, u4B0_DQ; + U32 u4PLL5_ADDR; + U32 u4PLL8_ADDR; + U32 u4SDM_PCW; + U32 u4PREDIV; + U32 u4POSDIV; + U32 u4CKDIV4; + U32 u4VCOFreq; + U32 u4DataRate; + U8 u1RxGatingPI = 0, u1RxGatingPI_start = 0, u1RxGatingPI_end = 63; + U8 backup_rank, u1RankIdx, u1FBKSEL; + + u1RxGatingPI = 0x0; + + u2gdelay_cell_ps = 0; + + // error handling + if (!p) + { + mcSHOW_ERR_MSG(("context NULL\n")); + return DRAM_FAIL; + } + + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY)), // need porting to Jmeter + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY + DDRPHY_AO_RANK_OFFSET)), // need porting to Jmeter + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER)), + //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), // for gating on/off + //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)), // for gating on/off + //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL)), // for gating on/off + ((DDRPHY_REG_SHU_CA_DLL1)), + ((DDRPHY_REG_SHU_B0_DLL1)), + ((DDRPHY_REG_SHU_B1_DLL1)), + ((DDRPHY_REG_B0_DQ2)), + ((DDRPHY_REG_B1_DQ2)), + ((DDRPHY_REG_CA_CMD2)), + ((DDRPHY_REG_SHU_B0_DQ13)), + ((DDRPHY_REG_SHU_B1_DQ13)), + ((DDRPHY_REG_SHU_CA_CMD13)), + + ((DDRPHY_REG_SHU_CA_DLL1) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_B0_DLL1) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_B1_DLL1) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_B0_DQ2) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_B1_DQ2) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_CA_CMD2) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_B0_DQ13) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_B1_DQ13) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_CA_CMD13) + SHIFT_TO_CHB_ADDR), +#if (CHANNEL_NUM > 2) + ((DDRPHY_REG_SHU_CA_DLL1) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_B0_DLL1) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_B1_DLL1) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_B0_DQ2) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_B1_DQ2) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_CA_CMD2) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_B0_DQ13) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_B1_DQ13) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_CA_CMD13) + SHIFT_TO_CHC_ADDR), + + ((DDRPHY_REG_SHU_CA_DLL1) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_B0_DLL1) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_B1_DLL1) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_B0_DQ2) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_B1_DQ2) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_CA_CMD2) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_B0_DQ13) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_B1_DQ13) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_CA_CMD13) + SHIFT_TO_CHD_ADDR), +#endif + }; + + backup_rank = u1GetRank(p); + + //backup register value + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + //OE disable - start + vIO32WriteFldMulti_All(DDRPHY_REG_B0_DQ2, P_Fld( 0 , B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0 ) \ + | P_Fld( 0 , B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0 ) \ + | P_Fld( 0 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0 ) \ + | P_Fld( 0 , B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0 ) \ + | P_Fld( 0 , B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0 ) \ + | P_Fld( 0xff , B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0 ) ); + + vIO32WriteFldMulti_All(DDRPHY_REG_B1_DQ2, P_Fld( 0 , B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1 ) \ + | P_Fld( 0 , B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1 ) \ + | P_Fld( 0 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1 ) \ + | P_Fld( 0 , B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1 ) \ + | P_Fld( 0 , B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1 ) \ + | P_Fld( 0xff , B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1 ) ); + + vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld( 0 , CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA ) \ + | P_Fld( 1 , CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA ) \ + | P_Fld( 0 , CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA ) \ + | P_Fld( 1 , CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA ) \ + | P_Fld( 0 , CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA ) \ + | P_Fld( 0xff , CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA ) ); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ13 , P_Fld( 0 , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0 )); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ13 , P_Fld( 0 , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1 )); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD13, P_Fld( 0 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \ + | P_Fld( 1 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA )); + //OE disable - end + + //DramcHWGatingOnOff(p, 0); // disable Gating tracking for DQS PI, Remove to vApplyConfigBeforeCalibration + + // @A60868 for *RANK_SEL_SER_EN* = 0 to DA_RX_ARDQ_RANK_SEL_TXD_*[0] + // for *RANK_SEL_SER_EN* = 1 to DA_RX_ARDQ_RANK_SEL_TXD_*[7:0] + // The *RANK_SEL_SER_EN* = 0 is old mode. + // The *RANK_SEL_SER_EN* = 1 is new mode when background no any access. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), 0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA); + + //@Darren, DLL off to stable fix middle transion from high to low or low to high at high vcore + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_DLL1, P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) + | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DLL1, P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) + | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DLL1, P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) + | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1)); + + //MCK4X CG + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMDQSIENCG_EN); + //@A60868, DQS PI mode for JMTR + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), 0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0); // DQS PI mode + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), 0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1); // DQS PI mode + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN); // enable toggle cnt + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), 0, MISC_CTRL4_R_OPT2_CG_DQSIEN); // Remove to Golden settings for Jmeter clock + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); // @Darren need confirm for DQS*_ERR_CNT, APHY PICG freerun + //@A60868, End + + // Bypass DQS glitch-free mode + // RG_RX_*RDQ_EYE_DLY_DQS_BYPASS_B** + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 1, B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), 1, B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1); + + //Enable DQ eye scan + //RG_*_RX_EYE_SCAN_EN + //RG_*_RX_VREF_EN + //RG_*_RX_SMT_EN + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN) + | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN) + | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); + //@A60868, JMTR en + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER), 1, MISC_JMETER_JMTR_EN); + //@A60868, End + + //@A60868, JM_SEL = 1, JM_SEL = 0 for LPBK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1); + //@A60868, End + + //Enable MIOCK jitter meter mode ( RG_RX_MIOCK_JIT_EN=1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN); + + //Disable DQ eye scan (b'1), for counter clear + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_DQSERRCNT_DIS); + + for (u1RxGatingPI = u1RxGatingPI_start; u1RxGatingPI < u1RxGatingPI_end; u1RxGatingPI++) + { + mcSHOW_DBG_MSG(("\n[DramcMiockJmeter] u1RxGatingPI = %d\n", u1RxGatingPI)); + + ucsearch_state = 0; + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + // SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0[6] no use (ignore) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1RxGatingPI, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); // for rank*_B0 + //Darren---vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), u1RxGatingPI, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); // for rank*_B0 + } + vSetRank(p, backup_rank); + + for (ucdqs_dly = u2Jm_dly_start; ucdqs_dly < u2Jm_dly_end; ucdqs_dly += u2Jm_dly_step) + { + + //@A60868, Set DQS delay (RG_*_RX_DQS_EYE_DLY) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), ucdqs_dly, B0_PHY2_RG_RX_ARDQS_JM_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), ucdqs_dly, B1_PHY2_RG_RX_ARDQS_JM_DLY_B1); + //@A60868, End + DramPhyReset(p); + + //Reset eye scan counters (reg_sw_rst): 1 to 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_REG_SW_RST); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_REG_SW_RST); + + //Enable DQ eye scan (b'1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); + + //2ns/sample, here we delay 1ms about 500 samples + mcDELAY_US(10); + + //Disable DQ eye scan (b'1), for counter latch + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); + + //Read the counter values from registers (toggle_cnt*, dqs_err_cnt*); + u4sample_cnt = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_TOGGLE_CNT), MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT); + u4ones_cnt[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT), MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT); + //u4ones_cnt[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT), MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT); + //u4ones_cnt[2] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT), MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT); + //u4ones_cnt[3] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT), MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT); + #ifdef ETT_PRINT_FORMAT + mcSHOW_DBG_MSG(("%d : %d, %d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0])); + #else + mcSHOW_DBG_MSG(("%3d : %8d, %8d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0])); + #endif + + //change to boolean value + if (u4ones_cnt[0] < (u4sample_cnt / 2)) + { + fgcurrent_value = 0; + } + else + { + fgcurrent_value = 1; + } + + #if 1//more than 1T data + { + if (ucsearch_state == 0) + { + //record initial value at the beginning + fginitial_value = fgcurrent_value; + ucsearch_state = 1; + } + else if (ucsearch_state == 1) + { + // check if change value + if (fgcurrent_value != fginitial_value) + { + // start of the period + fginitial_value = fgcurrent_value; + ucstart_period = ucdqs_dly; + ucsearch_state = 2; + } + } + else if (ucsearch_state == 2) + { + // check if change value + if (fgcurrent_value != fginitial_value) + { + fginitial_value = fgcurrent_value; + ucmiddle_period = ucdqs_dly; + ucsearch_state = 3; + } + } + else if (ucsearch_state == 3) + { + // check if change value + if (fgcurrent_value != fginitial_value) + { + // end of the period, break the loop + ucend_period = ucdqs_dly; + ucsearch_state = 4; + break; + } + } + else + { + //nothing + } + } + #else //only 0.5T data + { + if (ucsearch_state == 0) + { + //record initial value at the beginning + fginitial_value = fgcurrent_value; + ucsearch_state = 1; + } + else if (ucsearch_state == 1) + { + // check if change value + if (fgcurrent_value != fginitial_value) + { + // start of the period + fginitial_value = fgcurrent_value; + ucstart_period = ucdqs_dly; + ucsearch_state = 2; + } + } + else if (ucsearch_state == 2) + { + // check if change value + if (fgcurrent_value != fginitial_value) + { + // end of the period, break the loop + ucend_period = ucdqs_dly; + ucsearch_state = 4; + break; + } + } + } + #endif + } + + if ((ucsearch_state == 4) || (ucsearch_state == 3)) + break; + } + + //restore to orignal value + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + if (ucsearch_state != 4) + { + if (ucsearch_state != 3) + { + mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter - ch=%d\n", p->channel)); + mcSHOW_DBG_MSG(("\tLess than 0.5T data. Cannot calculate delay cell time\n\n")); + + u2g_num_dlycell_perT = 0; //for LP3 and LP4 lookup table used + + return DRAM_FAIL; + } + else + { + //Calculate 1 delay cell = ? ps + // 1T = ? delay cell + u2g_num_dlycell_perT = (ucmiddle_period - ucstart_period) * 2; + // 1T = ? ps + } + } + else + { + //Calculate 1 delay cell = ? ps + // 1T = ? delay cell + u2g_num_dlycell_perT = (ucend_period - ucstart_period); + // 1T = ? ps + } + + u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP); + u4PLL5_ADDR = DDRPHY_REG_SHU_PHYPLL1 + DDRPHY_AO_SHU_OFFSET * u1ShuLevel; + u4PLL8_ADDR = DDRPHY_REG_SHU_PHYPLL2 + DDRPHY_AO_SHU_OFFSET * u1ShuLevel; + u4PLL3_ADDR = DDRPHY_REG_SHU_PHYPLL3 + DDRPHY_AO_SHU_OFFSET * u1ShuLevel; + u4B0_DQ = DDRPHY_REG_SHU_B0_DQ1 + DDRPHY_AO_SHU_OFFSET * u1ShuLevel; + u4SDM_PCW = u4IO32ReadFldAlign(u4PLL5_ADDR, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW); + u4PREDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_PREDIV); + u4POSDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_POSDIV); + u4CKDIV4 = u4IO32ReadFldAlign(u4B0_DQ, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0); + u1FBKSEL = u4IO32ReadFldAlign(u4PLL3_ADDR, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL); + u4VCOFreq = (((52 >> u4PREDIV) * (u4SDM_PCW >> 8)) >> u4POSDIV) << u1FBKSEL; + u4DataRate = u4VCOFreq >> u4CKDIV4; + u2real_freq = u4DataRate >> 1; + u2real_period = (U16) (1000000 / u2real_freq); + + //calculate delay cell time + u2gdelay_cell_ps = u2real_period * 100 / u2g_num_dlycell_perT; + + if (ucsearch_state == 4) + { // 1T + mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n" + "1T = (%d-%d) = %d dly cells\n" + "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n", + p->channel, + ucend_period, ucstart_period, u2g_num_dlycell_perT, + u2real_freq, u2real_period, u2gdelay_cell_ps)); + } + else + { // 0.5T + mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n" + "1T = (%d-%d)*2 = %d dly cells\n" + "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n", + p->channel, + ucmiddle_period, ucstart_period, u2g_num_dlycell_perT, + u2real_freq, u2real_period, u2gdelay_cell_ps)); + } + + return DRAM_OK; + +// log example +/* dly: sample_cnt DQS0_cnt DQS1_cnt + 0 : 10962054, 0, 0 + 1 : 10958229, 0, 0 + 2 : 10961109, 0, 0 + 3 : 10946916, 0, 0 + 4 : 10955421, 0, 0 + 5 : 10967274, 0, 0 + 6 : 10893582, 0, 0 + 7 : 10974762, 0, 0 + 8 : 10990278, 0, 0 + 9 : 10972026, 0, 0 + 10 : 7421004, 0, 0 + 11 : 10943883, 0, 0 + 12 : 10984275, 0, 0 + 13 : 10955268, 0, 0 + 14 : 10960326, 0, 0 + 15 : 10952451, 0, 0 + 16 : 10956906, 0, 0 + 17 : 10960803, 0, 0 + 18 : 10944108, 0, 0 + 19 : 10959939, 0, 0 + 20 : 10959246, 0, 0 + 21 : 11002212, 0, 0 + 22 : 10919700, 0, 0 + 23 : 10977489, 0, 0 + 24 : 11009853, 0, 0 + 25 : 10991133, 0, 0 + 26 : 10990431, 0, 0 + 27 : 10970703, 11161, 0 + 28 : 10970775, 257118, 0 + 29 : 10934442, 9450467, 0 + 30 : 10970622, 10968475, 0 + 31 : 10968831, 10968831, 0 + 32 : 10956123, 10956123, 0 + 33 : 10950273, 10950273, 0 + 34 : 10975770, 10975770, 0 + 35 : 10983024, 10983024, 0 + 36 : 10981701, 10981701, 0 + 37 : 10936782, 10936782, 0 + 38 : 10889523, 10889523, 0 + 39 : 10985913, 10985913, 55562 + 40 : 10970235, 10970235, 272294 + 41 : 10996056, 10996056, 9322868 + 42 : 10972350, 10972350, 10969738 + 43 : 10963917, 10963917, 10963917 + 44 : 10967895, 10967895, 10967895 + 45 : 10961739, 10961739, 10961739 + 46 : 10937097, 10937097, 10937097 + 47 : 10937952, 10937952, 10937952 + 48 : 10926018, 10926018, 10926018 + 49 : 10943793, 10943793, 10943793 + 50 : 10954638, 10954638, 10954638 + 51 : 10968048, 10968048, 10968048 + 52 : 10944036, 10944036, 10944036 + 53 : 11012112, 11012112, 11012112 + 54 : 10969137, 10969137, 10969137 + 55 : 10968516, 10968516, 10968516 + 56 : 10952532, 10952532, 10952532 + 57 : 10985832, 10985832, 10985832 + 58 : 11002527, 11002527, 11002527 + 59 : 10950660, 10873571, 10950660 + 60 : 10949022, 10781797, 10949022 + 61 : 10974366, 10700617, 10974366 + 62 : 10972422, 1331974, 10972422 + 63 : 10926567, 0, 10926567 + 64 : 10961658, 0, 10961658 + 65 : 10978893, 0, 10978893 + 66 : 10962828, 0, 10962828 + 67 : 10957599, 0, 10957599 + 68 : 10969227, 0, 10969227 + 69 : 10960722, 0, 10960722 + 70 : 10970937, 0, 10963180 + 71 : 10962054, 0, 10711639 + 72 : 10954719, 0, 10612707 + 73 : 10958778, 0, 479589 + 74 : 10973898, 0, 0 + 75 : 11004156, 0, 0 + 76 : 10944261, 0, 0 + 77 : 10955340, 0, 0 + 78 : 10998153, 0, 0 + 79 : 10998774, 0, 0 + 80 : 10953234, 0, 0 + 81 : 10960020, 0, 0 + 82 : 10923831, 0, 0 + 83 : 10951362, 0, 0 + 84 : 10965249, 0, 0 + 85 : 10949103, 0, 0 + 86 : 10948707, 0, 0 + 87 : 10941147, 0, 0 + 88 : 10966572, 0, 0 + 89 : 10971333, 0, 0 + 90 : 10943721, 0, 0 + 91 : 10949337, 0, 0 + 92 : 10965942, 0, 0 + 93 : 10970397, 0, 0 + 94 : 10956429, 0, 0 + 95 : 10939896, 0, 0 + 96 : 10967112, 0, 0 + 97 : 10951911, 0, 0 + 98 : 10953702, 0, 0 + 99 : 10971090, 0, 0 + 100 : 10939590, 0, 0 + 101 : 10993392, 0, 0 + 102 : 10975932, 0, 0 + 103 : 10949499, 40748, 0 + 104 : 10962522, 258638, 0 + 105 : 10951524, 275292, 0 + 106 : 10982475, 417642, 0 + 107 : 10966887, 10564347, 0 + =============================================================================== + MIOCK jitter meter - channel=0 + =============================================================================== + 1T = (107-29) = 78 delay cells + Clock frequency = 936 MHz, Clock period = 1068 ps, 1 delay cell = 13 ps +*/ +} + +/* "picoseconds per delay cell" depends on Vcore only (frequency doesn't matter) + * 1. Retrieve current freq's vcore voltage using pmic API + * 2. Perform delay cell time calculation (Bypass if shuffle vcore value is the same as before) + */ +static void GetVcoreDelayCellTime(DRAMC_CTX_T *p, U8 shuffleIdx) +{ + U32 channel_i; + +#if __ETT__ +#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) + u4gVcore[shuffleIdx] = pmic_vcore_voltage_read(); +#endif + + /* delay cell calculation is skipped if vcore is same as previous shuffle's */ + if (u4gVcore[shuffleIdx] != u4previousVcore) + { + u4previousVcore = u4gVcore[shuffleIdx]; + DramcMiockJmeter(p); + } +#else + DramcMiockJmeter(p); +#endif + + for(channel_i=CHANNEL_A; channel_i < p->support_channel_num; channel_i++) + { + u2g_num_dlycell_perT_all[shuffleIdx][channel_i] = u2g_num_dlycell_perT; + u2gdelay_cell_ps_all[shuffleIdx][channel_i] = u2gdelay_cell_ps; + } +#if __ETT__ + mcSHOW_DBG_MSG(("Freq=%d, CH_%d, VCORE=%d, cell=%d\n", p->frequency, p->channel, u4gVcore[shuffleIdx], u2gdelay_cell_ps_all[shuffleIdx][p->channel])); +#endif + + return; +} + +void DramcMiockJmeterHQA(DRAMC_CTX_T *p) +{ + //do MiockJitterMeter@DDR2667 + U8 shuffleIdx; + + mcSHOW_DBG_MSG(("[MiockJmeterHQA]\n")); + + shuffleIdx = get_shuffleIndex_by_Freq(p); + + if(p->channel == CHANNEL_A) + { + if (p->frequency <= 600) + { + u2g_num_dlycell_perT_all[shuffleIdx][p->channel] = 0; // always lookup table + u2gdelay_cell_ps_all[shuffleIdx][p->channel] = 270; // @Darren, Wait arnold for lookup table + } + else + GetVcoreDelayCellTime(p, shuffleIdx); + } + + u2gdelay_cell_ps_all[shuffleIdx][CHANNEL_B] = u2gdelay_cell_ps_all[shuffleIdx][CHANNEL_A]; + +#ifdef FOR_HQA_TEST_USED + if (u2g_num_dlycell_perT_all[shuffleIdx][p->channel] == 0) GetVcoreDelayCellTimeFromTable(p); //lookup table +#endif + + /* Use highest freq's delay cell time measurement results as reference */ + p->u2num_dlycell_perT = u2g_num_dlycell_perT_all[shuffleIdx][p->channel]; + p->u2DelayCellTimex100 = u2gdelay_cell_ps_all[shuffleIdx][p->channel]; + mcSHOW_DBG_MSG3(("DelayCellTimex100 CH_%d, (VCORE=%d, cell=%d)\n",p->channel, u4gVcore[shuffleIdx], p->u2DelayCellTimex100)); +} +#endif + +//------------------------------------------------------------------------- +/** Dramc8PhaseCal + * start 8-Phase Calibration. + * @param p Pointer of context created by DramcCtxCreate. + * @param block_no (U8): block 0 or 1. + * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL + */ +//------------------------------------------------------------------------- + +DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) +{ +#if ENABLE_8PHASE_CALIBRATION + U8 u1DqsLevel = 0xff, u18Ph_dly_loop_break = 0; + U8 u1DqsienPI = 0; + U8 u18Phase_SM = DQS_8PH_DEGREE_0, u18Ph_dly = 0, u18Ph_start = 0, u18Ph_end = 0, u18Ph_dly_final = 0xff; + U16 u2R0 = 0xffff, u2R180 = 0xffff, u2R = 0xffff; + U16 u2P = 0xffff, ucdqs_dly = 0; + S16 s2Err_code = 0x7fff, s2Err_code_min = 0x7fff; + U16 u2Jm_dly_start = 0, u2Jm_dly_end = 512, u2Jm_dly_step = 1; + U32 u4sample_cnt, u4ones_cnt[DQS_NUMBER]; + U8 backup_rank, u1RankIdx, u18PhDlyBackup = 0; + U8 u1loop_cnt = 0, u1early_break_cnt = 5; + U32 u4backup_broadcast= GetDramcBroadcast(); + DRAM_STATUS_T eDRAMStatus = DRAM_OK; + +#ifdef DUMP_INIT_RG_LOG_TO_DE //for FT dump 3733 dram_init.c + return DRAM_OK; +#endif + + u1DqsienPI = 0x0; + + // error handling + if (!p) + { + mcSHOW_ERR_MSG(("context NULL\n")); + return DRAM_FAIL; + } + + if (p->frequency < 1866) + { + //mcSHOW_ERR_MSG(("skip 8-Phase Calib Freq is %d < 1866 !!!\n", p->frequency)); + return DRAM_OK; + } + + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4)), + (DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY)), // need porting to Jmeter + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY + DDRPHY_AO_RANK_OFFSET)), // need porting to Jmeter + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER)), + //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), // for gating on/off backup/restore + //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)), // for gating on/off backup/restore + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL)), // for gating on/off backup/restore +#if 0 + (DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0)), + (DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0)), + (DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)), +#endif + ((DDRPHY_REG_SHU_CA_DLL1)), + ((DDRPHY_REG_SHU_B0_DLL1)), + ((DDRPHY_REG_SHU_B1_DLL1)), + ((DDRPHY_REG_B0_DQ2)), + ((DDRPHY_REG_B1_DQ2)), + ((DDRPHY_REG_CA_CMD2)), + ((DDRPHY_REG_SHU_B0_DQ13)), + ((DDRPHY_REG_SHU_B1_DQ13)), + ((DDRPHY_REG_SHU_CA_CMD13)), + + ((DDRPHY_REG_SHU_CA_DLL1) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_B0_DLL1) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_B1_DLL1) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_B0_DQ2) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_B1_DQ2) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_CA_CMD2) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_B0_DQ13) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_B1_DQ13) + SHIFT_TO_CHB_ADDR), + ((DDRPHY_REG_SHU_CA_CMD13) + SHIFT_TO_CHB_ADDR), +#if (CHANNEL_NUM > 2) + ((DDRPHY_REG_SHU_CA_DLL1) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_B0_DLL1) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_B1_DLL1) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_B0_DQ2) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_B1_DQ2) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_CA_CMD2) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_B0_DQ13) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_B1_DQ13) + SHIFT_TO_CHC_ADDR), + ((DDRPHY_REG_SHU_CA_CMD13) + SHIFT_TO_CHC_ADDR), + + ((DDRPHY_REG_SHU_CA_DLL1) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_B0_DLL1) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_B1_DLL1) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_B0_DQ2) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_B1_DQ2) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_CA_CMD2) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_B0_DQ13) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_B1_DQ13) + SHIFT_TO_CHD_ADDR), + ((DDRPHY_REG_SHU_CA_CMD13) + SHIFT_TO_CHD_ADDR), +#endif + }; + + backup_rank = u1GetRank(p); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + //backup register value + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + //OE disable - start + vIO32WriteFldMulti_All(DDRPHY_REG_B0_DQ2, P_Fld( 0 , B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0 ) \ + | P_Fld( 0 , B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0 ) \ + | P_Fld( 0 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0 ) \ + | P_Fld( 0 , B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0 ) \ + | P_Fld( 0 , B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0 ) \ + | P_Fld( 0xff , B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0 ) ); + + vIO32WriteFldMulti_All(DDRPHY_REG_B1_DQ2, P_Fld( 0 , B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1 ) \ + | P_Fld( 0 , B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1 ) \ + | P_Fld( 0 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1 ) \ + | P_Fld( 0 , B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1 ) \ + | P_Fld( 0 , B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1 ) \ + | P_Fld( 0xff , B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1 ) ); + + vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld( 0 , CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA ) \ + | P_Fld( 1 , CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA ) \ + | P_Fld( 0 , CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA ) \ + | P_Fld( 1 , CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA ) \ + | P_Fld( 0 , CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA ) \ + | P_Fld( 0xff , CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA ) ); + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ13 , P_Fld( 0 , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0 ) \ + | P_Fld( 1 , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0 )); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ13 , P_Fld( 0 , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \ + | P_Fld( 1 , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1 )); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD13, P_Fld( 0 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \ + | P_Fld( 1 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA )); + //OE disable - end + + u18PhDlyBackup = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1), SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); + + //DramcHWGatingOnOff(p, 0); // disable Gating tracking for DQS PI, Remove to vApplyConfigBeforeCalibration + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) + | P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN)); + +#if 0 // 8-Phase calib must to do before DLL init for test only + //@A60868, Reset PI code to avoid 8-phase offset + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0), 0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0), 0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0), 0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); + mcDELAY_US(1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0), 1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0), 1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0), 1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); + //@A60868, End + + // @A60868, DQSIEN PI offset clear to 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6), 0, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6), 0, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6), 0, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA); +#endif + + // @A60868 for *RANK_SEL_SER_EN* = 0 to DA_RX_ARDQ_RANK_SEL_TXD_*[0] + // for *RANK_SEL_SER_EN* = 1 to DA_RX_ARDQ_RANK_SEL_TXD_*[7:0] + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), 0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA); + + //@Darren, DLL off to stable fix middle transion from high to low or low to high at high vcore + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_DLL1, P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) + | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DLL1, P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) + | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0)); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DLL1, P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) + | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1)); + + //MCK4X CG + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMDQSIENCG_EN); + //@A60868, DQS PI mode for JMTR + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), 0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0); // DQS PI mode + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), 0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1); // DQS PI mode + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN); // enable toggle cnt + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), 0, MISC_CTRL4_R_OPT2_CG_DQSIEN); // Remove to Golden settings for Jmeter clock + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); // for DQS*_ERR_CNT + //@A60868, End + + // Bypass DQS glitch-free mode + // RG_RX_*RDQ_EYE_DLY_DQS_BYPASS_B** + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 1, B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), 1, B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1); + + //Enable DQ eye scan + //RG_*_RX_EYE_SCAN_EN + //RG_*_RX_VREF_EN + //RG_*_RX_SMT_EN + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN) + | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN) + | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); + //@A60868, JMTR en + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_EN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER), 1, MISC_JMETER_JMTR_EN); + //@A60868, End + + //@A60868, JM_SEL = 1, JM_SEL = 0 for LPBK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1); + + //Enable MIOCK jitter meter mode ( RG_RX_MIOCK_JIT_EN=1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN); + + //Disable DQ eye scan (b'1), for counter clear + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_DQSERRCNT_DIS); + + for (u18Phase_SM = DQS_8PH_DEGREE_0; u18Phase_SM < DQS_8PH_DEGREE_MAX; u18Phase_SM++) + { + switch (u18Phase_SM) + { + case DQS_8PH_DEGREE_0: + u1DqsienPI = 16; + u18Ph_start = 0; + u18Ph_end = 1; + break; + case DQS_8PH_DEGREE_180: + u1DqsienPI = 48; + u18Ph_start = 0; + u18Ph_end = 1; + break; + case DQS_8PH_DEGREE_45: + u1DqsienPI = 24; + u18Ph_start = 0; + u18Ph_end = 32; + break; + default: + mcSHOW_ERR_MSG(("u18Phase_SM err!\n")); + #if __ETT__ + while (1); + #endif + } + + mcSHOW_DBG_MSG(("\n[Dramc8PhaseCal] 8-Phase SM_%d, 8PH_dly (%d~%d), DQSIEN PI = %d, 8PH_Dly = %d\n", u18Phase_SM, u18Ph_start, u18Ph_end, u1DqsienPI, u18PhDlyBackup)); + + //to see 1T(H,L) or 1T(L,H) from delaycell=0 to 127 + //NOTE: Must set dual ranks for Rx path + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + // SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0[6] no use (ignore) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1DqsienPI, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); // for rank*_B0 + } + vSetRank(p, backup_rank); + + for (u18Ph_dly = u18Ph_start; u18Ph_dly < u18Ph_end; u18Ph_dly++) + { + mcSHOW_DBG_MSG(("8PH dly = %d\n", u18Ph_dly)); + + u1DqsLevel = 0xff; + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1), u18Ph_dly, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1), u18Ph_dly, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1), u18Ph_dly, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA); + + for (ucdqs_dly = u2Jm_dly_start; ucdqs_dly < u2Jm_dly_end; ucdqs_dly += u2Jm_dly_step) + { + //Set DQS delay (RG_*_RX_DQS_EYE_DLY) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), ucdqs_dly, B0_PHY2_RG_RX_ARDQS_JM_DLY_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), ucdqs_dly, B1_PHY2_RG_RX_ARDQS_JM_DLY_B1); + DramPhyReset(p); + + //Reset eye scan counters (reg_sw_rst): 1 to 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_REG_SW_RST); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_REG_SW_RST); + + //Enable DQ eye scan (b'1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); + + //2ns/sample, here we delay 1ms about 500 samples + mcDELAY_US(10); + + //Disable DQ eye scan (b'1), for counter latch + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); + + //Read the counter values from registers (toggle_cnt*, dqs_err_cnt*); + u4sample_cnt = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_TOGGLE_CNT), MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT); + u4ones_cnt[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT), MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT); + //u4ones_cnt[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT), MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT); + //u4ones_cnt[2] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT), MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT); + //u4ones_cnt[3] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT), MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT); + //Darren-mcSHOW_DBG_MSG(("%3d : %8d, %8d, %8d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0], u4ones_cnt[1])); + + //change to boolean value + if (u4ones_cnt[0] < (u4sample_cnt / 2)) + { + if (u1DqsLevel == 0xff) // print once + { + mcSHOW_DBG_MSG(("[L] %d, %8d\n", ucdqs_dly, u4ones_cnt[0])); + //mcSHOW_DBG_MSG(("[L] %d, %8d, %8d\n", ucdqs_dly, u4ones_cnt[0], u4ones_cnt[1])); + } + + u1DqsLevel = 0; + } + else + { + if (u1DqsLevel == 0) // from low to high + { + u1DqsLevel = 1; + mcSHOW_DBG_MSG(("[H] %d, %8d\n", ucdqs_dly, u4ones_cnt[0])); + //mcSHOW_DBG_MSG(("[H] %d, %8d, %8d\n", ucdqs_dly, u4ones_cnt[0], u4ones_cnt[1])); + + if (u18Phase_SM == DQS_8PH_DEGREE_0) + { + u2R0 = ucdqs_dly; + mcSHOW_DBG_MSG(("R0 = %d\n", u2R0)); + break; // break ucdqs_dly for loop + } + else if (u18Phase_SM == DQS_8PH_DEGREE_180) + { + u2R180 = ucdqs_dly; + if (u2R180 > u2R0) + { + u2R = u2R0 + ((u2R180 - u2R0) >> 2); // u2R180 >= u2R0 for (u1R180 - u1R0)/4 for 180 degree. /2 for 90 degree + mcSHOW_DBG_MSG(("R = %d, R180 = %d\n", u2R, u2R180)); + break; // break ucdqs_dly for loop + } + else + { + u1DqsLevel = 0xff; //next u2Jm_dly to find edge (L->H) + } + } + else if (u18Phase_SM == DQS_8PH_DEGREE_45) + { + u2P = ucdqs_dly; + if (u2P > u2R0) // u2P ~= DQS_8PH_DEGREE_180 + { + // Absolute to find min diff + if (u2R > u2P) + s2Err_code = u2R - u2P; + else + s2Err_code = u2P - u2R; + + if (s2Err_code == 0) + { + u18Ph_dly_final = u18Ph_dly; + u18Ph_dly_loop_break = 1; + } + else if (s2Err_code < s2Err_code_min) + { + s2Err_code_min = s2Err_code; + u18Ph_dly_final = u18Ph_dly; + u1loop_cnt = 0; + } + else if (s2Err_code >= s2Err_code_min) + { + // check early break for u18Ph_dly for loop + u1loop_cnt++; + if (u1loop_cnt > u1early_break_cnt) + { + u18Ph_dly_loop_break = 1; + } + } + + mcSHOW_DBG_MSG(("diff (P-R) = %d, min = %d, break count = %d\n", s2Err_code, s2Err_code_min, u1loop_cnt)); + + break; // if (s2Err_code == s2Err_code_min) for next u18Ph_dly + } + else + { + u1DqsLevel = 0xff; //next u2Jm_dly to find edge (L->H) + } + } + else + { + mcSHOW_ERR_MSG(("u18Phase_SM err!\n")); + #if __ETT__ + while (1); + #endif + } + } + } + + } + + // Error handing + if ((u1DqsLevel == 0xff) || (u1DqsLevel == 0)) + { + // (u1DqsLevel == 0) => skip from 1 to all's 0 or all's 0 + // (u1DqsLevel == 0xff) => skip all's 1 + // NOTE: 8-Phase calib must from 0 to 1 + u18Ph_dly_final = u18PhDlyBackup; //rollback to init settings + eDRAMStatus = DRAM_FAIL; + mcSHOW_ERR_MSG(("\n[Dramc8PhaseCal] 8-Phase SM_%d is fail (to Default)!!!\n", u18Phase_SM)); + goto exit; + } else if (u18Ph_dly_loop_break == 1) + break; + + } + } + +exit: + mcSHOW_DBG_MSG(("\n[Dramc8PhaseCal] u18Ph_dly_final = %d\n\n", u18Ph_dly_final)); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ1, u18Ph_dly_final, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ1, u18Ph_dly_final, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD1, u18Ph_dly_final, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA); + + //restore to orignal value + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + DramcBroadcastOnOff(u4backup_broadcast); + + return eDRAMStatus; +#endif +} + +#if SIMULATION_SW_IMPED +void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where) +{ + U32 backup_broadcast; + + backup_broadcast = GetDramcBroadcast(); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + //DQ + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQDRVP2) | P_Fld(gDramcSwImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQDRVN2)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING2_DQDRVP1) | P_Fld(gDramcSwImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING2_DQDRVN1)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQODTP2) | P_Fld(gDramcSwImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQODTN2)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING4_DQODTP1) | P_Fld(gDramcSwImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING4_DQODTN1)); + + //DQS + #if SUPPORT_HYNIX_RX_DQS_WEAK_PULL + if (p->vendor_id == VENDOR_HYNIX) + { U32 temp_value[4]; + int i; + for(i=0; i<4; i++) + { + temp_value[i] = SwImpedanceAdjust(gDramcSwImpedanceResult[dq_freq_option][i], 2); + } + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[0], SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(temp_value[1], SHU_MISC_DRVING1_DQSDRVN2)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[0], SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(temp_value[1], SHU_MISC_DRVING1_DQSDRVN1)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[2], SHU_MISC_DRVING3_DQSODTP2) | P_Fld(temp_value[3], SHU_MISC_DRVING3_DQSODTN2)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[2], SHU_MISC_DRVING3_DQSODTP) | P_Fld(temp_value[3], SHU_MISC_DRVING3_DQSODTN)); + } + else + #endif + { + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(gDramcSwImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQSDRVN2)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(gDramcSwImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQSDRVN1)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQSODTP2) | P_Fld(gDramcSwImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQSODTN2)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQSODTP) | P_Fld(gDramcSwImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQSODTN)); + } + + //CMD & CLK + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[ca_freq_option][DRVP], SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(gDramcSwImpedanceResult[ca_freq_option][DRVN], SHU_MISC_DRVING2_CMDDRVN2)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[ca_freq_option][DRVP], SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(gDramcSwImpedanceResult[ca_freq_option][DRVN], SHU_MISC_DRVING2_CMDDRVN1)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[ca_freq_option][ODTP], SHU_MISC_DRVING4_CMDODTP2) | P_Fld(gDramcSwImpedanceResult[ca_freq_option][ODTN], SHU_MISC_DRVING4_CMDODTN2)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcSwImpedanceResult[ca_freq_option][ODTP], SHU_MISC_DRVING4_CMDODTP1) | P_Fld(gDramcSwImpedanceResult[ca_freq_option][ODTN], SHU_MISC_DRVING4_CMDODTN1)); + + //RG_TX_*RCKE_DRVP/RG_TX_*RCKE_DRVN doesn't set, so set 0xA first + //@Maoauo confirm, RG no function + //vIO32WriteFldAlign((DDRPHY_SHU_CA_CMD11 + save_to_where * SHU_GRP_DDRPHY_OFFSET), gDramcSwImpedanceResult[ca_freq_option][DRVP], SHU_CA_CMD11_RG_TX_ARCKE_DRVP); + //vIO32WriteFldAlign((DDRPHY_SHU_CA_CMD11 + save_to_where * SHU_GRP_DDRPHY_OFFSET), gDramcSwImpedanceResult[ca_freq_option][DRVN], SHU_CA_CMD11_RG_TX_ARCKE_DRVN); + + //CKE + // CKE is full swing. + // LP4/LP4X set DRVP/DRVN as LP3's default value + // DRVP=8 -> 0xA for 868 by Alucary Chen + // DRVN=9 -> 0xA for 868 by Alucary Chen + //DRVP[4:0] = RG_TX_ARCMD_PU_PRE<1:0>, RG_TX_ARCLK_DRVN_PRE<2:0> for La_fite only + //@Darren-vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), (8>>3)&0x3, SHU_CA_CMD3_RG_TX_ARCMD_PU_PRE); //Darren need confirm + //@Darren-vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD0 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 8&0x7, SHU_CA_CMD0_RG_TX_ARCLK_DRVN_PRE); //Darren need confirm + //DRVN[4:0] = RG_ARCMD_REV<12:8> + //@Darren-vIO32WriteFldAlign_All((DDRPHY_SHU_CA_DLL2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 9, SHU_CA_DLL2_RG_TX_ARCKE_DRVN_B0); + #if (fcFOR_CHIP_ID == fcA60868) // for 868 CS and CKE control together + vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xA, MISC_SHU_DRVING8_CS_DRVP); + vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xA, MISC_SHU_DRVING8_CS_DRVN); + #elif (fcFOR_CHIP_ID == fcMargaux) + // @Darren, confirm with ACD Alucary, + // MISC_SHU_DRVING8_CS_DRVP & MISC_SHU_DRVING8_CS_DRVN -> DA_TX_ARCKE_DRVP_C0[4:0] & DA_TX_ARCKE_DRVN_C0[4:0] + vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xF, MISC_SHU_DRVING8_CS_DRVP); + vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0x14, MISC_SHU_DRVING8_CS_DRVN); + #endif + + DramcBroadcastOnOff(backup_broadcast); +} + +//------------------------------------------------------------------------- +/** vImpCalVrefSel + * Set IMP_VREF_SEL for DRVP, DRVN, Run-time/Tracking + * (Refer to "IMPCAL Settings" document register "RG_RIMP_VREF_SEL" settings) + * @param p Pointer of context created by DramcCtxCreate. + * @param freq_region (enum): pass freq_region (IMP_LOW_FREQ/IMP_HIGH_FREQ) for LP4X + * @param u1ImpCalStage (U8): During DRVP, DRVN, run-time/tracking stages + * some vref_sel values are different + */ +//------------------------------------------------------------------------- +/* Definitions to make IMPCAL_VREF_SEL function more readable */ +#define IMPCAL_STAGE_DRVP 0 +#define IMPCAL_STAGE_DRVN 1 +#define IMPCAL_STAGE_ODTP 2 +#define IMPCAL_STAGE_ODTN 3 +#define IMPCAL_STAGE_TRACKING 4 + +/* LP4X IMP_VREF_SEL w/o term ==== */ +#define IMP_TRACK_LP4X_LOWFREQ_VREF_SEL 0x37 // for <= DDR3733 +#define IMP_TRACK_LP4X_HIGHFREQ_VREF_SEL 0x3a // for > 3733 and Samsung NT-ODTN +/* LPDDR5 IMP_VREF_SEL w/o term ==== */ +#define IMP_TRACK_LP5_LOWFREQ_VREF_SEL 0x38 // for <= DDR3733 +#define IMP_TRACK_LP5_HIGHFREQ_VREF_SEL 0x3a // for > 3733 and Samsung NT-ODTN + +static const U8 ImpLP4VrefSel[IMP_VREF_MAX][IMP_DRV_MAX] = { + /* DRVP DRVN ODTP ODTN */ +/* IMP_LOW_FREQ */ {0x37, 0x33, 0x00, 0x37}, +/* IMP_HIGH_FREQ */ {0x3a, 0x33, 0x00, 0x3a}, +/* IMP_NT_ODTN */ {0x2a, 0x2a, 0x00, 0x3a} +}; + +static const U8 ImpLP5VrefSel[IMP_VREF_MAX][IMP_DRV_MAX] = { + /* DRVP DRVN ODTP ODTN */ +/* IMP_LOW_FREQ */ {0x38, 0x33, 0x00, 0x38}, +/* IMP_HIGH_FREQ */ {0x3a, 0x33, 0x00, 0x3a}, +/* IMP_NT_ODTN */ {0x2a, 0x2a, 0x00, 0x3a} +}; + +/* Refer to "IMPCAL Settings" document register "RG_RIMP_VREF_SEL" settings */ +// @Maoauo: DRVP/ODTN for IMP tracking. But DRVN not support IMP tracking. (before La_fite) +// DRVP/DRVN/ODTN for IMP tracking after Pe_trus +static void vImpCalVrefSel(DRAMC_CTX_T *p, DRAMC_IMP_T efreq_region, U8 u1ImpCalStage) +{ + U8 u1RegTmpValue = 0; + U32 u4DrvFld = 0; + + if (p->dram_type == TYPE_LPDDR4X) + { + if (u1ImpCalStage == IMPCAL_STAGE_TRACKING) + u1RegTmpValue = (efreq_region == IMP_LOW_FREQ) ? IMP_TRACK_LP4X_LOWFREQ_VREF_SEL : IMP_TRACK_LP4X_HIGHFREQ_VREF_SEL; + else + u1RegTmpValue = ImpLP4VrefSel[efreq_region][u1ImpCalStage]; + } + else if (p->dram_type == TYPE_LPDDR5) + { + if (u1ImpCalStage == IMPCAL_STAGE_TRACKING) + u1RegTmpValue = (efreq_region == IMP_LOW_FREQ) ? IMP_TRACK_LP5_LOWFREQ_VREF_SEL : IMP_TRACK_LP5_HIGHFREQ_VREF_SEL; + else + u1RegTmpValue = ImpLP5VrefSel[efreq_region][u1ImpCalStage]; + } + else + { + mcSHOW_ERR_MSG(("[vImpCalVrefSel] Warnning: Need confirm DRAM type for IMP_VREF_SEL !!!\n")); + #if __ETT__ + while(1); + #endif + } + + switch (u1ImpCalStage) + { + case IMPCAL_STAGE_DRVP: + u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP; + break; + case IMPCAL_STAGE_DRVN: + u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN; + break; + case IMPCAL_STAGE_ODTN: + u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN; + break; + default: + mcSHOW_ERR_MSG(("[vImpCalVrefSel] Warnning: Need confirm u1ImpCalStage for SW IMP Calibration !!!\n")); + break; + } + + // dbg msg after vref_sel selection + mcSHOW_DBG_MSG3(("[vImpCalVrefSel] IMP_VREF_SEL 0x%x, IMPCAL stage:%u, freq_region:%u\n", + u1RegTmpValue, u1ImpCalStage, efreq_region)); + + /* Set IMP_VREF_SEL register field's value */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, u4DrvFld); + + return; +} + +static U32 DramcSwImpCalResult(DRAMC_CTX_T *p, const char *drvType, U32 u4Fld) +{ + U32 u4ImpxDrv = 0, u4ImpCalResult = 0; + U32 u4CheckImpChange = (u4Fld == SHU_MISC_IMPCAL1_IMPDRVP)? 1: 0; + + for (u4ImpxDrv = 0; u4ImpxDrv < 32; u4ImpxDrv++) + { +#if 0 // for A60868 no need + if (u4ImpxDrv == 16) //0~15, 29~31 + u4ImpxDrv = 29; +#endif + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4ImpxDrv, u4Fld); + mcDELAY_US(1); + u4ImpCalResult = u4IO32ReadFldAlign((DDRPHY_REG_MISC_PHY_RGS_CMD), MISC_PHY_RGS_CMD_RGS_RIMPCALOUT); + mcSHOW_DBG_MSG2(("OCD %s=%d ,CALOUT=%d\n", drvType, u4ImpxDrv, u4ImpCalResult)); + + if (u4ImpCalResult == u4CheckImpChange)//first found + { + mcSHOW_DBG_MSG2(("\nOCD %s calibration OK! %s=%d\n\n", drvType, drvType, u4ImpxDrv)); + break; + } + } + + if (u4ImpxDrv == 32) // Can't find SwImp drv results + { + u4ImpxDrv = 31; + mcSHOW_DBG_MSG2(("\nOCD %s calibration FAIL! %s=%d\n\n", drvType, drvType, u4ImpxDrv)); + } + + return u4ImpxDrv; +} + +DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region) +{ + U32 u4DRVP_Result = 0xff, u4ODTN_Result = 0xff, u4DRVN_Result = 0xff; + //U32 u4BaklReg_DDRPHY_MISC_IMP_CTRL0, u4BaklReg_DDRPHY_MISC_IMP_CTRL1; + U32 u4BaklReg_DRAMC_REG_IMPCAL; + U8 backup_channel; + U32 backup_broadcast; + U8 u1DrvType = 0, u1CALI_ENP = 0, u1CALI_ENN = 0, u1DDR4 = 0; + U32 u4SwImpCalResult = 0, u4DrvFld = 0; + const char *drvStr = "NULL"; + + backup_broadcast = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_FAIL); + + //Suspend: DA_RIMP_DMSUS=1 + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_LP_CTRL, P_Fld(0x0, MISC_LP_CTRL_RG_ARDMSUS_10) | \ + P_Fld(0x0, MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL) | \ + P_Fld(0x0, MISC_LP_CTRL_RG_RIMP_DMSUS_10) | \ + P_Fld(0x0, MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL)); + + //Disable IMP HW Tracking + //Hw Imp tracking disable for all channels Because SwImpCal will be K again when resume from DDR reserved mode + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 0, MISC_IMPCAL_IMPCAL_HW); + + backup_channel = p->channel; + vSetPHY2ChannelMapping(p, CHANNEL_A); + + //Register backup + //u4BaklReg_DDRPHY_MISC_IMP_CTRL0 = u4IO32Read4B((DDRPHY_MISC_IMP_CTRL0)); + //u4BaklReg_DDRPHY_MISC_IMP_CTRL1 = u4IO32Read4B((DDRPHY_MISC_IMP_CTRL1)); + u4BaklReg_DRAMC_REG_IMPCAL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL)); + + //RG_IMPCAL_VREF_SEL (now set in vImpCalVrefSel()) + //RG_IMPCAL_LP3_EN=0, RG_IMPCAL_LP4_EN=1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), 0, MISC_IMP_CTRL1_RG_RIMP_PRE_EN); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), P_Fld(0, MISC_IMPCAL_IMPCAL_CALI_ENN) | P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDP) | \ + P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDN)); //RG_RIMP_BIAS_EN and RG_RIMP_VREF_EN move to IMPPDP and IMPPDN + + if (is_lp5_family(p)) + u1DDR4 = 0; + else //LPDDR4 + u1DDR4 = 1; + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), P_Fld(1, MISC_IMP_CTRL1_RG_IMP_EN) | \ + P_Fld(0, MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL) | \ + P_Fld(1, MISC_IMP_CTRL1_RG_RIMP_VREF_EN) | \ + P_Fld(u1DDR4, MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL)); + mcDELAY_US(1); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), 1, MISC_IMPCAL_IMPCAL_CALI_EN); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), P_Fld(0, SHU_MISC_IMPCAL1_IMPDRVN) | P_Fld(0, SHU_MISC_IMPCAL1_IMPDRVP)); + + + //LP4X: ODTN/DRVN/DRVP calibration start + for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) // Calibration sequence for DRVP, DRVN and ODTN + { + if (u1DrvType == ODTP) // no use, skip ODTP + continue; + + /* Set IMP_VREF_SEL value for DRVP/DRVN and ODTN */ + vImpCalVrefSel(p, freq_region, u1DrvType); + + switch (u1DrvType) + { + case DRVP: + drvStr = "DRVP"; + u1CALI_ENP = 0x1; + u1CALI_ENN = 0x0; + u4DrvFld = SHU_MISC_IMPCAL1_IMPDRVP; + u4DRVP_Result = 0; + break; + case DRVN: + case ODTN: + drvStr = (u1DrvType == DRVN)? "DRVN" : "ODTN"; + u1CALI_ENP = 0x0; + u1CALI_ENN = (u1DrvType == DRVN)? 0x0: 0x1; // 0x1 change to ODTN path + u4DrvFld = SHU_MISC_IMPCAL1_IMPDRVN; + break; + default: + mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm u1DrvType for SW IMP Calibration !!!\n")); + break; + } + + // @A60868 for DRVn/p and ODTn select + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENP, MISC_IMPCAL_IMPCAL_CALI_ENP); //MISC_IMP_CTRL1_RG_IMP_OCD_PUCMP_EN move to CALI_ENP + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENN, MISC_IMPCAL_IMPCAL_CALI_ENN); //MISC_IMP_CTRL1_RG_RIMP_ODT_EN move to CALI_ENN + + mcSHOW_DBG_MSG2(("\n\n\tK %s\n", drvStr)); + + //DRVP=DRVP_FINAL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP); //PUCMP_EN move to CALI_ENP + //RIMP_DRV05 for LP4/5 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), 0, SHU_CA_CMD12_RG_RIMP_DRV05); + + + //If RGS_TX_OCD_IMPCALOUTX=1 + //RG_IMPX_DRVN++; + //Else save RG_IMPX_DRVN value and assign to DRVN + u4SwImpCalResult = DramcSwImpCalResult(p, drvStr, u4DrvFld); + + switch (u1DrvType) + { + case DRVP: + u4DRVP_Result = u4SwImpCalResult; + break; + case DRVN: + u4DRVN_Result = u4SwImpCalResult; + break; + case ODTN: + u4ODTN_Result = u4SwImpCalResult; + break; + default: + mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm u4SwImpCalResult for SW IMP Calibration !!!\n")); + break; + } + } + //Register Restore + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u4BaklReg_DRAMC_REG_IMPCAL); + //vIO32Write4B((DDRPHY_MISC_IMP_CTRL0), u4BaklReg_DDRPHY_MISC_IMP_CTRL0); + //vIO32Write4B((DDRPHY_MISC_IMP_CTRL1), u4BaklReg_DDRPHY_MISC_IMP_CTRL1); + + +/*** default value if K fail + LP3: DRVP=8, DRVN=9 + LP4: DRVP=6, DRVN=9, ODTN=14 + LP4X(UT): DRVP=12, DRVN=9 + LP4X(T): DRVP=5, DRVN=9, ODTN=14 + LP4P: DRVP=8, DRVN=10 +***/ + mcSHOW_DBG_MSG(("[SwImpedanceCal] DRVP=%d, DRVN=%d, ODTN=%d\n", u4DRVP_Result, u4DRVN_Result, u4ODTN_Result)); + + #if 0//HYNIX_IMPX_ADJUST + if (u1Para) + { + u4ODTN_Result = ImpedanceAdjustment_Hynix(u4ODTN_Result, u1Para); + } + #endif + + gDramcSwImpedanceResult[freq_region][DRVP] = u4DRVP_Result; + gDramcSwImpedanceResult[freq_region][DRVN] = u4DRVN_Result; + gDramcSwImpedanceResult[freq_region][ODTP] = 0; + gDramcSwImpedanceResult[freq_region][ODTN] = u4ODTN_Result; + +#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION + { + U8 u1drv; + { + for (u1drv = 0; u1drv < 4; u1drv++) + { + if (p->femmc_Ready == 0) + p->pSavetimeData->u1SwImpedanceResule[freq_region][u1drv] = gDramcSwImpedanceResult[freq_region][u1drv]; + else + { + gDramcSwImpedanceResult[freq_region][u1drv] = p->pSavetimeData->u1SwImpedanceResule[freq_region][u1drv]; + vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_FAST_K); + } + } + } + } +#endif + + mcSHOW_DBG_MSG(("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP], + gDramcSwImpedanceResult[freq_region][DRVN], gDramcSwImpedanceResult[freq_region][ODTN])); + +#if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST + if ((p->dram_type == TYPE_LPDDR4) && (freq_region == 0)) + { + gDramcSwImpedanceResult[freq_region][DRVP] = SwImpedanceAdjust(gDramcSwImpedanceResult[freq_region][DRVP], gDramcSwImpedanceAdjust[freq_region][DRVP]); + gDramcSwImpedanceResult[freq_region][DRVN] = SwImpedanceAdjust(gDramcSwImpedanceResult[freq_region][DRVN], gDramcSwImpedanceAdjust[freq_region][ODTN]); + } + else + { + gDramcSwImpedanceResult[freq_region][DRVP] = SwImpedanceAdjust(gDramcSwImpedanceResult[freq_region][DRVP], gDramcSwImpedanceAdjust[freq_region][DRVP]); + gDramcSwImpedanceResult[freq_region][ODTN] = SwImpedanceAdjust(gDramcSwImpedanceResult[freq_region][ODTN], gDramcSwImpedanceAdjust[freq_region][ODTN]); + } + + mcSHOW_DBG_MSG(("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d (After Adjust)\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP], + gDramcSwImpedanceResult[freq_region][DRVN], gDramcSwImpedanceResult[freq_region][ODTN])); +#endif + +#if __FLASH_TOOL_DA__ + if((gDramcSwImpedanceResult[freq_region][ODTN] ==0)||(gDramcSwImpedanceResult[freq_region][ODTN] >=31)) + { + mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, ODTN = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][ODTN])); + PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+ODTN)); + } + else if((gDramcSwImpedanceResult[freq_region][DRVP] ==0)||(gDramcSwImpedanceResult[freq_region][DRVP] >=31)) + { + mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, DRVP = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP])); + PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+DRVP)); + } + else if((gDramcSwImpedanceResult[freq_region][DRVN] ==0)||(gDramcSwImpedanceResult[freq_region][DRVN] >=31)) + { + mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, DRVN = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVN])); + PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+DRVN)); + } + else +#endif + { + vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_OK); + } + mcSHOW_DBG_MSG3(("[DramcSwImpedanceCal] Done\n\n")); + + vSetPHY2ChannelMapping(p, backup_channel); + DramcBroadcastOnOff(backup_broadcast); + + return DRAM_OK; +} +#endif //SIMULATION_SW_IMPED + +#if ENABLE_WRITE_DBI || TX_K_DQM_WITH_WDBI +void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK) +{ + U8 ucDataRateDivShift = 0; + S8 s1UIMove = 0; + + ucDataRateDivShift = u1MCK2UI_DivShift(p); + s1UIMove = iShiftMCK * (S8)(1 << ucDataRateDivShift); + ShiftDQUI(p, s1UIMove, ALL_BYTES); +} +#endif + +#if ENABLE_DUTY_SCAN_V2 + +#define DutyPrintAllLog 0 +#define DutyPrintCalibrationLog 0 + +#define DUTY_OFFSET_START -28 +#define DUTY_OFFSET_END 28 +#define DUTY_OFFSET_STEP 4 + +#define CLOCK_PI_START 0 +#define CLOCK_PI_END 63 + +#if FOR_DV_SIMULATION_USED +#define CLOCK_PI_STEP 8 +#else +#define CLOCK_PI_STEP 2 +#endif + +#define ClockDutyFailLowerBound 4500 // 45% +#define ClockDutyFailUpperBound 5500 // 55% +#define ClockDutyMiddleBound 5000 // 50% + +/* +* duty form smallest to biggest +* 011111->011110->...->000001-->000000=100000->100001-->...->111111 +*/ +static U8 DramcDutyDelayRGSettingConvert(DRAMC_CTX_T *p, S8 scDutyDelay, + U8 *tDly) +{ + U8 tDelay; + + if (scDutyDelay < 0) + { + tDelay = -scDutyDelay; + } + else if (scDutyDelay > 0) + { + tDelay = scDutyDelay + (1 << 5); + } + else + { + tDelay = 0; + } + + *tDly = tDelay; + return tDelay; +} + +static void DramcClockDutySetClkDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay) +{ + U8 u1ShuffleIdx = 0; + U32 save_offset; + U8 tDelay; + + DramcDutyDelayRGSettingConvert(p, scDutyDelay[0], &tDelay); + +#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ + for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) +#endif + { + save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET; + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_TXDUTY + save_offset), + P_Fld(tDelay, SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY)); + } +} + +static void DQSDutyScan_SetDqsDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay) +{ + U8 u1ShuffleIdx = 0, u1DQSIdx; + U32 save_offset; + U8 tDelay[2]; + +// mcSHOW_DBG_MSG(("CH%d, Final DQS0 duty delay cell = %d\n", p->channel, scDutyDelay[0])); +// mcSHOW_DBG_MSG(("CH%d, Final DQS1 duty delay cell = %d\n", p->channel, scDutyDelay[1])); + + for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++) + { + DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx])); + } + +#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ + for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) +#endif + { + { + for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++) + { + save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET; + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset, + P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0)); + } + } + } +} + +static void WCKDutyScan_SetWCKDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay) +{ + U8 u1ShuffleIdx = 0, u1DQSIdx; + U32 save_offset; + U8 tDelay[2]; + + for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++) + { + DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx])); + } + +#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ + for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) +#endif + { + { + for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++) + { + save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET; + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset, + P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0)); + } + } + } +} + +#if APPLY_DQDQM_DUTY_CALIBRATION +static void DQDQMDutyScan_SetDQDQMDelayCell(DRAMC_CTX_T *p, U8 u1ChannelIdx, S8 *scDutyDelay, U8 k_type) +{ + U8 u1ShuffleIdx = 0, u1DQSIdx; + U32 save_offset; + U8 tDelay[2]; + + for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++) + { + DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx])); + } + +#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ + for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) +#endif + { + for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++) + { + save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET; + + if (k_type == DutyScan_Calibration_K_DQ) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset, + P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0)); + } + + if (k_type == DutyScan_Calibration_K_DQM) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset, + P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0)); + } + } + } +} + +#if 0 +void DQDQMDutyScan_CopyDQRG2DQMRG(DRAMC_CTX_T *p) +{ + U8 u1ShuffleIdx = 0, u1DQSIdx, u1RankIdx = 0; + U32 save_offset; + U8 ucDQDQMDelay; + U8 ucRev_DQDQM_Bit0, ucRev_DQDQM_Bit1; + +#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ + for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) +#endif + { + for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++) + { + save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET_0X80; + + ucDQDQMDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0_DQ_DLY); + ucRev_DQDQM_Bit0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0_BIT0); + ucRev_DQDQM_Bit1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0_BIT0); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, P_Fld(ucDQDQMDelay, SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0_DQM_DLY) + | P_Fld(ucRev_DQDQM_Bit0, SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0_BIT0) + | P_Fld(ucRev_DQDQM_Bit1, SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0_BIT1)); + } + } + } +#endif +#endif + +S8 gcFinal_K_CLK_delay_cell[CHANNEL_NUM][DQS_NUMBER]; +S8 gcFinal_K_DQS_delay_cell[CHANNEL_NUM][DQS_NUMBER]; +S8 gcFinal_K_WCK_delay_cell[CHANNEL_NUM][DQS_NUMBER]; +#if APPLY_DQDQM_DUTY_CALIBRATION +S8 gcFinal_K_DQ_delay_cell[CHANNEL_NUM][DQS_NUMBER]; +S8 gcFinal_K_DQM_delay_cell[CHANNEL_NUM][DQS_NUMBER]; +#endif + +void DramcNewDutyCalibration(DRAMC_CTX_T *p) +{ + U8 u1backup_channel, u1backup_rank; + +#if(DQS_DUTY_SLT_CONDITION_TEST) + U16 u2TestCnt, u2FailCnt=0, u2TestCntTotal =20; //fra 400; + U8 u1ByteIdx, u1PI_FB; + U32 u4Variance; +#endif + + u1backup_rank = u1GetRank(p); + vSetRank(p, RANK_0); + +#if !FT_DSIM_USED +#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ + if((p->frequency == u2DFSGetHighestFreq(p)) && (Get_PRE_MIOCK_JMETER_HQA_USED_flag()==0)) +#else + //TODO if(Get_PRE_MIOCK_JMETER_HQA_USED_flag()==0) +#endif +#endif + { + U8 u1ChannelIdx; + u1backup_channel = vGetPHY2ChannelMapping(p); + + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if(p->femmc_Ready==1) + { + for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]); + DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]); + WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]); + #if APPLY_DQDQM_DUTY_CALIBRATION + DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); + DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); + #endif + } + vSetPHY2ChannelMapping(p, u1backup_channel); + return; + } + #endif + + vSetPHY2ChannelMapping(p, u1backup_channel); + } + + vSetRank(p, u1backup_rank); +} +#endif diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c new file mode 100644 index 0000000000..d0e16d492d --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c @@ -0,0 +1,2682 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include "dramc_top.h" + +#include "dramc_actiming.h" +#include "dramc_common.h" +#include "dramc_dv_init.h" +#include "dramc_int_global.h" +#include <emi.h> +#include "x_hal_io.h" +#include "sv_c_data_traffic.h" +#include "dramc_pi_api.h" +#include <soc/dramc_param.h> +#include <soc/emi.h> + +DRAMC_CTX_T dram_ctx_chb; + +#if (FOR_DV_SIMULATION_USED == 1) +U8 gu1BroadcastIsLP4 = TRUE; +#endif + +bool gAndroid_DVFS_en = TRUE; +bool gUpdateHighestFreq = FALSE; + +#define DV_SIMULATION_BYTEMODE 0 +#define DV_SIMULATION_LP5_TRAINING_MODE1 1 +#define DV_SIMULATION_LP5_CBT_PHASH_R 1 + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + SAVE_TIME_FOR_CALIBRATION_T SavetimeData; +#endif + +U8 gHQA_Test_Freq_Vcore_Level = 0; // 0: only 1 freq , others are multi freq 1: low vcore 2: high vcore + +#define ENABLE_DRAM_SINGLE_FREQ_SELECT 0xFF // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733 + +DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = { + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. + {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. + {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. + {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) +}; + + +DRAMC_CTX_T DramCtx_LPDDR4 = +{ + CHANNEL_SINGLE, // Channel number + CHANNEL_A, // DRAM_CHANNEL + RANK_DUAL, //DRAM_RANK_NUMBER_T + RANK_0, //DRAM_RANK_T + +#ifdef MTK_FIXDDR1600_SUPPORT + LP4_DDR1600, +#else +#if __FLASH_TOOL_DA__ + LP4_DDR1600, +#else +#if (DV_SIMULATION_LP4 == 1) + LP4_DDR1600, +#else + LP5_DDR3200, +#endif +#endif +#endif + DRAM_DFS_SHUFFLE_1, +#if DV_SIMULATION_LP4 + TYPE_LPDDR4X, // DRAM_DRAM_TYPE_T +#else + TYPE_LPDDR5, +#endif + FSP_0 , //// DRAM Fast switch point type, only for LP4, useless in LP3 + ODT_OFF, + {CBT_NORMAL_MODE, CBT_NORMAL_MODE}, // bring up LP4X rank0 & rank1 use normal mode +#if ENABLE_READ_DBI + {DBI_OFF,DBI_ON}, //read DBI +#else + {DBI_OFF,DBI_OFF}, //read DBI +#endif +#if ENABLE_WRITE_DBI + {DBI_OFF,DBI_ON}, // write DBI +#else + {DBI_OFF,DBI_OFF}, // write DBI +#endif + DATA_WIDTH_16BIT, // DRAM_DATA_WIDTH_T + DEFAULT_TEST2_1_CAL, // test2_1; + DEFAULT_TEST2_2_CAL, // test2_2; +#if ENABLE_K_WITH_WORST_SI_UI_SHIFT + TEST_WORST_SI_PATTERN, // test_pattern; +#else + TEST_XTALK_PATTERN, +#endif +#if (DV_SIMULATION_LP4 == 1) + 800, // frequency + 800, // freqGroup +#else + 1600, + 1600, +#endif + 0x88, //vendor_id initial value + REVISION_ID_MAGIC, + 0xff, //density + {0,0}, + 0, // u2num_dlycell_perT; + 270, // u2DelayCellTimex100; + +#if PRINT_CALIBRATION_SUMMARY + //aru4CalResultFlag[CHANNEL_NUM][RANK_MAX] + {{0,}}, + //aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX] + {{0,}}, + 1, + 0, +#endif + {0}, //BOOL arfgWriteLevelingInitShif; +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + FALSE, //femmc_Ready + 0, + 0, + 0, + &SavetimeData, +#endif + &gFreqTbl[DRAM_DFS_SHUFFLE_MAX-1], // default is DDR1600 1:8 mode + DRAM_DFS_REG_SHU0, + TRAINING_MODE2, + CBT_PHASE_RISING, + 0, //new CBT pattern + PHYPLL_MODE, + DBI_OFF, + FSP_MAX, + PINMUX_EMCP, + {DISABLE,DISABLE}, // disable 10GB + 0, +}; + + + +#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION) +DRAMC_CTX_T gTimeProfilingDramCtx; +U8 gtime_profiling_flag = 0; +#endif + +void vSetVcoreByFreq(DRAMC_CTX_T *p) +{ +#if 1//def MTK_PMIC_MT6359 +#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) +#if __FLASH_TOOL_DA__ + dramc_set_vcore_voltage(725000); +#else + unsigned int vio18, vcore, vdram, vddq, vmddr; + + vio18 = vcore = vdram = vddq = vmddr = 0; + +#if __ETT__ + hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr); +#elif 0//defined(VCORE_BIN) + switch (vGet_Current_ShuLevel(p)) { + case SRAM_SHU0: //4266 + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU0); + if (!vcore) + #endif + vcore = get_vcore_uv_table(0); + break; + case SRAM_SHU1: //3200 + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU1); + if (!vcore) + #endif + vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(1)) >> 1; + break; + case SRAM_SHU2: //2400 + case SRAM_SHU3: //1866 + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU2); + if (!vcore) + #endif + vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(2)) >> 1; + break; + case SRAM_SHU4: //1600 + case SRAM_SHU5: //1200 + case SRAM_SHU6: //800 + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU4); + if (!vcore) + #endif + vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(3)) >> 1; + break; + } +#else + switch (vGet_Current_ShuLevel(p)) { + case SRAM_SHU0: // 4266 + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU0); + #else + vcore = SEL_PREFIX_VCORE(LP4, KSHU0); + #endif + break; + case SRAM_SHU1: // 3200 + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU1); + #else + vcore = SEL_PREFIX_VCORE(LP4, KSHU1); + #endif + break; + case SRAM_SHU2: // 2400 + case SRAM_SHU3: //1866 + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU2); + #else + vcore = SEL_PREFIX_VCORE(LP4, KSHU2); + #endif + break; + case SRAM_SHU4: //1600 + case SRAM_SHU5: //1200 + case SRAM_SHU6: //800 + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU4); + #else + vcore = SEL_PREFIX_VCORE(LP4, KSHU4); + #endif + break; + default: + return; + } +#endif + + if (vcore) + dramc_set_vcore_voltage(vcore); + +#if defined(DRAM_HQA) + vio18 = SEL_VIO18; + if (vio18) + dramc_set_vio18_voltage(vio18); + + vdram = SEL_PREFIX_VDRAM(LP4); + if (vdram) + dramc_set_vdram_voltage(p->dram_type, vdram); + + vddq = SEL_PREFIX_VDDQ; + if (vddq) + dramc_set_vddq_voltage(p->dram_type, vddq); + + vmddr = SEL_PREFIX_VMDDR; + if (vmddr) + dramc_set_vmddr_voltage(vmddr); +#endif + +#ifdef FOR_HQA_REPORT_USED + switch (vGet_Current_ShuLevel(p)) { + case SRAM_SHU0: //3733 + case SRAM_SHU1: //3200 + case SRAM_SHU2: //2400 + case SRAM_SHU3: //1866 + case SRAM_SHU4: //1600 + case SRAM_SHU5: //1200 + case SRAM_SHU6: //800 + gHQA_Test_Freq_Vcore_Level = 0; //only 1 freq + break; + default: + print("[HQA] undefined shuffle level for Vcore (SHU%d)\r\n", vGet_Current_ShuLevel(p)); +#if __ETT__ + while(1); +#endif + break; + } +#endif + +#ifndef DDR_INIT_TIME_PROFILING + print("Read voltage for %d, %d\n", p->frequency, vGet_Current_ShuLevel(p)); + print("Vio18 = %d\n", dramc_get_vio18_voltage()); + print("Vcore = %d\n", dramc_get_vcore_voltage()); + print("Vdram = %d\n", dramc_get_vdram_voltage(p->dram_type)); + print("Vddq = %d\n", dramc_get_vddq_voltage(p->dram_type)); + print("Vmddr = %d\n", dramc_get_vmddr_voltage()); +#endif +#endif +#endif +#endif +} + +U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type) +{ +#if (defined(DRAM_HQA) || __ETT__) && (FOR_DV_SIMULATION_USED == 0) + if (get_voltage_type==0) + return dramc_get_vcore_voltage(); + + if (get_voltage_type==1) + return dramc_get_vdram_voltage(p->dram_type); + + if (get_voltage_type==2) + return dramc_get_vddq_voltage(p->dram_type); + + if (get_voltage_type==3) + return dramc_get_vio18_voltage(); + if (get_voltage_type==4) + return dramc_get_vmddr_voltage(); + +#endif + + return 0; +} + +#ifdef FOR_HQA_TEST_USED +VCORE_DELAYCELL_T gVcoreDelayCellTable[49]={ {500000, 512}, + {506250, 496}, + {512500, 482}, + {518750, 469}, + {525000, 457}, + {531250, 445}, + {537500, 434}, + {543750, 423}, + {550000, 412}, + {556250, 402}, + {562500, 393}, + {568750, 384}, + {575000, 377}, + {581250, 369}, + {587500, 362}, + {593750, 355}, + {600000, 348}, + {606250, 341}, + {612500, 335}, + {618750, 328}, + {625000, 322}, + {631250, 317}, + {637500, 312}, + {643750, 307}, + {650000, 302}, + {656250, 297}, + {662500, 292}, + {668750, 288}, + {675000, 284}, + {681250, 280}, + {687500, 276}, + {693750, 272}, + {700000, 269}, + {706250, 265}, + {712500, 262}, + {718750, 258}, + {725000, 255}, + {731250, 252}, + {737500, 249}, + {743750, 246}, + {750000, 243}, + {756250, 241}, + {762500, 238}, + {768750, 236}, + {775000, 233}, + {781250, 231}, + {787500, 229}, + {793750, 227}, + {800000, 225}, + //{825000, 718}, + //{831250, 717}, + //{837500, 715}, + //{843750, 713}, + //{850000, 708}, + //{856250, 705}, + //{862500, 702}, + //{868750, 700}, + //{875000, 698} + }; + +void GetVcoreDelayCellTimeFromTable(DRAMC_CTX_T *p) +{ + U32 channel_i, i; + U32 get_vcore = 0; + U16 u2gdelay_cell_ps = 0; + U8 u1delay_cell_cnt = 0; + VCORE_DELAYCELL_T *pVcoreDelayCellTable; + +#if (defined(DRAM_HQA) || __ETT__) && (FOR_DV_SIMULATION_USED == 0) + #if 1//__Petrus_TO_BE_PORTING__ + get_vcore = dramc_get_vcore_voltage(); + #endif +#endif + + pVcoreDelayCellTable = (VCORE_DELAYCELL_T *)gVcoreDelayCellTable; + u1delay_cell_cnt = sizeof(gVcoreDelayCellTable)/sizeof(gVcoreDelayCellTable[0]); + + for(i=0; i<u1delay_cell_cnt; i++) + { + if (get_vcore >= pVcoreDelayCellTable[i].u2Vcore) + { + u2gdelay_cell_ps = pVcoreDelayCellTable[i].u2DelayCell; + } + } + + mcSHOW_DBG_MSG(("[GetVcoreDelayCellTimeFromTable(%d)] VCore=%d(x100), DelayCell=%d(x100)\n", u1delay_cell_cnt, get_vcore, u2gdelay_cell_ps)); + + for(channel_i=CHANNEL_A; channel_i < p->support_channel_num; channel_i++) + { + u2gdelay_cell_ps_all[get_shuffleIndex_by_Freq(p)][channel_i] = u2gdelay_cell_ps; + u4gVcore[get_shuffleIndex_by_Freq(p)] = get_vcore/1000; + } +} +#endif + +///TODO: wait for porting +++ +#ifdef FIRST_BRING_UP +void Test_Broadcast_Feature(DRAMC_CTX_T *p) +{ + U32 u4RegBackupAddress[] = + { + (DRAMC_REG_SHURK_SELPH_DQ2), + (DRAMC_REG_SHURK_SELPH_DQ2 + SHIFT_TO_CHB_ADDR), + + (DDRPHY_REG_SHU_RK_B0_DQ0), + (DDRPHY_REG_SHU_RK_B0_DQ0 + SHIFT_TO_CHB_ADDR), + }; + U32 read_value; + U32 backup_broadcast; + + backup_broadcast = GetDramcBroadcast(); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + + vIO32Write4B(DRAMC_REG_SHURK_SELPH_DQ2, 0xA55A00FF); + vIO32Write4B(DDRPHY_REG_SHU_RK_B0_DQ0, 0xA55A00FF); + + read_value = u4IO32Read4B(DRAMC_REG_SHURK_SELPH_DQ2 + SHIFT_TO_CHB_ADDR); + if (read_value != 0xA55A00FF) + { + mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n")); + while (1); + } + + read_value = u4IO32Read4B(DDRPHY_REG_SHU_RK_B0_DQ0 + SHIFT_TO_CHB_ADDR); + if (read_value != 0xA55A00FF) + { + mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n")); + while (1); + } + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); + + DramcBroadcastOnOff(backup_broadcast); +} +#endif + +#ifdef ENABLE_MIOCK_JMETER +U8 gPRE_MIOCK_JMETER_HQA_USED_flag=0; + +static void Set_PRE_MIOCK_JMETER_HQA_USED_flag(U8 value) +{ + gPRE_MIOCK_JMETER_HQA_USED_flag = value; +} + +void Get_RX_DelayCell(DRAMC_CTX_T *p) +{ +#if defined(FOR_HQA_REPORT_USED) && (FOR_DV_SIMULATION_USED==0) && (SW_CHANGE_FOR_SIMULATION==0) + if (gHQALOG_RX_delay_cell_ps_075V == 0) + { +#if __ETT__ + mcSHOW_DBG_MSG(("RX delay cell calibration (%d):\n", hqa_vmddr_class)); + + switch (hqa_vmddr_class) + { + case 1: + dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, HV, LP4)); + break; + case 2: + dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, NV, LP4)); + break; + case 3: + dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, LV, LP4)); + break; + } +#else + // set vcore to RX used 0.75V + dramc_set_vcore_voltage(SEL_PREFIX_VMDDR); //set vmddr voltage to vcore to K RX delay cell +#endif + + DramcMiockJmeter(p); + + gHQALOG_RX_delay_cell_ps_075V = u2gdelay_cell_ps; + + // set vocre back + vSetVcoreByFreq(p); + } +#endif +} + +void PRE_MIOCK_JMETER_HQA_USED(DRAMC_CTX_T *p) +{ + U32 backup_freq_sel, backup_channel; + U32 channel_idx; + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if(p->femmc_Ready==1) + { + for(channel_idx=CHANNEL_A; channel_idx<p->support_channel_num; channel_idx++) + { + //for (shuffleIdx = DRAM_DFS_SHUFFLE_1; shuffleIdx < DRAM_DFS_SHUFFLE_MAX; shuffleIdx++) + { + u2g_num_dlycell_perT_all[p->shu_type][channel_idx] = p->pSavetimeData->u2num_dlycell_perT; + u2gdelay_cell_ps_all[p->shu_type][channel_idx] = p->pSavetimeData->u2DelayCellTimex100; + } + } + + p->u2num_dlycell_perT = p->pSavetimeData->u2num_dlycell_perT; + p->u2DelayCellTimex100 = p->pSavetimeData->u2DelayCellTimex100; + return; + } +#endif + + + backup_freq_sel = vGet_PLL_FreqSel(p); + backup_channel = p->channel; + + mcSHOW_DBG_MSG3(("[JMETER_HQA]\n")); + Set_PRE_MIOCK_JMETER_HQA_USED_flag(1); + + vSetPHY2ChannelMapping(p, CHANNEL_A); + + DramcMiockJmeterHQA(p); + + vSetPHY2ChannelMapping(p, backup_channel); + + Set_PRE_MIOCK_JMETER_HQA_USED_flag(0); + + vSet_PLL_FreqSel(p, backup_freq_sel); +} +#endif + + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION +#if !EMMC_READY +u32 g_dram_save_time_init_done[DRAM_DFS_SHUFFLE_MAX] = {0}; +SAVE_TIME_FOR_CALIBRATION_T SaveTimeDataByShuffle[DRAM_DFS_SHUFFLE_MAX]; +#endif +static DRAM_STATUS_T DramcSave_Time_For_Cal_End(DRAMC_CTX_T *p) +{ + if (!u1IsLP4Family(p->dram_type)) + return DRAM_FAIL; + + if (p->femmc_Ready == 0) + { + #if EMMC_READY + write_offline_dram_calibration_data(p->shu_type, p->pSavetimeData); + mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to emmc\n")); + #else + g_dram_save_time_init_done[p->shu_type] = 1; + memcpy(&(SaveTimeDataByShuffle[p->shu_type]), p->pSavetimeData, sizeof(SAVE_TIME_FOR_CALIBRATION_T)); + mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to SW memory\n")); + #endif + } + else + { + mcSHOW_DBG_MSG(("[FAST_K] Bypass saving calibration result to emmc\n")); + } + + return DRAM_OK; +} + +static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p) +{ + if (!u1IsLP4Family(p->dram_type)) + return DRAM_FAIL; + + if (doe_get_config("fullk")) + return DRAM_FAIL; + + // Parepare fask k data + #if EMMC_READY + // scy: only need to read emmc one time for each boot-up + //if (g_dram_save_time_init_done == 1) + // return DRAM_OK; + //else + // g_dram_save_time_init_done = 1; + if (read_offline_dram_calibration_data(p->shu_type, p->pSavetimeData) < 0) + { + p->femmc_Ready = 0; + memset(p->pSavetimeData, 0, sizeof(SAVE_TIME_FOR_CALIBRATION_T)); + } + else + { + p->femmc_Ready = 1; + } + + #else //EMMC is not avaliable, load off-line data + + if (g_dram_save_time_init_done[p->shu_type] == 0) + { + p->femmc_Ready = 0; + memset(p->pSavetimeData, 0, sizeof(SAVE_TIME_FOR_CALIBRATION_T)); + } + else + { + memcpy(p->pSavetimeData, &(SaveTimeDataByShuffle[p->shu_type]), sizeof(SAVE_TIME_FOR_CALIBRATION_T)); + p->femmc_Ready = 1; + } + #endif + + if (p->femmc_Ready == 1) + { + if (p->frequency < 1600) + { // freq < 1600, TX and RX tracking are disable. Therefore, bypass calibration. + p->Bypass_RDDQC = 1; + p->Bypass_RXWINDOW = 1; + p->Bypass_TXWINDOW = 1; + } + else + { + p->Bypass_RDDQC = 1; + p->Bypass_RXWINDOW = !ENABLE_RX_TRACKING; + p->Bypass_TXWINDOW = 0; + } + +#if RUNTIME_SHMOO_RELEATED_FUNCTION + p->Bypass_RDDQC = 1; + p->Bypass_RXWINDOW = 1; + p->Bypass_TXWINDOW = 1; +#endif + } + +#if EMMC_READY + mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SHU%d, femmc_Ready=%d\n", p->shu_type, p->femmc_Ready)); +#else + mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SHU%d, Init_done=%d, femmc_Ready=%d\n", p->shu_type, g_dram_save_time_init_done[p->shu_type], p->femmc_Ready)); +#endif + mcSHOW_DBG_MSG(("[FAST_K] Bypass_RDDQC %d, Bypass_RXWINDOW=%d, Bypass_TXWINDOW=%d\n", p->Bypass_RDDQC, p->Bypass_RXWINDOW, p->Bypass_TXWINDOW)); + + return DRAM_OK; +} +#endif + +#if ENABLE_RANK_NUMBER_AUTO_DETECTION +static void DramRankNumberDetection(DRAMC_CTX_T *p) +{ + U8 u1RankBak; + + u1RankBak = u1GetRank(p); // backup current rank setting + + vSetPHY2ChannelMapping(p, CHANNEL_A); // when switching channel, must update PHY to Channel Mapping + vSetRank(p, RANK_1); + + if (DramcWriteLeveling(p, AUTOK_ON, PI_BASED) == DRAM_OK) + { + p->support_rank_num = RANK_DUAL; + vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 0, SA_RESERVE_SINGLE_RANK); //keep support_rank_num to reserved rg + } + else + { + p->support_rank_num = RANK_SINGLE; + vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SINGLE_RANK); //keep support_rank_num to reserved rg + } + mcSHOW_DBG_MSG(("[RankNumberDetection] %d\n", p->support_rank_num)); + + vSetRank(p, u1RankBak); // restore rank setting +} +#endif + +static void UpdateGlobal10GBEnVariables(DRAMC_CTX_T *p) +{ + p->u110GBEn[RANK_0] = (get_row_width_by_emi(RANK_0) >= 18) ? ENABLE : DISABLE; + p->u110GBEn[RANK_1] = (get_row_width_by_emi(RANK_1) >= 18) ? ENABLE : DISABLE; + //mcSHOW_DBG_MSG(("[10GBEn] RANK0=%d, RANK1=%d\n", p->u110GBEn[RANK_0], p->u110GBEn[RANK_1])); +} + +void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p) +{ + U8 u1RankMax; + S8 s1RankIdx; + +#if GATING_ADJUST_TXDLY_FOR_TRACKING + DramcRxdqsGatingPreProcess(p); +#endif + + if (p->support_rank_num == RANK_DUAL) + u1RankMax = RANK_MAX; + else + u1RankMax = RANK_1; + + for (s1RankIdx = RANK_0; s1RankIdx < u1RankMax; s1RankIdx++) + { + vSetRank(p, s1RankIdx); + + vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable + dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0); + DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF); + +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable + } + + vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate()) + +#if GATING_ADJUST_TXDLY_FOR_TRACKING + DramcRxdqsGatingPostProcess(p); +#endif +} + +static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInfo) +{ + U8 u1RankIdx, u1DieNumber = 0; + U16 u2Density; + U16 u2MR7; + U16 u2MR8 = 0; + U64 u8Size = 0, u8Size_backup = 0; + + if (p->revision_id != REVISION_ID_MAGIC) + return 0; + + vSetPHY2ChannelMapping(p, CHANNEL_A); + + // Read MR5 for Vendor ID + DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id));// for byte mode, don't show value of another die. + p->vendor_id &= 0xFF; + mcSHOW_DBG_MSG(("[GetDramInforAfterCalByMRR] Vendor %x.\n", p->vendor_id)); + // Read MR6 for Revision ID + DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id));// for byte mode, don't show value of another die. + mcSHOW_DBG_MSG(("[GetDramInforAfterCalByMRR] Revision %x.\n", p->revision_id)); + // Read MR6 for Revision ID2 + DramcModeRegReadByRank(p, RANK_0, 7, &u2MR7);// for byte mode, don't show value of another die. + mcSHOW_DBG_MSG(("[GetDramInforAfterCalByMRR] Revision 2 %x.\n", u2MR7)); +#if (!__ETT__) && (FOR_DV_SIMULATION_USED==0) + set_dram_mr(5, p->vendor_id); + set_dram_mr(6, p->revision_id); + set_dram_mr(7, u2MR7); +#endif + if (DramInfo != NULL) + { + DramInfo->u2MR5VendorID = p->vendor_id; + DramInfo->u2MR6RevisionID = p->revision_id; + + for (u1RankIdx = 0; u1RankIdx < RANK_MAX; u1RankIdx++) + DramInfo->u8MR8RankSize[u1RankIdx] = 0; + } + + // Read MR8 for dram density + for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++) + { + #if 0//PRINT_CALIBRATION_SUMMARY + if ((p->aru4CalExecuteFlag[u1ChannelIdx][u1RankIdx] != 0) && \ + (p->aru4CalResultFlag[u1ChannelIdx][u1RankIdx] == 0)) + #endif + { + DramcModeRegReadByRank(p, u1RankIdx, 0, &(gu2MR0_Value[u1RankIdx])); + mcSHOW_DBG_MSG(("MR0 0x%x\n", gu2MR0_Value[u1RankIdx])); + + DramcModeRegReadByRank(p, u1RankIdx, 8, &u2Density); + mcSHOW_DBG_MSG(("MR8 0x%x\n", u2Density)); + u2MR8 |= (u2Density & 0xFF) << (u1RankIdx * 8); + + u1DieNumber = 1; + if (((u2Density >> 6) & 0x3) == 1) //OP[7:6] =0, x16 (normal mode) + u1DieNumber = 2; + + u2Density = (u2Density >> 2) & 0xf; + + switch (u2Density) + { + ///TODO: Darren, please check the value of u8Size. + case 0x0: + u8Size = 0x20000000; //4Gb = 512MB + //mcSHOW_DBG_MSG(("[EMI]DRAM density = 4Gb\n")); + break; + case 0x1: + u8Size = 0x30000000; //6Gb = 768MB + //mcSHOW_DBG_MSG(("[EMI]DRAM density = 6Gb\n")); + break; + case 0x2: + u8Size = 0x40000000; //8Gb = 1GB = 2^30 bytes = 0x40000000 bytes + //mcSHOW_DBG_MSG(("[EMI]DRAM density = 8Gb\n")); + break; + case 0x3: + u8Size = 0x60000000; //12Gb = 1.5GB = 3^30 bytes = 0x60000000 bytes + //mcSHOW_DBG_MSG(("[EMI]DRAM density = 12Gb\n")); + break; + case 0x4: + u8Size = 0x80000000; //16Gb = 2GB = 4^30 bytes = 0x80000000 bytes + //mcSHOW_DBG_MSG(("[EMI]DRAM density = 16Gb\n")); + break; + case 0x5: + u8Size = 0xc0000000; //24Gb = 3GB = 6^30 bytes = 0xc0000000 bytes + //mcSHOW_DBG_MSG(("[EMI]DRAM density = 24Gb\n")); + break; + case 0x6: + u8Size = 0x100000000L; //32Gb = 4GB = 8^30 bytes = 0x10000000 bytes + //mcSHOW_DBG_MSG(("[EMI]DRAM density = 32Gb\n")); + break; + default: + u8Size = 0; //reserved + } + + if (u8Size_backup < u8Size) // find max dram size for vDramcACTimingOptimize + { + u8Size_backup = u8Size; + p->density = u2Density; + } + + p->ranksize[u1RankIdx] = u8Size * u1DieNumber; //dram rank size = density * DieNumber + + if (DramInfo != NULL) + { + DramInfo->u8MR8RankSize[u1RankIdx] = p->ranksize[u1RankIdx]; + } + } + // 1GB = 2^30 bytes + // u8Size * (2^3) / (2^30) ==>Gb + mcSHOW_DBG_MSG(("RK%d, DieNum %d, Density %dGb, RKsize %dGb.\n\n", u1RankIdx, u1DieNumber, (U32)(u8Size >> 27), (U32)(p->ranksize[u1RankIdx] >> 27))); + } +#if (!__ETT__) && (FOR_DV_SIMULATION_USED==0) + set_dram_mr(8, u2MR8); +#endif + return 0; +} + +static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) +{ + U8 u1RankMax; + S8 s1RankIdx; + //DRAM_STATUS_T VrefStatus; + +#ifdef DDR_INIT_TIME_PROFILING + U32 CPU_Cycle; + TimeProfileBegin(); +#endif + +#if __Petrus_TO_BE_PORTING__ +#if ENABLE_PHY_RX_INPUT_OFFSET // skip when bring up + ///TODO: no shuffle, only need to do once under highest freq. + if(p->frequency == u2DFSGetHighestFreq(p)) + DramcRXInputBufferOffsetCal(p); + +#ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRX input cal takes %d us\n", CPU_Cycle)); + TimeProfileBegin(); +#endif +#endif +#endif + + +#if GATING_ADJUST_TXDLY_FOR_TRACKING + DramcRxdqsGatingPreProcess(p); +#endif + + if (p->support_rank_num==RANK_DUAL) + u1RankMax = RANK_MAX; + else + u1RankMax = RANK_1; + + //vAutoRefreshSwitch(p, DISABLE); //auto refresh is set as disable in LP4_DramcSetting, so don't need to disable again + vAutoRefreshSwitch(p, DISABLE); + +#if 1//(SIMUILATION_CBT == 1) + for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) + { + vSetRank(p, s1RankIdx); + #if PINMUX_AUTO_TEST_PER_BIT_CA + CheckCAPinMux(p); + #endif + + CmdBusTrainingLP45(p, AUTOK_OFF); + + #if ENABLE_EYESCAN_GRAPH + print_EYESCAN_LOG_message(p, 0); //draw CBT eyescan + #endif + + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRank %d CBT takes %d us\n", s1RankIdx, CPU_Cycle)); + TimeProfileBegin(); + #endif + } + vSetRank(p, RANK_0); + +#if __Petrus_TO_BE_PORTING__ + No_Parking_On_CLRPLL(p); +#endif + + // The patch must to do after cbt training + ShuffleDfsToFSP1(p); +#endif + +#if 0//(SIMULATION_WRITE_LEVELING == 1) + for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) + { + vSetRank(p, s1RankIdx); + + vAutoRefreshSwitch(p, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable + +#if (!WCK_LEVELING_FM_WORKAROUND) + if (u1IsLP4Family(p->dram_type)) +#endif + { + if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) // skip for DDR800 rank1 + { + mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); + + DramcWriteLeveling(p, AUTOK_OFF, PI_BASED); + + mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n")); + } + } + + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle)); + TimeProfileBegin(); + #endif + } + vSetRank(p, RANK_0); + + #if ENABLE_WDQS_MODE_2 // <=DDR1600 reduce PI change code time + if (!(u1IsLP4Div4DDR800(p)) && (p->frequency <= 800) && (p->support_rank_num == RANK_DUAL)) // skip DDR800semi, for DDR1200/DDR1600 only + WriteLevelingPosCal(p, PI_BASED); + #elif ENABLE_TX_WDQS // for WDQS mode 1 to avoid dual rank PI code incorrect + if (!(u1IsLP4Div4DDR800(p)) && (p->support_rank_num == RANK_DUAL)) + WriteLevelingPosCal(p, PI_BASED); + #endif +#endif /* (SIMULATION_WRITE_LEVELING == 1) */ + + for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) + { + vSetRank(p, s1RankIdx); + +#if 1//(SIMULATION_WRITE_LEVELING == 1) + vAutoRefreshSwitch(p, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable + +#if (!WCK_LEVELING_FM_WORKAROUND) + if (u1IsLP4Family(p->dram_type)) +#endif + { + if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) // skip for DDR800 rank1 + { + mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); + + DramcWriteLeveling(p, AUTOK_ON, PI_BASED); + + mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n")); + } + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle)); + TimeProfileBegin(); + #endif + } +#endif /* (SIMULATION_WRITE_LEVELING == 1) */ + + vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable + + dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0); + + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRank %d Gating takes %d us\n", s1RankIdx, CPU_Cycle)); + TimeProfileBegin(); + #endif + + DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF); + + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRank %d RX RDDQC takes %d us\n", s1RankIdx, CPU_Cycle)); + TimeProfileBegin(); + #endif + +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + + DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_DQM, FALSE, AUTOK_OFF); + + if (Get_Vref_Calibration_OnOff(p)==VREF_CALI_ON) + { + DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, TRUE, AUTOK_OFF); + } + +#if PINMUX_AUTO_TEST_PER_BIT_TX + CheckTxPinMux(p); +#endif + DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, FALSE, AUTOK_OFF); + +#if TX_K_DQM_WITH_WDBI + if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON)) + { + // K DQM with DBI_ON, and check DQM window spec. + //mcSHOW_DBG_MSG(("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n")); + vSwitchWriteDBISettings(p, DBI_ON); + DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQM_ONLY, FALSE, AUTOK_OFF); + vSwitchWriteDBISettings(p, DBI_OFF); + } +#endif + + #if ENABLE_EYESCAN_GRAPH + Dramc_K_TX_EyeScan_Log(p); + print_EYESCAN_LOG_message(p, 2); //draw TX eyescan + #endif + + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRank %d TX calibration takes %d us\n", s1RankIdx, CPU_Cycle)); + TimeProfileBegin(); + #endif + + DramcRxdatlatCal(p); + + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRank %d Datlat takes %d us\n", s1RankIdx, CPU_Cycle)); + TimeProfileBegin(); + #endif + +#if PINMUX_AUTO_TEST_PER_BIT_RX + CheckRxPinMux(p); +#endif + DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_OFF); + + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tRank %d RX calibration takes %d us\n", s1RankIdx, CPU_Cycle)); + TimeProfileBegin(); + #endif + // DramcRxdqsGatingCal(p); + +#if ENABLE_EYESCAN_GRAPH + print_EYESCAN_LOG_message(p, 1); //draw RX eyescan +#endif + +#if (SIMULATION_RX_DVS == 1) + if (p->frequency >=2133) + DramcRxDVSWindowCal(p); +#endif + +#if TX_OE_CALIBATION && !ENABLE_WDQS_MODE_2 + if(p->frequency >= 1600) + { + DramcTxOECalibration(p); + } +#endif + + vAutoRefreshSwitch(p, DISABLE); + + #if ENABLE_TX_TRACKING + DramcDQSOSCSetMR18MR19(p); + DramcDQSOSCMR23(p); + #endif + + } + +#if __Petrus_TO_BE_PORTING__ + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if(p->femmc_Ready==0) + #endif + { + if(p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) // for 3733/4266 + { + U8 u1ByteIdx, u1HighFreqRXVref[2]; + for(u1ByteIdx =0 ; u1ByteIdx<(p->data_width/DQS_BIT_NUMBER); u1ByteIdx++) + { + u1HighFreqRXVref[u1ByteIdx] = (gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx] + gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx]) >> 1; + mcSHOW_DBG_MSG(("RX Vref Byte%d (u1HighFreqRXVref) = %d = (%d+ %d)>>1\n", u1ByteIdx, u1HighFreqRXVref[u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx])); + } + + for(s1RankIdx=RANK_0; s1RankIdx < u1RankMax; s1RankIdx++) + { + vSetRank(p, s1RankIdx); + DramcRxWindowPerbitCal((DRAMC_CTX_T *) p, 1, u1HighFreqRXVref); + } + } + } +#endif + + vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate()) + + #if ENABLE_TX_TRACKING + DramcDQSOSCShuSettings(p); + #endif + +#if (SIMULATION_GATING && GATING_ADJUST_TXDLY_FOR_TRACKING) + DramcRxdqsGatingPostProcess(p); +#endif + +#if TDQSCK_PRECALCULATION_FOR_DVFS + DramcDQSPrecalculation_preset(p); +#endif + +#if SIMULATION_RX_DVS + if (p->frequency >=2133) + DramcDramcRxDVSCalPostProcess(p); +#endif + + DramcDualRankRxdatlatCal(p); + +#if RDSEL_TRACKING_EN + if (p->frequency >= 1866) + RDSELRunTimeTracking_preset(p); +#endif + +#if XRTWTW_NEW_CROSS_RK_MODE + if(p->support_rank_num == RANK_DUAL) + { + XRTWTW_SHU_Setting(p); + } +#endif + +#if __Petrus_TO_BE_PORTING__ +#if LJPLL_FREQ_DEBUG_LOG + DDRPhyFreqMeter(); +#endif +#endif + + #ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle=TimeProfileEnd(); + mcSHOW_TIME_MSG(("\tMisc takes %d us\n\n", s1RankIdx, CPU_Cycle)); + #endif +} + +static void vDramCalibrationSingleChannel(DRAMC_CTX_T *p) +{ +#if 0//!__ETT__ + /* + * Since DRAM calibration will cost much time, + * kick wdt here to prevent watchdog timeout. + */ +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + mtk_wdt_restart(); +#endif +#endif + + vCalibration_Flow_LP4(p); +} + +void vDramCalibrationAllChannel(DRAMC_CTX_T *p) +{ + U8 channel_idx, rank_idx; + +#ifdef DDR_INIT_TIME_PROFILING + U32 u4low_tick0, u4high_tick0, u4low_tick1, u4high_tick1; +#if __ETT__ + u4low_tick0 = GPT_GetTickCount(&u4high_tick0); +#else + u4low_tick0 = get_timer(0); +#endif +#endif + + vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) + { + vSetPHY2ChannelMapping(p, channel_idx);// when switching channel, must update PHY to Channel Mapping + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(0, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) + | P_Fld(1, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) + | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); + vDramCalibrationSingleChannel(p); + } + + vSetPHY2ChannelMapping(p, CHANNEL_A); + +#if PRINT_CALIBRATION_SUMMARY + vPrintCalibrationResult(p); +#endif + +#ifdef FOR_HQA_TEST_USED + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if (p->femmc_Ready == 1) + { + mcSHOW_DBG_MSG(("\nCalibration fast K is enable, cannot show HQA measurement information\n")); + } + else + #endif + print_HQA_measure_message(p); +#endif + + /* Enable/Disable calibrated rank's DBI function accordingly */ +#if ENABLE_READ_DBI + //Read DBI ON + vSetRank(p, RANK_0); + vSetPHY2ChannelMapping(p, CHANNEL_A); + + DramcReadDBIOnOff(p, p->DBI_R_onoff[p->dram_fsp]); +#endif + +#if ENABLE_WRITE_DBI + // Just settle the DBI parameters which would be stored into shuffle space. + if (p->DBI_W_onoff[p->dram_fsp]) + { + for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) + { + vSetPHY2ChannelMapping(p, channel_idx); + + for (rank_idx = RANK_0; rank_idx < RANK_MAX; rank_idx++) + { + vSetRank(p, rank_idx); + DramcWriteShiftMCKForWriteDBI(p, -1); //Tx DQ/DQM -1 MCK for write DBI ON + } + vSetRank(p, RANK_0); + } + vSetPHY2ChannelMapping(p, CHANNEL_A); + + // Improve Write DBI Power + ApplyWriteDBIPowerImprove(p, ENABLE); + + #if ENABLE_WRITE_DBI_Protect + ApplyWriteDBIProtect(p, ENABLE); + #endif + } + + DramcWriteDBIOnOff(p, p->DBI_W_onoff[p->dram_fsp]); +#endif + +#if TX_PICG_NEW_MODE + TXPICGSetting(p); +#endif + +#if XRTRTR_NEW_CROSS_RK_MODE + if (p->support_rank_num == RANK_DUAL) + { + XRTRTR_SHU_Setting(p); + } +#endif + +#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS) + FreqJumpRatioCalculation(p); +#endif + +#ifdef TEMP_SENSOR_ENABLE + DramcHMR4_Presetting(p); +#endif + +#if (ENABLE_PER_BANK_REFRESH == 1) + DramcEnablePerBankRefresh(p, ON); +#else + DramcEnablePerBankRefresh(p, OFF); +#endif + +#if DRAMC_MODIFIED_REFRESH_MODE + DramcModifiedRefreshMode(p); +#endif + +#if DRAMC_CKE_DEBOUNCE + DramcCKEDebounce(p); +#endif + +#if ENABLE_TX_TRACKING + U8 backup_channel = p->channel; + U8 channelIdx; + + for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++) + { + vSetPHY2ChannelMapping(p, channelIdx); + DramcHwDQSOSC(p); + } + + vSetPHY2ChannelMapping(p, backup_channel); + mcSHOW_DBG_MSG(("TX_TRACKING: ON\n")); +#else + mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n")); +#endif + + +#if ENABLE_DFS_RUNTIME_MRW + DFSRuntimeMRW_preset(p, vGet_Current_ShuLevel(p)); +#endif + +#ifdef DDR_INIT_TIME_PROFILING +#if __ETT__ + u4low_tick1 = GPT_GetTickCount(&u4high_tick1); + mcSHOW_TIME_MSG((" (4) vDramCalibrationAllChannel() take %d ms\n\r", ((u4low_tick1 - u4low_tick0) * 76) / 1000000)); +#else + u4low_tick1 = get_timer(u4low_tick0); + mcSHOW_TIME_MSG((" (4) vDramCalibrationAllChannel() take %d ms\n\r", u4low_tick1)); +#endif +#endif +} + +U8 gGet_MDL_Used_Flag = 0; +void Set_MDL_Used_Flag(U8 value) +{ + gGet_MDL_Used_Flag = value; +} + +U8 Get_MDL_Used_Flag(void) +{ + return gGet_MDL_Used_Flag; +} + +DRAMC_CTX_T *psCurrDramCtx; +U8 gfirst_init_flag = 0; +int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, + DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used) +{ + #if !SW_CHANGE_FOR_SIMULATION + + DRAMC_CTX_T * p; + U8 final_shu; + +#ifdef DDR_INIT_TIME_PROFILING + U32 CPU_Cycle; + TimeProfileBegin(); +#endif + + psCurrDramCtx = &DramCtx_LPDDR4; + +#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION) + if (gtime_profiling_flag == 0) + { + memcpy(&gTimeProfilingDramCtx, psCurrDramCtx, sizeof(DRAMC_CTX_T)); + gtime_profiling_flag = 1; + } + + p = &gTimeProfilingDramCtx; + gfirst_init_flag = 0; + + //DramcConfInfraReset(p); //No need when DDR_INIT_TIME_PROFILING_TEST_CNT=1 +#else + p = psCurrDramCtx; +#endif + + p->new_cbt_mode = 1; + + Set_MDL_Used_Flag(get_mdl_used); + + p->dram_type = dram_type; + + /* Convert DRAM_CBT_MODE_EXTERN_T to DRAM_CBT_MODE_T */ + switch ((int)dram_cbt_mode_extern) + { + case CBT_R0_R1_NORMAL: + p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; + p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; + break; + case CBT_R0_R1_BYTE: + p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1; + p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1; + break; + case CBT_R0_NORMAL_R1_BYTE: + p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; + p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1; + break; + case CBT_R0_BYTE_R1_NORMAL: + p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1; + p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; + break; + default: + mcSHOW_ERR_MSG(("Error!")); + break; + } + mcSHOW_DBG_MSG2(("dram_cbt_mode_extern: %d\n" + "dram_cbt_mode [RK0]: %d, [RK1]: %d\n", + (int)dram_cbt_mode_extern, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1])); + +#if ENABLE_APB_MASK_WRITE + U32 u4GPTTickCnt; + TimeProfileBegin(); + + EnableDramcAPBMaskWrite(p); + DramcRegAPBWriteMask(p); + + u4GPTTickCnt = TimeProfileEnd(); + mcSHOW_TIME_MSG(("[DramcRegAPBWriteMask] take %d ms\n", u4GPTTickCnt / 1000)); + + TestAPBMaskWriteFunc(p); + + while (1); +#endif + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on + + if (gfirst_init_flag == 0) + { + MPLLInit(); + Global_Option_Init(p); + gfirst_init_flag = 1; + } + +#ifdef FIRST_BRING_UP + Test_Broadcast_Feature(p); +#endif + +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + { + U32 backup_broadcast; + backup_broadcast = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + mdl_setting(p); + UpdateGlobal10GBEnVariables(p); // @Darren, for 10GB + TA2_Test_Run_Time_HW_Set_Column_Num(p); + DramcBroadcastOnOff(backup_broadcast); + } +#endif + + mcSHOW_DBG_MSG(("\n\n[Bian_co] ETT version 0.0.0.1\n dram_type %d, R0 cbt_mode %d, R1 cbt_mode %d VENDOR=%d\n\n", p->dram_type, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1], p->vendor_id)); + +#if __Petrus_TO_BE_PORTING__ + vDramcInit_PreSettings(p); +#endif + + // DramC & PHY init for all channels + //=== First frequency ====== + +#if defined(DUMP_INIT_RG_LOG_TO_DE) + vSetDFSFreqSelByTable(p, &gFreqTbl[1]); //0:3200 1:4266, 2:800, 3:1866, 4:1200, 5:2400, 6:1600 +#else + vSetDFSFreqSelByTable(p, &gFreqTbl[DRAM_DFS_SHUFFLE_MAX-1]); + //vSetDFSFreqSelByTable(p, &gFreqTbl[1]); +#endif + //#if (ENABLE_DRAM_SINGLE_FREQ_SELECT != 0xFF) || defined(FIRST_BRING_UP) || (__FLASH_TOOL_DA__) + if (is_dvfs_enabled()) + gAndroid_DVFS_en = TRUE; + else + gAndroid_DVFS_en = FALSE; + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + DramcSave_Time_For_Cal_Init(p); +#endif +#ifndef LOOPBACK_TEST + if (p->dram_type == TYPE_LPDDR4X) // LP4/LP4P need confirm + { + // LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 + // LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 + DramcSwImpedanceCal(p, 1, IMP_LOW_FREQ); + DramcSwImpedanceCal(p, 1, IMP_HIGH_FREQ); + #if ENABLE_SAMSUNG_NT_ODT + DramcSwImpedanceCal(p, 1, IMP_NT_ODTN); // for Samsung NT ODTN + #endif + } + else + { + mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm DRAM type for SW IMP Calibration !!!\n")); + #if __ETT__ + while (1); + #endif + } +#endif + +#ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle = TimeProfileEnd(); + mcSHOW_TIME_MSG(("(0)Pre_Init + SwImdepance takes %d ms\n\r", CPU_Cycle / 1000)); +#endif + +#ifdef DUMP_INIT_RG_LOG_TO_DE + gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1; + mcSHOW_DUMP_INIT_RG_MSG(("\n\n//=== DDR\033[1;32m%d\033[m\n",p->frequency<<1)); +#endif + + //Clk free run + //EnableDramcPhyDCM(p, 0); + + DFSInitForCalibration(p); + +#ifdef TEST_MODE_MRS + if (global_which_test == 0) + TestModeTestMenu(); +#endif + + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if (p->femmc_Ready==1) + { + p->support_rank_num = p->pSavetimeData->support_rank_num; + } +#endif + + #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + U32 backup_broadcast; + backup_broadcast = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + emi_init2(); + DramcBroadcastOnOff(backup_broadcast); + #endif + + if (Get_MDL_Used_Flag()==GET_MDL_USED) + { + // only K CHA to save time + vSetPHY2ChannelMapping(p, CHANNEL_A); + vCalibration_Flow_For_MDL(p); // currently for LP4 + GetDramInforAfterCalByMRR(p, DramInfo); + return 0; + } + else //NORMAL_USED + { + #if (fcFOR_CHIP_ID == fcMargaux) // @Darren, new chip need double confirm + if (p->DRAMPinmux == PINMUX_DSC) + UpdateDFSTbltoDDR3200(p); + #endif + vDramCalibrationAllChannel(p); + GetDramInforAfterCalByMRR(p, DramInfo); + vDramcACTimingOptimize(p); + } + + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + DramcSave_Time_For_Cal_End(p); + #endif + +#if ((!defined(FIRST_BRING_UP)) || (ENABLE_DRAM_SINGLE_FREQ_SELECT != 0xFF)) && (!__FLASH_TOOL_DA__) + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, p->pDFSTable->shuffleIdx); + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + DramcSave_Time_For_Cal_End(p); + #endif + LoadShuffleSRAMtoDramc(p, p->pDFSTable->shuffleIdx, DRAM_DFS_SHUFFLE_2); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + #if ENABLE_SRAM_DMA_WA + DPHYSRAMShuWAToSHU1(p); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + #endif + + S8 u1ShuIdx; +//#if (ENABLE_DRAM_SINGLE_FREQ_SELECT == 0xFF) + if (is_dvfs_enabled()) { + for (u1ShuIdx = DRAM_DFS_SHUFFLE_MAX - 2; u1ShuIdx >= DRAM_DFS_SHUFFLE_1; u1ShuIdx--) + { + #if (fcFOR_CHIP_ID == fcMargaux) && (ENABLE_DRAM_SINGLE_FREQ_SELECT == 0xFF) // @Darren, new chip need double confirm + if ((p->DRAMPinmux == PINMUX_DSC) && (gFreqTbl[u1ShuIdx].shuffleIdx == SRAM_SHU0)) + continue; + #endif + + vSetDFSFreqSelByTable(p, &gFreqTbl[u1ShuIdx]); + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + DramcSave_Time_For_Cal_Init(p); + #endif + DFSInitForCalibration(p); + vDramCalibrationAllChannel(p); + vDramcACTimingOptimize(p); + + #if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION + if (p->frequency == u2DFSGetHighestFreq(p)) + { + DramcRunTimeShmooRG_BackupRestore(p); + + RunTime_Shmoo_update_parameters(p); + } +#endif + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx].shuffleIdx); + #if (fcFOR_CHIP_ID == fcMargaux) && (ENABLE_DRAM_SINGLE_FREQ_SELECT == 0xFF) // @Darren, new chip need double confirm + if ((p->DRAMPinmux == PINMUX_DSC) && (gFreqTbl[u1ShuIdx].shuffleIdx == SRAM_SHU1)) + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx + 1].shuffleIdx); // Copy SRAM_SHU1 to SRAM_SHU0 + #endif + + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + DramcSave_Time_For_Cal_End(p); + #endif + } + } +#endif //((!defined(FIRST_BRING_UP)) || (ENABLE_DRAM_SINGLE_FREQ_SELECT != 0xFF)) && (!__FLASH_TOOL_DA__) + +#ifdef DDR_INIT_TIME_PROFILING + TimeProfileBegin(); +#endif + + vAfterCalibration(p); + +#ifdef ENABLE_POST_PACKAGE_REPAIR + PostPackageRepair(); +#endif + +#if __Petrus_TO_BE_PORTING__ + +#if 0//TX_OE_CALIBATION, for DMA test + U8 u1ChannelIdx, u1RankIdx; + for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++) + for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + vSetRank(p, u1RankIdx); + DramcTxOECalibration(p); + } + + vSetPHY2ChannelMapping(p, CHANNEL_A); + vSetRank(p, RANK_0); + + U32 u4err_value; + DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_PREPARE_DATA_ONLY, p->support_channel_num); + u4err_value = DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_CHECK_DATA_ACCESS_AND_COMPARE, p->support_channel_num); + mcSHOW_DBG_MSG(("DramC_TX_OE_Calibration 0x%X\n", u4err_value)); +#endif + +#if !LCPLL_IC_SCAN +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + print_DBG_info(p); + Dump_EMIRegisters(p); +#endif +#endif + +#if 0 + DramcRegDump(p, SRAM_SHU0); +#endif + +// ETT_NO_DRAM #endif + +#if ETT_NO_DRAM + //NoDramDramcRegDump(p); + NoDramRegFill(); +#endif +#endif //#if __Petrus_TO_BE_PORTING__ + + #if DRAMC_MODEREG_CHECK + DramcModeReg_Check(p); + #endif + + #if __FLASH_TOOL_DA__ + vPrintPinInfoResult(p); + vGetErrorTypeResult(p); + #endif + #if CPU_RW_TEST_AFTER_K + mcSHOW_DBG_MSG(("\n[MEM_TEST] 02: After DFS, before run time config\n")); + vDramCPUReadWriteTestAfterCalibration(p); +#endif + + #if TA2_RW_TEST_AFTER_K + mcSHOW_DBG_MSG(("\n[TA2_TEST]\n")); + TA2_Test_Run_Time_HW(p); + #endif + +#if __ETT__ +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + if (!(p->femmc_Ready == 0)) +#elif defined(DDR_INIT_TIME_PROFILING) +if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of loop +#endif +#endif + { + EnableDFSHwModeClk(p); + mcSHOW_DBG_MSG(("DFS_SHUFFLE_HW_MODE: ON\n")); + if (gAndroid_DVFS_en == TRUE) // shuffle to DDR3733 boot + { +#if defined(SLT) + final_shu = SRAM_SHU1; //DDR3200 +#else + final_shu = SRAM_SHU0; //DDR4266 +#endif + + vSetDFSFreqSelByTable(p, get_FreqTbl_by_shuffleIndex(p, final_shu)); + DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU1); + DramcDFSDirectJump_SRAMShuRGMode(p, final_shu); + print("switch to %d Mbps bootup\n", p->frequency * 2); + } + + +#if __Petrus_TO_BE_PORTING__ + #if (DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM && defined(DUMMY_READ_FOR_TRACKING)) + DramcDummyReadForSPMSideBand(p); // SPM dummy read 1us <-> 4us for DVT only (it must call after TransferPLLToSPMControl) + #endif + + EnableDramcTrackingBySPMControl(p); + + mcSHOW_DBG_MSG(("\n\nSettings after calibration\n\n")); + mcDUMP_REG_MSG(("\n\nSettings after calibration\n\n")); +#endif + + DramcRunTimeConfig(p); + } + + #if CPU_RW_TEST_AFTER_K + mcSHOW_DBG_MSG(("\n[MEM_TEST] 03: After run time config\n")); + vDramCPUReadWriteTestAfterCalibration(p); + #endif + + #if TA2_RW_TEST_AFTER_K + mcSHOW_DBG_MSG(("\n[TA2_TEST]\n")); + TA2_Test_Run_Time_HW(p); + #endif + + +#if (__ETT__ && CPU_RW_TEST_AFTER_K) + /* 0x46000000 is LK base addr */ + //while(1) + { + //if ((s4value = dramc_complex_mem_test (0x46000000, 0x2000)) == 0) + if ((s4value = dramc_complex_mem_test (0x40024000, 0x20000)) == 0) + { + mcSHOW_DBG_MSG(("1st complex R/W mem test pass\n")); + } + else + { + mcSHOW_DBG_MSG(("1st complex R/W mem test fail :-%d\n", -s4value)); +#if defined(SLT) + mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000\n")); + while (1); +#endif + } + } +#endif + +#if MRW_CHECK_ONLY + vPrintFinalModeRegisterSetting(p); +#endif + +#ifdef DDR_INIT_TIME_PROFILING + CPU_Cycle = TimeProfileEnd(); + mcSHOW_TIME_MSG((" (5) After calibration takes %d ms\n\r", CPU_Cycle / 1000)); +#endif // end of DDR_INIT_TIME_PROFILING + +#endif//SW_CHANGE_FOR_SIMULATION + //Low_Power_Scenarios_Test(p); + + //vSetDFSFreqSelByTable(p, get_FreqTbl_by_shuffleIndex(p, SRAM_SHU1)); + //DramcDFSDirectJump(p, SRAM_SHU1);//Switch to CLRPLL + + //ETT_DRM(p); + return 0; +} +///TODO: wait for porting --- + + +///TODO: wait for porting +++ +static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t *psra) +{ + U8 ii; + + ///TODO: wait for porting +++ +#if GATING_ADJUST_TXDLY_FOR_TRACKING + DramcRxdqsGatingPreProcess(DramConfig); +#endif + ///TODO: wait for porting --- + + vAutoRefreshSwitch(DramConfig, DISABLE); + +#if 1//(SIMUILATION_CBT == 1) + for (ii = RANK_0; ii < DramConfig->support_rank_num; ii++) + { + vSetRank(DramConfig, ii); + + if (!psra || psra->cbt) { + mcSHOW_DBG_MSG(("\n----->DramcCBT begin...\n")); + timestamp_show(); + #if CBT_O1_PINMUX_WORKAROUND + CmdBusTrainingLP45(DramConfig, AUTOK_OFF); //Cannot use aito-k in A60868 + #else + if (psra) + CmdBusTrainingLP45(DramConfig, psra->cbt_autok); + else + CmdBusTrainingLP45(DramConfig, AUTOK_OFF); + #endif + timestamp_show(); + mcSHOW_DBG_MSG(("DramcCBT end<-----\n\n")); + } + #if ENABLE_EYESCAN_GRAPH + mcSHOW_DBG_MSG(("CBT EYESCAN start<-----\n\n")); + print_EYESCAN_LOG_message(DramConfig, 0); //draw CBT eyescan + mcSHOW_DBG_MSG(("CBT EYESCAN end<-----\n\n")); + #endif + } + + vSetRank(DramConfig, RANK_0); + + ///TODO: wait for porting +++ +#if __A60868_TO_BE_PORTING__ + No_Parking_On_CLRPLL(DramConfig); +#endif // __A60868_TO_BE_PORTING__ + ///TODO: wait for porting --- +#endif /* (SIMUILATION_CBT == 1) */ + + for (ii = RANK_0; ii < DramConfig->support_rank_num; ii++) + { + vSetRank(DramConfig, ii); + + vAutoRefreshSwitch(DramConfig, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable + +#if 1//(SIMULATION_WRITE_LEVELING == 1) +#if (!WCK_LEVELING_FM_WORKAROUND) + if (u1IsLP4Family(DramConfig->dram_type)) +#endif + { + if (!(u1IsLP4Div4DDR800(DramConfig) && (DramConfig->rank == RANK_1))) // skip for DDR800 rank1 + { + if (!psra || psra->wl) { + mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); + timestamp_show(); + if (psra) + { + DramcWriteLeveling(DramConfig, psra->wl_autok, PI_BASED); + } + else + DramcWriteLeveling(DramConfig, AUTOK_OFF, PI_BASED); + + timestamp_show(); + mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n")); + } + } + } +#endif /* (SIMULATION_WRITE_LEVELING == 1) */ + + vAutoRefreshSwitch(DramConfig, ENABLE); + +#if 1//(SIMULATION_GATING == 1) + if (!psra || psra->gating) { + mcSHOW_DBG_MSG(("\n----->DramcGating begin...\n")); + timestamp_show(); + if (psra) + dramc_rx_dqs_gating_cal(DramConfig, psra->gating_autok, 0); + else + dramc_rx_dqs_gating_cal(DramConfig, AUTOK_OFF, 0); + timestamp_show(); + mcSHOW_DBG_MSG(("DramcGating end < -----\n\n")); + } +#endif + +#if 1//(SIMULATION_RX_RDDQC == 1) + if (!psra || psra->rddqc) { + mcSHOW_DBG_MSG(("\n----->DramcRxWindowPerbitCal RDDQC begin...\n")); + timestamp_show(); + + #if 0 // Used when testing LP5 RK1 WCK2CK in high efficiency mode and differential mode. + p->rank = 1; + // For test HEFF = 1 / WCKDUAL = 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL), 0, SHU_WCKCTRL_WCKDUAL); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), + P_Fld(1, SHU_COMMON0_LP5WCKON) | + P_Fld(1, SHU_COMMON0_LP5HEFF_MODE)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 0, CKECTRL_CKE2RANK_OPT8); + #endif + DramcRxWindowPerbitCal(DramConfig, PATTERN_RDDQC, NULL, AUTOK_OFF); + timestamp_show(); + mcSHOW_DBG_MSG(("DramcRxWindowPerbitCal end<-----\n\n")); + } +#endif // (SIMULATION_RX_RDDQC == 1) + +#if (__LP5_COMBO__ == TRUE) +#if (SIMULATION_DUTY_CYC_MONITOR == 1) + if (is_lp5_family(DramConfig) && DramConfig->frequency >= GetFreqBySel(DramConfig,LP5_DDR4266)) + { + if (!psra) { + mcSHOW_DBG_MSG(("\n----->DramcDutyCycleMonitor begin...\n")); + timestamp_show(); + DramcDutyCycleMonitor(DramConfig); + timestamp_show(); + mcSHOW_DBG_MSG(("DramcDutyCycleMonitor end<-----\n\n")); + + mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(DLY) begin...\n")); + timestamp_show(); + DramcWriteLeveling(DramConfig, psra->wl_autok, DLY_BASED); + timestamp_show(); + mcSHOW_DBG_MSG(("DramcWriteLeveling(DLY)end<-----\n\n")); + } + } +#endif /* (SIMULATION_DUTY_CYC_MONITOR == 1) */ +#endif // (__LP5_COMBO__ == TRUE) + +#if 1//(SIMULATION_TX_PERBIT == 1) + if (!psra || psra->tx_perbit) { + mcSHOW_DBG_MSG(("\n----->DramcTxWindowPerbitCal begin...\n")); + timestamp_show(); + if (psra) + DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM, + FALSE, psra->tx_auto_cal); + else + DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM, + FALSE, AUTOK_OFF); + if (Get_Vref_Calibration_OnOff(DramConfig) == VREF_CALI_ON) { + if (psra) + DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY, + TRUE, psra->tx_auto_cal); + else + DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY, + TRUE, AUTOK_OFF); + } + if (psra) + DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY, + FALSE, psra->tx_auto_cal); + else + DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY, + FALSE, AUTOK_OFF); + timestamp_show(); + mcSHOW_DBG_MSG(("DramcTxWindowPerbitCal end<-----\n\n")); + + #if ENABLE_EYESCAN_GRAPH + mcSHOW_DBG_MSG(("\n----->DramcTxEYESCAN begin...\n")); + Dramc_K_TX_EyeScan_Log(DramConfig); + print_EYESCAN_LOG_message(DramConfig, 2); //draw TX eyescan + mcSHOW_DBG_MSG(("\n----->DramcTxEYESCAN end...\n")); + #endif + } +#endif // (SIMULATION_TX_PERBIT == 1) + +#if 1//(SIMULATION_DATLAT == 1) + if (1) { // No parameter in correspondence with by now + mcSHOW_DBG_MSG(("\n----->DramcRxdatlatCal begin...\n")); + timestamp_show(); + + DramcRxdatlatCal(DramConfig); + + timestamp_show(); + mcSHOW_DBG_MSG(("DramcRxdatlatCal end<-----\n\n")); + } +#endif // (SIMULATION_DATLAT == 1) + +#if 1//(SIMULATION_RX_PERBIT == 1) + if (!psra || psra->rx_perbit) { + mcSHOW_DBG_MSG(("\n----->DramcRxWindowPerbitCal begin...\n")); + timestamp_show(); + if (psra) + DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, + NULL /*Set Vref = 0 to test*/, psra->rx_auto_cal); + else + DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, + NULL /*Set Vref = 0 to test*/, AUTOK_OFF); + timestamp_show(); + mcSHOW_DBG_MSG(("DramcRxWindowPerbitCal end<-----\n\n")); + + #if ENABLE_EYESCAN_GRAPH + mcSHOW_DBG_MSG(("DramcRxWindowPerbitCal EYESCAN start<-----\n\n")); + print_EYESCAN_LOG_message(DramConfig, 1); //draw RX eyescan + mcSHOW_DBG_MSG(("DramcRxWindowPerbitCal EYESCAN end<-----\n\n")); + #endif + } +#endif // (SIMULATION_RX_PERBIT == 1) + +#if (SIMULATION_RX_DVS == 1) + if (DramConfig->frequency >=2133) + DramcRxDVSWindowCal(DramConfig); +#endif + +#if TX_OE_CALIBATION + if (DramConfig->frequency >= 1600) + { + DramcTxOECalibration(DramConfig); + } +#endif // TX_OE_CALIBATION + + #if ENABLE_TX_TRACKING + #if 0 /* Starting from Vinson, no need to pre-calculate MR23 for different freqs */ + if (gu1MR23Done == FALSE) + { + DramcDQSOSCAuto(p); + } + #endif + DramcDQSOSCAuto(DramConfig); + DramcDQSOSCMR23(DramConfig); + DramcDQSOSCSetMR18MR19(DramConfig); + #endif + } + + vSetRank(DramConfig, RANK_0); + + #if ENABLE_TX_TRACKING + DramcDQSOSCShuSettings(DramConfig); + #endif + +///TODO: wait for porting +++ +#if GATING_ADJUST_TXDLY_FOR_TRACKING + DramcRxdqsGatingPostProcess(DramConfig); +#endif + +#if TDQSCK_PRECALCULATION_FOR_DVFS + DramcDQSPrecalculation_preset(DramConfig); +#endif + +#if SIMULATION_RX_DVS + if (DramConfig->frequency >=2133) + DramcDramcRxDVSCalPostProcess(DramConfig); +#endif + +#if XRTWTW_NEW_CROSS_RK_MODE + if (DramConfig->support_rank_num == RANK_DUAL) + { + XRTWTW_SHU_Setting(DramConfig); + } +#endif + +#if DV_SIMULATION_DATLAT + DramcDualRankRxdatlatCal(DramConfig); +#endif + +#if RDSEL_TRACKING_EN + if (DramConfig->frequency != 400) + RDSELRunTimeTracking_preset(DramConfig); +#endif + +///TODO: wait for porting --- + +} + +static void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t *psra) +{ + U8 channel_idx, rank_idx; + + CKEFixOnOff(DramConfig, CKE_WRITE_TO_ALL_RANK, CKE_FIXOFF, CKE_WRITE_TO_ALL_CHANNEL); + for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++) + { + vSetPHY2ChannelMapping(DramConfig, channel_idx);// when switching channel, must update PHY to Channel Mapping + CKEFixOnOff(DramConfig, CKE_WRITE_TO_ALL_RANK, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + DPI_vDramCalibrationSingleChannel(DramConfig, psra); + } + + vSetPHY2ChannelMapping(DramConfig, CHANNEL_A); + +///TODO: wait for porting +++ +#if ENABLE_READ_DBI + DramcReadDBIOnOff(DramConfig, DramConfig->DBI_R_onoff[DramConfig->dram_fsp]); +#endif + +#if ENABLE_WRITE_DBI + // Just settle the DBI parameters which would be stored into shuffle space. + if (DramConfig->DBI_W_onoff[DramConfig->dram_fsp]) + { + for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++) + { + vSetPHY2ChannelMapping(DramConfig, channel_idx); + + for (rank_idx = RANK_0; rank_idx < DramConfig->support_rank_num; rank_idx++) + { + vSetRank(DramConfig, rank_idx); + DramcWriteShiftMCKForWriteDBI(DramConfig, -1); //Tx DQ/DQM -1 MCK for write DBI ON + } + vSetRank(DramConfig, RANK_0); + } + vSetPHY2ChannelMapping(DramConfig, CHANNEL_A); + + // Improve Write DBI Power + ApplyWriteDBIPowerImprove(DramConfig, ENABLE); + + #if ENABLE_WRITE_DBI_Protect + ApplyWriteDBIProtect(DramConfig, ENABLE); + #endif + } + DramcWriteDBIOnOff(DramConfig, DramConfig->DBI_W_onoff[DramConfig->dram_fsp]); + + +#endif + +#if XRTRTR_NEW_CROSS_RK_MODE + if (DramConfig->support_rank_num == RANK_DUAL) + { + XRTRTR_SHU_Setting(DramConfig); + } +#endif + +#if DV_SIMULATION_DFS +#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS) + FreqJumpRatioCalculation(DramConfig); +#endif +#endif + +#ifdef TEMP_SENSOR_ENABLE + DramcHMR4_Presetting(DramConfig); +#endif + +#if (ENABLE_PER_BANK_REFRESH == 1) + DramcEnablePerBankRefresh(DramConfig, ON); +#else + DramcEnablePerBankRefresh(DramConfig, OFF); +#endif + +#if ENABLE_TX_TRACKING + U8 backup_channel = DramConfig->channel; + U8 channelIdx; + + for (channelIdx = CHANNEL_A; channelIdx < DramConfig->support_channel_num; channelIdx++) + { + vSetPHY2ChannelMapping(DramConfig, channelIdx); + DramcHwDQSOSC(DramConfig); + } + + vSetPHY2ChannelMapping(DramConfig, backup_channel); + mcSHOW_DBG_MSG(("TX_TRACKING: ON\n")); +#else + mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n")); +#endif + +///TODO: wait for porting --- + +} + +///TODO: wait for porting +++ +#if __A60868_TO_BE_PORTING__ +void RG_dummy_write(DRAMC_CTX_T *p, U32 pattern) +{ + unsigned int ii; + for (ii = 0; ii < 20; ii++) + vIO32WriteFldAlign(DDRPHY_RFU_0X1D4, pattern, RFU_0X1D4_RESERVED_0X1D4); +} + +void EnablePLLtoSPMControl(DRAMC_CTX_T *p) +{ + vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL); // DFS SPM mode for calibration +} +#endif // __A60868_TO_BE_PORTING__ +///TODO: wait for porting --- + +void dump_dramc_ctx(DRAMC_CTX_T *p) +{ + mcSHOW_DBG_MSG(("== DRAMC_CTX_T ==\n")); + mcSHOW_DBG_MSG(("support_channel_num: %d\n", p->support_channel_num)); + mcSHOW_DBG_MSG(("channel: %d\n", p->channel)); + mcSHOW_DBG_MSG(("support_rank_num: %d\n", p->support_rank_num)); + mcSHOW_DBG_MSG(("rank: %d\n", p->rank)); + mcSHOW_DBG_MSG(("freq_sel: %d\n", p->freq_sel)); + mcSHOW_DBG_MSG(("shu_type: %d\n", p->shu_type)); + mcSHOW_DBG_MSG(("dram_type: %d\n", p->dram_type)); + mcSHOW_DBG_MSG(("dram_fsp: %d\n", p->dram_fsp)); + mcSHOW_DBG_MSG(("odt_onoff: %d\n", p->odt_onoff)); + mcSHOW_DBG_MSG(("dram_cbt_mode: %d, %d\n", (int)p->dram_cbt_mode[0], (int)p->dram_cbt_mode[1])); + mcSHOW_DBG_MSG(("DBI_R_onoff: %d, %d\n", (int)p->DBI_R_onoff[0], (int)p->DBI_R_onoff[1])); + mcSHOW_DBG_MSG(("DBI_W_onoff: %d, %d\n", (int)p->DBI_W_onoff[0], (int)p->DBI_W_onoff[1])); + mcSHOW_DBG_MSG(("data_width: %d\n", p->data_width)); + mcSHOW_DBG_MSG(("test2_1: 0x%x\n", p->test2_1)); + mcSHOW_DBG_MSG(("test2_2: 0x%x\n", p->test2_2)); + mcSHOW_DBG_MSG(("frequency: %d\n", p->frequency)); + mcSHOW_DBG_MSG(("freqGroup: %d\n", p->freqGroup)); + mcSHOW_DBG_MSG(("lp5_training_mode: %d\n", p->lp5_training_mode)); + mcSHOW_DBG_MSG(("lp5_cbt_phase: %d\n", p->lp5_cbt_phase)); + mcSHOW_DBG_MSG(("new_cbt_mode: %d\n", p->new_cbt_mode)); + mcSHOW_DBG_MSG(("u1PLLMode: %d\n", p->u1PLLMode)); + mcSHOW_DBG_MSG(("curDBIState: %d\n", p->curDBIState)); +} + + +void DPI_SW_main_LP4(DRAMC_CTX_T *ExtConfig, cal_sv_rand_args_t *psra) +{ + u32 value; +#if DV_SIMULATION_DFS + S8 s1ShuIdx; +#endif + + DRAMC_CTX_T *p = &DramCtx_LPDDR4; //default; + + p->dram_type = ExtConfig->dram_type; + if(p->dram_type==TYPE_LPDDR5) + { + MEM_TYPE = LPDDR5; + } + else + { + MEM_TYPE = LPDDR4; + } + + p->dram_cbt_mode[0] = ExtConfig->dram_cbt_mode[0]; + p->dram_cbt_mode[1] = ExtConfig->dram_cbt_mode[1]; + p->freq_sel = ExtConfig->freq_sel; + p->frequency = ExtConfig->frequency; + p->freqGroup = ExtConfig->freqGroup; + p->new_cbt_mode = ExtConfig->new_cbt_mode; + +#if 0 // for Refs +DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = { + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. + {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. + {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. + {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) +}; +#endif + if (u1IsLP4Family(p->dram_type)) + { + if((ExtConfig->freq_sel==LP4_DDR3733) || (ExtConfig->freq_sel==LP4_DDR4266)) + { + p->pDFSTable = &gFreqTbl[1]; + } + else if(ExtConfig->freq_sel==LP4_DDR1600) + { + p->pDFSTable = &gFreqTbl[6]; + } + else if(ExtConfig->freq_sel==LP4_DDR800) + { + p->pDFSTable = &gFreqTbl[2]; + } + /*else if(ExtConfig->freq_sel==LP4_DDR400) + { + p->pDFSTable = &gFreqTbl[2]; + }*/ + } + + enter_function(); + + if (!psra) { + /* + * for SA's simulation + */ + mcSHOW_DBG_MSG(("enter SA's simulation flow.\n")); + p->support_channel_num = CHANNEL_SINGLE; + p->channel = CHANNEL_A; + p->support_rank_num = RANK_DUAL; + /* DramRank */ + p->rank = RANK_0; + /* DRAMC operation clock frequency in MHz */ + #if (fcFOR_CHIP_ID == fcA60868) + #if DV_SIMULATION_DFS + p->pDFSTable = &gFreqTbl[DRAM_DFS_SHUFFLE_2]; + p->shu_type = DRAM_DFS_SHUFFLE_2; + #endif + #endif +#if 0 + /* DRAM type */ + #if DV_SIMULATION_LP4 + p->dram_type = TYPE_LPDDR4X; + //p->freq_sel = LP4_DDR3200;//DV_SIMULATION_RUN_FREQ_SEL; + //p->frequency = 1600;//DV_SIMULATION_RUN_FREQ; + p->freq_sel = LP4_DDR1600;//DV_SIMULATION_RUN_FREQ_SEL; + p->frequency = 800;//DV_SIMULATION_RUN_FREQ; + #else + p->dram_type = TYPE_LPDDR5; + p->freq_sel = LP5_DDR3200;//DV_SIMULATION_RUN_FREQ_SEL; + p->frequency = 1600;//DV_SIMULATION_RUN_FREQ; + #endif +#endif + /* DRAM Fast switch point type, only for LP4, useless in LP3 */ + p->dram_fsp = FSP_0; + +#if 0 + #if DV_SIMULATION_BYTEMODE + p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1; + p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1; + #else + p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; + p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; + #endif +#endif + /* IC and DRAM read DBI */ + p->DBI_R_onoff[FSP_0] = DBI_OFF; /* only for LP4, uesless in LP3 */ + p->DBI_R_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + #if ENABLE_READ_DBI + p->DBI_R_onoff[FSP_1] = DBI_ON; /* only for LP4, uesless in LP3 */ + #else + p->DBI_R_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + #endif + /* IC and DRAM write DBI */ + p->DBI_W_onoff[FSP_0] = DBI_OFF; /* only for LP4, uesless in LP3 */ + p->DBI_W_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + #if ENABLE_WRITE_DBI + p->DBI_W_onoff[FSP_1] = DBI_ON; /* only for LP4, uesless in LP3 */ + #else + p->DBI_W_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + #endif + /* bus width */ + p->data_width = DATA_WIDTH_16BIT; + /* DRAMC internal test engine-2 parameters in calibration */ + p->test2_1 = DEFAULT_TEST2_1_CAL; + p->test2_2 = DEFAULT_TEST2_2_CAL; + /* DRAMC test pattern in calibration */ + p->test_pattern = TEST_XTALK_PATTERN; + /* u2DelayCellTimex100 */ + p->u2DelayCellTimex100 = 250; // @Darren, 2.5ps + p->vendor_id = 0x1; + p->density = 0; + /* p->ranksize = {0,0}; */ + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + #if DV_SIMULATION_LP5_TRAINING_MODE1 + p->lp5_training_mode = TRAINING_MODE1; + #else + p->lp5_training_mode = TRAINING_MODE2; + #endif + + #if DV_SIMULATION_LP5_CBT_PHASH_R + p->lp5_cbt_phase = CBT_PHASE_RISING; + #else + p->lp5_cbt_phase = CBT_PHASE_FALLING; + #endif + } else { + /* + * for DV's regression + */ + mcSHOW_DBG_MSG(("enter DV's regression flow.\n")); + p->support_channel_num = CHANNEL_SINGLE; + p->channel = psra->calibration_channel; + p->support_rank_num = RANK_DUAL; + /* DramRank */ + p->rank = psra->calibration_rank; + /* DRAMC operation clock frequency in MHz */ + #if (fcFOR_CHIP_ID == fcA60868) + #if DV_SIMULATION_DFS + p->pDFSTable = &gFreqTbl[DRAM_DFS_SHUFFLE_2]; + p->shu_type = DRAM_DFS_SHUFFLE_2; + #endif + #endif + + /* DRAM type */ + //p->dram_type = psra->dram_type; + //p->freq_sel = LP5_DDR4266;//DV_SIMULATION_RUN_FREQ_SEL; + //p->frequency = 2133;//DV_SIMULATION_RUN_FREQ; + //set_type_freq_by_svargs(p, psra); + + /* DRAM Fast switch point type, only for LP4, useless in LP3 */ + p->dram_fsp = FSP_0; + + p->dram_cbt_mode[RANK_0] = psra->rk0_cbt_mode; + p->dram_cbt_mode[RANK_1] = psra->rk1_cbt_mode; + + /* IC and DRAM read DBI */ + p->DBI_R_onoff[FSP_0] = (psra->mr3_value >> 6) & 0x1; /* only for LP4, uesless in LP3 */ + p->DBI_R_onoff[FSP_1] = (psra->mr3_value >> 6) & 0x1; /* only for LP4, uesless in LP3 */ + p->DBI_R_onoff[FSP_2] = (psra->mr3_value >> 6) & 0x1; + /* IC and DRAM write DBI */ + p->DBI_W_onoff[FSP_0] = (psra->mr3_value >> 7) & 0x1; /* only for LP4, uesless in LP3 */ + p->DBI_W_onoff[FSP_1] = (psra->mr3_value >> 7) & 0x1; /* only for LP4, uesless in LP3 */ + p->DBI_W_onoff[FSP_2] = (psra->mr3_value >> 7) & 0x1; + /* bus width */ + p->data_width = DATA_WIDTH_16BIT; + /* DRAMC internal test engine-2 parameters in calibration */ + p->test2_1 = DEFAULT_TEST2_1_CAL; + p->test2_2 = DEFAULT_TEST2_2_CAL; + /* DRAMC test pattern in calibration */ + p->test_pattern = TEST_XTALK_PATTERN; + /* u2DelayCellTimex100 */ + p->u2DelayCellTimex100 = 0; + p->vendor_id = 0x1; + p->density = 0; + /* p->ranksize = {0,0}; */ + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; + p->lp5_training_mode = psra->cbt_training_mode; + p->lp5_cbt_phase = psra->cbt_phase; + p->new_cbt_mode = psra->new_cbt_mode; + } + +#if QT_GUI_Tool + p->lp5_training_mode = ExtConfig->lp5_training_mode; +#endif + + if (psra && is_lp5_family(p)) { + p->dram_fsp = (psra->mr16_value >> 2) & 0x3; + } else if (psra && u1IsLP4Family(p->dram_type)) { + p->dram_fsp = (psra->mr13_value >> 7) & 0x1; + } + +// p->dram_type = TYPE_LPDDR5; +// #define __FW_VER__ "WCK leveling with DLY +16! and MRinit for FSP1 -- 777" + #define __FW_VER__ "All struct move done, new RX range -- 444" + + if (u1IsLP4Family(p->dram_type)) { + mcSHOW_DBG_MSG(("%s enter == LP4 == ...%s\n", __FUNCTION__, __FW_VER__)); + } else { + mcSHOW_DBG_MSG(("%s enter == LP5 == ...%s\n", __FUNCTION__, __FW_VER__)); + } + mcSHOW_DBG_MSG((CHK_INCLUDE_LOCAL_HEADER)); + + mcSHOW_DBG_MSG(("SIMULATION_LP4_ZQ ... %d\n", SIMULATION_LP4_ZQ)); + mcSHOW_DBG_MSG(("SIMULATION_SW_IMPED ... %d\n", SIMULATION_SW_IMPED)); + mcSHOW_DBG_MSG(("SIMULATION_MIOCK_JMETER ... %d\n", SIMULATION_MIOCK_JMETER)); + mcSHOW_DBG_MSG(("SIMULATION_8PHASE ... %d\n", SIMULATION_8PHASE)); + mcSHOW_DBG_MSG(("SIMULATION_RX_INPUT_BUF ... %d\n", SIMULATION_RX_INPUT_BUF)); + mcSHOW_DBG_MSG(("SIMUILATION_CBT ... %d\n", SIMUILATION_CBT)); + mcSHOW_DBG_MSG(("SIMULATION_WRITE_LEVELING ... %d\n", SIMULATION_WRITE_LEVELING)); + mcSHOW_DBG_MSG(("SIMULATION_DUTY_CYC_MONITOR ... %d\n", SIMULATION_DUTY_CYC_MONITOR)); + mcSHOW_DBG_MSG(("SIMULATION_GATING ... %d\n", SIMULATION_GATING)); + mcSHOW_DBG_MSG(("SIMULATION_DATLAT ... %d\n", SIMULATION_DATLAT)); + mcSHOW_DBG_MSG(("SIMULATION_RX_RDDQC ... %d\n", SIMULATION_RX_RDDQC)); + mcSHOW_DBG_MSG(("SIMULATION_RX_PERBIT ... %d\n", SIMULATION_RX_PERBIT)); + mcSHOW_DBG_MSG(("SIMULATION_TX_PERBIT ... %d\n", SIMULATION_TX_PERBIT)); + mcSHOW_DBG_MSG(("\n\n")); + + mcSHOW_DBG_MSG(("============== CTX before calibration ================\n")); + dump_dramc_ctx(p); + + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + + //vIO32Write4B_All2(p, DDRPHY_SHU_RK_CA_CMD1, 0x0FFF); + value = u4Dram_Register_Read(p, DRAMC_REG_DDRCOMMON0); + mcSHOW_DBG_MSG(("Get Addr:0x%x, Value:0x%x\n", DRAMC_REG_DDRCOMMON0, value)); + + value = u4Dram_Register_Read(p, DDRPHY_REG_SHU_RK_CA_CMD1); + mcSHOW_DBG_MSG(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_SHU_RK_CA_CMD1, value)); + + value = u4Dram_Register_Read(p, DDRPHY_REG_MISC_DQO1); + mcSHOW_DBG_MSG(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_MISC_DQO1, value)); + + value = u4Dram_Register_Read(p, DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL ); + mcSHOW_DBG_MSG(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL, value)); + + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on + + Global_Option_Init(p); + +#if __A60868_TO_BE_PORTING__ + vDramcInit_PreSettings(p); + + DDRPhyFreqSel(p, p->pDFSTable->freq_sel); + + vSetPHY2ChannelMapping(p, p->channel); +#endif // __A60868_TO_BE_PORTING__ + ///TODO: wait for porting --- + + + if (u1IsLP4Family(p->dram_type)) + { + vSetDFSFreqSelByTable(p, p->pDFSTable); // for LP4x + } + else ///TODO: Jeremy, modify this when LP5 gFreqtbl ready + { + DDRPhyFreqSel(p, p->freq_sel); + } + +#if (SIMULATION_SW_IMPED == 1) + mcSHOW_DBG_MSG(("\n----->DramcSwImpedanceCal begin...\n")); + timestamp_show(); + // LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 + // LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 + DramcSwImpedanceCal(p, 1, IMP_LOW_FREQ); + DramcSwImpedanceCal(p, 1, IMP_HIGH_FREQ); + timestamp_show(); + mcSHOW_DBG_MSG(("DramcSwImpedanceCal end<-----\n\n")); +#endif /* (SIMULATION_SW_IMPED == 1) */ + +#if DV_SIMULATION_INIT_C + ///TODO: wait for porting +++ + DramcInit(p); + + // Before calibration setting + vBeforeCalibration(p); +#if __A60868_TO_BE_PORTING__ + #if DV_SIMULATION_BEFORE_K + vApplyConfigBeforeCalibration(p); + //vMR2InitForSimulationTest(p); + #endif + +#ifdef DUMP_INIT_RG_LOG_TO_DE + #if 0 //Dump RG to other shuffle for FT used, don't delete + mcSHOW_DUMP_INIT_RG_MSG(("\n\n\n\n\n\n===== Save to Shuffle RG ======\n")); + DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3); + #endif + while (1); +#endif +#endif +#endif // __A60868_TO_BE_PORTING__ + ///TODO: wait for porting --- + + +#if (SIMULATION_MIOCK_JMETER == 1) + mcSHOW_DBG_MSG(("\n----->DramcMiockJmeter begin...\n")); + timestamp_show(); + PRE_MIOCK_JMETER_HQA_USED(p); + timestamp_show(); + mcSHOW_DBG_MSG(("DramcMiockJmeter end<-----\n\n")); +#endif /* (SIMULATION_MIOCK_JMETER == 1) */ + +#if (SIMULATION_8PHASE == 1) + if(is_lp5_family(p) && (p->frequency >= 2133)) { + mcSHOW_DBG_MSG(("\n----->Dramc8PhaseCal begin...\n")); + timestamp_show(); + Dramc8PhaseCal(p); // it must set before duty calib + timestamp_show(); + mcSHOW_DBG_MSG(("Dramc8PhaseCal end<-----\n\n")); + } +#endif /* (SIMULATION_8PHASE == 1) */ + + ///TODO: wait for porting +++ + #if !DV_SIMULATION_DFS // No calib will use legacy mode init settings + DPI_vDramCalibrationAllChannel(p, psra); // for DDR1600 1:8 mode + #endif + +#if DV_SIMULATION_DFS + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, p->pDFSTable->shuffleIdx); + LoadShuffleSRAMtoDramc(p, p->pDFSTable->shuffleIdx, DRAM_DFS_SHUFFLE_2); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + #if ENABLE_SRAM_DMA_WA + DPHYSaveToSRAMShuWA(p, p->pDFSTable->shuffleIdx); + #endif + + #if (fcFOR_CHIP_ID == fcA60868) + for (s1ShuIdx = DRAM_DFS_SHUFFLE_MAX - 10; s1ShuIdx >= DRAM_DFS_SHUFFLE_1; s1ShuIdx--) + #else + for (s1ShuIdx = DRAM_DFS_SHUFFLE_MAX - 2; s1ShuIdx >= DRAM_DFS_SHUFFLE_1; s1ShuIdx--) + #endif + { + vSetDFSFreqSelByTable(p, &gFreqTbl[s1ShuIdx]); + DramcInit(p); + // Before calibration setting + vBeforeCalibration(p); + + #if DV_SIMULATION_BEFORE_K + vApplyConfigBeforeCalibration(p); + #endif + + #if (SIMULATION_8PHASE == 1) + if(is_lp5_family(p) && (p->frequency >= 2133)) { + mcSHOW_DBG_MSG(("\n----->Dramc8PhaseCal begin...\n")); + timestamp_show(); + Dramc8PhaseCal(p); // it must set before duty calib + timestamp_show(); + mcSHOW_DBG_MSG(("Dramc8PhaseCal end<-----\n\n")); + } + #endif /* (SIMULATION_8PHASE == 1) */ + + #if !DV_SIMULATION_DFS // No calib will use legacy mode init settings + DPI_vDramCalibrationAllChannel(p, psra); // for gDVDFSTbl + #endif + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[s1ShuIdx].shuffleIdx); + #if ENABLE_SRAM_DMA_WA + DPHYSaveToSRAMShuWA(p, gFreqTbl[s1ShuIdx].shuffleIdx); + #endif + } +#endif + ///TODO: wait for porting --- + + + + + ///TODO: wait for porting +++ + vAfterCalibration(p); + +#if SIMULATION_RUNTIME_CONFIG + DramcRunTimeConfig(p); +#endif + +#if __A60868_TO_BE_PORTING__ +#if DV_SIMULATION_AFTER_K + vApplyConfigAfterCalibration(p); +#endif + +#if DV_SIMULATION_RUN_TIME_MRW + enter_pasr_dpd_config(0, 0xFF); +#endif + +#if DV_SIMULATION_RUN_TIME_MRR + DramcModeRegReadByRank(p, RANK_0, 4, &u2val1); + DramcModeRegReadByRank(p, RANK_0, 5, &u2val2); + DramcModeRegReadByRank(p, RANK_0, 8, &u2val3); + mcSHOW_DBG_MSG(("[Runtime time MRR] MR4 = 0x%x, MR5 = 0x%x, MR8 = 0x%x\n", u2val1, u2val2, u2val3)); +#endif + +#if 0//DV_SIMULATION_DFS // NOTE: Don't use DramcDFSDirectJump_SPMMode. it will cause NULL object access. + // high freq -> low freq + for (s1ShuIdx = 0; s1ShuIdx < DV_SIMULATION_DFS_SHU_MAX; s1ShuIdx++) + DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].shuffleIdx); + // low freq -> high freq + for (s1ShuIdx = DV_SIMULATION_DFS_SHU_MAX - 1; s1ShuIdx >= DRAM_DFS_SHUFFLE_1; s1ShuIdx--) + DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].shuffleIdx); +#endif + +#if DV_SIMULATION_SPM_CONTROL + EnablePLLtoSPMControl(p); +#endif + + RG_dummy_write(p, 0xAAAAAAAA); +#endif // __A60868_TO_BE_PORTING__ + ///TODO: wait for porting --- + + //Temp_TA2_Test_After_K(p); + + //Ett_Mini_Strss_Test(p); +#if MRW_CHECK_ONLY + vPrintFinalModeRegisterSetting(p); +#endif +#if PRINT_CALIBRATION_SUMMARY + vPrintCalibrationResult(p); +#endif + + exit_function(); +} + +///TODO: wait for porting +++ +#if __A60868_TO_BE_PORTING__ +#if SW_CHANGE_FOR_SIMULATION +void main(void) +{ + + DRAMC_CTX_T DramConfig; + DramConfig.channel = CHANNEL_A; + DramConfig.support_rank_num = RANK_DUAL; + // DramRank + DramConfig.rank = RANK_0; + // DRAM type + DramConfig.dram_type = TYPE_LPDDR4X; + // DRAM Fast switch point type, only for LP4, useless in LP3 + DramConfig.dram_fsp = FSP_0; + // DRAM CBT mode, only for LP4, useless in LP3 + DramConfig.dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; + DramConfig.dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; + // IC and DRAM read DBI + DramConfig.DBI_R_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3 + #if ENABLE_READ_DBI + DramConfig.DBI_R_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3 + #else + DramConfig.DBI_R_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3 + #endif + // IC and DRAM write DBI + DramConfig.DBI_W_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3 + #if ENABLE_WRITE_DBI + DramConfig.DBI_W_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3 + #else + DramConfig.DBI_W_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3 + #endif + // bus width + DramConfig.data_width = DATA_WIDTH_32BIT; + // DRAMC internal test engine-2 parameters in calibration + DramConfig.test2_1 = DEFAULT_TEST2_1_CAL; + DramConfig.test2_2 = DEFAULT_TEST2_2_CAL; + // DRAMC test pattern in calibration + DramConfig.test_pattern = TEST_XTALK_PATTERN; + // DRAMC operation clock frequency in MHz + DramConfig.frequency = 800; + + //DramConfig.enable_rx_scan_vref =DISABLE; + //DramConfig.enable_tx_scan_vref =DISABLE; + //DramConfig.dynamicODT = DISABLE; + + MPLLInit(); + + Global_Option_Init(&DramConfig); + + // DramC & PHY init for all channels + DDRPhyFreqSel(&DramConfig, LP4_DDR1600); + + +#if WRITE_LEVELING_MOVE_DQS_INSTEAD_OF_CLK + memset(DramConfig.arfgWriteLevelingInitShif, FALSE, sizeof(DramConfig.arfgWriteLevelingInitShif)); + //>fgWriteLevelingInitShif= FALSE; +#endif + + DramcInit(&DramConfig); + + vApplyConfigBeforeCalibration(&DramConfig); + vMR2InitForSimulationTest(&DramConfig); + + vSetPHY2ChannelMapping(&DramConfig, DramConfig.channel); + + #if SIMULATION_SW_IMPED + DramcSwImpedanceCal(&DramConfig, 1, LOW_FREQ); //for DRVN/P and ODTN + //DramcSwImpedanceCal(&DramConfig, 1, HIGH_FREQ); //for DRVN/P and ODTN + #endif + + +#if SIMULATION_LP4_ZQ + if (DramConfig.dram_type == TYPE_LPDDR4 || DramConfig.dram_type == TYPE_LPDDR4X || DramConfig.dram_type == TYPE_LPDDR4P) + { + DramcZQCalibration(&DramConfig); + } +#endif + + #if SIMUILATION_LP4_CBT + CmdBusTrainingLP4(&DramConfig); + #endif + +#if SIMULATION_WRITE_LEVELING + DramcWriteLeveling(&DramConfig); +#endif + + #if SIMULATION_GATING + // Gating calibration of single rank + DramcRxdqsGatingCal(&DramConfig); + + // Gating calibration of both rank + //DualRankDramcRxdqsGatingCal(&DramConfig); + #endif + +#if SIMUILATION_LP4_RDDQC + DramcRxWindowPerbitCal(&DramConfig, 0, NULL); +#endif + + #if SIMULATION_DATLAT + // RX Datlat calibration of single rank + DramcRxdatlatCal(&DramConfig); + + // RX Datlat calibration of two rank + //DramcDualRankRxdatlatCal(&DramConfig); + #endif + + #if SIMULATION_RX_PERBIT + DramcRxWindowPerbitCal(&DramConfig, 1, NULL); + #endif + + #if SIMULATION_TX_PERBIT + DramcTxWindowPerbitCal(&DramConfig, TX_DQ_DQS_MOVE_DQ_DQM); + DramcTxWindowPerbitCal(&DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY); + #endif + + #if ENABLE_READ_DBI + //Read DBI ON + SetDramModeRegForReadDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_R_onoff[DramConfig.dram_fsp]); + #endif + + #if ENABLE_WRITE_DBI + //Write DBI ON + DramcWriteShiftMCKForWriteDBI(&DramConfig, -1); + SetDramModeRegForWriteDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]); + #endif + + #if ENABLE_READ_DBI + DramcReadDBIOnOff(&DramConfig, DramConfig.DBI_R_onoff[DramConfig.dram_fsp]); + #endif + + #if ENABLE_WRITE_DBI + DramcWriteDBIOnOff(&DramConfig, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]); + #endif +} +#endif //SW_CHANGE_FOR_SIMULATION +#endif // __A60868_TO_BE_PORTING__ +///TODO: wait for porting --- + diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c new file mode 100644 index 0000000000..8af6a36851 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c @@ -0,0 +1,1198 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//============================================================================= +// Include Files +//============================================================================= +//#include <common.h> +//#include <ett_common.h> +//#include <test_case_controller.h> +//#include <api.h> +//#include "gpio.h" +//#include "ett_cust.h" +//#include "emi_setting.h" +//#include "pll.h" +//#include "dramc_pi_api.h" +#include <assert.h> +#include <print.h> +#include <string.h> +#include "dramc_common.h" +#include "dramc_int_global.h" + +#include <emi_hw.h> +#include <emi.h> + +#if !__FLASH_TOOL_DA__ && !__ETT__ +#include "custom_emi.h" // fix build error: emi_settings +#endif + +#if (FOR_DV_SIMULATION_USED==0) +#include <soc/mt6359p.h> +#include <soc/regulator.h> + +/* now we can use definition MTK_PMIC_MT6359 + * ============================================================== + * PMIC |Power |Dflt. Volt. |Step |Support FPWM |Cmt. + * -------------------------------------------------------------- + * MT6359 |Vcore |0.8v |6.25mV |Yes | + * |Vm18 |1.8v |0.1V |No | + * -------------------------------------------------------------- + * MT6360 |Vdram |1.125v |5mV |Yes |(DRAM Vdram) + * |Vmddr |0.75v |10mV |No |(AP Vdram) + * |Vddq |0.6v |10mV |No | + * ============================================================== + */ +//#define MTK_PMIC_MT6359 +#endif + +#if !__ETT__ +#define mt_reg_sync_write(x,y) mt_reg_sync_writel(y,x) +#endif +#define seclib_get_devinfo_with_index(x) 0 + +#ifdef MTK_PMIC_MT6359 +#include <regulator/mtk_regulator.h> +#include <mt6359.h> +#endif + +#include <soc/dramc_param.h> +#include <soc/emi.h> + +//============================================================================= +// Definition +//============================================================================= + +//============================================================================= +// Global Variables +//============================================================================= +int emi_setting_index = -1; + +#ifdef MTK_PMIC_MT6359 +static struct mtk_regulator reg_vio18, reg_vdram, reg_vcore, reg_vddq, reg_vmddr; +#endif + +#ifdef LAST_DRAMC +static LAST_DRAMC_INFO_T* last_dramc_info_ptr; +#endif + +#ifdef VOLTAGE_SEL +static VOLTAGE_SEL_INFO_T voltage_sel_info_ptr; +#endif + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION +extern u64 get_part_addr(const char *name); +#endif + +#if defined(SLT) && (!__ETT__) +#include <pl_version.h> +static u64 part_dram_data_addr_slt = 0; +int read_slt_data(DRAM_SLT_DATA_T *data); +int write_slt_data(DRAM_SLT_DATA_T *data); +int clean_slt_data(void); +#endif +//============================================================================= +// External references +//============================================================================= +extern char* opt_dle_value; + +void print_DBG_info(DRAMC_CTX_T *p); + +void mdl_setting(DRAMC_CTX_T *p) +{ + EMI_SETTINGS *emi_set; + + if(emi_setting_index == -1) + emi_set = &default_emi_setting; +#if (FOR_DV_SIMULATION_USED==0) + else + emi_set = &emi_settings[emi_setting_index]; +#endif + + emi_init(); + + //The following is MDL settings + set_cen_emi_cona(emi_set->EMI_CONA_VAL); + set_cen_emi_conf(emi_set->EMI_CONF_VAL); + set_cen_emi_conh(emi_set->EMI_CONH_VAL); + + // CHNA and CHNB uses the same CH0 setting + set_chn_emi_cona(emi_set->CHN0_EMI_CONA_VAL); + //set_chn_emi_conc(0x4); + + p->vendor_id = emi_set->iLPDDR3_MODE_REG_5; +} + +void print_DBG_info(DRAMC_CTX_T *p) +{ +} + +int mt_get_dram_type(void) +{ + unsigned int dtype = mt_get_dram_type_from_hw_trap(); + + if (dtype == TYPE_LPDDR4X) + return DTYPE_LPDDR4X; + else + ASSERT(0); + + return 0; +} + +#ifdef DDR_RESERVE_MODE +extern u32 g_ddr_reserve_enable; +extern u32 g_ddr_reserve_success; +#define TIMEOUT 3 +extern void before_Dramc_DDR_Reserved_Mode_setting(void); + +#define CHAN_DRAMC_NAO_MISC_STATUSA(base) (base + 0x80) +#define SREF_STATE (1 << 16) + +unsigned int is_dramc_exit_slf(void) +{ + unsigned int ret; + + ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_A_DRAMC_NAO_BASE_ADDRESS); + if ((ret & SREF_STATE) != 0) { + dramc_crit("DRAM CHAN-A is in self-refresh (MISC_STATUSA = 0x%x)\n", ret); + return 0; + } + + ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_B_DRAMC_NAO_BASE_ADDRESS); + if ((ret & SREF_STATE) != 0) { + dramc_crit("DRAM CHAN-B is in self-refresh (MISC_STATUSA = 0x%x)\n", ret); + return 0; + } + + dramc_crit("ALL DRAM CHAN is not in self-refresh\n"); + return 1; +} + +#endif + +unsigned int dramc_set_vcore_voltage(unsigned int vcore) +{ +#ifdef MTK_PMIC_MT6359 + return mtk_regulator_set_voltage(®_vcore, vcore, MAX_VCORE); +#endif + dramc_debug("%s set vcore to %d\n", __func__, vcore); + //mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); + + mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore); + + return 0; +} + +unsigned int dramc_get_vcore_voltage(void) +{ +#ifdef MTK_PMIC_MT6359 + return mtk_regulator_get_voltage(®_vcore); +#else + return mainboard_get_regulator_vol(MTK_REGULATOR_VCORE); +#endif +} + +unsigned int dramc_set_vdram_voltage(unsigned int ddr_type, unsigned int vdram) +{ +#ifdef MTK_PMIC_MT6359 + mtk_regulator_set_voltage(®_vdram, vdram, MAX_VDRAM); +#endif + mainboard_set_regulator_vol(MTK_REGULATOR_VDD2, vdram); + return 0; +} + +unsigned int dramc_get_vdram_voltage(unsigned int ddr_type) +{ +#ifdef MTK_PMIC_MT6359 + return mtk_regulator_get_voltage(®_vdram); +#else + return mainboard_get_regulator_vol(MTK_REGULATOR_VDD2); +#endif +} + +unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq) +{ +#ifdef MTK_PMIC_MT6359 + mtk_regulator_set_voltage(®_vddq, vddq, MAX_VDDQ); +#endif + mainboard_set_regulator_vol(MTK_REGULATOR_VDDQ, vddq); + return 0; +} + +unsigned int dramc_get_vddq_voltage(unsigned int ddr_type) +{ +#ifdef MTK_PMIC_MT6359 + return mtk_regulator_get_voltage(®_vddq); +#else + return mainboard_get_regulator_vol(MTK_REGULATOR_VDDQ); +#endif +} + +unsigned int dramc_set_vmddr_voltage(unsigned int vmddr) +{ +#ifdef MTK_PMIC_MT6359 + return mtk_regulator_set_voltage(®_vmddr, vmddr, MAX_VMDDR); +#endif + mainboard_set_regulator_vol(MTK_REGULATOR_VMDDR, vmddr); + return 0; +} + +unsigned int dramc_get_vmddr_voltage(void) +{ +#ifdef MTK_PMIC_MT6359 + return mtk_regulator_get_voltage(®_vmddr); +#else + return mainboard_get_regulator_vol(MTK_REGULATOR_VMDDR); +#endif +} + +unsigned int dramc_set_vio18_voltage(unsigned int vio18) +{ +#ifdef MTK_PMIC_MT6359 + unsigned int twist = vio18 % UNIT_VIO18_STEP / UNIT_VIO18; + vio18 -= vio18 % UNIT_VIO18_STEP; + pmic_config_interface(PMIC_RG_VM18_VOCAL_ADDR, twist, PMIC_RG_VM18_VOCAL_MASK, PMIC_RG_VM18_VOCAL_SHIFT); + return mtk_regulator_set_voltage(®_vio18, vio18, MAX_VIO18); +#else + mainboard_set_regulator_vol(MTK_REGULATOR_VDD1, vio18); + return 0; +#endif +} + + +unsigned int dramc_get_vio18_voltage(void) +{ +#ifdef MTK_PMIC_MT6359 + unsigned int twist = 0; + pmic_read_interface(PMIC_RG_VM18_VOCAL_ADDR, &twist, PMIC_RG_VM18_VOCAL_MASK, PMIC_RG_VM18_VOCAL_SHIFT); + return mtk_regulator_get_voltage(®_vio18) + twist * UNIT_VIO18; +#else + return mainboard_get_regulator_vol(MTK_REGULATOR_VDD1); +#endif +} + +#define GPIO_TRAPPING_REG (0x100056f0) +unsigned int is_discrete_lpddr4(void) +{ + unsigned int type, ret; + + type = get_ddr_type(); + + ret = (type == DDR_TYPE_DISCRETE) ? 1 : 0; + dramc_debug("%s: %d\n", __func__, ret); + + return ret; +} + +unsigned int mt_get_dram_type_from_hw_trap(void) +{ + return TYPE_LPDDR4X; +} + +void setup_dramc_voltage_by_pmic(void) +{ +#ifdef VOLTAGE_SEL + int vcore; +#endif +#ifdef MTK_PMIC_MT6359 + int ret; + + ret = mtk_regulator_get("vm18", ®_vio18); + if (ret) + dramc_debug("mtk_regulator_get vio18 fail\n"); + + ret = mtk_regulator_get("vcore", ®_vcore); + if (ret) + dramc_debug("mtk_regulator_get vcore fail\n"); + + ret = mtk_regulator_get("VDRAM1", ®_vdram); + if (ret) + printf("mtk_regulator_get vdram fail\n"); + + ret = mtk_regulator_get("VDRAM2", ®_vddq); + if (ret) + printf("mtk_regulator_get vddq fail\n"); + + ret = mtk_regulator_get("VMDDR", ®_vmddr); + if (ret) + printf("mtk_regulator_get vmddr fail\n"); + + mtk_regulator_set_mode(®_vcore, 0x1); + mtk_regulator_set_mode(®_vdram, 0x1); + + #ifdef VOLTAGE_SEL + dramc_set_vio18_voltage(vio18_voltage_select()); + #else + dramc_set_vio18_voltage(SEL_VIO18); + #endif +#if defined(VCORE_BIN) + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU0); + if (vcore) + dramc_set_vcore_voltage(vcore); + else + #endif + dramc_set_vcore_voltage(get_vcore_uv_table(0)); +#else + #ifdef VOLTAGE_SEL + dramc_set_vcore_voltage(vcore_voltage_select(KSHU0)); + #else + dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KSHU0)); + #endif +#endif + #ifdef VOLTAGE_SEL + dramc_set_vdram_voltage(TYPE_LPDDR4, vdram_voltage_select()); + #else + dramc_set_vdram_voltage(TYPE_LPDDR4, SEL_PREFIX_VDRAM(LP4)); + #endif + + #ifdef VOLTAGE_SEL + dramc_set_vddq_voltage(TYPE_LPDDR4, vddq_voltage_select()); + #else + dramc_set_vddq_voltage(TYPE_LPDDR4, SEL_PREFIX_VDDQ); + #endif + + #ifdef VOLTAGE_SEL + dramc_set_vmddr_voltage(vmddr_voltage_select()); + #else + dramc_set_vmddr_voltage(SEL_PREFIX_VMDDR); + #endif + + dramc_debug("Vio18 = %d\n", dramc_get_vio18_voltage()); + dramc_debug("Vcore = %d\n", dramc_get_vcore_voltage()); + dramc_debug("Vdram = %d\n", dramc_get_vdram_voltage(TYPE_LPDDR4)); + dramc_debug("Vddq = %d\n", dramc_get_vddq_voltage(TYPE_LPDDR4)); + dramc_debug("Vmddr = %d\n", dramc_get_vmddr_voltage()); +#endif +} + +static void restore_vcore_setting(void) +{ +#ifdef VOLTAGE_SEL + int vcore; +#endif +#ifdef MTK_PMIC_MT6359 + int ret; + + ret = mtk_regulator_get("vcore", ®_vcore); + if (ret) + printf("mtk_regulator_get vcore fail\n"); + +#if defined(VCORE_BIN) + #ifdef VOLTAGE_SEL + vcore = vcore_voltage_select(KSHU0); + if ((doe_get_config("dram_fix_3094_0825")) || (doe_get_config("dram_all_3094_0825")) || (doe_get_config("dram_opp0_3733_others_3094_0825"))) + dramc_set_vcore_voltage(825000); + else if (doe_get_config("dram_fix_3094_0725") || (doe_get_config("dram_fix_2400_0725")) || (doe_get_config("dram_fix_1534_0725")) || (doe_get_config("dram_fix_1200_0725")) || (doe_get_config("dram_all_3094_0725")) || (doe_get_config("dram_all_1534_0725")) || (doe_get_config("dram_opp0_3094_others_1534_0725")) || (doe_get_config("dram_opp0_2400_others_1534_0725"))) + dramc_set_vcore_voltage(725000); + else if ((doe_get_config("dram_fix_1200_065")) || (doe_get_config("dram_fix_800_065"))) + dramc_set_vcore_voltage(650000); + else if (vcore) + dramc_set_vcore_voltage(vcore); + else + #endif + dramc_set_vcore_voltage(get_vcore_uv_table(0)); +#else + #ifdef VOLTAGE_SEL + dramc_set_vcore_voltage(vcore_voltage_select(KSHU0)); + #else + dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KSHU0)); + #endif +#endif + + dramc_debug("Vcore = %d\n", dramc_get_vcore_voltage()); +#endif +} + +void switch_dramc_voltage_to_auto_mode(void) +{ +#ifdef MTK_PMIC_MT6359 + mtk_regulator_set_mode(®_vcore, 0x0); + mtk_regulator_set_mode(®_vdram, 0x0); +#endif +} + +#ifdef COMBO_MCP +static int mt_get_mdl_number(void) +{ + static int found = 0; + static int mdl_number = -1; + + found = 1; + mdl_number = get_ddr_geometry(); + + return mdl_number; +} +#endif + +int get_dram_channel_support_nr(void) +{ + return DRAMC_MAX_CH; +} + +int get_dram_channel_nr(void) +{ + return get_channel_nr_by_emi(); +} + +int get_dram_rank_nr(void) +{ + int index; + int cen_emi_cona; + +#ifdef COMBO_MCP +#ifdef DDR_RESERVE_MODE + if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1) { + return get_rank_nr_by_emi(); + } else +#endif + { + index = mt_get_mdl_number(); + if (index < 0 || index >= num_of_emi_records) + return 0; + + cen_emi_cona = emi_settings[index].EMI_CONA_VAL; + } +#else + cen_emi_cona = default_emi_setting.EMI_CONA_VAL; +#endif + + if ((cen_emi_cona & (1 << 17)) != 0 || //for channel 0 + (cen_emi_cona & (1 << 16)) != 0 ) //for channel 1 + return 2; + else + return 1; +} + +int get_dram_mr_cnt(void) +{ + return DRAMC_MR_CNT; +} + +int get_dram_freq_cnt(void) +{ + return DRAMC_FREQ_CNT; +} + +#if (FOR_DV_SIMULATION_USED==0) +#if !__FLASH_TOOL_DA__ && !__ETT__ + +void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK]) +{ +#ifdef COMBO_MCP + int index, rank_nr, i; + +#ifdef DDR_RESERVE_MODE + if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1) + { + get_rank_size_by_emi(dram_rank_size); + } + else +#endif + { + index = mt_get_mdl_number(); + + if (index < 0 || index >= num_of_emi_records) + { + return; + } + + rank_nr = get_dram_rank_nr(); + + for(i = 0; i < rank_nr; i++){ + dram_rank_size[i] = emi_settings[index].DRAM_RANK_SIZE[i]; + dramc_debug("%d:dram_rank_size:%llx\n",i,dram_rank_size[i]); + } + } + return; +#else + get_rank_size_by_emi(dram_rank_size); + return; +#endif +} + +void get_dram_freq_step(u32 dram_freq_step[]) +{ + unsigned int i; + unsigned int defined_step[DRAMC_FREQ_CNT] = { + 4266, 3200, 2400, 1866, 1600, 1200, 800}; + + if (is_discrete_lpddr4()) { + defined_step[0] = 3200; + } + for (i = 0; i < DRAMC_FREQ_CNT; i++) { + dram_freq_step[i] = defined_step[i]; + } +} + +void set_dram_mr(unsigned int index, unsigned short value) +{ +#if 0 + unsigned short value_2rk; + + value_2rk = value & 0xFF; + value_2rk |= (value_2rk << 8); + + switch (index) { + case 5: + mr5 = value_2rk; + break; + case 6: + mr6 = value_2rk; + break; + case 7: + mr7 = value_2rk; + break; + case 8: + mr8 = value; + default: + break; + } +#endif +} + +unsigned short get_dram_mr(unsigned int index) +{ + unsigned int value = 0; +#if 0 + switch (index) { + case 5: + value = last_dramc_info_ptr->mr5; + break; + case 6: + value = last_dramc_info_ptr->mr6; + break; + case 7: + value = last_dramc_info_ptr->mr7; + break; + case 8: + value = last_dramc_info_ptr->mr8; + default: + break; + } + return (unsigned short)(value & 0xFFFF); +#else + return (unsigned short)(value & 0xFFFF); +#endif +} + +void get_dram_mr_info(struct mr_info_t mr_info[]) +{ +#if 0 + unsigned int i; + unsigned int mr_list[DRAMC_MR_CNT] = {5, 6, 7, 8}; + + for (i = 0; i < DRAMC_MR_CNT; i++) { + mr_info[i].mr_index = mr_list[i]; + mr_info[i].mr_value = get_dram_mr(mr_list[i]); + } +#endif +} + +#endif //#if !__FLASH_TOOL_DA__ && !__ETT__ +#endif + +static void freq_table_are_all_3094(void) +{ + gFreqTbl[0].freq_sel = LP4_DDR3200; + gFreqTbl[0].divmode = DIV8_MODE; + gFreqTbl[0].shuffleIdx = SRAM_SHU1; + gFreqTbl[0].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[1].freq_sel = LP4_DDR3200; + gFreqTbl[1].divmode = DIV8_MODE; + gFreqTbl[1].shuffleIdx = SRAM_SHU3; + gFreqTbl[1].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[2].freq_sel = LP4_DDR3200; + gFreqTbl[2].divmode = DIV8_MODE; + gFreqTbl[2].shuffleIdx = SRAM_SHU2; + gFreqTbl[2].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[3].freq_sel = LP4_DDR3200; + gFreqTbl[3].divmode = DIV8_MODE; + gFreqTbl[3].shuffleIdx = SRAM_SHU0; + gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[4].freq_sel = LP4_DDR3200; + gFreqTbl[4].divmode = DIV8_MODE; + gFreqTbl[4].shuffleIdx = SRAM_SHU5; + gFreqTbl[4].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[5].freq_sel = LP4_DDR3200; + gFreqTbl[5].divmode = DIV8_MODE; + gFreqTbl[5].shuffleIdx = SRAM_SHU4; + gFreqTbl[5].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[6].freq_sel = LP4_DDR3200; + gFreqTbl[6].divmode = DIV8_MODE; + gFreqTbl[6].shuffleIdx = SRAM_SHU6; + gFreqTbl[6].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE; + +} + +static void freq_table_are_all_1534(void) +{ + gFreqTbl[0].freq_sel = LP4_DDR1600; + gFreqTbl[0].divmode = DIV8_MODE; + gFreqTbl[0].shuffleIdx = SRAM_SHU1; + gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[1].freq_sel = LP4_DDR1600; + gFreqTbl[1].divmode = DIV8_MODE; + gFreqTbl[1].shuffleIdx = SRAM_SHU3; + gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[2].freq_sel = LP4_DDR1600; + gFreqTbl[2].divmode = DIV8_MODE; + gFreqTbl[2].shuffleIdx = SRAM_SHU2; + gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[3].freq_sel = LP4_DDR1600; + gFreqTbl[3].divmode = DIV8_MODE; + gFreqTbl[3].shuffleIdx = SRAM_SHU0; + gFreqTbl[3].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[4].freq_sel = LP4_DDR1600; + gFreqTbl[4].divmode = DIV8_MODE; + gFreqTbl[4].shuffleIdx = SRAM_SHU5; + gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[5].freq_sel = LP4_DDR1600; + gFreqTbl[5].divmode = DIV8_MODE; + gFreqTbl[5].shuffleIdx = SRAM_SHU4; + gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[6].freq_sel = LP4_DDR1600; + gFreqTbl[6].divmode = DIV8_MODE; + gFreqTbl[6].shuffleIdx = SRAM_SHU6; + gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE; + +} + +static void freq_table_opp0_3733_others_3094(void) +{ + gFreqTbl[0].freq_sel = LP4_DDR3200; + gFreqTbl[0].divmode = DIV8_MODE; + gFreqTbl[0].shuffleIdx = SRAM_SHU1; + gFreqTbl[0].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[1].freq_sel = LP4_DDR3200; + gFreqTbl[1].divmode = DIV8_MODE; + gFreqTbl[1].shuffleIdx = SRAM_SHU3; + gFreqTbl[1].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[2].freq_sel = LP4_DDR3200; + gFreqTbl[2].divmode = DIV8_MODE; + gFreqTbl[2].shuffleIdx = SRAM_SHU2; + gFreqTbl[2].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[3].freq_sel = LP4_DDR3733; + gFreqTbl[3].divmode = DIV8_MODE; + gFreqTbl[3].shuffleIdx = SRAM_SHU0; + gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[4].freq_sel = LP4_DDR3200; + gFreqTbl[4].divmode = DIV8_MODE; + gFreqTbl[4].shuffleIdx = SRAM_SHU5; + gFreqTbl[4].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[5].freq_sel = LP4_DDR3200; + gFreqTbl[5].divmode = DIV8_MODE; + gFreqTbl[5].shuffleIdx = SRAM_SHU4; + gFreqTbl[5].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[6].freq_sel = LP4_DDR3200; + gFreqTbl[6].divmode = DIV8_MODE; + gFreqTbl[6].shuffleIdx = SRAM_SHU6; + gFreqTbl[6].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE; +} + +static void freq_table_opp0_3094_others_1534(void) +{ + gFreqTbl[0].freq_sel = LP4_DDR1600; + gFreqTbl[0].divmode = DIV8_MODE; + gFreqTbl[0].shuffleIdx = SRAM_SHU1; + gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[1].freq_sel = LP4_DDR1600; + gFreqTbl[1].divmode = DIV8_MODE; + gFreqTbl[1].shuffleIdx = SRAM_SHU3; + gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[2].freq_sel = LP4_DDR1600; + gFreqTbl[2].divmode = DIV8_MODE; + gFreqTbl[2].shuffleIdx = SRAM_SHU2; + gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[3].freq_sel = LP4_DDR3200; + gFreqTbl[3].divmode = DIV8_MODE; + gFreqTbl[3].shuffleIdx = SRAM_SHU0; + gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[4].freq_sel = LP4_DDR1600; + gFreqTbl[4].divmode = DIV8_MODE; + gFreqTbl[4].shuffleIdx = SRAM_SHU5; + gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[5].freq_sel = LP4_DDR1600; + gFreqTbl[5].divmode = DIV8_MODE; + gFreqTbl[5].shuffleIdx = SRAM_SHU4; + gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[6].freq_sel = LP4_DDR1600; + gFreqTbl[6].divmode = DIV8_MODE; + gFreqTbl[6].shuffleIdx = SRAM_SHU6; + gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE; +} + +static void freq_table_opp0_2400_others_1534(void) +{ + gFreqTbl[0].freq_sel = LP4_DDR1600; + gFreqTbl[0].divmode = DIV8_MODE; + gFreqTbl[0].shuffleIdx = SRAM_SHU1; + gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[1].freq_sel = LP4_DDR1600; + gFreqTbl[1].divmode = DIV8_MODE; + gFreqTbl[1].shuffleIdx = SRAM_SHU3; + gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[2].freq_sel = LP4_DDR1600; + gFreqTbl[2].divmode = DIV8_MODE; + gFreqTbl[2].shuffleIdx = SRAM_SHU2; + gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[3].freq_sel = LP4_DDR2400; + gFreqTbl[3].divmode = DIV8_MODE; + gFreqTbl[3].shuffleIdx = SRAM_SHU0; + gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K; + gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[4].freq_sel = LP4_DDR1600; + gFreqTbl[4].divmode = DIV8_MODE; + gFreqTbl[4].shuffleIdx = SRAM_SHU5; + gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[5].freq_sel = LP4_DDR1600; + gFreqTbl[5].divmode = DIV8_MODE; + gFreqTbl[5].shuffleIdx = SRAM_SHU4; + gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE; + + gFreqTbl[6].freq_sel = LP4_DDR1600; + gFreqTbl[6].divmode = DIV8_MODE; + gFreqTbl[6].shuffleIdx = SRAM_SHU6; + gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT; + gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON; + gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE; +} +#if (CFG_DRAM_LOG_TO_STORAGE) + +extern u64 get_part_addr(const char *name); +u64 part_dram_data_addr_uart = 0; +u32 log_start = 0; +static char logbuf[1024]; +static int logcount; +#endif + +#ifdef VOLTAGE_SEL +void update_voltage_select_info(void) +{ + voltage_sel_info_ptr.vcore = doe_get_config("vcore"); + voltage_sel_info_ptr.vdram = doe_get_config("vdram"); + voltage_sel_info_ptr.vddq = doe_get_config("vddq"); + voltage_sel_info_ptr.vmddr = doe_get_config("vmddr"); + voltage_sel_info_ptr.vio18 = doe_get_config("vio18"); + + print("DOE setting: vcore %d, vdram %d, vddq %d, vmddr %d, vio18 %d \n", + voltage_sel_info_ptr.vcore, voltage_sel_info_ptr.vdram, + voltage_sel_info_ptr.vddq, voltage_sel_info_ptr.vmddr, + voltage_sel_info_ptr.vio18); +} + +int vio18_voltage_select() +{ + if (voltage_sel_info_ptr.vio18 == LEVEL_LV) { + return HQA_VIO18_LV; + } else if (voltage_sel_info_ptr.vio18 == LEVEL_HV) { + return HQA_VIO18_HV; + } else { + return HQA_VIO18_NV; + } +} + +int vmddr_voltage_select() +{ + if (voltage_sel_info_ptr.vmddr == LEVEL_LV) { + return HQA_VMDDR_LV_LP4; + } else if (voltage_sel_info_ptr.vmddr == LEVEL_HV) { + return HQA_VMDDR_HV_LP4; + } else { + return HQA_VMDDR_NV_LP4; + } +} + +int vddq_voltage_select() +{ + if (voltage_sel_info_ptr.vddq == LEVEL_LV) { + return HQA_VDDQ_LV_LP4; + } else if (voltage_sel_info_ptr.vddq == LEVEL_HV) { + return HQA_VDDQ_HV_LP4; + } else { + return HQA_VDDQ_NV_LP4; + } +} + +int vdram_voltage_select(void) +{ + if (voltage_sel_info_ptr.vdram == LEVEL_LV) { + return HQA_VDRAM_LV_LP4; + } else if (voltage_sel_info_ptr.vdram == LEVEL_HV) { + return HQA_VDRAM_HV_LP4; + } else { + return HQA_VDRAM_NV_LP4; + } +} + +int vcore_voltage_select(DRAM_KSHU kshu) +{ + int ret = 0; + if (voltage_sel_info_ptr.vcore == LEVEL_LV) { + switch(kshu) { + case KSHU0: + ret = HQA_VCORE_LV_LP4_KSHU0_PL; + break; + case KSHU1: + ret = HQA_VCORE_LV_LP4_KSHU1_PL; + break; + case KSHU2: + ret = HQA_VCORE_LV_LP4_KSHU2_PL; + break; + case KSHU3: + ret = HQA_VCORE_LV_LP4_KSHU3_PL; + break; + case KSHU4: + ret = HQA_VCORE_LV_LP4_KSHU4_PL; + break; + case KSHU5: + ret = HQA_VCORE_LV_LP4_KSHU5_PL; + break; + case KSHU6: + ret = HQA_VCORE_LV_LP4_KSHU6_PL; + break; + }; + } else if (voltage_sel_info_ptr.vcore == LEVEL_HV) { + switch(kshu) { + case KSHU0: + ret = HQA_VCORE_HV_LP4_KSHU0_PL; + break; + case KSHU1: + ret = HQA_VCORE_HV_LP4_KSHU1_PL; + break; + case KSHU2: + ret = HQA_VCORE_HV_LP4_KSHU2_PL; + break; + case KSHU3: + ret = HQA_VCORE_HV_LP4_KSHU3_PL; + break; + case KSHU4: + ret = HQA_VCORE_HV_LP4_KSHU4_PL; + break; + case KSHU5: + ret = HQA_VCORE_HV_LP4_KSHU5_PL; + break; + case KSHU6: + ret = HQA_VCORE_HV_LP4_KSHU6_PL; + break; + }; + } else { +#if defined(VCORE_BIN) + ret = 0; +#else + switch(kshu) { + case KSHU0: + ret = HQA_VCORE_NV_LP4_KSHU0_PL; + break; + case KSHU1: + ret = HQA_VCORE_NV_LP4_KSHU1_PL; + break; + case KSHU2: + ret = HQA_VCORE_NV_LP4_KSHU2_PL; + break; + case KSHU3: + ret = HQA_VCORE_NV_LP4_KSHU3_PL; + break; + case KSHU4: + ret = HQA_VCORE_NV_LP4_KSHU4_PL; + break; + case KSHU5: + ret = HQA_VCORE_NV_LP4_KSHU5_PL; + break; + case KSHU6: + ret = HQA_VCORE_NV_LP4_KSHU6_PL; + break; + }; +#endif + } + + return ret; +} + +#endif + +#if (FOR_DV_SIMULATION_USED==0) +#if !__ETT__ +void mt_set_emi(struct dramc_param *dparam) +{ + int index; + /*unsigned int SW_CTRL_VC, HW_CTRL_VC;*/ + EMI_SETTINGS *emi_set = &emi_settings[0]; + + int segment; + +#ifdef VOLTAGE_SEL + update_voltage_select_info(); +#endif +#if ENABLE_PINMUX_FOR_RANK_SWAP + EMI_rank_swap_handle(); +#endif + + // set voltage and hw trapping before mdl + setup_dramc_voltage_by_pmic(); + + if ((doe_get_config("dram_all_3094_0825")) || (doe_get_config("dram_all_3094_0725"))) + freq_table_are_all_3094(); + else if (doe_get_config("dram_all_1534_0725")) + freq_table_are_all_1534(); + else if (doe_get_config("dram_opp0_3733_others_3094_0825")) + freq_table_opp0_3733_others_3094(); + else if (doe_get_config("dram_opp0_3094_others_1534_0725")) + freq_table_opp0_3094_others_1534(); + else if (doe_get_config("dram_opp0_2400_others_1534_0725")) + freq_table_opp0_2400_others_1534(); + +#ifdef COMBO_MCP + + index = mt_get_mdl_number(); + dramc_crit("[EMI] MDL number = %d\r\n", index); + if (index < 0 || index >= num_of_emi_records) + { + die("[EMI] setting failed 0x%x\r\n", index); + } + else + { + emi_setting_index = index; + emi_set = &emi_settings[emi_setting_index]; + } + dramc_crit("[EMI] Get MDL freq = %d\r\n", emi_set->DRAMC_ACTIME_UNION[0]); +#else + dramc_crit("[EMI] ComboMCP not ready, using default setting\n"); + emi_setting_index = -1; + emi_set = &default_emi_setting; +#endif + segment = (seclib_get_devinfo_with_index(7) & 0xFF); + if ((segment == 0x80) || (segment == 0x01) || (segment == 0x40) || (segment == 0x02)) + { + emi_set->DRAMC_ACTIME_UNION[0] = 3733; + } +#ifdef DDR_RESERVE_MODE + if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==0) + Before_Init_DRAM_While_Reserve_Mode_fail(emi_set->type & 0xF); +#endif + +#if (CFG_DRAM_LOG_TO_STORAGE) + log_start = 1; + print("log_start=0x%x part_dram_data_addr_uart=0x%llx \n",log_start,part_dram_data_addr_uart); +#endif +#if defined(SLT) + SLT_Init_DRAM((emi_set->type & 0xF), emi_set->dram_cbt_mode_extern, NULL, NORMAL_USED); +#else + Init_DRAM((emi_set->type & 0xF), emi_set->dram_cbt_mode_extern, NULL, NORMAL_USED); +#endif + switch_dramc_voltage_to_auto_mode(); + restore_vcore_setting(); + +#if (CFG_DRAM_LOG_TO_STORAGE) + log_start = 0; + print("log_start=0x%x part_dram_data_addr_uart=0x%llx \n",log_start,part_dram_data_addr_uart); +#endif +#if 0 + { + DRAMC_CTX_T * p = psCurrDramCtx; + DramcRegDump(p); + } +#endif +} +#endif +#endif + +#define DRAMC_ADDR_SHIFT_CHN(addr, channel) (addr + (channel * 0x10000)) + +#if (FOR_DV_SIMULATION_USED==0) // for DV sim build pass +int doe_get_config(const char* feature) +{ +#if defined(ENABLE_DOE) + char *doe_feature = dconfig_getenv(feature); + int doe_result = atoi(doe_feature); + dramc_crit("DOE force setting %s=%d\n", feature, doe_result); + return doe_result; +#else + return 0; +#endif +} +#endif + +#if (CFG_DRAM_LOG_TO_STORAGE) +void log_to_storage(const char c) +{ + int ret, clr_count; + blkdev_t *bootdev = NULL; + static u8 logen = 0; + + bootdev = blkdev_get(CFG_BOOT_DEV); + + if (log_start && (!logen)) { + logen = 1; + logcount = 0; + part_dram_data_addr_uart = get_part_addr("boot_para") + 0x100000; // addr = 0x1f300000, the first 1MB for debug + memset(&logbuf, 0, sizeof(logbuf)); + for (clr_count = 0; clr_count < 3072 ; clr_count++) //3M + ret = blkdev_write(bootdev, (part_dram_data_addr_uart + (1024 * clr_count)), 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER)); + } + + if (log_start) { + if (((((char) c >> 4) & 0x7) > 1) & ((((char) c >> 4) & 0x7) < 7)) + logbuf[logcount] = ((char) c & 0xF0) | (((char) c >> 2) & 0x03) | (((char) c << 2) & 0x0C); + else + logbuf[logcount] = (char) c; + logcount = logcount + 1; + //write to storage + if (logcount==1024) { + logcount = 0; + ret = blkdev_write(bootdev, part_dram_data_addr_uart, 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER)); + part_dram_data_addr_uart = part_dram_data_addr_uart + 1024; + } + } +} +#endif +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + +u32 g_dram_storage_api_err_code; + +#if !__ETT__ +int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData) +{ + struct sdram_params *params; + + if (!dramc_params) + return -1; + params = &dramc_params->dramc_datas.freq_params[shuffle]; + + dramc_info("read calibration data from shuffle %d(For verify: WL B0:%u, B1: %u)\n", + shuffle, params->wr_level[CHANNEL_A][RANK_0][0], params->wr_level[CHANNEL_B][RANK_0][0]); + /* copy the data stored in storage to the data structure for calibration */ + memcpy(offLine_SaveData, params, sizeof(*offLine_SaveData)); + + return 0; +} + +int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData) +{ + return 0; +} + +int clean_dram_calibration_data(void) +{ + return 0; +} +#endif + +#endif + + +#if __FLASH_TOOL_DA__ +unsigned int get_mr8_by_mrr(U8 channel, U8 rank) +{ + DRAMC_CTX_T *p = psCurrDramCtx; + unsigned int mr8_value; + + p->channel = channel; + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_MRRRK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 8, SWCMD_CTRL0_MRSMA); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRREN); + while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRR_RESPONSE) ==0) + mcDELAY_US(1); + mr8_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS), MRR_STATUS_MRR_REG); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRREN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 0, SWCMD_CTRL0_MRRRK); + + return (mr8_value & 0xff); +} +#endif + diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c new file mode 100644 index 0000000000..327f5caeb1 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c @@ -0,0 +1,1729 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//----------------------------------------------------------------------------- +// Include files +//----------------------------------------------------------------------------- +#include "dramc_common.h" +#include "dramc_int_global.h" +#include "x_hal_io.h" +#include "dramc_top.h" + + +//----------------------------------------------------------------------------- +// Global variables +//----------------------------------------------------------------------------- + +//U8 gu1MR23Done = FALSE; /* Not used starting from Vinson (all freqs use MR23=0x3F) */ +U8 gu1MR23[CHANNEL_NUM][RANK_MAX]; +/* DQSOSCTHRD_INC & _DEC are 12 bits (Starting from Vinson) */ +U16 gu2DQSOSCTHRD_INC[CHANNEL_NUM][RANK_MAX]; +U16 gu2DQSOSCTHRD_DEC[CHANNEL_NUM][RANK_MAX]; +U16 gu2MR18[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR18 (DQS ocillator count - MSB) */ +U16 gu2MR19[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR19 (DQS ocillator count - LSB) */ +U16 gu2DQSOSC[CHANNEL_NUM][RANK_MAX]; /* Stores tDQSOSC results */ +U16 gu2DQSOscCnt[CHANNEL_NUM][RANK_MAX][2]; + + +void DramcDQSOSCInit(void) +{ + memset(gu1MR23, 0x3F, sizeof(gu1MR23)); /* MR23 should be 0x3F for all freqs (Starting from Vinson) */ + memset(gu2DQSOSCTHRD_INC, 0x6, sizeof(gu2DQSOSCTHRD_INC)); + memset(gu2DQSOSCTHRD_DEC, 0x4, sizeof(gu2DQSOSCTHRD_DEC)); +} + +static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p) +{ + U32 u4Response; + U32 u4TimeCnt = TIME_OUT_CNT; + U32 u4RegBackupAddress[] = {DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)}; + + // Backup rank, CKE fix on/off, HW MIOCK control settings + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); + + mcSHOW_DBG_MSG3(("[ZQCalibration]\n")); + //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); + + // Disable HW MIOCK control to make CLK always on + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON); + mcDELAY_US(1); + + //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank. + CKEFixOnOff(p, CKE_WRITE_TO_ALL_RANK, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + //ZQCAL Start + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_WCK2DQI_START_SWTRIG); + + do + { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE); + u4TimeCnt --; + mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + + mcSHOW_DBG_MSG3(("%d- ", u4TimeCnt)); + //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); + }while((u4Response==0) &&(u4TimeCnt>0)); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_WCK2DQI_START_SWTRIG); + + if(u4TimeCnt==0)//time out + { + mcSHOW_DBG_MSG(("ZQCAL Start fail (time out)\n")); + //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n")); + return DRAM_FAIL; + } + + // Restore rank, CKE fix on, HW MIOCK control settings + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); + + mcSHOW_DBG_MSG3(("\n[DramcZQCalibration] Done\n\n")); + //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n")); + + return DRAM_OK; +} + +static DRAM_STATUS_T DramcStartDQSOSC(DRAMC_CTX_T *p) +{ +// return DramcStartDQSOSC_SCSM(p); +// return DramcStartDQSOSC_RTSWCMD(p); + return DramcStartDQSOSC_SWCMD(p); +} + +DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p) +{ + U8 u1MR23 = gu1MR23[p->channel][p->rank]; + U16 u2MR18, u2MR19; + U16 u2DQSCnt; + U16 u2DQSOsc[2]; + U32 u4RegBak[2]; + +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + + u4RegBak[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); + u4RegBak[1] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); + + //LPDDR4-3200, PI resolution = tCK/64 =9.76ps + //Only if MR23>=16, then error < PI resolution. + //Set MR23 == 0x3f, stop after 63*16 clock + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u1GetRank(p), MRS_MRSRK); + DramcModeRegWriteByRank(p, p->rank, 23, u1MR23); + + //SW mode + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), 1, SHU_DQSOSC_SET0_DQSOSCENDIS); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON); + + CKEFixOnOff(p, p->rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + DramcStartDQSOSC(p); + mcDELAY_US(1); + + DramcModeRegReadByRank(p, p->rank, 18, &u2MR18); + DramcModeRegReadByRank(p, p->rank, 19, &u2MR19); + +#if (SW_CHANGE_FOR_SIMULATION == 0) + //B0 + u2DQSCnt = (u2MR18 & 0x00FF) | ((u2MR19 & 0x00FF) << 8); + if (u2DQSCnt != 0) + u2DQSOsc[0] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * p->frequency); //tDQSOSC = 16*MR23*tCK/2*count + else + u2DQSOsc[0] = 0; + + //B1 + u2DQSCnt = (u2MR18 >> 8) | ((u2MR19 & 0xFF00)); + if (u2DQSCnt != 0) + u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * p->frequency); //tDQSOSC = 16*MR23*tCK/2*count + else + u2DQSOsc[1] = 0; + mcSHOW_DBG_MSG(("[DQSOSCAuto] RK%d, (LSB)MR18= 0x%x, (MSB)MR19= 0x%x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", u1GetRank(p), u2MR18, u2MR19, u2DQSOsc[0], u2DQSOsc[1])); +#endif + + gu2MR18[p->channel][p->rank] = u2MR18; + gu2MR19[p->channel][p->rank] = u2MR19; + gu2DQSOSC[p->channel][p->rank] = u2DQSOsc[0]; + + if (u2DQSOsc[1] != 0 && u2DQSOsc[1] < u2DQSOsc[0]) + gu2DQSOSC[p->channel][p->rank] = u2DQSOsc[1]; + + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4RegBak[0]); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4RegBak[1]); + + return DRAM_OK; +} + + +#if ENABLE_TX_TRACKING +/* Using gu2DQSOSC results calculated from DramcDQSOSCAuto + * -> calculate DQSOSCTHRD_INC, DQSOSCTHRD_DEC + * _INC, _DEC formulas are extracted from "Verification plan of Vinson LPDDR4 HW TX Tracking" doc + */ +DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p) +{ +#if (SW_CHANGE_FOR_SIMULATION == 0) + /* Preloader doesn't support floating point numbers -> Manually expand/simpify _INC, _DEC formula */ + U8 u1MR23 = gu1MR23[p->channel][p->rank]; + U16 u2DQSOSC = gu2DQSOSC[p->channel][p->rank]; + U32 u4tCK = 1000000 / p->frequency; + + if (u2DQSOSC != 0) + { + gu2DQSOSCTHRD_INC[p->channel][p->rank] = (3 * u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 20); + gu2DQSOSCTHRD_DEC[p->channel][p->rank] = (u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 10); + } + + mcSHOW_DBG_MSG(("CH%d_RK%d: MR19=0x%X, MR18=0x%X, DQSOSC=%d, MR23=%u, INC=%u, DEC=%u\n", p->channel, p->rank, + gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank], gu2DQSOSC[p->channel][p->rank], + u1MR23, gu2DQSOSCTHRD_INC[p->channel][p->rank], gu2DQSOSCTHRD_DEC[p->channel][p->rank])); +#endif + return DRAM_OK; +} + + +/* Sets DQSOSC_BASE for specified rank/byte */ +DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p) +{ + U16 u2DQSOscCnt[2]; + + DramcDQSOSCAuto(p); + + //B0 + gu2DQSOscCnt[p->channel][p->rank][0] = u2DQSOscCnt[0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8); + //B1 + gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00)); + + if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) && (gu2DQSOscCnt[p->channel][p->rank][1] == 0)) + { + gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = u2DQSOscCnt[0]; + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), P_Fld(u2DQSOscCnt[0], SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(u2DQSOscCnt[1], SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); + + mcSHOW_DBG_MSG(("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank])); + mcDUMP_REG_MSG(("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank])); + return DRAM_OK; +} + +DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p) +{ + U16 u2PRDCNT = 0x3FF, u2PRDCNTtmp = 0x3FF; + U8 u1PRDCNT_DIV = 4; + U16 u2DQSOSCENCNT = 0xFFF; + U8 u1FILT_PITHRD = 0; + U8 u1W2R_SEL = 0; + U8 u1RankIdx, u1RankIdxBak; + U8 u1DQSOSCRCNT = 0, u1IsDiv4 = 0, u1RoundUp= 0; + u1RankIdxBak = u1GetRank(p); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), 0x0, SHU_TX_SET0_DQS2DQ_FILT_PITHRD); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x0, DQSOSCR_R_DMDQS2DQ_FILT_OPT); + if (p->frequency <= 400) + { + u1FILT_PITHRD = 0x5; + if (vGet_Div_Mode(p) == DIV4_MODE) + u1W2R_SEL = 0x2; + else + u1W2R_SEL = 0x5; + } + else if (p->frequency <= 600) + { + u1FILT_PITHRD = 0x6; + if (vGet_Div_Mode(p) == DIV4_MODE) + u1W2R_SEL = 0x2; + else + u1W2R_SEL = 0x5; + } + else if (p->frequency <= 800) + { + u1FILT_PITHRD = 0x6; + if (vGet_Div_Mode(p) == DIV4_MODE) + u1W2R_SEL = 0x2; + else + u1W2R_SEL = 0x5; + } + else if (p->frequency <= 933) + { + u1FILT_PITHRD = 0x9; + u1W2R_SEL = 0x2; + } + else if (p->frequency <= 1200) + { + u1FILT_PITHRD = 0xb; + u1W2R_SEL = 0x2; + } + else if (p->frequency <= 1333) + { + u1FILT_PITHRD = 0xc; + u1W2R_SEL = 0x2; + } + else if (p->frequency <= 1600) + { + u1FILT_PITHRD = 0xE; + u1W2R_SEL = 0x2; + } + else if (p->frequency <= 1866) + { + u1FILT_PITHRD = 0x12; + u1W2R_SEL = 0x2; + } + else //4266 + { + u1FILT_PITHRD = 0x17; + u1W2R_SEL = 0x2; + } + + if (vGet_Div_Mode(p) == DIV4_MODE) + { + u1PRDCNT_DIV = 2; + u1IsDiv4 = 1; + } + + u1DQSOSCRCNT = ((p->frequency << u1IsDiv4))/100; + if ((p->frequency%100) != 0) // @Darren, Round up for tOSCO timing (40ns) + u1DQSOSCRCNT++; + if (gu1MR23[p->channel][RANK_1] > gu1MR23[p->channel][RANK_0]) + u2PRDCNTtmp = ((gu1MR23[p->channel][RANK_1]*100)/u1PRDCNT_DIV); + else + u2PRDCNTtmp = ((gu1MR23[p->channel][RANK_0]*100)/u1PRDCNT_DIV); + + u2PRDCNT = (u2PRDCNTtmp + ((u1DQSOSCRCNT*100)/16))/100; + u1RoundUp = (u2PRDCNTtmp + ((u1DQSOSCRCNT*100)/16))%100; + if (u1RoundUp != 0) + u2PRDCNT++; + + //Don't power down dram during DQS interval timer run time, (MR23[7:0] /4) + (tOSCO/MCK unit/16) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2PRDCNT, SHU_DQSOSC_SET0_DQSOSC_PRDCNT); + + //set tOSCO constraint to read MR18/MR19, should be > 40ns/MCK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSCR), u1DQSOSCRCNT, SHU_DQSOSCR_DQSOSCRCNT);//@Darren, unit: MCK to meet spec. tOSCO=40ns/MCK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), (u1FILT_PITHRD>>1), SHU_TX_SET0_DQS2DQ_FILT_PITHRD); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(u1W2R_SEL, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL)); + + /* Starting from Vinson, DQSOSCTHRD_INC & _DEC is split into RK0 and RK1 */ + //Rank 0 + + + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), gu2DQSOSCTHRD_INC[p->channel][u1RankIdx], SHURK_DQSOSC_THRD_DQSOSCTHRD_INC); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), gu2DQSOSCTHRD_DEC[p->channel][u1RankIdx], SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC); + } + vSetRank(p, u1RankIdxBak); + + //set interval to do MPC(start DQSOSC) command, and dramc send DQSOSC start to rank0/1/2 at the same time + //TX tracking period unit: 3.9us + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2DQSOSCENCNT, SHU_DQSOSC_SET0_DQSOSCENCNT); + + return DRAM_OK; +} + +void DramcHwDQSOSC(DRAMC_CTX_T *p) +{ + DRAM_RANK_T rank_bak = u1GetRank(p); + DRAM_CHANNEL_T ch_bak = p->channel; + + //Enable TX tracking new mode + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), 1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); + + //Enable Freq_RATIO update + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0), P_Fld(1, TX_TRACKING_SET0_SHU_PRELOAD_TX_HW) + | P_Fld(0, TX_TRACKING_SET0_SHU_PRELOAD_TX_START) + | P_Fld(0, TX_TRACKING_SET0_SW_UP_TX_NOW_CASE)); + + //DQSOSC MPC command violation +#if ENABLE_TMRRI_NEW_MODE + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 1, MPC_CTRL_MPC_BLOCKALE_OPT); +#else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0, MPC_CTRL_MPC_BLOCKALE_OPT); +#endif + + //DQS2DQ UI/PI setting controlled by HW + #if ENABLE_SW_TX_TRACKING + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW); + #else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW); + #if ENABLE_PA_IMPRO_FOR_TX_TRACKING + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 1, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING); + #endif + #endif + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW); + + //Set dqsosc oscillator run time by MRW + //write RK0 MR23 + #if 0 + vSetRank(p, RANK_0); + vSetPHY2ChannelMapping(p, CHANNEL_A); + DramcModeRegWrite(p, 23, u1MR23); + vSetPHY2ChannelMapping(p, CHANNEL_B); + DramcModeRegWrite(p, 23, u1MR23); + //write RK1 MR23 + vSetRank(p, RANK_1); + vSetPHY2ChannelMapping(p, CHANNEL_A); + DramcModeRegWrite(p, 23, u1MR23); + vSetPHY2ChannelMapping(p, CHANNEL_B); + DramcModeRegWrite(p, 23, u1MR23); + #endif + + //Enable HW read MR18/MR19 for each rank + #if ENABLE_SW_TX_TRACKING + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSCRDIS); + #else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_DQSOSCRDIS); + #endif + + vSetRank(p, RANK_0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN); + if (p->support_rank_num == RANK_DUAL) + { + vSetRank(p, RANK_1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN); + } + + //@Jouling, Update MP setting + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_DRSCLR_RK0_EN); //Set as 1 to fix issue of RANK_SINGLE, dual rank can also be enable + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSC_CALEN); + + vSetRank(p, rank_bak); + vSetPHY2ChannelMapping(p, ch_bak); +} + +void Enable_TX_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset) +{ + //DDR800 do not enable tracking + if (p->pDFSTable->shuffleIdx == SRAM_SHU6) //add if(u1ShuffleIdx==DRAM_DFS_SRAM_MAX) to avoid enable tx-tracking when running DDR800 as RG-SHU0 + { + vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0 + u4DramcShuOffset, 1, SHU_DQSOSC_SET0_DQSOSCENDIS); + } + else + { + vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0 + u4DramcShuOffset, 0, SHU_DQSOSC_SET0_DQSOSCENDIS); + } +} +#endif + +#if RDSEL_TRACKING_EN +void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset) +{ + //Only enable at DDR3733 + if (p->pDFSTable->shuffleIdx == SRAM_SHU0) //add if(u1ShuffleIdx==DRAM_DFS_SRAM_MAX) to avoid enable tx-tracking when running DDR800 as RG-SHU0 + { + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK + u4DramcShuOffset, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK + u4DramcShuOffset, P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) + | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK)); + } + else + { + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK + u4DramcShuOffset, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN); + } +} +#endif + +#ifdef HW_GATING +void Enable_Gating_Tracking(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset) +{ + if (p->pDFSTable->shuffleIdx == SRAM_SHU6) { + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL + u4DDRPhyShuOffset, + P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) | + P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN)); + } else { + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL + u4DDRPhyShuOffset, + P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | + P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN)); + } +} +#endif + +void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset) +{ + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13 + u4DDRPhyShuOffset, 1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ13 + u4DDRPhyShuOffset, 1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1); + + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10 + u4DDRPhyShuOffset, 1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10 + u4DDRPhyShuOffset, 1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1); + + // Set 1 to be make TX DQS/DQ/DQM PI take effect when TX OE low, for new cross rank mode. + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2 + u4DDRPhyShuOffset, 1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2 + u4DDRPhyShuOffset, 1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1); + + // Default settings before init + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11 + u4DDRPhyShuOffset, 1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11 + u4DDRPhyShuOffset, 1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11 + u4DDRPhyShuOffset, 1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA); + + // vReplaceDVInit + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10 + u4DDRPhyShuOffset, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA); +} + +#if ENABLE_TX_WDQS // @Darren, To avoid unexpected DQS toggle during calibration +void Enable_TxWDQS(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq) +{ +#if ENABLE_LP4Y_DFS + U8 DQSB_READ_BASE = u2Freq<=800 ? 0 : 1; // for LP4Y +#else + U8 DQSB_READ_BASE = 1; +#endif + + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ13 + u4DDRPhyShuOffset , P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 ) + | P_Fld(DQSB_READ_BASE, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 ) + | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0 ) + | P_Fld(DQSB_READ_BASE, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0 )); + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ13 + u4DDRPhyShuOffset , P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 ) + | P_Fld(DQSB_READ_BASE, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 ) + | P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1 ) + | P_Fld(DQSB_READ_BASE, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1 )); +} +#endif + +#if ENABLE_SW_TX_TRACKING & __ETT__ +void DramcSWTxTracking(DRAMC_CTX_T *p) +{ + U8 u1MR4OnOff; + U8 rankIdx, rankBak; + U8 u1SRAMShuLevel = get_shuffleIndex_by_Freq(p); + U8 u1CurrentShuLevel; + U16 u2MR1819_Base[RANK_MAX][2], u2MR1819_Runtime[RANK_MAX][2]; + U16 u2DQSOSC_INC[RANK_MAX] = {6}, u2DQSOSC_DEC[RANK_MAX] = {4}; + U8 u1AdjPI[RANK_MAX][2]; + U8 u1OriginalPI_DQ[DRAM_DFS_SHUFFLE_MAX][RANK_MAX][2]; + U8 u1UpdatedPI_DQ[DRAM_DFS_SHUFFLE_MAX][RANK_MAX][2]; + U8 u1OriginalPI_DQM[DRAM_DFS_SHUFFLE_MAX][RANK_MAX][2]; + U8 u1UpdatedPI_DQM[DRAM_DFS_SHUFFLE_MAX][RANK_MAX][2]; + U8 u1FreqRatioTX[DRAM_DFS_SHUFFLE_MAX]; + U8 shuIdx, shuBak, byteIdx; + + for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++) + { + DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_shuffleIndex(p, shuIdx); + if (pDstFreqTbl == NULL) + { + mcSHOW_ERR_MSG(("NULL pFreqTbl %d\n", shuIdx)); + while (1); + } + + if (pDstFreqTbl->freq_sel == LP4_DDR800) + { + u1FreqRatioTX[shuIdx] = 0; + } + else + { + u1FreqRatioTX[shuIdx] = ((GetFreqBySel(p, pDstFreqTbl->freq_sel)) * 8) / p->frequency; + mcSHOW_DBG_MSG(("[SWTxTracking] ShuLevel=%d, Ratio[%d]=%d (%d, %d)\n", u1SRAMShuLevel, shuIdx, u1FreqRatioTX[shuIdx], GetFreqBySel(p, pDstFreqTbl->freq_sel), p->frequency)); + } + } + + mcSHOW_DBG_MSG(("[SWTxTracking] channel=%d\n", p->channel)); + rankBak = u1GetRank(p); + shuBak = p->ShuRGAccessIdx; + + u1CurrentShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP); + + for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++) + { + if (shuIdx == p->pDFSTable->shuffleIdx) { + p->ShuRGAccessIdx = u1CurrentShuLevel; + } else { + LoadShuffleSRAMtoDramc(p, shuIdx, !u1CurrentShuLevel); + p->ShuRGAccessIdx = !u1CurrentShuLevel; + } + + for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++) + { + vSetRank(p, rankIdx); + + u1OriginalPI_DQ[shuIdx][p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQ_B0); + u1OriginalPI_DQ[shuIdx][p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQ_B1); + + u1OriginalPI_DQM[shuIdx][p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQM_B0); + u1OriginalPI_DQM[shuIdx][p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQM_B1); + } + } + + u1MR4OnOff = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), HMR4_REFRDIS); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS); + + p->ShuRGAccessIdx = u1CurrentShuLevel; + + for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++) + { + vSetRank(p, rankIdx); + + u2DQSOSC_INC[p->rank] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), SHURK_DQSOSC_THRD_DQSOSCTHRD_INC); + u2DQSOSC_DEC[p->rank] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC); + + u2MR1819_Base[p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), SHURK_DQSOSC_DQSOSC_BASE_RK0); + u2MR1819_Base[p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), SHURK_DQSOSC_DQSOSC_BASE_RK0_B1); + + DramcDQSOSCAuto(p); + + u2MR1819_Runtime[p->rank][0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8); + if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) + { + u2MR1819_Runtime[p->rank][1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00)); + } + else + { + u2MR1819_Runtime[p->rank][1] = u2MR1819_Runtime[p->rank][0]; + } + + //INC : MR1819>base. PI- + //DEC : MR1819<base. PI+ + for (byteIdx = 0; byteIdx < 2; byteIdx++) + { + U16 deltaMR1819 = 0; + + if (u2MR1819_Runtime[p->rank][byteIdx] >= u2MR1819_Base[p->rank][byteIdx]) + { + deltaMR1819 = u2MR1819_Runtime[p->rank][byteIdx] - u2MR1819_Base[p->rank][byteIdx]; + u1AdjPI[rankIdx][byteIdx] = deltaMR1819 / u2DQSOSC_INC[rankIdx]; + for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++) + { + u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]); + u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]); + mcSHOW_DBG_MSG(("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d INC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx + , u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_INC[rankIdx] + , u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx])); + } + } + else + { + deltaMR1819 = u2MR1819_Base[p->rank][byteIdx] - u2MR1819_Runtime[p->rank][byteIdx]; + u1AdjPI[rankIdx][byteIdx] = deltaMR1819 / u2DQSOSC_DEC[rankIdx]; + for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++) + { + u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]); + u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]); + mcSHOW_DBG_MSG(("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d DEC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx + , u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_DEC[rankIdx] + , u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx])); + } + } + } + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_TXUPDMODE); + + p->ShuRGAccessIdx = !u1CurrentShuLevel; + for (shuIdx = 0; shuIdx < DRAM_DFS_SHUFFLE_MAX; shuIdx++) + { + LoadShuffleSRAMtoDramc(p, shuIdx, !u1CurrentShuLevel); + + for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++) + { + vSetRank(p, rankIdx); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), + P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | + P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), + P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | + P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1)); + } + + DramcSaveToShuffleSRAM(p, !u1CurrentShuLevel, shuIdx); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_MANUTXUPD); + + while ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TCMDO1LAT), TCMDO1LAT_MANUTXUPD_B0_DONE) != 1) && (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TCMDO1LAT), TCMDO1LAT_MANUTXUPD_B1_DONE) != 1)) + { + mcDELAY_US(1); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_TXUPDMODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_MANUTXUPD); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), u1MR4OnOff, HMR4_REFRDIS); + + vSetRank(p, rankBak); + p->ShuRGAccessIdx = shuBak; +} +#endif + + +#if ENABLE_RX_TRACKING +void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p) +{ + U8 ii, backup_rank; + U32 u4WbrBackup = GetDramcBroadcast(); + + backup_rank = u1GetRank(p); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + + //Enable RX_FIFO macro DIV4 clock CG + vIO32WriteFldAlign((DDRPHY_REG_MISC_CG_CTRL1), 0xffffffff, MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL); + + for (ii = RANK_0; ii < p->support_rank_num; ii++) + { + vSetRank(p, ii); + + //DVS mode to RG mode + vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x0, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0); + vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x0, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1); + + //Turn off F_DLY individual calibration option (CTO_AGENT_RDAT cannot separate DR/DF error) + //tracking rising and update rising/falling together + vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x1, RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0); + vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x1, RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1); + + //DQ/DQM/DQS DLY MAX/MIN value under Tracking mode + /* DQS, DQ, DQM (DQ, DQM are tied together now) -> controlled using DQM MAX_MIN */ + + /* Byte 0 */ + vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS3), P_Fld(0x0, RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0) | P_Fld(0xff, RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0)); + vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS4), P_Fld(0x0, RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0) | P_Fld(0x1ff, RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0)); + + /* Byte 1 */ + vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS3), P_Fld(0x0, RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1) | P_Fld(0xff, RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1)); + vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS4), P_Fld(0x0, RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1) | P_Fld(0x1ff, RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1)); + + //Threshold for LEAD/LAG filter + vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS1), P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD) | P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG)); + vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS1), P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD) | P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG)); + + //DQ/DQS Rx DLY adjustment for tracking mode + vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0) | P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0)); + vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1) | P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1)); + + vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0) | P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0)); + vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1) | P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1)); + + } + vSetRank(p, backup_rank); + + //Tracking lead/lag counter >> Rx DLY adjustment fixed to 1 + vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x0, B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0); + vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x0, B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1); + + //DQIEN pre-state option to block update for RX ASVA 1-2 + vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0); + vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1); + + DramcBroadcastOnOff(u4WbrBackup); +} +#endif + +void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p) +{ + U8 u1DVS_Delay; + U8 u1DVS_En=1; + U32 u4WbrBackup = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + + //Monitor window size setting + //DDRPHY.SHU*_B*_DQ5.RG_RX_ARDQS0_DVS_DLY_B* (suggested value from A-PHY owner) +//WHITNEY_TO_BE_PORTING +#if (fcFOR_CHIP_ID == fcMargaux) + // 6400 5500 4266 3733 3200 2400 1600 1200 800 + //UI 156p 181p 234p 268p 312p 417p 625p 833p 1250p + //DVS_EN O O O O O O X X X + //INI 1 2 3 N=5 N=5 N=7 N=12 N=15 N=15 + //DVS delay O O O X X X X X X + //calibration + + if(p->frequency >= 3200) + { + u1DVS_Delay =1; + } + else if(p->frequency >= 2250) + { + u1DVS_Delay = 2; + } + else if(p->frequency >= 2133) + { + u1DVS_Delay = 3; + } + else if(p->frequency >= 1600) + { + u1DVS_Delay =5; + } + else if(p->frequency >= 1200) + { + u1DVS_Delay =7; + } + else if(p->frequency >= 800) + { + u1DVS_Delay =12; + u1DVS_En =0; + } + else + { + u1DVS_Delay =15; + u1DVS_En =0; + } +#endif + + vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ5), u1DVS_Delay, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0); + vIO32WriteFldAlign((DDRPHY_REG_SHU_B1_DQ5), u1DVS_Delay, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1); + + /* Bian_co HW design issue: run-time PBYTE flag will lose it's function and become per-bit -> set to 0 */ + vIO32WriteFldMulti((DDRPHY_REG_SHU_B0_DQ7), P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) + | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)); + vIO32WriteFldMulti((DDRPHY_REG_SHU_B1_DQ7), P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) + | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)); + + //Enable A-PHY DVS LEAD/LAG + vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ11), u1DVS_En, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0); + vIO32WriteFldAlign((DDRPHY_REG_SHU_B1_DQ11), u1DVS_En, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1); + + DramcBroadcastOnOff(u4WbrBackup); +} + +#if ENABLE_RX_TRACKING +void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p) +{ + DRAM_CHANNEL_T channel_bak = p->channel; + U8 ii, backup_rank; + U32 u4WbrBackup = GetDramcBroadcast(); + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); + + vSetPHY2ChannelMapping(p, CHANNEL_A); + backup_rank = u1GetRank(p); + + //Rx DLY tracking setting (Static) + vIO32WriteFldMulti((DDRPHY_REG_B0_RXDVS0), + P_Fld(1, B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0) | + P_Fld(0, B0_RXDVS0_R_RX_RANKINCTL_B0) | + P_Fld(1, B0_RXDVS0_R_RX_RANKINSEL_B0)); + + vIO32WriteFldMulti((DDRPHY_REG_B1_RXDVS0), + P_Fld(1, B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1) | + P_Fld(0, B1_RXDVS0_R_RX_RANKINCTL_B1) | + P_Fld(1, B1_RXDVS0_R_RX_RANKINSEL_B1)); + + vIO32WriteFldMulti((DDRPHY_REG_B0_DQ9), P_Fld(0x1, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0 | P_Fld(0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0))); + vIO32WriteFldMulti((DDRPHY_REG_B1_DQ9), P_Fld(0x1, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1) | P_Fld(0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1)); + vIO32WriteFldMulti((DDRPHY_REG_CA_CMD9), P_Fld(0, CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_VALID_LAT_CA)); + + //Rx DLY tracking function CG enable + vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0); + vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1); + + //Rx DLY tracking lead/lag counter enable + vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0); + vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1); + + //fra 0: origin mode (use LEAD/LAG rising tracking) 1: new mode (use LEAD/LAG rising/fall tracking, more faster) + vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS1), 1, B0_RXDVS1_F_LEADLAG_TRACK_B0); + vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS1), 1, B1_RXDVS1_F_LEADLAG_TRACK_B1); + + for (ii = RANK_0; ii < RANK_MAX; ii++) + { + vSetRank(p, ii); + + //Rx DLY tracking update enable (HW mode) + vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), + P_Fld(2, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0) | + P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0) | + P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0)); + + vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), + P_Fld(2, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1) | + P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1) | + P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1)); + } + vSetRank(p, backup_rank); + + //Rx DLY tracking: "TRACK_CLR" let rx_dly reload the correct dly setting + vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 1, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0); + vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 1, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1); + vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0); + vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1); + + DramcBroadcastOnOff(u4WbrBackup); +} +#endif + +///TODO: wait for porting +++ +#if __A60868_TO_BE_PORTING__ +#if RX_DLY_TRACK_ONLY_FOR_DEBUG +void DramcRxDlyTrackDebug(DRAMC_CTX_T *p) +{ + /* indicate ROW_ADR = 2 for dummy write & read for Rx dly track debug feature, avoid pattern overwrite by MEM_TEST + * pattern(0xAAAA5555) locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */ + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(2, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR) + | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR) + | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN)); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(2, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR) + | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR) + | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN)); + vIO32WriteFldAlign_All(DRAMC_REG_RK0_DUMMY_RD_BK, 0, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK); + vIO32WriteFldAlign_All(DRAMC_REG_RK1_DUMMY_RD_BK, 0, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK); + + vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA0, 0xAAAA5555); + vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA1, 0xAAAA5555); + vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA2, 0xAAAA5555); + vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA3, 0xAAAA5555); + vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA0, 0xAAAA5555); + vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA1, 0xAAAA5555); + vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA2, 0xAAAA5555); + vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA3, 0xAAAA5555); + + //disable Rx dly track debug and clear status lock + vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN) + | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR) + | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN)); + + //trigger dummy write pattern 0xAAAA5555 + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG); + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG); + + // enable Rx dly track debug feature + vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN) + | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR) + | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN)); +} + +void DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T *p) +{ + U32 backup_rank, u1ChannelBak, u4value; + U8 u1ChannelIdx, u1ChannelMax = p->support_channel_num;//channel A/B ... + + u1ChannelBak = p->channel; + backup_rank = u1GetRank(p); + + for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++) + { + p->channel = u1ChannelIdx; + + u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO18)); + //mcSHOW_DBG_MSG(("\nCH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m\n",u1ChannelIdx,u4value)); + if (u4value & 1) + { + mcSHOW_DBG_MSG(("=== CH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m, %s %s shu: %d\n", u1ChannelIdx, u4value, + u4value & 0x2? "RK0: fail":"",u4value&0x4?"RK1: fail":"", (u4value >> 4) & 0x3)); + } + } +} +#endif + +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) +#if (__ETT__ || CPU_RW_TEST_AFTER_K) +void DramcPrintRXDQDQSStatus(DRAMC_CTX_T *p, U8 u1Channel) +{ + U8 u1RankIdx, u1RankMax, u1ChannelBak, u1ByteIdx, ii; + U32 u4ResultDQS_PI, u4ResultDQS_UI, u4ResultDQS_UI_P1; + U8 u1Dqs_pi[DQS_BIT_NUMBER], u1Dqs_ui[DQS_BIT_NUMBER], u1Dqs_ui_P1[DQS_BIT_NUMBER]; + U16 u2TmpValue, u2TmpUI[DQS_NUMBER], u2TmpPI[DQS_NUMBER]; + U32 MANUDLLFRZ_bak, STBSTATE_OPT_bak; + U32 backup_rank; + U8 u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1; + + u1ChannelBak = p->channel; + vSetPHY2ChannelMapping(p, u1Channel); + backup_rank = u1GetRank(p); + + if (p->support_rank_num == RANK_DUAL) + u1RankMax = RANK_MAX; + else + u1RankMax = RANK_1; + + for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + mcSHOW_DBG_MSG(("[RXDQDQSStatus] CH%d, RK%d\n", p->channel, u1RankIdx)); + if (u1RankIdx == 0) + u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO22)); + if (u1RankIdx == 1) + u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO23)); + + u1DQX_B0 = u4ResultDQS_PI & 0xff; + u1DQS0 = (u4ResultDQS_PI >> 8) & 0xff; + u1DQX_B1 = (u4ResultDQS_PI >> 16) & 0xff; + u1DQS1 = (u4ResultDQS_PI >> 24) & 0xff; + + mcSHOW_DBG_MSG(("DQX_B0, DQS0, DQX_B1, DQS1 =(%d, %d, %d, %d)\n\n", u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1)); + + } + vSetRank(p, backup_rank); + + p->channel = u1ChannelBak; + vSetPHY2ChannelMapping(p, u1ChannelBak); +} +#endif +#endif + +void DummyReadForDqsGatingRetryShuffle(DRAMC_CTX_T *p, bool bEn) +{ + if (bEn == 1) + { + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM)//Retry once + | P_Fld(1, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE) + | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN) + | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN) + | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE) + | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE) + | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS)); + } + else + { + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE) + | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN) + | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN)); + } + return; +} + +void DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T *p, bool bEn) +{ + U8 backup_rank = p->rank; + U8 rankIdx; + + if (bEn == 1) + { + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent + vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DQSG_DMYRD_EN) + | P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM) + | P_Fld(1, DUMMY_RD_DUMMY_RD_SW)); + for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++) + { + vSetRank(p, rankIdx); + vIO32WriteFldAlign_All(DRAMC_REG_RK_DUMMY_RD_ADR, 0, RK_DUMMY_RD_ADR_DMY_RD_LEN); + } + vSetRank(p, backup_rank); + } + else + { + } + return; +} + +#endif // __A60868_TO_BE_PORTING__ + +#ifdef DUMMY_READ_FOR_TRACKING +void DramcDummyReadAddressSetting(DRAMC_CTX_T *p) +{ + U8 backup_channel = p->channel, backup_rank = p->rank; + U8 channelIdx, rankIdx; + dram_addr_t dram_addr; + + for (channelIdx = CHANNEL_A; channelIdx < CHANNEL_NUM; channelIdx++) + { + vSetPHY2ChannelMapping(p, channelIdx); + for (rankIdx = RANK_0; rankIdx < RANK_MAX; rankIdx++) + { + vSetRank(p, rankIdx); + + dram_addr.ch = channelIdx; + dram_addr.rk = rankIdx; + + get_dummy_read_addr(&dram_addr); + mcSHOW_DBG_MSG3(("=== dummy read address: CH_%d, RK%d, row: 0x%x, bk: %d, col: 0x%x\n\n", + channelIdx, rankIdx, dram_addr.row, dram_addr.bk, dram_addr.col)); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR2), P_Fld(dram_addr.row, RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR) + | P_Fld(dram_addr.bk, RK_DUMMY_RD_ADR2_DMY_RD_BK)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), P_Fld(dram_addr.col, RK_DUMMY_RD_ADR_DMY_RD_COL_ADR) + | P_Fld(0, RK_DUMMY_RD_ADR_DMY_RD_LEN)); + } + } + + vSetPHY2ChannelMapping(p, backup_channel); + vSetRank(p, backup_rank); + +} + +void DramcDummyReadForTrackingEnable(DRAMC_CTX_T *p) +{ + U8 backup_rank = p->rank; + U8 rankIdx; + + /* Dummy read pattern (Better efficiency during rx dly tracking) DE: YH Tsai, Wei-jen */ + for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++) + { + vSetRank(p, rankIdx); + + vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA0, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA0_DMY_RD_RK0_WDATA0 + vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA1, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA1_DMY_RD_RK0_WDATA1 + vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA2, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA2_DMY_RD_RK0_WDATA2 + vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA3, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA3_DMY_RD_RK0_WDATA3 + } + vSetRank(p, backup_rank); + + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent + +#if 0//__ETT__ + /* indicate ROW_ADR = 2 for Dummy Write pattern address, in order to avoid pattern will be overwrited by MEM_TEST(test range 0xffff) + * Pattern locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */ + dram_addr_t dram_addr; + + dram_addr.ch = 0; + dram_addr.rk = 0; + get_dummy_read_addr(&dram_addr); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR) + | P_Fld(dram_addr.col, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR) + | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN)); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_BK), dram_addr.bk, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK); + + dram_addr.rk = 1; + get_dummy_read_addr(&dram_addr); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR) + | P_Fld(dram_addr.col, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR) + | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN)); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_BK), dram_addr.bk, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK); + + /* trigger dummy write pattern 0xAAAA5555 */ + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG); + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG); +#else + DramcDummyReadAddressSetting(p); +#endif + + /* DUMMY_RD_RX_TRACK = 1: + * During "RX input delay tracking enable" and "DUMMY_RD_EN=1" Dummy read will force a read command to a certain rank, + * ignoring whether or not EMI has executed a read command to that certain rank in the past 4us. + */ + + if (p->frequency >= 1600) + { + vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DMY_RD_RX_TRACK) | P_Fld(1, DUMMY_RD_DUMMY_RD_EN)); + mcSHOW_DBG_MSG(("High Freq DUMMY_READ_FOR_TRACKING: ON\n")); + } + else + { + mcSHOW_DBG_MSG(("Low Freq DUMMY_READ_FOR_TRACKING: OFF\n")); + } + + return; +} +#endif + +#ifdef IMPEDANCE_HW_SAVING +void DramcImpedanceHWSaving(DRAMC_CTX_T *p) +{ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_HWSAVE_EN); +} +#endif + +#ifdef IMPEDANCE_TRACKING_ENABLE +void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p) +{ + U8 u1CHAB_en = DISABLE; + #if 0 //Impedance tracking offset for DRVP+2 + vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL1, P_Fld(2, IMPEDAMCE_CTRL1_DQS1_OFF) | P_Fld(2, IMPEDAMCE_CTRL1_DOS2_OFF)); + vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL2, P_Fld(2, IMPEDAMCE_CTRL2_DQ1_OFF) | P_Fld(2, IMPEDAMCE_CTRL2_DQ2_OFF)); + #endif + + //Write (DRAMC _BASE+ 0x8B) [31:0] = 32'he4000000//enable impedance tracking + //u1CHAB_en = (p->support_channel_num == CHANNEL_DUAL) ? ENABLE : DISABLE;// @tg Only CHA do Impcal tracking for Margaux + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, u1CHAB_en, MISC_CTRL0_IMPCAL_CHAB_EN);//Set CHA this bit to enable dual channel tracking + + //During shuffle, after CH_A IMP update done, CH_B has no enough time to update (IMPCAL_IMPCAL_DRVUPDOPT=1) + //enable ECO function for impedance load last tracking result of previous shuffle level (IMPCAL_IMPCAL_CHGDRV_ECO_OPT=1) + //enable ECO function for impcal_sm hange when DRVP>=0x1D (IMPCAL_IMPCAL_SM_ECO_OPT=1) + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_HW) | P_Fld(0, MISC_IMPCAL_IMPCAL_EN) | + P_Fld(1, MISC_IMPCAL_IMPCAL_SWVALUE_EN) | P_Fld(1, MISC_IMPCAL_IMPCAL_NEW_OLD_SL) | + P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT) | P_Fld(1, MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT) | + P_Fld(1, MISC_IMPCAL_IMPCAL_SM_ECO_OPT) | P_Fld(1, MISC_IMPCAL_IMPBINARY) | + P_Fld(1, MISC_IMPCAL_DRV_ECO_OPT)); + + //dual channel continuously tracking @ system busy, self-refresh, Hhbrid-S1 + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, 0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT); + //@tg.Only CHA do Impcal tracking, CHB sync CHA result value + vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | + P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | + P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE)); + + // no update imp CA, because CA is unterm now + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV); + + // CH_A set 1, CH_B set 0 (mp setting) + vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | + P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV) | + P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | //Update mp setting + P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting + vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHB_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | + P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV) | + P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | //Update mp setting + P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting +#if (CHANNEL_NUM > 2) + vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV)); +#endif + + //Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode) + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DRVCGWREF); //@Maoauo, Wait AB refresh to avoid IO drive via logic design + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DQDRVSWUPD); +} +#endif + +/* divRoundClosest() - to round up to the nearest integer + * discard four, but treat five as whole (of decimal points) + */ +static int divRoundClosest(const int n, const int d) +{ + return ((n < 0) ^ (d < 0))? ((n - d / 2) / d): ((n + d / 2) / d); +} + + +#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS) +void FreqJumpRatioCalculation(DRAMC_CTX_T *p) +{ + U32 shuffle_src_freq, shuffle_dst_index, jump_ratio_index; + U16 u2JumpRatio[12] = {0}; /* Used to record __DBQUOTE_ANCHOR__ calulation results */ + U16 u2Freq = 0; + + /* Calculate jump ratios and save to u2JumpRatio array */ + jump_ratio_index = 0; + + if (p->frequency != 400) + { + shuffle_src_freq = p->frequency; + for (shuffle_dst_index = DRAM_DFS_SHUFFLE_1; shuffle_dst_index < DRAM_DFS_SHUFFLE_MAX; shuffle_dst_index++) + { + DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_shuffleIndex(p, shuffle_dst_index); + if (pDstFreqTbl == NULL) + { + mcSHOW_ERR_MSG(("NULL pFreqTbl\n")); + #if __ETT__ + while (1); + #endif + } + #if 0 //cc mark since been removed in new flow + if (pDstFreqTbl->freq_sel == LP4_DDR800) + { + u2JumpRatio[jump_ratio_index] = 0; + } + else + #endif + { + u2Freq = GetFreqBySel(p, pDstFreqTbl->freq_sel); + u2JumpRatio[jump_ratio_index] = divRoundClosest(u2Freq * 32, shuffle_src_freq); + //u2JumpRatio[jump_ratio_index] = (pDstFreqTbl->frequency/shuffle_src_freq)*32; + //mcSHOW_DBG_MSG3(("shuffle_%d=DDR%d / shuffle_%d=DDR%d \n", shuffle_dst_index, pFreqTbl->frequency<<1, + // shuffle_src_index, get_FreqTbl_by_shuffleIndex(p,shuffle_src_index)->frequency<<1)); + //mcSHOW_DBG_MSG3(("Jump_RATIO_%d : 0x%x\n", jump_ratio_index, u2JumpRatio[jump_ratio_index], + // get_FreqTbl_by_shuffleIndex(p,shuffle_src_index)->frequency)); + } + mcSHOW_DBG_MSG3(("Jump_RATIO [%d]: %x\tFreq %d -> %d\tDDR%d -> DDR%d\n", jump_ratio_index, u2JumpRatio[jump_ratio_index], get_shuffleIndex_by_Freq(p), shuffle_dst_index, shuffle_src_freq << 1, u2Freq << 1)); + jump_ratio_index++; + } + } + + /* Save jumpRatios into corresponding register fields */ + vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(u2JumpRatio[0], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0) + | P_Fld(u2JumpRatio[1], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) + | P_Fld(u2JumpRatio[2], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) + | P_Fld(u2JumpRatio[3], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3)); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET1, P_Fld(u2JumpRatio[4], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4) + | P_Fld(u2JumpRatio[5], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5) + | P_Fld(u2JumpRatio[6], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6) + | P_Fld(u2JumpRatio[7], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7)); + vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET2, P_Fld(u2JumpRatio[8], SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8) + | P_Fld(u2JumpRatio[9], SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9)); + return; +} +#endif + + +#if TDQSCK_PRECALCULATION_FOR_DVFS +void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p) +{ + U8 mck, ui, pi; + U8 mck_p1, ui_p1; + U8 byte_idx, rank; + U8 backup_rank; + U8 mck2ui; + + backup_rank = u1GetRank(p); + +#if 1//(fcFOR_CHIP_ID == fcMargaux) + mck2ui = 4; +#else + ///TODO: use vGet_Div_Mode() instead later + if (vGet_Div_Mode(p) == DIV16_MODE) + mck2ui = 4; /* 1:16 mode */ + else if (vGet_Div_Mode(p) == DIV8_MODE) + mck2ui = 3; /* 1: 8 mode */ + else + mck2ui = 2; /* 1: 4 mode */ +#endif + + mcSHOW_DBG_MSG(("Pre-setting of DQS Precalculation\n")); + + for (byte_idx = 0; byte_idx < (p->data_width / DQS_BIT_NUMBER); byte_idx++) { + for (rank = RANK_0; rank < p->support_rank_num; rank++) { + vSetRank(p, rank); + + if (byte_idx == 0) { + mck = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0); + ui = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0); + + mck_p1= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0); + ui_p1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0); + + pi = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), + P_Fld((mck << mck2ui) + ui, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0) | + P_Fld(pi, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI), + P_Fld((mck << mck2ui) +ui, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | + P_Fld((mck_p1 << mck2ui) + ui_p1, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0) | + P_Fld(pi, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0)); + } else { + mck = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1); + ui = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1); + + mck_p1= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1); + ui_p1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1); + + pi = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), + P_Fld((mck << mck2ui) + ui, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1) | + P_Fld(pi, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI), + P_Fld((mck << mck2ui) +ui, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | + P_Fld((mck_p1 << mck2ui) + ui_p1, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1) | + P_Fld(pi, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0)); + } + } + } + + vSetRank(p, backup_rank); + + /* Disable DDR800semi precal */ + if (vGet_Current_ShuLevel(p) == SRAM_SHU6) {///TODO: Confirm DDR800's shuffle + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_PRE_TDQSCK), + 0x1, SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL), + 0x1, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN); + } + else + { + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_PRE_TDQSCK), + 0x0, SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL), + 0x0, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN); + } +} + +#if 0 +void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calculation +{ + U8 u1ByteIdx, u1RankNum, u1RankBackup = p->rank; + U8 u1ShuLevel = vGet_Current_ShuLevel(p); + U8 u1UI_value, u1PI_value, u1MCK_value; + U16 u2Byte_offset; + U32 u1Delay_Addr[2] = {0}, u1Delay_Fld[2]; + REG_FLD_DQS_PRE_K TransferReg; + + mcSHOW_DBG_MSG(("Pre-setting of DQS Precalculation\n")); + mcDUMP_REG_MSG(("Pre-setting of DQS Precalculation\n")); + + if ((u1ShuLevel >= SRAM_SHU4) && (u1ShuLevel <= SRAM_SHU7)) + { //SHU4, 5, 6, 7 + u1Delay_Addr[0] = ((u1ShuLevel / 6) * 0x4) + 0x30; //Offset of phase0 UI register + u1Delay_Addr[1] = 0x38; //Offset of phase1 UI register + u2Byte_offset = 0xc; + } + else if (u1ShuLevel >= SRAM_SHU8) + { //SHU8, 9 + u1Delay_Addr[0] = 0x260; //Offset of phase0 UI register + u1Delay_Addr[1] = 0x268; //Offset of phase1 UI register + u2Byte_offset = 0x4; + } + else //SHU0, 1, 2, 3 + { + u1Delay_Addr[0] = ((u1ShuLevel / 2) * 0x4); //Offset of phase0 UI register + u1Delay_Addr[1] = 0x8; //Offset of phase1 UI register + u2Byte_offset = 0xc; + } + + u1Delay_Fld[0] = u1ShuLevel % 2; //Field of phase0 PI and UI + u1Delay_Fld[1] = u1ShuLevel % 4; //Field of phase1 UI + + switch (u1Delay_Fld[0]) //Phase0 UI and PI + { + case 0: + TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0; + TransferReg.u4PI_Fld = RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0; + break; + case 1: + TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0; + TransferReg.u4PI_Fld = RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0; + break; + default: + break; + } + + if (u1ShuLevel == SRAM_SHU8) + { + TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B0R0; //Byte0 + TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B1R0; //Byte1 + } + else if (u1ShuLevel == SRAM_SHU9) + { + TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B0R0; //Byte0 + TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B1R0; //Byte1 + } + else //(u1ShuLevel < SRAM_SHU8) + { + switch (u1Delay_Fld[1]) //Phase1 UI + { + case 0: + TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0; + break; + case 1: + TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0; + break; + case 2: + TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0; + break; + case 3: + TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0; + break; + default: + break; + } + } + + for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++) + { + for (u1RankNum = 0; u1RankNum < p->support_rank_num; u1RankNum++) + { + vSetRank(p, u1RankNum); + + if (u1ByteIdx == 0) + { + u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED); + u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED); + u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS0IEN); + } + else //Byte1 + { + u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED); + u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED); + u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS1IEN); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld);//UI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), u1PI_value, TransferReg.u4PI_Fld); //PI + + if (u1ByteIdx == 0) + { + u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1); + u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1); + } + else //Byte1 + { + u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1); + u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1); + } + + if ((u1ShuLevel == SRAM_SHU8) || (u1ShuLevel == SRAM_SHU9)) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1]), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[u1ByteIdx]); //phase1 UI + else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[0]); //phase1 UI + } + } + vSetRank(p, u1RankBackup); + + return; +} +#endif + +void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p) +{ + //DQS pre-K new mode + //cc mark removed vIO32WriteFldAlign_All(DRAMC_REG_RK0_PRE_TDQSCK15, 0x1, RK0_PRE_TDQSCK15_SHUFFLE_LEVEL_MODE_SELECT); + //Enable pre-K HW + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW); + //Select HW flow + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS); + //Set Auto save to RG + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL); +} +#endif + +#if 0 /* CC mark to use DV initial setting */ +void DramcHWGatingInit(DRAMC_CTX_T *p) +{ +#ifdef HW_GATING + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + 0, MISC_SHU_STBCAL_STBCALEN); + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), + P_Fld(0, MISC_STBCAL_STBCAL2R) | + //cc mark P_Fld(0,STBCAL_STB_SELPHYCALEN) | + P_Fld(0, MISC_STBCAL_STBSTATE_OPT) | + P_Fld(0, MISC_STBCAL_RKCHGMASKDIS) | + P_Fld(0, MISC_STBCAL_REFUICHG) | + P_Fld(1, MISC_STBCAL_PICGEN)); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), P_Fld(1, MISC_STBCAL_DQSIENCG_CHG_EN)); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_CG_RKEN); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 1, MISC_STBCAL_DQSIENCG_NORMAL_EN); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMDQSIENCG_EN); + + DramcHWDQSGatingTracking_ModeSetting(p); +#endif +} +#endif + +void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff) +{ +#ifdef HW_GATING + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, + P_Fld(u1OnOff, MISC_DVFSCTL2_R_DVFS_OPTION) | + P_Fld(u1OnOff, MISC_DVFSCTL2_R_DVFS_PARK_N)); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), + u1OnOff, MISC_STBCAL2_STB_GERRSTOP); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + u1OnOff, MISC_SHU_STBCAL_STBCALEN); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + u1OnOff, MISC_SHU_STBCAL_STB_SELPHCALEN); +#else + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, + P_Fld(0x0, MISC_DVFSCTL2_R_DVFS_OPTION) | + P_Fld(0x0, MISC_DVFSCTL2_R_DVFS_PARK_N)); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, + MISC_STBCAL2_STB_GERRSTOP); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + 0, MISC_SHU_STBCAL_STBCALEN); + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), + 0, MISC_SHU_STBCAL_STB_SELPHCALEN); +#endif +} + + +void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff) +{ +#ifdef HW_GATING + // STBCAL2_STB_DBG_EN = 0x3, byte0/1 enable + U8 u1EnB0B1 = (u1OnOff == ENABLE)? 0x3: 0x0; + + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2, + P_Fld(u1EnB0B1, MISC_STBCAL2_STB_DBG_EN) | + P_Fld(u1OnOff, MISC_STBCAL2_STB_PIDLYCG_IG) | + P_Fld(u1OnOff, MISC_STBCAL2_STB_UIDLYCG_IG) | + P_Fld(u1OnOff, MISC_STBCAL2_STB_GERRSTOP) | + P_Fld(0, MISC_STBCAL2_STB_DBG_CG_AO) | + P_Fld(0, MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT)); +#endif + +#if ENABLE_RX_FIFO_MISMATCH_DEBUG + vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 1, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 1, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1); +#endif +} + +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) +#if (__ETT__ || CPU_RW_TEST_AFTER_K) +#if 0 // Please use memeset to initail value, due to different CHANNEL_NUM +U16 u2MaxGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +U16 u2MinGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +#endif +void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel) +{ +#ifdef HW_GATING + U8 u1RankIdx, u1RankMax, u1ChannelBak; + U8 u1Dqs_pi[DQS_BIT_NUMBER]={0}, u1Dqs_ui[DQS_BIT_NUMBER]={0}, u1Dqs_ui_P1[DQS_BIT_NUMBER]={0}; + U32 MANUDLLFRZ_bak, STBSTATE_OPT_bak; + U32 backup_rank; + + u1ChannelBak = p->channel; + vSetPHY2ChannelMapping(p, u1Channel); + backup_rank = u1GetRank(p); + + if (p->support_rank_num == RANK_DUAL) + u1RankMax = RANK_MAX; + else + u1RankMax = RANK_1; + + MANUDLLFRZ_bak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), DLLFRZ_CTRL_MANUDLLFRZ); + STBSTATE_OPT_bak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), MISC_STBCAL_STBSTATE_OPT); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), 1, DLLFRZ_CTRL_MANUDLLFRZ); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 1, MISC_STBCAL_STBSTATE_OPT); + + for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + mcSHOW_DBG_MSG(("[DramcHWGatingStatus] Channel=%d, Rank=%d\n", p->channel, u1RankIdx)); + + u1Dqs_pi[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0), + GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0); + u1Dqs_ui[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0), + GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P0_DLY_RK0); + u1Dqs_ui_P1[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0), + GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P1_DLY_RK0);; + + u1Dqs_pi[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0), + GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_PI_DLY_RK0); + u1Dqs_ui[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0), + GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P0_DLY_RK0); + u1Dqs_ui_P1[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0), + GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0);; + + mcSHOW_DBG_MSG(("Byte0(ui, pi) =(%d, %d)\n Byte1(ui, pi) =(%d, %d)\n", + u1Dqs_ui[0], u1Dqs_pi[0], u1Dqs_ui[1], u1Dqs_pi[1])); + mcSHOW_DBG_MSG(("UI_Phase1 (DQS0~3) =(%d, %d, %d, %d)\n\n", + u1Dqs_ui_P1[0], u1Dqs_ui_P1[1], u1Dqs_ui_P1[2], u1Dqs_ui_P1[3])); + } + + vSetRank(p, backup_rank); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), STBSTATE_OPT_bak, MISC_STBCAL_STBSTATE_OPT); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), MANUDLLFRZ_bak, DLLFRZ_CTRL_MANUDLLFRZ); + + p->channel = u1ChannelBak; + vSetPHY2ChannelMapping(p, u1ChannelBak); +#endif +} + +void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel) +{ +#ifdef HW_GATING +#if __A60868_TO_BE_PORTING__ + U8 u1RankIdx, u1RankMax, u1Info_NUM, u1Info_Max_MUM = 16; + U8 u1ChannelBak, u1RankBak; + + U8 u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI, u1DBG_Dqs0_PI; + U8 u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI, u1DBG_Dqs1_PI; + U16 u4DBG_Dqs0_Info, u4DBG_Dqs1_Info; + U32 u4DBG_Dqs01_Info; + + U32 u4Dqs0_MAX_MIN_DLY, u4Dqs1_MAX_MIN_DLY; + U16 u2Dqs0_UI_MAX_DLY, u2Dqs0_PI_MAX_DLY, u2Dqs0_UI_MIN_DLY, u2Dqs0_PI_MIN_DLY; + U16 u2Dqs1_UI_MAX_DLY, u2Dqs1_PI_MAX_DLY, u2Dqs1_UI_MIN_DLY, u2Dqs1_PI_MIN_DLY; + U8 u1ShuffleLevel; + + u1ChannelBak = p->channel; + vSetPHY2ChannelMapping(p, u1Channel); + u1RankBak = u1GetRank(p); + + if (p->support_rank_num == RANK_DUAL) + u1RankMax = RANK_MAX; + else + u1RankMax = RANK_1; + + //Run Time HW Gating Debug Information + //for(u1RankIdx=0; u1RankIdx<u1RankMax; u1RankIdx++) + for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) + { + vSetRank(p, u1RankIdx); + + u1ShuffleLevel = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL); + + mcSHOW_DBG_MSG3(("\n[HWGatingTrackingRecord] Channel=%d, Rank=%d, SHU_LEVEL=%d\n", p->channel, u1RankIdx, u1ShuffleLevel)); + + mcSHOW_DBG_MSG3(("Run Time HW Gating Debug Information :\n")); + mcSHOW_DBG_MSG3((" B0=(DFS,Lead,Lag,4T, UI, PI), B1=(DFS,Lead,Lag,4T, UI, PI)\n")); + + for (u1Info_NUM = 0; u1Info_NUM < u1Info_Max_MUM; u1Info_NUM++) + { + //DFS_ST(Shuffle Level): bit[15:14] + //Shift_R(Lead): bit[13] + //Shift_L(Lag) : bit[12] + //UI_DLY : bit[11:06] + //PI_DLY : bit[05:00] + u4DBG_Dqs01_Info = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B01_STB_DBG_INFO_00 + 0x4 * u1Info_NUM)); + u4DBG_Dqs0_Info = (u4DBG_Dqs01_Info >> 0) & 0xffff; + u4DBG_Dqs1_Info = (u4DBG_Dqs01_Info >> 16) & 0xffff; + + u1DBG_Dqs0_DFS = (u4DBG_Dqs0_Info >> 14) & 0x03; + u1DBG_Dqs0_Lead = (u4DBG_Dqs0_Info >> 13) & 0x01; + u1DBG_Dqs0_Lag = (u4DBG_Dqs0_Info >> 12) & 0x01; + u1DBG_Dqs0_UI = (u4DBG_Dqs0_Info >> 6) & 0x3f; + u1DBG_Dqs0_PI = (u4DBG_Dqs0_Info >> 0) & 0x3f; + + u1DBG_Dqs1_DFS = (u4DBG_Dqs1_Info >> 14) & 0x03; + u1DBG_Dqs1_Lead = (u4DBG_Dqs1_Info >> 13) & 0x01; + u1DBG_Dqs1_Lag = (u4DBG_Dqs1_Info >> 12) & 0x01; + u1DBG_Dqs1_UI = (u4DBG_Dqs1_Info >> 6) & 0x3f; + u1DBG_Dqs1_PI = (u4DBG_Dqs1_Info >> 0) & 0x3f; + + if (u1Info_NUM < 10) + { + mcSHOW_DBG_MSG3(("Info= %d ", u1Info_NUM)); + } + else + { + mcSHOW_DBG_MSG3(("Info=%d ", u1Info_NUM)); + } + + mcSHOW_DBG_MSG3(("B0=( %d, %d, %d, %d, %d, %d), B1=( %d, %d, %d, %d, %d, %d)\n", + u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI / 8, u1DBG_Dqs0_UI % 8, u1DBG_Dqs0_PI, + u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI / 8, u1DBG_Dqs1_UI % 8, u1DBG_Dqs1_PI)); + } + + //Run Time HW Gating Max and Min Value Record + //Run Time HW Gating MAX_DLY UI : bit[27:22] + //Run Time HW Gating MAX_DLY PI : bit[21:16] + //Run Time HW Gating MIN_DLY UI : bit[11:06] + //Run Time HW Gating MIN_DLY PI : bit[05:00] + u4Dqs0_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B0_STB_MAX_MIN_DLY)); + u2Dqs0_UI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 22) & 0x3f; + u2Dqs0_PI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 16) & 0x3f; + u2Dqs0_UI_MIN_DLY = (u4Dqs0_MAX_MIN_DLY >> 6) & 0x3f; + u2Dqs0_PI_MIN_DLY = (u4Dqs0_MAX_MIN_DLY >> 0) & 0x3f; + + u4Dqs1_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B1_STB_MAX_MIN_DLY)); + u2Dqs1_UI_MAX_DLY = (u4Dqs1_MAX_MIN_DLY >> 22) & 0x3f; + u2Dqs1_PI_MAX_DLY = (u4Dqs1_MAX_MIN_DLY >> 16) & 0x3f; + u2Dqs1_UI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 6) & 0x3f; + u2Dqs1_PI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 0) & 0x3f; + + mcSHOW_DBG_MSG3(("B0 = MAX(4T, UI, PI) MIN(4T, UI, PI), B1 = MAX(4T, UI, PI) MIN(4T, UI, PI)\n")); + mcSHOW_DBG_MSG3(("B0 = MAX( %d, %d, %d) MIN( %d, %d, %d), B1 = MAX( %d, %d, %d) MIN( %d, %d, %d)\n", + u2Dqs0_UI_MAX_DLY / 8, u2Dqs0_UI_MAX_DLY % 8, u2Dqs0_PI_MAX_DLY, + u2Dqs0_UI_MIN_DLY / 8, u2Dqs0_UI_MIN_DLY % 8, u2Dqs0_PI_MIN_DLY, + u2Dqs1_UI_MAX_DLY / 8, u2Dqs1_UI_MAX_DLY % 8, u2Dqs1_PI_MAX_DLY, + u2Dqs1_UI_MIN_DLY / 8, u2Dqs1_UI_MIN_DLY % 8, u2Dqs1_PI_MIN_DLY)); + } + vSetRank(p, u1RankBak); + p->channel = u1ChannelBak; + vSetPHY2ChannelMapping(p, u1ChannelBak); +#endif +#endif +} + +///TODO: wait for porting +++ +#if __A60868_TO_BE_PORTING__ + +void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p) +{ +#if RX_PICG_NEW_MODE + //RX FIFO debug feature, MP setting should enable debug function for Gating error information + //APHY control new mode + U32 u1ChannelBak, u4value; + U8 u1ChannelIdx; + + u1ChannelBak = p->channel; + + for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++) + { + p->channel = u1ChannelIdx; + + u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24); //DDRPHY NAO bit24~27 + if (u4value) + { + mcSHOW_DBG_MSG(("\n[RXFIFODebugStatus] CH_%d MISC_STBERR_RK0_R_RX_ARDQ = 0x\033[1;36m%x\033[m for Gating error information\n", u1ChannelIdx, u4value)); + } + } + p->channel = u1ChannelBak; + vSetPHY2ChannelMapping(p, u1ChannelBak); +#endif +} +#endif //#if __ETT__ +#endif + +#endif /// __A60868_TO_BE_PORTING__ +///TODO: wait for porting +++ diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c new file mode 100644 index 0000000000..e10f729637 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c @@ -0,0 +1,2524 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +//----------------------------------------------------------------------------- +// Include files +//----------------------------------------------------------------------------- +#include "dramc_top.h" +#include "dramc_common.h" +#include "dramc_int_global.h" //for gu1BroadcastIsLP4 +#include "dramc_dv_init.h" +#include "dramc_actiming.h" +#include "x_hal_io.h" +#if __ETT__ +#include <barriers.h> +#endif +#include "emi.h" + +//----------------------------------------------------------------------------- +// Global variables +//----------------------------------------------------------------------------- + +#if (fcFOR_CHIP_ID == fcA60868) +U8 u1EnterRuntime; +#endif + +U8 u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type) +{ + if (dram_type == TYPE_LPDDR5) + return FALSE; + else + return TRUE; +} + +u8 is_lp5_family(DRAMC_CTX_T *p) +{ + return p->dram_type == TYPE_LPDDR5? TRUE: FALSE; +} + +u8 is_heff_mode(DRAMC_CTX_T *p) +{ + u8 res = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), + SHU_COMMON0_LP5HEFF_MODE); + mcSHOW_DBG_MSG5(("HEFF Mode: %d\n", res)); + return res? TRUE: FALSE; +} + +static u8 lp5heff; + +u8 lp5heff_save_disable(DRAMC_CTX_T *p) +{ + /* save it */ + lp5heff = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), + SHU_COMMON0_LP5HEFF_MODE); + + /* disable it */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), + P_Fld(0, SHU_COMMON0_LP5HEFF_MODE)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RKCFG), + 0, RKCFG_CKE2RANK); + + + return lp5heff; +} + +void lp5heff_restore(DRAMC_CTX_T *p) +{ + /* restore it */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), + P_Fld(lp5heff, SHU_COMMON0_LP5HEFF_MODE)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RKCFG), + lp5heff, RKCFG_CKE2RANK); +} + +#if FOR_DV_SIMULATION_USED +U8 u1BroadcastOnOff = 0; +#endif +U32 GetDramcBroadcast(void) +{ +#if (fcFOR_CHIP_ID == fcA60868) + return 0; +#endif + +#if (FOR_DV_SIMULATION_USED == 0) + return *((volatile unsigned int *)(DRAMC_WBR)); +#else + return u1BroadcastOnOff; +#endif +} + +void DramcBroadcastOnOff(U32 bOnOff) +{ +#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) + + #if (fcFOR_CHIP_ID == fcA60868) + return; //disable broadcast in A60868 + #endif + + #if __Petrus_TO_BE_PORTING__ + U8 u1BroadcastStatus = 0; + // INFRA_RSVD3[9:8] = protect_set_clr_mask + u1BroadcastStatus = (*((volatile unsigned int *)(INFRA_RSVD3)) >> 8) & 0x3; + if (u1BroadcastStatus & 0x1) // Enable new infra access by Preloader + { + if (bOnOff == DRAMC_BROADCAST_ON) + *((volatile unsigned int *)(DRAMC_WBR_SET)) = DRAMC_BROADCAST_SET; + else + *((volatile unsigned int *)(DRAMC_WBR_CLR)) = DRAMC_BROADCAST_CLR; + } + else + #endif + *((volatile unsigned int *)(DRAMC_WBR)) = bOnOff; + dsb(); +#endif + +#if (FOR_DV_SIMULATION_USED == 1) + if (gu1BroadcastIsLP4 == TRUE) + { + #if (fcFOR_CHIP_ID == fcA60868) + bOnOff = 0; + #endif + if (bOnOff) + { + broadcast_on(); + mcSHOW_DBG_MSG(("Broadcast ON\n")); + u1BroadcastOnOff = bOnOff; + } + else + { + broadcast_off(); + mcSHOW_DBG_MSG(("Broadcast OFF\n")); + u1BroadcastOnOff = bOnOff; + } + } +#endif + +#ifdef DUMP_INIT_RG_LOG_TO_DE + if(gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag) + { + U8 u1BroadcastStatus = 0; + U32 addr, val; + + addr = DRAMC_WBR; + val = bOnOff; + // *((volatile unsigned int *)(DRAMC_WBR)) = bOnOff; + + mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",addr, val)); + // mcDELAY_MS(1); +#if (FOR_DV_SIMULATION_USED==0) + GPT_Delay_ms(1); +#endif + } +#endif + } + + + +#if __ETT__ +const U32 u4Cannot_Use_Dramc_WBR_Reg[]= +{ + DDRPHY_REG_CA_DLL_ARPI5, + DDRPHY_REG_B0_DLL_ARPI5, + DDRPHY_REG_B1_DLL_ARPI5, + + DDRPHY_REG_SHU_CA_DLL0, + DDRPHY_REG_SHU_CA_DLL1, + + DDRPHY_REG_CA_LP_CTRL0, + + DDRPHY_REG_MISC_DVFSCTL2, + DDRPHY_REG_MISC_SHU_OPT, + + DDRPHY_REG_MISC_DVFSCTL, + DDRPHY_REG_MISC_DVFSCTL3, + + DDRPHY_REG_MISC_CKMUX_SEL, + DRAMC_REG_DVFS_CTRL0 +}; +#define CANNOT_USE_WBR_SIZE ((sizeof(u4Cannot_Use_Dramc_WBR_Reg)) / (sizeof(U32))) +void CheckDramcWBR(U32 u4address) +{ + + U32 i, channel_and_value; + if (GetDramcBroadcast()==DRAMC_BROADCAST_ON) + { + #if ((CHANNEL_NUM == 1) || (CHANNEL_NUM == 2)) + channel_and_value = 0x1; + #else //for channel number = 3 or 4 + channel_and_value = 0x3; + #endif + if ((((u4address - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & channel_and_value) != CHANNEL_A) + { + mcSHOW_ERR_MSG(("Error! virtual address 0x%x is not CHA and cannot use Dramc WBR\n", u4address)); + while (1); + } + for (i = 0; i < CANNOT_USE_WBR_SIZE; i++) + { + if (u4Cannot_Use_Dramc_WBR_Reg[i] == u4address) + { + mcSHOW_ERR_MSG(("Error! virtual address 0x%x cannot use Dramc WBR\n", u4address)); + while (1); + } + } + } +} +#endif + +void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel) +{ + p->channel = (DRAM_CHANNEL_T)u1Channel; +} + +U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p) +{ + return p->channel; +} + +void vSetChannelNumber(DRAMC_CTX_T *p) +{ + #if 1//(!FOR_DV_SIMULATION_USED) + p->support_channel_num = CHANNEL_NUM; + #else + p->support_channel_num = CHANNEL_SINGLE; + #endif +} + +void vSetRank(DRAMC_CTX_T *p, U8 ucRank) +{ + p->rank = (DRAM_RANK_T)ucRank; +} + +U8 u1GetRank(DRAMC_CTX_T *p) +{ + return p->rank; +} + +void vSetRankNumber(DRAMC_CTX_T *p) +{ +#if(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) + if (u4IO32ReadFldAlign(DRAMC_REG_SA_RESERVE, SA_RESERVE_SINGLE_RANK) == 1) + { + p->support_rank_num =RANK_SINGLE; + } + else +#endif + { + p->support_rank_num = RANK_DUAL; + } +} + +void vSetFSPNumber(DRAMC_CTX_T *p) +{ +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + p->support_fsp_num = 3; + else +#endif + p->support_fsp_num = 2; +} + +static void setFreqGroup(DRAMC_CTX_T *p) +{ + + /* Below listed conditions represent freqs that exist in ACTimingTable + * -> Should cover freqGroup settings for all real freq values + */ +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + if (p->frequency <= 400) // DDR800 + { + p->freqGroup = 400; + } + else if (p->frequency <= 600) // DDR1200 + { + p->freqGroup = 600; + } + else if (p->frequency <= 800) // DDR1600 + { + p->freqGroup = 800; + } + else if (p->frequency <= 933) //DDR1866 + { + p->freqGroup = 933; + } + else if (p->frequency <= 1200) //DDR2400, DDR2280 + { + p->freqGroup = 1200; + } + else if (p->frequency <= 1600) // DDR3200 + { + p->freqGroup = 1600; + } + else if (p->frequency <= 1866) // DDR3733 + { + p->freqGroup = 1866; + } + else if (p->frequency <= 2133) // DDR4266 + { + p->freqGroup = 2133; + } + else if (p->frequency <= 2400) // DDR4800 + { + p->freqGroup = 2400; + } + else if (p->frequency <= 2750) // DDR5500 + { + p->freqGroup = 2750; + } + else if (p->frequency <= 3000) // DDR6000 + { + p->freqGroup = 3000; + } + else // DDR6600 + { + p->freqGroup = 3300; + } + } + else +#endif + { + if (p->frequency <= 200) // DDR400 + { + p->freqGroup = 200; + } + else if (p->frequency <= 400) // DDR800 + { + p->freqGroup = 400; + } + else if (p->frequency <= 600) // DDR1200 + { + p->freqGroup = 600; + } + else if (p->frequency <= 800) // DDR1600 + { + p->freqGroup = 800; + } + else if (p->frequency <= 933) //DDR1866 + { + p->freqGroup = 933; + } + else if (p->frequency <= 1200) //DDR2400, DDR2280 + { + p->freqGroup = 1200; + } + else if (p->frequency <= 1333) // DDR2667 + { + p->freqGroup = 1333; + } + else if (p->frequency <= 1600) // DDR3200 + { + p->freqGroup = 1600; + } + else if (p->frequency <= 1866) // DDR3733 + { + p->freqGroup = 1866; + } + else // DDR4266 + { + p->freqGroup = 2133; + } + } + + mcSHOW_DBG_MSG3(("[setFreqGroup] p-> frequency %u, freqGroup: %u\n", p->frequency, p->freqGroup)); + return; +} + + +#define CKGEN_FMETER 0x0 +#define ABIST_FMETER 0x1 + +U16 gddrphyfmeter_value = 0; +U16 DDRPhyFMeter(void) +{ + return gddrphyfmeter_value; +} + +#if __ETT__ || defined(SLT) +void GetPhyPllFrequency(DRAMC_CTX_T *p) +{ + //U8 u1ShuLevel = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL); + U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP); + U32 u4PLL5_ADDR = DDRPHY_REG_SHU_PHYPLL1 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; + U32 u4PLL8_ADDR = DDRPHY_REG_SHU_PHYPLL2 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; + U32 u4B0_DQ = DDRPHY_REG_SHU_B0_DQ1 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; + U32 u4PLL3_ADDR = DDRPHY_REG_SHU_PHYPLL3 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; + //Darren-U32 u4PLL4 = DDRPHY_SHU_PLL4 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; // for DDR4266 + U32 u4B0_DQ6 = DDRPHY_REG_SHU_B0_DQ6 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; + + /* VCOFreq = FREQ_XTAL x ((RG_RCLRPLL_SDM_PCW) / 2^(RG_*_RCLRPLL_PREDIV)) / 2^(RG_*_RCLRPLL_POSDIV) */ + U32 u4SDM_PCW = u4IO32ReadFldAlign(u4PLL5_ADDR, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW); + U32 u4PREDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_PREDIV); + U32 u4POSDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_POSDIV); + U32 u4CKDIV4 = u4IO32ReadFldAlign(u4B0_DQ, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0); + U8 u1FBKSEL = u4IO32ReadFldAlign(u4PLL3_ADDR, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL); + //Darren-U16 u2CKMUL2 = u4IO32ReadFldAlign(u4PLL4, SHU_PLL4_RG_RPHYPLL_RESERVED); + U8 u1SopenDQ = u4IO32ReadFldAlign(u4B0_DQ6, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0); + + U32 u4VCOFreq = (((52>>u4PREDIV)*(u4SDM_PCW>>8))>>u4POSDIV) << u1FBKSEL; + U32 u4DataRate = u4VCOFreq>>u4CKDIV4; + if (u1SopenDQ == ENABLE) // for 1:4 mode DDR800 (3.2G/DIV4) + u4DataRate >>= 2; + + //mcSHOW_DBG_MSG(("PCW=0x%X, u4PREDIV=%d, u4POSDIV=%d, CKDIV4=%d, DataRate=%d\n", u4SDM_PCW, u4PREDIV, u4POSDIV, u4CKDIV4, u4DataRate)); + mcSHOW_DBG_MSG(("[F] DataRate=%d at SHU%d\n", u4DataRate, u1ShuLevel)); +} +#endif + +DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p) +{ + return p->pDFSTable->freq_sel; +} + +void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel) +{ + p->pDFSTable->freq_sel = sel; +} + +DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p) +{ + return p->pDFSTable->ddr_loop_mode; +} + + +void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode) +{ + p->pDFSTable->divmode = eMode; +} + +DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p) +{ + return p->pDFSTable->divmode; +} + +void vSet_Current_ShuLevel(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1ShuIndex) +{ + p->pDFSTable->shuffleIdx = u1ShuIndex; +} + +DRAM_DFS_SRAM_SHU_T vGet_Current_ShuLevel(DRAMC_CTX_T *p) +{ + return p->pDFSTable->shuffleIdx; +} + + +#if 0 +void vSet_Duty_Calibration_Mode(DRAMC_CTX_T *p, U8 kMode) +{ + p->pDFSTable->duty_calibration_mode = kMode; +} +#endif + +DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p) +{ + return p->pDFSTable->duty_calibration_mode; +} + +VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p) +{ + return p->pDFSTable->vref_calibartion_enable; +} + +/* vGet_Dram_CBT_Mode + * Due to current HW design (both ranks share the same set of ACTiming regs), mixed + * mode LP4 now uses byte mode ACTiming settings. This means most calibration steps + * should use byte mode code flow. + * Note: The below items must have per-rank settings (Don't use this function) + * 1. CBT training 2. TX tracking + */ +DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p) +{ + if (p->support_rank_num == RANK_DUAL) + { + if(p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE && p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE) + return CBT_NORMAL_MODE; + } + else // Single rank + { + if(p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) + return CBT_NORMAL_MODE; + } + + return CBT_BYTE_MODE1; +} + +void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p) +{ +#if __ETT__ + mcSHOW_DBG_MSG(("===============================================================================\n" + "Dram Type= %d, Freq= %u, FreqGroup= %u, CH_%d, rank %d\n" + "fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n" + "===============================================================================\n", + p->dram_type, DDRPhyFMeter()?DDRPhyFMeter():p->frequency, p->freqGroup, p->channel, p->rank, + p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p))); +#else + mcSHOW_DBG_MSG(("==\n" + "Dram Type= %d, Freq= %u, CH_%d, rank %d\n" + "fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n" + "==\n", + p->dram_type, + DDRPhyFMeter(), + p->channel, + p->rank, + p->dram_fsp, + p->odt_onoff, + p->dram_cbt_mode[p->rank], + vGet_Div_Mode(p))); +#endif +} + +#if VENDER_JV_LOG +void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p) +{ + mcSHOW_DBG_MSG5(("\n\nDram type:")); + + switch (p->dram_type) + { + case TYPE_LPDDR4: + mcSHOW_DBG_MSG5(("LPDDR4\t")); + break; + + case TYPE_LPDDR4X: + mcSHOW_DBG_MSG5(("LPDDR4X\t")); + break; + + case TYPE_LPDDR4P: + mcSHOW_DBG_MSG5(("LPDDR4P\t")); + break; + } + + mcSHOW_DBG_MSG5(("Freq: %d, FreqGroup %u, channel %d, rank %d\n" + "dram_fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n\n", + p->frequency, p->freqGroup, p->channel, p->rank, + p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p))); + + return; +} +#endif + +U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel) +{ + U16 u2freq=0; + + switch(sel) + { + case LP4_DDR4266: + u2freq=2133; + break; + case LP4_DDR3733: + u2freq=1866; + break; + case LP4_DDR3200: + u2freq=1600; + break; + case LP4_DDR2667: + u2freq=1333; + break; + case LP4_DDR2400: + u2freq=1200; + break; + case LP4_DDR1866: + u2freq=933; + break; + case LP4_DDR1600: + u2freq=800; + break; + case LP4_DDR1200: + u2freq=600; + break; + case LP4_DDR800: + u2freq=400; + break; + case LP4_DDR400: + u2freq=200; + break; + + case LP5_DDR6400: + u2freq=3200; + break; + case LP5_DDR6000: + u2freq=3000; + break; + case LP5_DDR5500: + u2freq=2750; + break; + case LP5_DDR4800: + u2freq=2400; + break; + case LP5_DDR4266: + u2freq=2133; + break; + case LP5_DDR3733: + u2freq=1866; + break; + case LP5_DDR3200: + u2freq=1600; + break; + case LP5_DDR2400: + u2freq=1200; + break; + case LP5_DDR1600: + u2freq=800; + break; + case LP5_DDR1200: + u2freq=600; + break; + case LP5_DDR800: + u2freq=400; + break; + + default: + mcSHOW_ERR_MSG(("[GetFreqBySel] freq sel is incorrect !!!\n")); + break; + } + + return u2freq; +} + +DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq) +{ + DRAM_PLL_FREQ_SEL_T sel=0; + + switch(u2freq) + { + case 2133: + sel=LP4_DDR4266; + break; + case 1866: + sel=LP4_DDR3733; + break; + case 1600: + sel=LP4_DDR3200; + break; + case 1333: + sel=LP4_DDR2667; + break; + case 1200: + sel=LP4_DDR2400; + break; + case 933: + sel=LP4_DDR1866; + break; + case 800: + sel=LP4_DDR1600; + break; + case 600: + sel=LP4_DDR1200; + break; + case 400: + sel=LP4_DDR800; + break; + case 200: + sel=LP4_DDR400; + break; + default: + mcSHOW_ERR_MSG(("[GetSelByFreq] sel is incorrect !!!\n")); + break; + } + + return sel; +} + +void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel) +{ + p->freq_sel = sel; + p->frequency = GetFreqBySel(p, sel); + + if(is_lp5_family(p)) + { + ///TODO: Dennis + //p->dram_fsp = (p->frequency < LP5_MRFSP_TERM_FREQ)? FSP_0: FSP_1; + p->dram_fsp = FSP_0; + #if LP5_DDR4266_RDBI_WORKAROUND + if(p->frequency >= 2133) + p->DBI_R_onoff[FSP_0] = DBI_ON; + #endif + p->odt_onoff = (p->frequency < LP5_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON; + + if(p->frequency >= 2750) + vSet_Div_Mode(p, DIV16_MODE); + } + else + { + p->dram_fsp = (p->frequency < LP4_MRFSP_TERM_FREQ)? FSP_0: FSP_1; + p->odt_onoff = (p->frequency < LP4_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON; + } + + if (p->dram_type == TYPE_LPDDR4P) + p->odt_onoff = ODT_OFF; + + p->shu_type = get_shuffleIndex_by_Freq(p); + setFreqGroup(p); /* Set p->freqGroup to support freqs not in ACTimingTable */ + + ///TODO: add DBI_onoff by condition + //p->DBI_onoff = p->odt_onoff; +} + + +U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p) +{ + U8 u1ShuffleIdx = 0; + U16 u2Freq=0; + static U16 u2FreqMax=0; + + if ((u2FreqMax == 0) || (gUpdateHighestFreq == TRUE)) + { + gUpdateHighestFreq = FALSE; + u2FreqMax = 0; + for (u1ShuffleIdx = DRAM_DFS_SHUFFLE_1; u1ShuffleIdx < DRAM_DFS_SHUFFLE_MAX; u1ShuffleIdx++) + { + u2Freq = GetFreqBySel(p, gFreqTbl[u1ShuffleIdx].freq_sel); + if(u2FreqMax < u2Freq) + u2FreqMax = u2Freq; + } + } + + return u2FreqMax; +} + +U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type) +{ +#if ENABLE_EYESCAN_GRAPH +#if (fcFOR_CHIP_ID == fcA60868) //need check unterm highest freq is saved at SRAM_SHU4?? + //CBT + if (get_type == 0) + if (ENABLE_EYESCAN_CBT==1) return ENABLE; //TO DO :Temp Force open EYESCAN + + //RX + if (get_type == 1) + if (ENABLE_EYESCAN_RX==1) return ENABLE; //TO DO :Temp Force open EYESCAN + + //TX + if (get_type == 2) + if (ENABLE_EYESCAN_TX==1) return ENABLE; //TO DO :Temp Force open EYESCAN + +#else + //CBT + if (get_type == 0) + { + if (gCBT_EYE_Scan_flag==0) return DISABLE; + if (gCBT_EYE_Scan_only_higheset_freq_flag == 0) return ENABLE; //K All freq + if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; // K highest freq + if (gEye_Scan_unterm_highest_flag==1 && vGet_Current_ShuLevel(p)==SRAM_SHU2) return ENABLE; // K unterm highest freq + } + + //RX + if (get_type == 1) + { + if (gRX_EYE_Scan_flag==0) return DISABLE; + if (gRX_EYE_Scan_only_higheset_freq_flag == 0) return ENABLE; //K All freq + if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; // K highest freq + if (gEye_Scan_unterm_highest_flag==1 && vGet_Current_ShuLevel(p)==SRAM_SHU2) return ENABLE; // K unterm highest freq + } + + //TX + if (get_type == 2) + { + if (gTX_EYE_Scan_flag==0) return DISABLE; + if (gTX_EYE_Scan_only_higheset_freq_flag == 0) return ENABLE; //K All freq + if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; // K highest freq + if (gEye_Scan_unterm_highest_flag==1 && vGet_Current_ShuLevel(p)==SRAM_SHU2) return ENABLE; // K unterm highest freq + } + +#endif +#endif + + return DISABLE; +} + +void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff) +{ + // DRAMC Write-DBI On/Off + vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, onoff, SHU_TX_SET0_DBIWR); + mcSHOW_DBG_MSG(("DramC Write-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off"))); +} + +void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff) +{ + // DRAMC Read-DBI On/Off + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ7, onoff, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ7, onoff, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1); + mcSHOW_DBG_MSG(("DramC Read-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off"))); +} +#if ENABLE_READ_DBI +void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff) +{ +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + //mcSHOW_DBG_MSG(("--Fsp%d --\n", p->dram_fsp)); + + //DRAM MR3[6] read-DBI On/Off + u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0xbf) | (onoff << 6)); + DramcModeRegWriteByRank(p, p->rank, 3, u1MR03Value[u1fsp]); +} +#endif + +#if ENABLE_WRITE_DBI +void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff) +{ +#if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); +#endif + //DRAM MR3[7] write-DBI On/Off + u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0x7F) | (onoff << 7)); + DramcModeRegWriteByRank(p, p->rank, 3, u1MR03Value[u1fsp]); +} +#endif + +void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, CKE_FIX_CHANNEL WriteChannelNUM) +{ + U8 u1CKEOn, u1CKEOff; + + if (option == CKE_DYNAMIC) //if CKE is dynamic, set both CKE fix On and Off as 0 + { //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) + u1CKEOn = u1CKEOff = 0; + } + else //if CKE fix on is set as 1, CKE fix off should also be set as 0; vice versa + { + u1CKEOn = option; + u1CKEOff = (1 - option); + } + + if (WriteChannelNUM == CKE_WRITE_TO_ALL_CHANNEL) //write register to all channel + { + if((u1RankIdx == RANK_0)||(u1RankIdx == CKE_WRITE_TO_ALL_RANK)) + { + vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(u1CKEOff, CKECTRL_CKEFIXOFF) + | P_Fld(u1CKEOn, CKECTRL_CKEFIXON)); + } + + if(u1RankIdx == RANK_1||((u1RankIdx == CKE_WRITE_TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL))) + { + vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(u1CKEOff, CKECTRL_CKE1FIXOFF) + | P_Fld(u1CKEOn, CKECTRL_CKE1FIXON)); + } + } + else + { + if((u1RankIdx == RANK_0) || (u1RankIdx == CKE_WRITE_TO_ALL_RANK)) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(u1CKEOff, CKECTRL_CKEFIXOFF) + | P_Fld(u1CKEOn, CKECTRL_CKEFIXON)); + } + + if((u1RankIdx == RANK_1) ||((u1RankIdx == CKE_WRITE_TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL))) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(u1CKEOff, CKECTRL_CKE1FIXOFF) + | P_Fld(u1CKEOn, CKECTRL_CKE1FIXON)); + } + } +} + + +void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option) +{ + if (option == ENABLE) + { + //enable autorefresh + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_REFDIS); //REFDIS=0, enable auto refresh + } + else // DISABLE + { + //disable autorefresh + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS); //REFDIS=1, disable auto refresh + + //because HW will actually disable autorefresh after refresh_queue empty, so we need to wait quene empty. + mcDELAY_US(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_QUEUE_CNT) * 4); //wait refresh_queue_cnt * 3.9us + } +} + + +//------------------------------------------------------------------------- +/** vCKERankCtrl + * Control CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT)) + * Note: Sets CKE toggle mode for all channels + * @param p Pointer of context created by DramcCtxCreate. + * @param CKECtrlMode Indicates + */ +//------------------------------------------------------------------------- +void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode) +{ + /* Struct indicating all register fields mentioned in "multi rank CKE control" */ + typedef struct + { + U8 u1CKE2Rank: Fld_wid(RKCFG_CKE2RANK); + U8 u1CKE2Rank_Opt :Fld_wid(CKECTRL_CKE2RANK_OPT); + U8 u1CKE2Rank_Opt2 :Fld_wid(CKECTRL_CKE2RANK_OPT2); + U8 u1CKE2Rank_Opt3: Fld_wid(CKECTRL_CKE2RANK_OPT3); + U8 u1CKE2Rank_Opt5: Fld_wid(CKECTRL_CKE2RANK_OPT5); + U8 u1CKE2Rank_Opt6: Fld_wid(CKECTRL_CKE2RANK_OPT6); + U8 u1CKE2Rank_Opt7: Fld_wid(CKECTRL_CKE2RANK_OPT7); + U8 u1CKE2Rank_Opt8: Fld_wid(CKECTRL_CKE2RANK_OPT8); + U8 u1CKETimer_Sel: Fld_wid(CKECTRL_CKETIMER_SEL); + U8 u1FASTWake: Fld_wid(SHU_DCM_CTRL0_FASTWAKE); + U8 u1FASTWake2: Fld_wid(SHU_DCM_CTRL0_FASTWAKE2); + U8 u1FastWake_Sel: Fld_wid(CKECTRL_FASTWAKE_SEL); + U8 u1CKEWake_Sel: Fld_wid(CKECTRL_CKEWAKE_SEL); + U8 u1ClkWiTrfc: Fld_wid(ACTIMING_CTRL_CLKWITRFC); + } CKE_CTRL_T; + + /* CKE_Rank dependent/independent mode register setting values */ + CKE_CTRL_T CKE_Mode, CKE_Rank_Independent = { .u1CKE2Rank = 0, .u1CKE2Rank_Opt3 = 0, .u1CKE2Rank_Opt2 = 1, + .u1CKE2Rank_Opt5 = 0, .u1CKE2Rank_Opt6 = 0, .u1CKE2Rank_Opt7 = 1, .u1CKE2Rank_Opt8 = 0, + .u1CKETimer_Sel = 0, .u1FASTWake = 1, .u1FASTWake2 = 1, .u1FastWake_Sel = 1, .u1CKEWake_Sel = 0, .u1ClkWiTrfc = 0 + }, + CKE_Rank_Dependent = { .u1CKE2Rank = 1, .u1CKE2Rank_Opt3 = 0, + .u1CKE2Rank_Opt5 = 0, .u1CKE2Rank_Opt6 = 0, .u1CKE2Rank_Opt7 = 0, .u1CKE2Rank_Opt8 = 0, .u1CKETimer_Sel = 1, + .u1FASTWake = 1, .u1FASTWake2 = 0, .u1FastWake_Sel = 0, .u1CKEWake_Sel = 0, .u1ClkWiTrfc = 0 + }; + //Select CKE control mode + CKE_Mode = (CKECtrlMode == CKE_RANK_INDEPENDENT)? CKE_Rank_Independent: CKE_Rank_Dependent; + + //Apply CKE control mode register settings + vIO32WriteFldAlign_All(DRAMC_REG_RKCFG, CKE_Mode.u1CKE2Rank, RKCFG_CKE2RANK); + vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(CKE_Mode.u1CKE2Rank_Opt3, CKECTRL_CKE2RANK_OPT3) + | P_Fld(CKE_Mode.u1CKE2Rank_Opt, CKECTRL_CKE2RANK_OPT) + | P_Fld(CKE_Mode.u1CKE2Rank_Opt2, CKECTRL_CKE2RANK_OPT2) + | P_Fld(CKE_Mode.u1CKE2Rank_Opt5, CKECTRL_CKE2RANK_OPT5) + | P_Fld(CKE_Mode.u1CKE2Rank_Opt6, CKECTRL_CKE2RANK_OPT6) + | P_Fld(CKE_Mode.u1CKE2Rank_Opt7, CKECTRL_CKE2RANK_OPT7) + | P_Fld(CKE_Mode.u1CKE2Rank_Opt8, CKECTRL_CKE2RANK_OPT8) + | P_Fld(CKE_Mode.u1CKETimer_Sel, CKECTRL_CKETIMER_SEL) + | P_Fld(CKE_Mode.u1FastWake_Sel, CKECTRL_FASTWAKE_SEL) + | P_Fld(CKE_Mode.u1CKEWake_Sel, CKECTRL_CKEWAKE_SEL)); + + vIO32WriteFldMulti_All(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(CKE_Mode.u1FASTWake, SHU_DCM_CTRL0_FASTWAKE) | P_Fld(CKE_Mode.u1FASTWake2, SHU_DCM_CTRL0_FASTWAKE2)); + + vIO32WriteFldAlign_All(DRAMC_REG_ACTIMING_CTRL, CKE_Mode.u1ClkWiTrfc, ACTIMING_CTRL_CLKWITRFC); +} + + +#define MAX_CMP_CPT_WAIT_LOOP 100000 // max loop +static void DramcSetRWOFOEN(DRAMC_CTX_T *p, U8 u1onoff) +{ + U32 u4loop_count = 0; + + { + while(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REQQ_EMPTY) != 1) + { + mcDELAY_US(1); + u4loop_count ++; + + if(u4loop_count > MAX_CMP_CPT_WAIT_LOOP) + { + mcSHOW_ERR_MSG(("RWOFOEN timout! queue is not empty\n")); + #if __ETT__ + while(1); + #else + break; + #endif + } + } + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SCHEDULER_COM), u1onoff, SCHEDULER_COM_RWOFOEN); + } +} + + +//static void DramcEngine2CleanWorstSiPattern(DRAMC_CTX_T *p) +//{ +// vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), +// P_Fld(0, TEST2_A3_AUTO_GEN_PAT) | +// P_Fld(0, TEST2_A3_HFIDPAT) | +// P_Fld(0, TEST2_A3_TEST_AID_EN)); +//} + + +static void DramcEngine2SetUiShift(DRAMC_CTX_T *p, U8 option)//UI shift function +{ + if(option == ENABLE) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), + P_Fld(1, TEST2_A0_TA2_LOOP_EN) | + P_Fld(3, TEST2_A0_LOOP_CNT_INDEX)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(1, TEST2_A3_TEST2_PAT_SHIFT) | + P_Fld(0, TEST2_A3_PAT_SHIFT_SW_EN)); + } + else + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), + P_Fld(0, TEST2_A0_TA2_LOOP_EN) | + P_Fld(0, TEST2_A0_LOOP_CNT_INDEX)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_TEST2_PAT_SHIFT)); + } +} + + +void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel) +{ + //LPDDR2_3_ADRDECEN_TARKMODE =0, always rank0 + /* ADRDECEN_TARKMODE: rank input selection + * 1'b1 select CTO_AGENT1_RANK, 1'b0 rank by address decode + */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), 1, TEST2_A3_ADRDECEN_TARKMODE); + + // DUMMY_TESTAGENTRKSEL =0, select rank according to CATRAIN_TESTAGENTRK + /* TESTAGENTRKSEL: Test agent access rank mode selection + * 2'b00: rank selection by TESTAGENTRK, 2'b01: rank selection by CTO_AGENT_1_BK_ADR[0] + * 2'b10: rank selection by CTO_AGENT1_COL_ADR[3], 2'b11: rank selection by CTO_AGENT1_COL_ADR[4] + */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTAGENTRKSEL); + + //CATRAIN_TESTAGENTRK = u1RankSel + /* TESTAGENTRK: Specify test agent rank + * 2'b00 rank 0, 2'b01 rank 1, 2'b10 rank 2 + */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), u1RankSel, TEST2_A4_TESTAGENTRK); +} + + +void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift) //u1LoopCnt is related to rank +{ + + if ((u1TestPat == TEST_XTALK_PATTERN) || (u1TestPat == TEST_SSOXTALK_PATTERN)) //xtalk or SSO+XTALK + { + //TEST_REQ_LEN1=1 is new feature, hope to make dq bus continously. + //but DV simulation will got problem of compare err + //so go back to use old way + //TEST_REQ_LEN1=0, R_DMRWOFOEN=1 + if (u1Len1Flag != 0) + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(1, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0, LEN1 of 256bits data + DramcSetRWOFOEN(p, 0); //@IPM will fix for LEN1=1 issue + + } + else + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0 + DramcSetRWOFOEN(p, 1); + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_AUTO_GEN_PAT) | + P_Fld(0, TEST2_A3_HFIDPAT) | + P_Fld(0, TEST2_A3_TEST_AID_EN) | + P_Fld(0, TEST2_A3_TESTAUDPAT) | + P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)); //dont use audio pattern + + if (u1TestPat == TEST_SSOXTALK_PATTERN) + { + //set addr 0x48[16] to 1, TESTXTALKPAT = 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(1, TEST2_A4_TESTXTALKPAT) | + P_Fld(0, TEST2_A4_TESTAUDMODE) | + P_Fld(0, TEST2_A4_TESTAUDBITINV)); //use XTALK pattern, dont use audio pattern + + //R_DMTESTSSOPAT=0, R_DMTESTSSOXTALKPAT=0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(1, TEST2_A4_TESTSSOPAT) | + P_Fld(0, TEST2_A4_TESTSSOXTALKPAT)); //dont use sso, sso+xtalk pattern + } + else //select XTALK pattern + { + //set addr 0x48[16] to 1, TESTXTALKPAT = 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(1, TEST2_A4_TESTXTALKPAT) | + P_Fld(0, TEST2_A4_TESTAUDMODE) | + P_Fld(0, TEST2_A4_TESTAUDBITINV)); //use XTALK pattern, dont use audio pattern + + //R_DMTESTSSOPAT=0, R_DMTESTSSOXTALKPAT=0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(0, TEST2_A4_TESTSSOPAT) | + P_Fld(0, TEST2_A4_TESTSSOXTALKPAT)); //dont use sso, sso+xtalk pattern + } + } + else if (u1TestPat == TEST_AUDIO_PATTERN) //AUDIO + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0 + // set AUDINIT=0x11 AUDINC=0x0d AUDBITINV=1 AUDMODE=1(1:read only(address fix), 0: write/read address change) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(0x00000011, TEST2_A4_TESTAUDINIT) | + P_Fld(0x0000000d, TEST2_A4_TESTAUDINC) | + P_Fld(0, TEST2_A4_TESTXTALKPAT) | + P_Fld(0, TEST2_A4_TESTAUDMODE) | + P_Fld(1, TEST2_A4_TESTAUDBITINV)); + + // set addr 0x044 [7] to 1 ,select audio pattern + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_AUTO_GEN_PAT) | + P_Fld(0, TEST2_A3_HFIDPAT) | + P_Fld(0, TEST2_A3_TEST_AID_EN) | + P_Fld(1, TEST2_A3_TESTAUDPAT) | + P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)); + } + else if (u1TestPat == TEST_WORST_SI_PATTERN) //TEST2_OFF > 'h56 + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(u1Len1Flag, TEST2_A4_TEST_REQ_LEN1)| + P_Fld(0, TEST2_A4_TESTAUDINIT) | + P_Fld(0, TEST2_A4_TESTAUDINC) | + P_Fld(0, TEST2_A4_TESTXTALKPAT) | + P_Fld(0, TEST2_A4_TESTSSOPAT) + ); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_TESTAUDPAT) | + P_Fld(1, TEST2_A3_AUTO_GEN_PAT) | + P_Fld(1, TEST2_A3_HFIDPAT) | + P_Fld(1, TEST2_A3_TEST_AID_EN) | + P_Fld(u1LoopCnt, TEST2_A3_TESTCNT) + ); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x56, TEST2_A2_TEST2_OFF);//Set to min value to save time; + } + else //ISI + { + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0 + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_AUTO_GEN_PAT) | + P_Fld(0, TEST2_A3_HFIDPAT) | + P_Fld(0, TEST2_A3_TEST_AID_EN) | + P_Fld(0, TEST2_A3_TESTAUDPAT) | + P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTXTALKPAT); + } + + DramcEngine2SetUiShift(p, u1EnableUiShift); //Enalbe/Disable UI shift +} + +#define CMP_CPT_POLLING_PERIOD 1 // timeout for TE2: (CMP_CPT_POLLING_PERIOD X MAX_CMP_CPT_WAIT_LOOP) +#define MAX_CMP_CPT_WAIT_LOOP 100000 // max loop +static void DramcEngine2CheckComplete(DRAMC_CTX_T *p, U8 u1status) +{ + U32 u4loop_count = 0; + U32 u4Ta2_loop_count = 0; + U32 u4ShiftUiFlag = 0;//Use TEST_WORST_SI_PATTERN_UI_SHIFT + + while ((u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) & u1status) != u1status) + { + mcDELAY_US(CMP_CPT_POLLING_PERIOD); + u4loop_count++; + if ((u4loop_count > 3) && (u4loop_count <= MAX_CMP_CPT_WAIT_LOOP)) + { + //mcSHOW_ERR_MSG(("TESTRPT_DM_CMP_CPT: %d\n", u4loop_count)); + } + else if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP) + { + /*TINFO="fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count*/ + mcSHOW_DBG_MSG(("fcWAVEFORM_MEASURE_A %d :time out, [22:20]=0x%x\n", u4loop_count, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT))); + + //mcFPRINTF((fp_A60501, "fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count)); + + break; + } + } + + u4loop_count = 0; + u4ShiftUiFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TEST2_PAT_SHIFT); + if(u4ShiftUiFlag)//Use TEST_WORST_SI_PATTERN_UI_SHIFT + { + while ((u4Ta2_loop_count = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_LOOP_CNT))) != 8) + { + u4loop_count++; + if(u4loop_count > MAX_CMP_CPT_WAIT_LOOP) + { + mcSHOW_DBG_MSG(("over MAX_CMP_CPT_WAIT_LOOP[%d] TEST_LOOP_CNT[%d]\n", u4loop_count, u4Ta2_loop_count)); + break; + } + } + } +} + +static U32 DramcEngine2Compare(DRAMC_CTX_T *p, DRAM_TE_OP_T wr) +{ + U32 u4result = 0xffffffff; + U32 u4loopcount; + U8 u1status = 1; //RK0 + U32 u4ShiftUiFlag = 0; + + u4loopcount = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TESTCNT); + if (u4loopcount == 1) + u1status = 3; //RK0/1 + + u4ShiftUiFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TEST2_PAT_SHIFT); + + if (wr == TE_OP_WRITE_READ_CHECK) + { + if(!u4ShiftUiFlag)//Could not use while UI shift is open + { + // read data compare ready check + DramcEngine2CheckComplete(p, u1status); + + // disable write + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_TEST2W) | + P_Fld(0, TEST2_A3_TEST2R) | + P_Fld(0, TEST2_A3_TEST1)); + + mcDELAY_US(1); + + // enable read + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_TEST2W) | + P_Fld(1, TEST2_A3_TEST2R) | + P_Fld(0, TEST2_A3_TEST1)); + } + } + + // 5 + // read data compare ready check + DramcEngine2CheckComplete(p, u1status); + + // delay 10ns after ready check from DE suggestion (1ms here) + //mcDELAY_US(1); + + u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & u1status; //CMP_ERR_RK0/1 + + return u4result; +} + +//------------------------------------------------------------------------- +/** DramcEngine2 + * start the self test engine 2 inside dramc to test dram w/r. + * @param p Pointer of context created by DramcCtxCreate. + * @param wr (DRAM_TE_OP_T): TE operation + * @param test2_1 (U32): 28bits,base address[27:0]. + * @param test2_2 (U32): 28bits,offset address[27:0]. (unit is 16-byte, i.e: 0x100 is 0x1000). + * @param loopforever (S16): 0 read\write one time ,then exit + * >0 enable eingie2, after "loopforever" second ,write log and exit + * -1 loop forever to read\write, every "period" seconds ,check result ,only when we find error,write log and exit + * -2 loop forever to read\write, every "period" seconds ,write log ,only when we find error,write log and exit + * -3 just enable loop forever ,then exit + * @param period (U8): it is valid only when loopforever <0; period should greater than 0 + * @param u1LoopCnt (U8): test loop number of test agent2 loop number =2^(u1LoopCnt) ,0 one time + * @retval status (U32): return the value of DM_CMP_ERR ,0 is ok ,others mean error + */ +//------------------------------------------------------------------------- +static U32 uiReg0D0h; +DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift) +{ + U8 u1Len1Flag; + + // error handling + if (!p) + { + mcSHOW_ERR_MSG(("context is NULL\n")); + return DRAM_FAIL; + } + + // check loop number validness +// if ((u1LoopCnt > 15) || (u1LoopCnt < 0)) // U8 >=0 always. + if (u1LoopCnt > 15) + { + mcSHOW_ERR_MSG(("wrong param: u1LoopCnt > 15\n")); + return DRAM_FAIL; + } + + u1Len1Flag = (u1TestPat & 0x80) >> 7; + u1TestPat = u1TestPat & 0x7f; + + DramcSetRankEngine2(p, p->rank); + + uiReg0D0h = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), + P_Fld(0, DUMMY_RD_DQSG_DMYRD_EN) | + P_Fld(0, DUMMY_RD_DQSG_DMYWR_EN) | + P_Fld(0, DUMMY_RD_DUMMY_RD_EN) | + P_Fld(0, DUMMY_RD_SREF_DMYRD_EN) | + P_Fld(0, DUMMY_RD_DMY_RD_DBG) | + P_Fld(0, DUMMY_RD_DMY_WR_DBG)); //must close dummy read when do test agent + + //fixme-zj vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTCHIP_DMA1), 0, TESTCHIP_DMA1_DMA_LP4MATAB_OPT); + + // disable self test engine1 and self test engine2 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_TEST2W) | + P_Fld(0, TEST2_A3_TEST2R) | + P_Fld(0, TEST2_A3_TEST1)); + + // 1.set pattern ,base address ,offset address + // 2.select ISI pattern or audio pattern or xtalk pattern + // 3.set loop number + // 4.enable read or write + // 5.loop to check DM_CMP_CPT + // 6.return CMP_ERR + // currently only implement ucengine_status = 1, others are left for future extension + + // 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), + P_Fld(test2_1 >> 24, TEST2_A0_TEST2_PAT0) | + P_Fld(test2_2 >> 24, TEST2_A0_TEST2_PAT1)); + +#if (__LP5_COMBO__ == TRUE) + if (TRUE == is_lp5_family(p)) + { + // LP5 TA2 base: 0x0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), + test2_1 & 0x00ffffff, RK_TEST2_A1_TEST2_BASE); + } + else +#endif + { + // LP4 TA2 base: 0x10000. It's only TBA constrain, but not HW. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), + (test2_1 + 0x10000) & 0x00ffffff, RK_TEST2_A1_TEST2_BASE); + } + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), + test2_2 & 0x00ffffff, TEST2_A2_TEST2_OFF); + + // 2 & 3 + // (TESTXTALKPAT, TESTAUDPAT) = 00 (ISI), 01 (AUD), 10 (XTALK), 11 (UNKNOWN) + DramcEngine2SetPat(p, u1TestPat, u1LoopCnt, u1Len1Flag, u1EnableUiShift); + + return DRAM_OK; +} + + +U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 u1TestPat) +{ + U32 u4result = 0xffffffff; + + // 4 + if (wr == TE_OP_READ_CHECK) + { + if ((u1TestPat == 1) || (u1TestPat == 2)) + { + //if audio pattern, enable read only (disable write after read), AUDMODE=0x48[15]=0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTAUDMODE); + } + + // enable read, 0x008[31:29] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_TEST2W) | + P_Fld(1, TEST2_A3_TEST2R) | + P_Fld(0, TEST2_A3_TEST1)); + } + else if (wr == TE_OP_WRITE_READ_CHECK) + { + // enable write + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(1, TEST2_A3_TEST2W) | + P_Fld(0, TEST2_A3_TEST2R) | + P_Fld(0, TEST2_A3_TEST1)); + } + DramcEngine2Compare(p, wr); + + // delay 10ns after ready check from DE suggestion (1ms here) + mcDELAY_US(1); + + // 6 + // return CMP_ERR, 0 is ok ,others are fail,diable test2w or test2r + // get result + // or all result + u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))); + + // disable read + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), + P_Fld(0, TEST2_A3_TEST2W) | + P_Fld(0, TEST2_A3_TEST2R) | + P_Fld(0, TEST2_A3_TEST1)); + + return u4result; +} + +void DramcEngine2End(DRAMC_CTX_T *p) +{ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), + P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0 + DramcSetRWOFOEN(p, 1); + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), uiReg0D0h); +} + +U8 u1MaType = 0x2; // for DV sim +void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p) +{ + U8 u1ChannelIdx = 0; + U8 u1EmiChIdx = 0; + U32 u4matypeR0 = 0, u4matypeR1 = 0; + U32 u4matype = 0; + U32 u4EmiOffset = 0; + DRAM_CHANNEL_T eOriChannel = p->channel; + + for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + + u4EmiOffset = 0; + u1EmiChIdx = u1ChannelIdx; +#if (CHANNEL_NUM > 2) + if (u1ChannelIdx >= CHANNEL_C) + { + u4EmiOffset = 0x4000; // 0x1021D000 for CH2/3 + u1EmiChIdx = u1ChannelIdx-2; + } +#endif + + u4matype = u4IO32Read4B(EMI_APB_BASE + u4EmiOffset); + u4matypeR0 = ((u4matype >> (4 + u1EmiChIdx * 16)) & 0x3) + 1; //refer to init_ta2_single_channel() + u4matypeR1 = ((u4matype >> (6 + u1EmiChIdx * 16)) & 0x3) + 1; //refer to init_ta2_single_channel() + + if(p->support_rank_num==RANK_SINGLE) + { + u4matype = u4matypeR0; + } + else + { + u4matype = (u4matypeR0 > u4matypeR1) ? u4matypeR1 : u4matypeR0; //get min value + } + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MATYPE), u4matype, MATYPE_MATYPE); + } + vSetPHY2ChannelMapping(p, eOriChannel); + u1MaType = u4matype; + + return; +} + +/* ---------------------------------------------------------------------- + * LP4 RG Address + * bit: 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * --------------------------------------------------------------- + * RG: - - R R R R R R R R R R R R R R R R R R|B B B|C C C C C C - - - + * 2_BASE 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0|A A A|9 8 7 6 5 4 + * 7 6 5 4 3 2 1 0 |2 1 0| + * AXI --------------------------------------------------------------- + * Addr: R R R R R R R R R R R R R R R R|B B B|C C C|C|C C C C C C C - + * 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0|A A A|9 8 7|H|6 5 4 3 2 1 0 + * 5 4 3 2 1 0 |2 1 0| | | + * ---------------------------------------------------------------------- + */ +#define TA2_RANK0_ADDRESS (0x40200000) +#define AXI_CHAN_BIT_WIDTH 1//2: 4_channel 1: 2_channel +#define OFFSET_OF_RG_BASE_AND_AXI 2 +#define LEN1_INTRINSIC_OFFSET 2 +#define TRANSFER_DRAM_ADDR_BY_EMI_API 1 //1: by emi API 0: by above table +void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode)/* Should call after TA2_Test_Run_Time_Pat_Setting() */ +{ + DRAM_CHANNEL_T eOriChannel = p->channel; + DRAM_RANK_T eOriRank = p->rank; + U32 u4BaseR0, u4BaseR1, u4Offset, u4Addr; + U32 u4matypeR0, u4matypeR1, u4LEN1; + U8 u1ChannelIdx, uiRWOFOEN, u1RkIdx; + + u4Addr = TA2_RANK0_ADDRESS & 0x1fffffff; + if (u1IsLP4Family(p->dram_type)) + { +#if TRANSFER_DRAM_ADDR_BY_EMI_API + { + dram_addr_t dram_addr = {0}; + unsigned long long ull_axi_addr = TA2_RANK0_ADDRESS; + phy_addr_to_dram_addr(&dram_addr, ull_axi_addr); //Make sure row. bank. column are correct + u4BaseR0 = ((dram_addr.row << 12) | (dram_addr.bk << 9) | (dram_addr.col >> 1)) >> 3;// >>1: RG C4 @3th bit >>3: RG start with bit 3 + } +#else + // >>AXI_CHAN_BIT_WIDTH: drop bit8; >>OFFSET_OF_RG_BASE_AND_AXI: align with RG row; >>3: RG start with bit 3 + u4BaseR0 = (((u4Addr & ~0x1ff) >> AXI_CHAN_BIT_WIDTH) | (u4Addr & 0xff)) >> (OFFSET_OF_RG_BASE_AND_AXI + 3); +#endif + u4Offset = len >> (AXI_CHAN_BIT_WIDTH + 5);//5:0x20 bytes(256 bits) address coverage per pattern(128 bits data + 128 bits bubble); offset should bigger than 0xFF + } + else + { + u4BaseR0 = u4Addr >> 4; + if (rksel_mode == TA2_RKSEL_XRT) + { + u4Offset = len >> 4;//16B per pattern + } + else + { + u4Offset = (len >> 4) >> 1;//16B per pattern //len should be >>2 or test engine will time out + } + } + u4BaseR1 = u4BaseR0; + + u4matypeR0 = ((u4IO32Read4B(EMI_APB_BASE) >> 4) & 0x3) + 1; + u4matypeR1 = ((u4IO32Read4B(EMI_APB_BASE) >> 6) & 0x3) + 1; + if (u4matypeR0 != u4matypeR1)//R0 R1 mix mode + { + (u4matypeR0 > u4matypeR1)? (u4BaseR0 >>= 1): (u4BaseR1 >>= 1);//set the correct start address, refer to mapping table + u4Offset >>= 1;//set min value + } + + u4Offset = (u4Offset == 0) ? 1 : u4Offset; //halt if u4Offset = 0 + + u4LEN1 = u4IO32ReadFldAlign(DRAMC_REG_TEST2_A4, TEST2_A4_TEST_REQ_LEN1); + if(u4LEN1) + { + u4Offset = u4Offset - LEN1_INTRINSIC_OFFSET; + } + +#if ENABLE_EMI_LPBK_TEST && EMI_USE_TA2 + if (gEmiLpbkTest) + { + u4matypeR0 = 2; + u4matypeR1 = 2; + u4Offset = 3; + //u4Offset = 6;//3; //6: for emilpbk_dq_dvs_leadlag_toggle_ringcnt + } +#endif + + if (TA2_RKSEL_XRT == rksel_mode) + { + // In order to enhance XRT R2R/W2W probability, use TEST2_4_TESTAGENTRKSEL=3, PERFCTL0_RWOFOEN=0 mode + uiRWOFOEN = 0; + mcSHOW_DBG_MSG(("=== TA2 XRT R2R/W2W\n")); + } + else + { + uiRWOFOEN = 1; +#if !ENABLE_EMI_LPBK_TEST + mcSHOW_DBG_MSG(("=== TA2 HW\n")); +#endif + } +#if !ENABLE_EMI_LPBK_TEST + mcSHOW_DBG_MSG(("=== OFFSET:0x%x\n", u4Offset)); +#endif + for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++) + { + p->channel = (DRAM_CHANNEL_T)u1ChannelIdx; + + for(u1RkIdx = 0; u1RkIdx < p->support_rank_num; u1RkIdx++) + { + p->rank = (DRAM_RANK_T)u1RkIdx; + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), u4BaseR0, RK_TEST2_A1_TEST2_BASE);//fill based on RG table for Rank 0 + } + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), u4Offset, TEST2_A2_TEST2_OFF);//128 bits data length per offest + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), rksel_mode, TEST2_A4_TESTAGENTRKSEL); + DramcSetRWOFOEN(p, uiRWOFOEN); + } + p->channel = eOriChannel; + p->rank = eOriRank; + //TA2_Test_Run_Time_HW_Set_Column_Num(p); + + return; +} +#if ETT_MINI_STRESS_USE_TA2_LOOP_MODE +#define TA2_PAT TEST_WORST_SI_PATTERN +#else +#define TA2_PAT TEST_XTALK_PATTERN +#endif +void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch) +{ + static U8 u1Pat = TA2_PAT, u1loop = 1; + U8 u1ChannelIdx = 0; + DRAM_CHANNEL_T eOriChannel = p->channel; + + if (u1loop || PatSwitch == TA2_PAT_SWITCH_ON) + { +#if !ENABLE_EMI_LPBK_TEST + mcSHOW_DBG_MSG(("TA2 PAT: %d\n", u1Pat)); +#endif + for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++) + { + p->channel = (DRAM_CHANNEL_T)u1ChannelIdx; + DramcEngine2SetPat(p, u1Pat, p->support_rank_num - 1, 0, TE_NO_UI_SHIFT); + } + p->channel = eOriChannel; + + #if !ETT_MINI_STRESS_USE_TA2_LOOP_MODE + { + U32 u4Value = 0; + u4Value = (u1Pat == TEST_WORST_SI_PATTERN) ? 1 : 0; //Worst SI pattern + loop mode + LEN1 + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_TA2_LOOP_EN); + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_LOOP_NV_END); + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_ERR_BREAK_EN); + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, u4Value, TEST2_A4_TEST_REQ_LEN1); + } + #endif + if (PatSwitch) + u1Pat = (u1Pat + 1) % 4; + else + u1loop = 0; + } + return; +} + +void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable) +{ + DRAM_CHANNEL_T eOriChannel = p->channel; + U8 u1ChannelIdx; + +#if !ENABLE_EMI_LPBK_TEST + mcSHOW_DBG_MSG(("\nTA2 Trigger Write\n")); +#endif + for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++) + { + p->channel = (DRAM_CHANNEL_T)u1ChannelIdx; + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u1Enable, TEST2_A3_TEST2W); + } + p->channel = eOriChannel; + return; +} + +static void TA2_Show_Cnt(DRAMC_CTX_T * p, U32 u4ErrorValue) +{ + static U32 err_count = 0; + static U32 pass_count = 0; + U8 u1RankIdx = 0; + for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++) + { + if (u4ErrorValue & (1 << u1RankIdx)) + { + err_count++; + mcSHOW_DBG_MSG(("HW channel(%d) Rank(%d), TA2 failed, pass_cnt:%d, err_cnt:%d\n", p->channel, u1RankIdx, pass_count, err_count)); + } + else + { + pass_count++; + mcSHOW_DBG_MSG(("HW channel(%d) Rank(%d), TA2 pass, pass_cnt:%d, err_cnt:%d\n", p->channel, u1RankIdx, pass_count, err_count)); + } + } +} +#if ETT_MINI_STRESS_USE_TA2_LOOP_MODE +U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p) +{ + U8 u1ChannelIdx = 0; + U32 u4ErrorValue = 0; + U32 bit_error = 0; + DRAM_CHANNEL_T eOriChannel = p->channel; + for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK); + if (u4ErrorValue & 0x3) //RK0 or RK1 test fail + { + mcSHOW_DBG_MSG(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)))); +#if defined(SLT) + mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000, line: %d\n",__LINE__)); + while (1); +#endif + } + TA2_Show_Cnt(p, u4ErrorValue); + bit_error |= u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1)); + } + vSetPHY2ChannelMapping(p, eOriChannel); + return bit_error; +} +#else +U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p) +{ + U8 u1ChannelIdx = 0; + U32 u4ErrorValue = 0; + U32 u4Ta2LoopEn = 0; + U32 u4loopcount = 0; + U8 u1status = 0; + U32 bit_error = 0; + static U32 err_count = 0; + static U32 pass_count = 0; + DRAM_CHANNEL_T eOriChannel = p->channel; + + for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++) + { + vSetPHY2ChannelMapping(p, u1ChannelIdx); + u4Ta2LoopEn = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), TEST2_A0_TA2_LOOP_EN); + //mcSHOW_DBG_MSG(("### u4Ta2LoopEn:%d ### \n", u4Ta2LoopEn)); + + if(u4Ta2LoopEn) + { + u4loopcount = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TESTCNT); + if (u4loopcount == 1) + u1status = 3; //RK0/1 + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END);//cancel NV_END + DramcEngine2CheckComplete(p, u1status);//Wait for complete + //mcSHOW_DBG_MSG(("TESTRPT_TESTSTAT:%x\n", u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));//check TESTRPT_TESTSTAT + u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3; //CMP_ERR_RK0/1 + } + else + u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK); + + if (u4ErrorValue & 0x3) //RK0 or RK1 test fail + { + mcSHOW_DBG_MSG(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)))); +#if defined(SLT) + mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000, line: %d\n",__LINE__)); + while (1); +#endif + } + TA2_Show_Cnt(p, u4ErrorValue); + + bit_error |= u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1)); + } + vSetPHY2ChannelMapping(p, eOriChannel); + + return bit_error; +} +#endif + +void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p) +{ + DRAM_CHANNEL_T channel_bak = p->channel; + DRAM_RANK_T rank_bak = p->rank; + + TA2_Test_Run_Time_HW_Presetting(p, 0x10000, TA2_RKSEL_HW); //TEST2_2_TEST2_OFF = 0x400 + TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF); + TA2_Test_Run_Time_HW_Write(p, ENABLE); + //mcDELAY_MS(1); + TA2_Test_Run_Time_HW_Status(p); + + p->channel = channel_bak; + p->rank = rank_bak; + return; +} + +void Temp_TA2_Test_After_K(DRAMC_CTX_T * p) +{ + DRAM_CHANNEL_T channel_bak = p->channel; + DRAM_RANK_T rank_bak = p->rank; + + do { + TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON); + TA2_Test_Run_Time_HW_Presetting(p, 0x200000, TA2_RKSEL_HW); + TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W + TA2_Test_Run_Time_HW_Status(p); + }while(1); + + p->channel = channel_bak; + p->rank = rank_bak; + return; +} + +static U8 *DramcFetchGlobalMR(DRAMC_CTX_T *p, U8 mr_idx) +{ + U8 *pMRGlobalValue = NULL; + + switch (mr_idx) + { + case 13: pMRGlobalValue = &u1MR13Value[p->rank]; break; + case 26: pMRGlobalValue = &u1MR26Value[p->rank]; break; + case 30: pMRGlobalValue = &u1MR30Value[p->rank]; break; + default: + mcSHOW_ERR_MSG(("%s NULL\n", __func__)); + #if __ETT__ + while(1); + #endif + break; + } + + return pMRGlobalValue; +} + +#if MRW_BACKUP +U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank) +{ + U8 u1Value=0xff; + U8 u1Fsp; + U8 u1MRBackup_ERR_Flag=0, u1backupRK=p->rank; + U16 u2Offset=0x0; + REG_TRANSFER_T TransferReg; + + u1Fsp = FSP_0; + + #if (__LP5_COMBO__ == TRUE) + if (is_lp5_family(p)) + { + switch(u1MRIdx) + { + case 1: + case 2: + case 3: + case 10: + case 11: + case 12: + case 14: + case 15: + case 17: + case 18: + case 19: + case 20: + case 24: + case 30: + case 41: + u1Fsp = gFSPWR_Flag[u1Rank]; + break; + } + } + else + #endif + { + switch(u1MRIdx) + { + case 1: + case 2: + case 3: + case 11: + case 12: + case 14: + case 22: + u1Fsp = gFSPWR_Flag[u1Rank]; + break; + } + } + if (u1Fsp == FSP_0) /* All MR */ + { + switch (u1MRIdx) + { + case 1: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR1; + break; + case 2: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR2; + break; + case 3: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR3; + break; + case 4: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR4; + break; + case 9: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR9; + break; + case 10: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR10; + break; + case 11: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR11; + break; + case 12: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR12; + break; + case 13: + //MR13(LP4) work around, two RG is not synchronized + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR13; + break; + case 14: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR14; + break; + case 15: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR15; + break; + case 16: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR16; + break; + case 17: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR17; + break; + case 18: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR18; + break; + case 19: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR19; + break; + case 20: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR20; + break; + case 21: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR21; + break; + case 22: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR22; + break; + case 23: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR23; + break; + case 24: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR24; + break; + case 25: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR25; + break; + case 26: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR26; + break; + case 27: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR27; + break; + case 28: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR28; + break; + case 30: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR30; + break; + case 31: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR31; + break; + case 32: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR32; + break; + case 33: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR33; + break; + case 34: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR34; + break; + case 37: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR37; + break; + case 39: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR39; + break; + case 40: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR40; + break; + case 41: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR41; + break; + case 42: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR42; + break; + case 46: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR46; + break; + case 48: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR48; + break; + case 51: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_09_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR51; + break; + case 63: + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_09_RK0_FSP0; + TransferReg.u4Fld = MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR63; + break; + } + } + else if (u1MRIdx == 21 || u1MRIdx == 22) /* MR only in FSP0/FSP1 */ + { + if (u1MRIdx == 21) + { + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP1; + TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR21; + } + else + { + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1; + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR22; + } + } + else /* MR in FSP0/FSP1/FSP2 */ + { + if (u1MRIdx <= 20) + { + if (u1MRIdx <= 10) + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP1; + else if (u1MRIdx <= 15) + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP1; + else + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1; + TransferReg.u4Addr += ((u1Fsp - FSP_1) * 0x30); + if (u1MRIdx == 1 || u1MRIdx == 11 || u1MRIdx == 17) + TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR1; + else if (u1MRIdx == 2 || u1MRIdx == 12 || u1MRIdx == 18) + TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR2; + else if (u1MRIdx == 3 || u1MRIdx == 14 || u1MRIdx == 19) + TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR3; + else + TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR10; + } + else if (u1Fsp == FSP_2 && u1MRIdx == 24) + { + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP2; + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR24; + } + else if (u1Fsp == FSP_1 && u1MRIdx == 41) + { + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1; + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR41; + } + else + { + TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1 + ((u1Fsp - FSP_1) * 0x30); + if ((u1Fsp == FSP_1 && u1MRIdx == 24) || (u1Fsp == FSP_2 && u1MRIdx == 30)) + { + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR24; + } + else + { + TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR30; + } + } + } + vSetRank(p, u1Rank); + if (u1MRBackup_ERR_Flag==0) + { + u1Value=u4IO32ReadFldAlign(DRAMC_REG_ADDR(TransferReg.u4Addr), TransferReg.u4Fld); + mcSHOW_MRW_MSG((" [MRW Backup] Rank%d FSP%d MR%d=0x%x\n",u1Rank, gFSPWR_Flag[u1Rank], u1MRIdx, u1Value)); + } + vSetRank(p, u1backupRK); + + return u1Value; + +} +#endif + +void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listVal8, U8 msk8, U8 UpdateMode) +{ + U8 *pMRGlobalValue = DramcFetchGlobalMR(p, mr_idx); + + // ASSERT (pMRGlobalValue != NULL) + + *pMRGlobalValue = ((*pMRGlobalValue & ~msk8) | listVal8); + + if (UpdateMode == TO_MR) + DramcModeRegWriteByRank(p, p->rank, mr_idx, *pMRGlobalValue); +} + +void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode) +{ + U8 *pMRGlobalValue = DramcFetchGlobalMR(p, mr_idx); + + // ASSERT (pMRGlobalValue != NULL) + + *pMRGlobalValue &= ~(Fld2Msk32(mr_fld)); + *pMRGlobalValue |= (value << Fld_shft(mr_fld)); + + if (UpdateMode == TO_MR) + DramcModeRegWriteByRank(p, p->rank, mr_idx, *pMRGlobalValue); +} + +void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u2pValue) +{ + U32 u4MRValue; +#ifdef DUMP_INIT_RG_LOG_TO_DE + gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag=0; +#endif + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), p->rank, SWCMD_CTRL0_MRRRK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1MRIdx, SWCMD_CTRL0_MRSMA); + + // MRR command will be fired when MRREN 0->1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRREN); + + // wait MRR command fired. + while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRR_RESPONSE) == 0) + { + mcDELAY_US(1); + } + + // Since LP3 does not support CG condition, LP3 can not use MRR_STATUS_MRR_SW_REG to do sw mrr. + // After fix HW CG condition, LP3 will use MRR_STATUS_MRR_SW_REG to do sw mrr. + U32 u4MRRReg; + if (u1IsLP4Family(p->dram_type)) + u4MRRReg = MRR_STATUS_MRR_SW_REG; + else + u4MRRReg = MRR_STATUS_MRR_REG; + + // Read out mode register value + u4MRValue = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS), u4MRRReg); + *u2pValue = (U16)u4MRValue; + + // Set MRREN =0 for next time MRR. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRREN); + +#ifdef DUMP_INIT_RG_LOG_TO_DE + gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag=1; +#endif + + mcSHOW_DBG_MSG3(("Read MR%d =0x%x\n", u1MRIdx, u4MRValue)); +} + + +void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue) +{ + U16 u2Value = 0; + U8 u1RankBak; + + /* Since, TMRRI design changed (2 kinds of modes depending on value of R_DMRK_SCINPUT_OPT) + * DE: Jouling, Berson + * To specify SW_MRR rank -> new mode(scinput_opt == 0): MRSRK + * old mode(scinput_opt == 1): MRRRK + * Note: MPCRK is not used by SW to control rank anymore + */ + //Backup & set rank + u1RankBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK); //backup rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK); //set rank + + //Mode reg read + DramcModeRegRead(p, u1MRIdx, &u2Value); + *u2pValue = u2Value; + + //Restore rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1RankBak, SWCMD_CTRL0_MRSRK); + +} + +void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len) +{ + U32 u4Response, u4TimeCnt, ii; + U8 u1MRRK[6] = {0}, u1MRMA[6] = {0}, u1MROP[6] = {0}; + + if (u1Len > 6 || u1Len == 0) + return; + + for (ii = 0;ii < u1Len;ii++) + { + u1MRRK[ii] = u1Rank[ii]; + u1MRMA[ii] = u1MRIdx[ii]; + u1MROP[ii] = u1Value[ii]; + } + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0), + P_Fld(3, RTMRW_CTRL0_RTMRW_LAT) | + P_Fld(0x20, RTMRW_CTRL0_RTMRW_AGE) | + P_Fld(u1Len - 1, RTMRW_CTRL0_RTMRW_LEN) | + P_Fld(u1MRRK[0], RTMRW_CTRL0_RTMRW0_RK) | + P_Fld(u1MRRK[1], RTMRW_CTRL0_RTMRW1_RK) | + P_Fld(u1MRRK[2], RTMRW_CTRL0_RTMRW2_RK) | + P_Fld(u1MRRK[3], RTMRW_CTRL0_RTMRW3_RK) | + P_Fld(u1MRRK[4], RTMRW_CTRL0_RTMRW4_RK) | + P_Fld(u1MRRK[5], RTMRW_CTRL0_RTMRW5_RK)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1), + P_Fld(u1MRMA[0], RTMRW_CTRL1_RTMRW0_MA) | + P_Fld(u1MRMA[1], RTMRW_CTRL1_RTMRW1_MA) | + P_Fld(u1MRMA[2], RTMRW_CTRL1_RTMRW2_MA) | + P_Fld(u1MRMA[3], RTMRW_CTRL1_RTMRW3_MA)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2), + P_Fld(u1MROP[0], RTMRW_CTRL2_RTMRW0_OP) | + P_Fld(u1MROP[1], RTMRW_CTRL2_RTMRW1_OP) | + P_Fld(u1MROP[2], RTMRW_CTRL2_RTMRW2_OP) | + P_Fld(u1MROP[3], RTMRW_CTRL2_RTMRW3_OP)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL3), + P_Fld(u1MRMA[4], RTMRW_CTRL3_RTMRW4_MA) | + P_Fld(u1MRMA[5], RTMRW_CTRL3_RTMRW5_MA) | + P_Fld(u1MROP[4], RTMRW_CTRL3_RTMRW4_OP) | + P_Fld(u1MROP[5], RTMRW_CTRL3_RTMRW5_OP)); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), + 1, MPC_CTRL_RTMRW_HPRI_EN); + mcDELAY_US(5); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), + 1, SWCMD_EN_RTMRWEN); + +#if __LP5_COMBO__ +#if WORKAROUND_LP5_HEFF + if (is_heff_mode(p)) + { + mcDELAY_US(1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), + 1, CKECTRL_CKE2RANK_OPT6); + } +#endif +#endif + + u4TimeCnt = TIME_OUT_CNT; + + do { + u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), + SPCMDRESP_RTMRW_RESPONSE); + u4TimeCnt--; + mcDELAY_US(5); + } while ((u4Response == 0) && (u4TimeCnt > 0)); + + if (u4TimeCnt == 0)//time out + { + mcSHOW_DBG_MSG(("[LP5 RT MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank[0], u1MRIdx[0], u1Value[0])); + } + +#if __LP5_COMBO__ +#if WORKAROUND_LP5_HEFF + if (is_heff_mode(p)) + { + mcDELAY_US(1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), + 0, CKECTRL_CKE2RANK_OPT6); + } +#endif +#endif + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), + 0, SWCMD_EN_RTMRWEN); +} + +static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value) +{ + U32 counter = 0; + U32 u4RabnkBackup; + U32 u4register_024; + + // backup rank + u4RabnkBackup = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK); + + //backup register of CKE fix on/off + u4register_024 = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); + + // set rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK); + + //CKE must be fix on when doing MRW + CKEFixOnOff(p, u1Rank, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1MRIdx, SWCMD_CTRL0_MRSMA); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Value, SWCMD_CTRL0_MRSOP); + + // MRW command will be fired when MRWEN 0->1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRWEN); + + // wait MRW command fired. + while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) == 0) + { + counter++; + mcSHOW_DBG_MSG2(("wait MRW command Rank%d MR%d =0x%x fired (%d)\n", u1Rank, u1MRIdx, u1Value, counter)); + mcDELAY_US(1); + } + + // Set MRWEN =0 for next time MRW. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRWEN); + + // restore CKEFIXON value + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4register_024); + + // restore rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4RabnkBackup, SWCMD_CTRL0_MRSRK); +} + +void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value) +{ + mcSHOW_DBG_MSG2(("MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value)); + +#ifndef ENABLE_POST_PACKAGE_REPAIR + if ((u1MRIdx == 0x04) && (u1Value & 0x10)) + { + mcSHOW_ERR_MSG(("ERROR MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value)); + while(1); + } +#endif + #if (fcFOR_CHIP_ID == fcA60868) + // RTMRW & RTSWCMD-MRW can not be used in runtime + + if (u1EnterRuntime) + { + DramcModeRegWriteByRank_SCSM(p, u1Rank, u1MRIdx, u1Value); + } + else +#endif + { + #if (__LP5_COMBO__ == TRUE) + if (is_lp5_family(p)) + { + #if ENABLE_RUNTIME_MRW_FOR_LP5 + DramcModeRegWriteByRank_RTMRW(p, &u1Rank, &u1MRIdx, &u1Value, 1); + #else + DramcModeRegWriteByRank_RTSWCMD_MRW(p, u1Rank, u1MRIdx, u1Value); + #endif + } + else + #endif + { + DramcModeRegWriteByRank_SCSM(p, u1Rank, u1MRIdx, u1Value); + } + } + + #if MRW_CHECK_ONLY + u1PrintModeRegWrite = 1; + U8 u1Backup_Rank; + U8 u1RankIdx, u1RankNum, u1RankStart; + U8 u1FSPMRIdx; + + u1Backup_Rank=p->rank; + + if (u1Rank==3) + { + u1RankNum = 2; + u1RankStart = 0; + } + else + { + u1RankNum = 1; + u1RankStart = u1Rank; + } + + #if (__LP5_COMBO__ == TRUE) + if (is_lp5_family(p)) + u1FSPMRIdx=16; + else + #endif + u1FSPMRIdx=13; + + for (u1RankIdx=u1RankStart;u1RankIdx<u1RankStart+u1RankNum;u1RankIdx++) + { + vSetRank(p, u1RankIdx); + if (u1MRIdx==u1FSPMRIdx) + { + u2MRRecord[p->channel][u1RankIdx][FSP_0][u1FSPMRIdx] =u1Value; + u2MRRecord[p->channel][u1RankIdx][FSP_1][u1FSPMRIdx] =u1Value; + } + else + u2MRRecord[p->channel][u1RankIdx][gFSPWR_Flag[u1RankIdx]][u1MRIdx] = u1Value; + + if(u1PrintModeRegWrite) + { + #if VENDER_JV_LOG + mcSHOW_JV_LOG_MSG(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value)); + #endif + #if MRW_CHECK_ONLY + mcSHOW_MRW_MSG(("MRW CH%d Rank%d FSP%d MR%d =0x%x\n", p->channel, u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, u1Value)); + #endif + mcSHOW_DBG_MSG2(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value)); + mcDUMP_REG_MSG(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value)); + } + #if MRW_BACKUP + U8 MR_backup; + + MR_backup=DramcMRWriteBackup(p, u1MRIdx, u1RankIdx); + if (MR_backup!=0xff) + mcSHOW_MRW_MSG((" [MRW Check] Rank%d FSP%d Backup_MR%d= 0x%x MR%d= 0x%x ==>%s\n", u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, MR_backup, u1MRIdx, u1Value, (u1Value==MR_backup?"PASS":"FAIL"))); + #endif + + #if (__LP5_COMBO__ == TRUE) + if (is_lp5_family(p)) + { + if (u1MRIdx==u1FSPMRIdx) + gFSPWR_Flag[u1RankIdx] = u1Value & 0x3; + } + else + #endif + { + if (u1MRIdx==u1FSPMRIdx) + gFSPWR_Flag[u1RankIdx] = (u1Value>> 6) & 0x1; + } + } + vSetRank(p, u1Backup_Rank); + #endif +} + +#ifdef __ETT__ +static U8 u1gpRegBackup; +#endif +U32 u4gpRegBackupVlaue[100]; +void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num) +{ + U32 u4RegIdx; + +#ifdef __ETT__ + if (backup_num > 100 || u1gpRegBackup) + { + mcSHOW_ERR_MSG(("[DramcBackupRegisters] backup number over 64!!!\n")); + while (1); + } + + u1gpRegBackup++; +#endif + + for (u4RegIdx = 0; u4RegIdx < backup_num; u4RegIdx++) + { + u4gpRegBackupVlaue[u4RegIdx] = u4IO32Read4B(backup_addr[u4RegIdx]); + //mcSHOW_DBG_MSG(("Backup Reg(0x%X) = 0x%X\n", backup_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx])); + } +} + +void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num) +{ + U32 u4RegIdx; + +#ifdef __ETT__ + if (u1gpRegBackup == 0) + { + mcSHOW_ERR_MSG(("[DramcRestoreRegisters] Need to call backup first\n")); + } + + u1gpRegBackup--; +#endif + + for (u4RegIdx = 0; u4RegIdx < restore_num; u4RegIdx++) + { + vIO32Write4B(restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]); + //mcSHOW_DBG_MSG(("Restore Reg(0x%X) = 0x%X\n", restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx])); + } +} + +#if 0 +//#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION) +void DramcConfInfraReset(DRAMC_CTX_T *p) +{ +#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) + | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN)); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL) + | P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM)); + mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM); + +#if (fcFOR_CHIP_ID == fcLafite) + // 26M + vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX) //move CKMUX_SEL_R_PHYCTRLMUX to here (it was originally between MISC_CG_CTRL0_CLK_MEM_SEL and MISC_CTRL0_R_DMRDSEL_DIV2_OPT) + | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM)); // PHYCTRLDCM 1: follow DDRPHY_conf DCM settings, 0: follow infra DCM settings + vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL0, P_Fld(0, MISC_CG_CTRL0_W_CHG_MEM) + | P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL));//[5:4] mem_ck mux: 2'b00: 26MHz, [0]: change memory clock + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);//change clock freq + mcDELAY_US(1); + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);//disable memory clock change + + // dramc conf reset + //mcSHOW_TIME_MSG(("Before infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148))); + *(volatile unsigned *)(0x10001140) = (0x1 << 15); + //mcSHOW_TIME_MSG(("After infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148))); + __asm__ __volatile__ ("dsb" : : : "memory"); + mcDELAY_US(200); + //mcSHOW_TIME_MSG(("Before infra clear, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148))); + *(volatile unsigned *)(0x10001144) = (0x1 << 15); + //mcSHOW_TIME_MSG(("After infra clear, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148))); + + #if 0 + mcDELAY_US(200); + *(volatile unsigned *)(0x10007018) = 0x88000040; + mcDELAY_US(200); + *(volatile unsigned *)(0x10007018) = 0x88000000; + mcDELAY_US(200); + #endif + + //DDRPHY Reset + vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x0, B0_DQ3_RG_ARDQ_RESETB_B0); + vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); + vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x0, B1_DQ3_RG_ARDQ_RESETB_B1); + vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); + vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x0, CA_CMD3_RG_ARCMD_RESETB); + vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); + vIO32WriteFldAlign(DDRPHY_PLL4, 0x0, PLL4_RG_RPHYPLL_RESETB);//Since there is only 1 PLL, only control CHA + mcDELAY_US(200); + vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x1, B0_DQ3_RG_ARDQ_RESETB_B0); + vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); + vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x1, B1_DQ3_RG_ARDQ_RESETB_B1); + vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); + vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x1, CA_CMD3_RG_ARCMD_RESETB); + vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); + vIO32WriteFldAlign(DDRPHY_PLL4, 0x1, PLL4_RG_RPHYPLL_RESETB);//Since there is only 1 PLL, only control CHA + + //Disable SPM control + vIO32WriteFldMulti(SPM_POWERON_CONFIG_EN, P_Fld(0xB16, POWERON_CONFIG_EN_PROJECT_CODE) | P_Fld(0, POWERON_CONFIG_EN_BCLK_CG_EN)); + + //For FMeter after dcm enable + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL2, 0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN); + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL2, 0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON); +#endif +#endif +} +#endif + +#define PATTERN1 0x5A5A5A5A +#define PATTERN2 0xA5A5A5A5 + +#if defined(DDR_INIT_TIME_PROFILING) || ENABLE_APB_MASK_WRITE +U32 l_low_tick0, l_high_tick0, l_low_tick1, l_high_tick1; +void TimeProfileBegin(void) +{ +#if __ETT__ + l_low_tick0 = GPT_GetTickCount(&l_high_tick0); +#else + l_low_tick0 = get_timer(0); +#endif +} + +U32 TimeProfileEnd(void) +{ +#if __ETT__ + l_low_tick1 = GPT_GetTickCount(&l_high_tick1); + + //mcSHOW_TIME_MSG(("Time0 %u %u\n", l_high_tick0, l_low_tick0)); + //mcSHOW_TIME_MSG(("Time1 %u %u\n", l_high_tick1, l_low_tick1)); + return ((l_low_tick1 - l_low_tick0) * 76) / 1000; +#else + l_low_tick1 = get_timer(l_low_tick0); + return l_low_tick1 * 1000; +#endif +} +#endif + +#if QT_GUI_Tool +void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt) +{ + u1TestPat = u1TestPat & 0x7f; + + DramcSetRankEngine2(p, p->rank); + + uiReg0D0h=u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), P_Fld(0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0, DUMMY_RD_DQSG_DMYWR_EN) | P_Fld(0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0, DUMMY_RD_DMY_RD_DBG) | P_Fld(0, DUMMY_RD_DMY_WR_DBG)); //must close dummy read when do test agent + + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTCHIP_DMA1), 0, TESTCHIP_DMA1_DMA_LP4MATAB_OPT);//Eddie + // disable self test engine1 and self test engine2 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1)); + + // 1.set pattern ,base address ,offset address + // 2.select ISI pattern or audio pattern or xtalk pattern + // 3.set loop number + // 4.enable read or write + // 5.loop to check DM_CMP_CPT + // 6.return CMP_ERR + // currently only implement ucengine_status = 1, others are left for future extension + + // 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), P_Fld(test2_1>>24,TEST2_A0_TEST2_PAT0)|P_Fld(test2_2>>24,TEST2_A0_TEST2_PAT1)); + + #if (FOR_DV_SIMULATION_USED==1 || SW_CHANGE_FOR_SIMULATION==1) + //DV sim memory 0~0x100 has values, can't used + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A1), (test2_1+0x100) & 0x00ffffff, TEST2_A1_TEST2_BASE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0x10000, RK_TEST2_A1_TEST2_BASE); //LPDDR4 Setting + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0x0, RK_TEST2_A1_TEST2_BASE); //Eddie Change to 0 for LP5 + #else + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0, RK_TEST2_A1_TEST2_BASE); + #endif + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x2, TEST2_A2_TEST2_OFF);//Eddie + + return; +} +#endif diff --git a/src/vendorcode/mediatek/mt8192/dramc/emi.c b/src/vendorcode/mediatek/mt8192/dramc/emi.c new file mode 100644 index 0000000000..c440b0091d --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/dramc/emi.c @@ -0,0 +1,817 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include <assert.h> +#include <emi_hw.h> +#include <emi.h> +#include "dramc_reg_base_addr.h" +#include <dramc_top.h> +#include <soc/emi.h> + +#ifdef LAST_EMI +static LAST_EMI_INFO_T* last_emi_info_ptr; +#endif + +static inline unsigned int mt_emi_sync_read(unsigned long long addr) +{ + dsb(); + return *((volatile unsigned int *)addr); +} + +#define mt_emi_sync_write(addr, value) \ + do { \ + *((volatile unsigned int *)(addr)) = value; \ + dsb(); \ + } while (0) + +#define mt_emi_sync_write_or(addr, or_value) \ + do { \ + mt_emi_sync_write(addr, \ + mt_emi_sync_read(addr) | or_value); \ + } while (0) + +static void emi_cen_config(void) +{ +#ifndef ONE_CH + #ifdef RANK_512MB // => 2channel , dual rank , total=2G + mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a154); + #else //RANK_1G => 2channel , dual rank , total=4G + mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f154); + #endif +#else + #ifdef RANK_512MB + mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a054); + #else + mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f054); + #endif +#endif + + // overhead: 20190821 item1 - synced + mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33); //3733 (1:8) r4 - r1 overhead // TBD - change to 4266 + mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025); //3733 (1:8) r8 - r5 overhead // TBD - change to 4266 + mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027); //3733 (1:8) r12 - r9 overhead // TBD - change to 4266 + mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d); //3733 (1:8) r16 - r13 overhead // TBD - change to 4266 + mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33); //3200 (1:8) r4 - r1 overhead + mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025); //3200 (1:8) r8 - r5 overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027); //3200 (1:8) r12 - r9 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d); //3200 (1:8) r16 - r13 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c); //2400 (1:8) r4 - r1 overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21); //2400 (1:8) r8 - r5 overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23); //2400 (1:8) r12 - r9 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228); //2400 (1:8) r16 - r13 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1866 (1:8) r4 - r1 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1866 (1:8) r8 - r5 overhead + mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1866 (1:8) r12 - r9 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1866 (1:8) r16 - r13 overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28); //1600 (1:8) r4 - r1 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20); //1600 (1:8) r8 - r5 overhead + mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24); //1600 (1:8) r12 - r9 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229); //1600 (1:8) r16 - r13 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28); //1200 (1:8) r4 - r1 overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20); //1200 (1:8) r8 - r5 overhead + mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24); //1200 (1:8) r12 - r9 overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229); //1200 (1:8) r16 - r13 overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28); //800 (1:4) r12 - r9 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322); //800 (1:4) r4 - r1 overhead + mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a); //800 (1:4) r16 - r13 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f); //800 (1:4) r8 - r5 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28); //800 (1:4) r12 - r9 overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322); //800 (1:4) r4 - r1 overhead + mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a); //800 (1:4) r16 - r13 overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f); //800 (1:4) r8 - r5 overhead + + mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead // TBD - change to 4266 + mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead // TBD - change to 4266 + mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241); //2400 (1:8) r8 - r2 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1866 (1:8) r8 - r2 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1866 (1:8) r16 - r10 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542); //1600 (1:8) r8 - r2 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542); //1200 (1:8) r8 - r2 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835); //1200 (1:8) r16 - r10 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034); //800 (1:4) r8 - r2 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39); //800 (1:4) r16 - r10 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034); //800 (1:4) r8 - r2 non-align overhead + mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39); //800 (1:4) r16 - r10 non-align overhead + + // + mt_emi_sync_write(EMI_APB_BASE+0x00000018,0x3657587a); + mt_emi_sync_write(EMI_APB_BASE+0x00000020,0x0000c042); + mt_emi_sync_write(EMI_APB_BASE+0x00000028,0x08421000); + mt_emi_sync_write(EMI_APB_BASE+0x00000038,0x00000083); + mt_emi_sync_write(EMI_APB_BASE+0x0000003c,0x00073210); + mt_emi_sync_write(EMI_APB_BASE+0x00000040,0x00008802); + mt_emi_sync_write(EMI_APB_BASE+0x00000048,0x00000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal rea d/write :8/7 + mt_emi_sync_write(EMI_APB_BASE+0x00000068,0x00000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1 + mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1 + mt_emi_sync_write(EMI_APB_BASE+0x0000007c,0x00001123); + mt_emi_sync_write(EMI_APB_BASE+0x00000718,0x00001123); + mt_emi_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8); + mt_emi_sync_write(EMI_APB_BASE+0x000000d4,0x25252525); + mt_emi_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8); + mt_emi_sync_write(EMI_APB_BASE+0x000000dc,0x25252525); + mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter di v2, [4]=1 + mt_emi_sync_write(EMI_APB_BASE+0x000000f0,0x384a0014); + mt_emi_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000100,0x20107244); + mt_emi_sync_write(EMI_APB_BASE+0x00000108,0x10107044); + mt_emi_sync_write(EMI_APB_BASE+0x00000110,0x343450df); + mt_emi_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0); + mt_emi_sync_write(EMI_APB_BASE+0x00000120,0x10106048); + mt_emi_sync_write(EMI_APB_BASE+0x00000128,0x343450df); + mt_emi_sync_write(EMI_APB_BASE+0x00000130,0x83837044); + mt_emi_sync_write(EMI_APB_BASE+0x00000138,0x83837044); + mt_emi_sync_write(EMI_APB_BASE+0x00000140,0x00007108); + mt_emi_sync_write(EMI_APB_BASE+0x00000144,0x00007108); + mt_emi_sync_write(EMI_APB_BASE+0x00000150,0x090a4000); + mt_emi_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00); + mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001); //[27:20] enable monitor + mt_emi_sync_write(EMI_APB_BASE+0x0000071c,0x10000008); + mt_emi_sync_write(EMI_APB_BASE+0x00000800,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000820,0x24240101); + mt_emi_sync_write(EMI_APB_BASE+0x00000824,0x01012424); + mt_emi_sync_write(EMI_APB_BASE+0x00000828,0x50500101); + mt_emi_sync_write(EMI_APB_BASE+0x0000082c,0x01015050); + mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30); // [6] MD_HRT_URGENT_MASK, if 1 -> mask MD_HRT_URGENT, + mt_emi_sync_write(EMI_APB_BASE+0x00000834,0x05050003); + mt_emi_sync_write(EMI_APB_BASE+0x00000838,0x254dffff); + mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c); //update + mt_emi_sync_write(EMI_APB_BASE+0x00000840,0x000003e8); + mt_emi_sync_write(EMI_APB_BASE+0x00000844,0x0000036b); + mt_emi_sync_write(EMI_APB_BASE+0x00000848,0x00000290); + mt_emi_sync_write(EMI_APB_BASE+0x0000084c,0x00000200); + mt_emi_sync_write(EMI_APB_BASE+0x00000850,0x00000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000854,0x00000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff); //ignore rff threshold + mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785); + mt_emi_sync_write(EMI_APB_BASE+0x00000874,0x000001b5); + mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000); //update + mt_emi_sync_write(EMI_APB_BASE+0x0000087c,0x0255250d); + mt_emi_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59); + mt_emi_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff); + mt_emi_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff); + mt_emi_sync_write(EMI_APB_BASE+0x000008c0,0x0000014b); + mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000); //update + mt_emi_sync_write(EMI_APB_BASE+0x000008c8,0x00000185); + mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000); //update + mt_emi_sync_write(EMI_APB_BASE+0x000008d0,0x00000185); + mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000); //update + mt_emi_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000920,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000930,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000934,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000938,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x000009f0,0x41547082); + mt_emi_sync_write(EMI_APB_BASE+0x000009f4,0x38382a38); + mt_emi_sync_write(EMI_APB_BASE+0x000009f8,0x000001d4); + mt_emi_sync_write(EMI_APB_BASE+0x000009fc,0x00000190); + mt_emi_sync_write(EMI_APB_BASE+0x00000b00,0x0000012c); + mt_emi_sync_write(EMI_APB_BASE+0x00000b04,0x000000ed); + mt_emi_sync_write(EMI_APB_BASE+0x00000b08,0x000000c8); + mt_emi_sync_write(EMI_APB_BASE+0x00000b0c,0x00000096); + mt_emi_sync_write(EMI_APB_BASE+0x00000b10,0x000000c8); + mt_emi_sync_write(EMI_APB_BASE+0x00000b14,0x000000c8); + mt_emi_sync_write(EMI_APB_BASE+0x00000b28,0x26304048); + mt_emi_sync_write(EMI_APB_BASE+0x00000b2c,0x20201820); + mt_emi_sync_write(EMI_APB_BASE+0x00000b60,0x181e282f); + mt_emi_sync_write(EMI_APB_BASE+0x00000b64,0x14140f18); + mt_emi_sync_write(EMI_APB_BASE+0x00000b98,0x7496c8ea); + mt_emi_sync_write(EMI_APB_BASE+0x00000b9c,0x64644b64); + mt_emi_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101); + mt_emi_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101); + mt_emi_sync_write(EMI_APB_BASE+0x00000c08,0x7496c8ea); // 20190821 item3 - synced // TB D- 4266 may need changes + mt_emi_sync_write(EMI_APB_BASE+0x00000c0c,0x64644b64); // 20190821 item3 - synced // TB D- 4266 may need changes + mt_emi_sync_write(EMI_APB_BASE+0x00000c40,0x01010101); + mt_emi_sync_write(EMI_APB_BASE+0x00000c44,0x01010101); + mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025); //ignore wff threshold + mt_emi_sync_write(EMI_APB_BASE+0x00000c80,0x000003e8); + mt_emi_sync_write(EMI_APB_BASE+0x00000c84,0x0000036b); + mt_emi_sync_write(EMI_APB_BASE+0x00000c88,0x00000290); + mt_emi_sync_write(EMI_APB_BASE+0x00000c8c,0x00000200); + mt_emi_sync_write(EMI_APB_BASE+0x00000c90,0x000001b5); + mt_emi_sync_write(EMI_APB_BASE+0x00000c94,0x0000014b); + mt_emi_sync_write(EMI_APB_BASE+0x00000c98,0x00000185); + mt_emi_sync_write(EMI_APB_BASE+0x00000c9c,0x00000185); + mt_emi_sync_write(EMI_APB_BASE+0x00000cb0,0x52698ca0); + mt_emi_sync_write(EMI_APB_BASE+0x00000cb4,0x46463546); + mt_emi_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101); + mt_emi_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101); + + mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0 + mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1 + mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0 + mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1 + mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000); //APR shf1 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1 + mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000); //APW shf1 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0 + mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1 + mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet + mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0 + mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1 + mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh + mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR + mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select + mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB + mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control + mt_emi_sync_write(EMI_APB_BASE+0x00000e04,0x00000166); + mt_emi_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000e14,0x00400166); + mt_emi_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000e24,0x00000266); + mt_emi_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000e34,0x00400266); + mt_emi_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff); + + // Added by Wei-Lun - START + // prtcl chker - golden setting + mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff); // cyc + mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85); // ctl + mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff); // msk + + mt_emi_sync_write(EMI_APB_BASE+0x0000034c,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000354,0x001ffc85); + mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff); // msk + + mt_emi_sync_write(EMI_APB_BASE+0x00000394,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x0000039c,0x001ffc85); + mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff); // msk + + mt_emi_sync_write(EMI_APB_BASE+0x000003d8,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x000003dc,0x001ffc85); + mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff); // msk + + mt_emi_sync_write(EMI_APB_BASE+0x000003fc,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x0000040c,0x001ffc85); + mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff); // msk + + mt_emi_sync_write(EMI_APB_BASE+0x0000044c,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000454,0x001ffc85); + mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff); // msk + + mt_emi_sync_write(EMI_APB_BASE+0x0000049c,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x000004a4,0x001ffc85); + mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff); // msk + + mt_emi_sync_write(EMI_APB_BASE+0x0000050c,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000514,0x001ffc85); + mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff); // msk + + // maxbw monitor - golden setting + + // enable dbw0 cnter for max bw correlation (m3/4 no filters are enabled) + // Added by Wei-Lun - END + + //weilun for new feature + mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000); // dvfs level setting for chn_em i rw switching shf + + // cen_emi timeout value + mt_emi_sync_write(EMI_APB_BASE+0x00000628,0x60606060); + mt_emi_sync_write(EMI_APB_BASE+0x0000062c,0x60606060); + + // fine-grained qos + mt_emi_sync_write(EMI_APB_BASE+0x00000050,0x00000000); + + // ostd->bw + mt_emi_sync_write(EMI_APB_BASE+0x0000061c,0x08ffbbff); + mt_emi_sync_write(EMI_APB_BASE+0x00000624,0xffff5b3c); + mt_emi_sync_write(EMI_APB_BASE+0x00000774,0xffff00ff); + mt_emi_sync_write(EMI_APB_BASE+0x0000077c,0x00ffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000784,0xffff00ff); + mt_emi_sync_write(EMI_APB_BASE+0x0000078c,0x00ffffff); + mt_emi_sync_write(EMI_APB_BASE+0x00000958,0x00000000); + + // hash rule + mt_emi_sync_write(EMI_APB_BASE+0x000007a4,0xC0000000); +} + +static void emi_chn_config(void) +{ +#ifdef RANK_512MB // => 2channel , dual rank , total=2G + mt_emi_sync_write(CHN0_EMI_BASE+0x00000000,0x0400a051); +#else //RANK_1G => 2channel , dual rank , total=4G + mt_emi_sync_write(CHN0_EMI_BASE+0x00000000,0x0400f051); +#endif + mt_emi_sync_write(CHN0_EMI_BASE+0x00000008,0x00ff6048); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000010,0x00000004); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000018,0x99f08c03); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000) + mt_emi_sync_write(CHN0_EMI_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]= 2 + mt_emi_sync_write(CHN0_EMI_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN + mt_emi_sync_write(CHN0_EMI_BASE+0x00000058,0x00000000); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000090,0x000002ff); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000098,0x00003111); //mw2 + mt_emi_sync_write(CHN0_EMI_BASE+0x00000140,0x22607188); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000144,0x22607188); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000148,0x3719595e); // chuan + mt_emi_sync_write(CHN0_EMI_BASE+0x0000014c,0x2719595e); // chuan + mt_emi_sync_write(CHN0_EMI_BASE+0x00000150,0x64f3ff79); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000154,0x64f3ff79); // update timeout settin g: bit 12~15 + mt_emi_sync_write(CHN0_EMI_BASE+0x00000158,0x011b0868); + +// #ifdef SCN_ICFP +// mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0x88410222); // Stop urgent read f irst when write command buffer remain < 8 +// #else //SCN_UI +// mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0x82410222); // Stop urgent read f irst when write command buffer remain < 2 +// #endif + + mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0xa7414222); // Stop urgent read firs t when write command buffer remain < 7, [31] ultra_read_first, [30:28] wr_rsv_thr_l, [27: 24] wr_rsv_thr_h, + mt_emi_sync_write(CHN0_EMI_BASE+0x0000016c,0x0000f801); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000170,0x40000000); + mt_emi_sync_write(CHN0_EMI_BASE+0x000001b0,0x000c802f); // Rank-Aware arbitration + mt_emi_sync_write(CHN0_EMI_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration + mt_emi_sync_write(CHN0_EMI_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration + mt_emi_sync_write(CHN0_EMI_BASE+0x000003fc,0x00000000); // Write M17_toggle_mask = 0 + mt_emi_sync_write(CHN0_EMI_BASE+0x00000080,0xaa0148ff); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000088,0xaa6168ff); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000404,0xaa516cff); + mt_emi_sync_write(CHN0_EMI_BASE+0x00000408,0xaa0140ff); + mt_emi_sync_write(CHN0_EMI_BASE+0x0000040c,0x9f658633); +} + +static void emi_sw_setting(void) +{ + int emi_dcm; + /* Enable MPU violation interrupt to MD for D1 and D7 */ + *((volatile unsigned int *)EMI_MPU_CTRL_D(1)) |= 0x10; + *((volatile unsigned int *)EMI_MPU_CTRL_D(7)) |= 0x10; + + /* for DVFS BW monitor */ + *((volatile unsigned int *) EMI_BWCT0) = 0x05008305; + *((volatile unsigned int *) EMI_BWCT0_6TH) = 0x08FF8705; + *((volatile unsigned int *) EMI_BWCT0_3RD) = 0x0DFF8A05; + *((volatile unsigned int *) EMI_THRO_CTRL1) |= 0x300; + +#ifdef LAST_EMI + last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI); + if (last_emi_info_ptr->isu_magic != LAST_EMI_MAGIC_PATTERN) { + last_emi_info_ptr->isu_magic = LAST_EMI_MAGIC_PATTERN; + last_emi_info_ptr->isu_version = 0xFFFFFFFF; + last_emi_info_ptr->isu_dram_type = 0; + last_emi_info_ptr->isu_diff_us = 0; + last_emi_info_ptr->os_flag_sspm = 0; + last_emi_info_ptr->os_flag_ap = 0; + } + emi_isu = atoi(dconfig_getenv("emi_isu")); + emi_log("[EMI DOE] emi_isu %d\n", emi_isu); + if (emi_isu == 1) + last_emi_info_ptr->isu_ctrl = 0xDECDDECD; + else if (emi_isu == 2) + last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0; + else { +#if CFG_LAST_EMI_BW_DUMP + last_emi_info_ptr->isu_ctrl = 0xDECDDECD; +#else + last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0; +#endif + } +#endif + *((volatile unsigned int *)0x10219858) |= 0x1 << 11; + emi_dcm = 0;//atoi(dconfig_getenv("emi_dcm")); + emi_log("[EMI DOE] emi_dcm %d\n", emi_dcm); + if (emi_dcm == 1) { + *((volatile unsigned int *)EMI_CONM) &= ~0xFF000000; + *((volatile unsigned int *)EMI_CONN) &= ~0xFF000000; + } else if (emi_dcm == 2) { + *((volatile unsigned int *)EMI_CONM) |= 0xFF000000; + *((volatile unsigned int *)EMI_CONN) |= 0xFF000000; + } + dsb(); +} + +void emi_init(void) +{ + /* emi_config_lpddr4_2ch_golden_20191202_1000.c */ + //Broadcast on + mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG,0x0000007f); + + emi_cen_config(); + emi_chn_config(); + + //Broadcast off + mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG,0x00000000); +} + +void emi_init2(void) +{ + unsigned int emi_temp_data; + + //Broadcast on + mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x0000007f); + + mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001); // [0] EMI enable + mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400); //[10] EMI enable + + #ifdef MARGAUX_REAL_CHIP_EMI_GOLDEN_SETTING + + mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010); // [4] Disable emi_mpu_reg in terrupt + + // Clear rank_arb_en + emi_temp_data = mt_emi_sync_read(CHN0_EMI_BASE+0x000001b0); // read ch0 + emi_temp_data = emi_temp_data & ~(0x1); + mt_emi_sync_write(CHN0_EMI_BASE+0x000001b0, emi_temp_data); // broadcast to all channel + // auto-config rank_arb_en according to dual_rank_en setting + // assume all channel with same configuration + emi_temp_data = mt_emi_sync_read(CHN0_EMI_BASE+0x00000000); // read ch0 + emi_temp_data = emi_temp_data & 0x1; + mt_emi_sync_write_or(CHN0_EMI_BASE+0x000001b0, emi_temp_data); // broadcast to a ll channel + + // ----- from dcm_setting.c ----- + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x100, 0xFFFFFFFF); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x104, 0xFFFFFFFF); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x108, 0xFFFFFFFF); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x10C, 0xFFFFFFFF); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x110, 0x01F00000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x114, 0xC0040180); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x118, 0x00000000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x11C, 0x00000003); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x120, 0x0C000000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x124, 0x00C00000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x128, 0x01F08000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x12C, 0x00000000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x130, 0x20003040); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x134, 0x00000000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x138, 0x00001000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x13C, 0x00000000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x140, 0x10020F20); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x144, 0x00019000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x148, 0x040A0818); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x14C, 0x00000370); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x150, 0xC001C080); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x154, 0x33000E01); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x158, 0x180067E1); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x15C, 0x000C008C); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x160, 0x020C0008); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x164, 0x0C00007E); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x168, 0x80050006); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x16C, 0x00030000); + + + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x0000000F); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0x00000000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x030, 0x001F0044); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x038, 0x200000FF); + + mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000); // enable infra_local_cg + + #ifdef MARGAUX_EMI_MP_SETTING + // Enable rdata_prty_gen & wdata_prty_chk + + // emi bus parity workaround + emi_temp_data = mt_emi_sync_read(0x40000000); + mt_emi_sync_write(0x40000000, emi_temp_data); + emi_temp_data = mt_emi_sync_read(0x40000100); + mt_emi_sync_write(0x40000100, emi_temp_data); + emi_temp_data = mt_emi_sync_read(0x40000200); + mt_emi_sync_write(0x40000200, emi_temp_data); + emi_temp_data = mt_emi_sync_read(0x40000300); + mt_emi_sync_write(0x40000300, emi_temp_data); + + mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000); // enable cen_emi parity (w) + mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000050,0x00000004); // enable chn_emi par ity + + /*TINFO="Enable APMCU Early CKE"*/ + //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x00006000); + //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x000007f4); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000007); // set disph_chn_en = 0x7 + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007); // set disph_chg_en = 0x1 + + /*TINFO="read emi_reg_pd then write apmcu config reg"*/ + emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050); + emi_temp_data = emi_temp_data & 0xf; + mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data); + + /*TINFO="Enable EMI wdata bus encode function"*/ + mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000); // enable cen_emi wdata bus e ncode // *EMI_CONN |= (0x1 << 21); + mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000050,0x00000010); // enable chn_emi wda ta bus encode // *CHN0_EMI_CHN_EMI_DFTC |= (0x1 <<4); + #else + // MP_dsim_v02 test (from v01) - all fr + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x003F0000); + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0xA0000000); + #endif + + #endif + + mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040); // disable EBG + + //Broadcast off + mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00000000); + + emi_sw_setting(); +} + +int get_row_width_by_emi(unsigned int rank) +{ + unsigned int emi_cona; + unsigned int shift_row, shift_ext; + int row_width; + + if (rank == 0) { + shift_row = 12; + shift_ext = 22; + } else if (rank == 1) { + shift_row = 14; + shift_ext = 23; + } else + return -1; + + emi_cona = mt_emi_sync_read(EMI_CONA); + row_width = + ((emi_cona >> shift_row) & 0x3) | + ((emi_cona >> shift_ext) & 0x4); + + return (row_width + 13); +} + +int get_channel_nr_by_emi(void) +{ + int channel_nr; + + channel_nr = 0x1 << ((mt_emi_sync_read(EMI_CONA) >> 8) & 0x3); + + return channel_nr; +} + +int get_rank_nr_by_emi(void) +{ + unsigned int cen_emi_cona = mt_emi_sync_read(EMI_CONA); + + if (cen_emi_cona & (0x3 << 16)) + return 2; + else + return 1; +} + +_Static_assert(DRAMC_MAX_RK > 1, "rank number is violated"); +void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]) +{ + unsigned int quad_ch_ratio; + unsigned long long ch0_rank0_size, ch0_rank1_size; + unsigned long long ch1_rank0_size, ch1_rank1_size; + unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH); + unsigned long long dq_width; + + dq_width = 2; + + dram_rank_size[0] = 0; + dram_rank_size[1] = 0; + + ch0_rank0_size = (cen_emi_conh >> 16) & 0xF; + ch0_rank1_size = (cen_emi_conh >> 20) & 0xF; + ch1_rank0_size = (cen_emi_conh >> 24) & 0xF; + ch1_rank1_size = (cen_emi_conh >> 28) & 0xF; + + quad_ch_ratio = (get_rank_nr_by_emi() == 4)? 2 : 1; + ch0_rank0_size = (ch0_rank0_size * quad_ch_ratio) << 28; + ch0_rank1_size = (ch0_rank1_size * quad_ch_ratio) << 28; + ch1_rank0_size = (ch1_rank0_size * quad_ch_ratio) << 28; + ch1_rank1_size = (ch1_rank1_size * quad_ch_ratio) << 28; + + if(ch0_rank0_size == 0) { + die("[EMI] undefined CONH for CH0 RANK0\n"); + } + dram_rank_size[0] += ch0_rank0_size; + + if (get_rank_nr_by_emi() > 1) { + if(ch0_rank1_size == 0) { + die("[EMI] undefined CONH for CH0 RANK1\n"); + } + dram_rank_size[1] += ch0_rank1_size; + } + + if(get_channel_nr_by_emi() > 1) { + if(ch1_rank0_size == 0) { + die("[EMI] undefined CONH for CH1 RANK0\n"); + } + dram_rank_size[0] += ch1_rank0_size; + + if (get_rank_nr_by_emi() > 1) { + if(ch1_rank1_size == 0) { + die("[EMI] undefined CONH for CH1 RANK1\n"); + } + dram_rank_size[1] += ch1_rank1_size; + } + } + + emi_log("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n", + dram_rank_size[0], dram_rank_size[1]); +} + +void set_cen_emi_cona(unsigned int cona_val) +{ + mt_emi_sync_write(EMI_CONA, cona_val); +} + +void set_cen_emi_conf(unsigned int conf_val) +{ + mt_emi_sync_write(EMI_CONF, conf_val); +} + +void set_cen_emi_conh(unsigned int conh_val) +{ + mt_emi_sync_write(EMI_CONH, conh_val); +} + +void set_chn_emi_cona(unsigned int cona_val) +{ + mt_emi_sync_write(CHN_EMI_CONA(CHN0_EMI_BASE), cona_val); + mt_emi_sync_write(CHN_EMI_CONA(CHN1_EMI_BASE), cona_val); +} + +void set_chn_emi_conc(unsigned int conc_val) +{ + mt_emi_sync_write(CHN_EMI_CONC(CHN0_EMI_BASE), conc_val); + mt_emi_sync_write(CHN_EMI_CONC(CHN1_EMI_BASE), conc_val); +} + +unsigned int get_cen_emi_cona(void) +{ + return mt_emi_sync_read(EMI_CONA); +} + +/* assume all chn emi setting are the same */ +unsigned int get_chn_emi_cona(void) +{ + unsigned int ch0_emi_cona; + + ch0_emi_cona = mt_emi_sync_read(CHN0_EMI_BASE); + + return ch0_emi_cona; +} + +void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr) +{ + unsigned int cen_emi_cona, cen_emi_conf; + unsigned long long rank_size[DRAMC_MAX_RK]; + unsigned int channel_num, rank_num; + unsigned int bit_scramble, bit_xor, bit_shift, channel_pos, channel_width; + unsigned int temp; + unsigned int index; + + cen_emi_cona = mt_emi_sync_read(EMI_CONA); + cen_emi_conf = mt_emi_sync_read(EMI_CONF) >> 8; + get_rank_size_by_emi(rank_size); + rank_num = (unsigned int) get_rank_nr_by_emi(); + channel_num = (unsigned int) get_channel_nr_by_emi(); + + phy_addr -= 0x40000000; + for (index = 0; index < rank_num; index++) { + if (phy_addr >= rank_size[index]) + phy_addr -= rank_size[index]; + else + break; + } + + for (bit_scramble = 11; bit_scramble < 17; bit_scramble++) { + bit_xor = (cen_emi_conf >> (4 * (bit_scramble - 11))) & 0xf; + bit_xor &= phy_addr >> 16; + for (bit_shift = 0; bit_shift < 4; bit_shift++) + phy_addr ^= ((bit_xor>>bit_shift)&0x1) << bit_scramble; + } + + if (channel_num > 1) { + channel_pos = ((cen_emi_cona >> 2) & 0x3) + 7; + + for (channel_width = bit_shift = 0; bit_shift < 4; bit_shift++) { + if ((unsigned int)(1 << bit_shift) >= channel_num) + break; + channel_width++; + } + + switch (channel_width) { + case 2: + dram_addr->addr = ((phy_addr & ~(((0x1 << 2) << channel_pos) - 1)) >> 2); + break; + default: + dram_addr->addr = ((phy_addr & ~(((0x1 << 1) << channel_pos) - 1)) >> 1); + break; + } + dram_addr->addr |= (phy_addr & ((0x1 << channel_pos) - 1)); + } + + temp = dram_addr->addr >> 1; + switch ((cen_emi_cona >> 4) & 0x3) { + case 0: + dram_addr->col = temp & 0x1FF; + temp = temp >> 9; + break; + case 1: + dram_addr->col = temp & 0x3FF; + temp = temp >> 10; + break; + case 2: + default: + dram_addr->col = temp & 0x7FF; + temp = temp >> 11; + break; + } + dram_addr->bk = temp & 0x7; + temp = temp >> 3; + + dram_addr->row = temp; + + emi_log("[EMI] ch%d, rk%d, dram addr: %x\n", dram_addr->ch, dram_addr->rk, dram_addr->addr); + emi_log("[EMI] bk%x, row%x, col%x\n", dram_addr->bk, dram_addr->row, dram_addr->col); +} + +static unsigned int cen_emi_conh_backup = 0; +static unsigned int chn_emi_cona_backup = 0; + +/* return the start address of rank1 */ +unsigned int set_emi_before_rank1_mem_test(void) +{ + cen_emi_conh_backup = mt_emi_sync_read(EMI_CONH); + chn_emi_cona_backup = get_chn_emi_cona(); + + if (get_rank_nr_by_emi() == 2) { + /* set the rank size to 1GB for 2 channels */ + mt_emi_sync_write(EMI_CONH, + (cen_emi_conh_backup & 0x0000ffff) | 0x22220000); + set_chn_emi_cona( + (chn_emi_cona_backup & 0xff00ffff) | 0x00220000); + } else { + /* set the rank size to 1GB for 1 channel */ + mt_emi_sync_write(EMI_CONH, + (cen_emi_conh_backup & 0x0000ffff) | 0x44440000); + set_chn_emi_cona( + (chn_emi_cona_backup & 0xff00ffff) | 0x00440000); + } + + return 0x40000000; +} + +void restore_emi_after_rank1_mem_test(void) +{ + mt_emi_sync_write(EMI_CONH, cen_emi_conh_backup); + set_chn_emi_cona(chn_emi_cona_backup); +} + +unsigned long long platform_memory_size(void) +{ + static unsigned long long mem_size = 0; + int nr_rank; + int i; + unsigned long long rank_size[DRAMC_MAX_RK]; + + if (!mem_size) { + nr_rank = get_dram_rank_nr(); + + get_dram_rank_size(rank_size); + + for (i = 0; i < nr_rank; i++) + mem_size += rank_size[i]; + } + + return mem_size; +} + +size_t sdram_size(void) +{ + int rank_num; + size_t dram_size = 0; + u64 rank_size[RANK_MAX]; + + get_rank_size_by_emi(rank_size); + rank_num = get_rank_nr_by_emi(); + + for (int i = 0; i < rank_num; i++) + dram_size += rank_size[i]; + + return dram_size; +} diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h new file mode 100644 index 0000000000..773c3e41bc --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h @@ -0,0 +1,3597 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_AO_REGS_H__ +#define __DDRPHY_AO_REGS_H__ + +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x10238000 +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x10248000 + +#define DDRPHY_AO_BASE_ADDRESS Channel_A_DDRPHY_AO_BASE_VIRTUAL + +#define DDRPHY_REG_PHYPLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0000) + #define PHYPLL0_RG_RPHYPLL_SDM_SSC_EN Fld(1, 2) //[2:2] + #define PHYPLL0_RG_RPHYPLL_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_PHYPLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0004) + #define PHYPLL1_RG_RPHYPLL_TSTOP_EN Fld(1, 0) //[0:0] + #define PHYPLL1_RG_RPHYPLL_TSTOD_EN Fld(1, 1) //[1:1] + #define PHYPLL1_RG_RPHYPLL_TSTFM_EN Fld(1, 2) //[2:2] + #define PHYPLL1_RG_RPHYPLL_TSTCK_EN Fld(1, 3) //[3:3] + #define PHYPLL1_RG_RPHYPLL_TST_EN Fld(1, 4) //[4:4] + #define PHYPLL1_RG_RPHYPLL_TSTLVROD_EN Fld(1, 5) //[5:5] + #define PHYPLL1_RG_RPHYPLL_TST_SEL Fld(4, 8) //[11:8] + +#define DDRPHY_REG_PHYPLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0008) + #define PHYPLL2_RG_RPHYPLL_RESETB Fld(1, 16) //[16:16] + #define PHYPLL2_RG_RPHYPLL_ATPG_EN Fld(1, 17) //[17:17] + #define PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN Fld(1, 21) //[21:21] + #define PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN Fld(1, 22) //[22:22] + +#define DDRPHY_REG_CLRPLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0020) + #define CLRPLL0_RG_RCLRPLL_SDM_SSC_EN Fld(1, 2) //[2:2] + #define CLRPLL0_RG_RCLRPLL_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_RK_B0_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0060) + #define RK_B0_RXDVS0_R_RK0_B0_DVS_LEAD_LAG_CNT_CLR Fld(1, 26) //[26:26] + #define RK_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_CLR Fld(1, 27) //[27:27] + #define RK_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_ENA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_RK_B0_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x0064) + #define RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG Fld(16, 0) //[15:0] + #define RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_RK_B0_RXDVS2 (DDRPHY_AO_BASE_ADDRESS + 0x0068) + #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0 Fld(2, 16) //[17:16] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0 Fld(2, 18) //[19:18] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0 Fld(1, 23) //[23:23] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0 Fld(2, 24) //[25:24] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0 Fld(2, 26) //[27:26] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0 Fld(1, 28) //[28:28] + #define RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0 Fld(1, 29) //[29:29] + #define RK_B0_RXDVS2_R_RK0_DVS_MODE_B0 Fld(2, 30) //[31:30] + +#define DDRPHY_REG_RK_B0_RXDVS3 (DDRPHY_AO_BASE_ADDRESS + 0x006C) + #define RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0 Fld(8, 0) //[7:0] + #define RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_RK_B0_RXDVS4 (DDRPHY_AO_BASE_ADDRESS + 0x0070) + #define RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0 Fld(9, 0) //[8:0] + #define RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_B0_LP_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0160) + #define B0_LP_CTRL0_RG_ARDMSUS_10_B0 Fld(1, 0) //[0:0] + #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_3_1 Fld(3, 1) //[3:1] + #define B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL Fld(1, 4) //[4:4] + #define B0_LP_CTRL0_RG_DA_PICG_B0_CTRL_LOW_BY_LPC Fld(1, 5) //[5:5] + #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_6_6 Fld(1, 6) //[6:6] + #define B0_LP_CTRL0_RG_TX_ARDQ_RESETB_B0_LP_SEL Fld(1, 7) //[7:7] + #define B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL Fld(1, 8) //[8:8] + #define B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL Fld(1, 9) //[9:9] + #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_11_10 Fld(2, 10) //[11:10] + #define B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL Fld(1, 12) //[12:12] + #define B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL Fld(1, 13) //[13:13] + #define B0_LP_CTRL0_RG_B0_DLL_EN_OP_SEQ_LP_SEL Fld(1, 14) //[14:14] + #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_15 Fld(1, 15) //[15:15] + #define B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL Fld(1, 16) //[16:16] + #define B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL Fld(1, 17) //[17:17] + #define B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL Fld(1, 18) //[18:18] + #define B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL Fld(1, 19) //[19:19] + #define B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL Fld(1, 20) //[20:20] + #define B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL Fld(1, 21) //[21:21] + #define B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL Fld(1, 22) //[22:22] + #define B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL Fld(1, 23) //[23:23] + #define B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL Fld(1, 24) //[24:24] + #define B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL Fld(1, 25) //[25:25] + #define B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL Fld(1, 26) //[26:26] + #define B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL Fld(1, 27) //[27:27] + #define B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL Fld(1, 28) //[28:28] + #define B0_LP_CTRL0_RG_ARPI_DDR400_EN_B0_LP_SEL Fld(1, 29) //[29:29] + #define B0_LP_CTRL0_RG_MIDPI_EN_B0_OP_LP_SEL Fld(1, 30) //[30:30] + #define B0_LP_CTRL0_RG_MIDPI_CKDIV4_EN_B0_OP_LP_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B0_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0164) + #define B0_RXDVS0_R_RX_RANKINSEL_B0 Fld(1, 0) //[0:0] + #define B0_RXDVS0_B0_RXDVS0_RFU Fld(3, 1) //[3:1] + #define B0_RXDVS0_R_RX_RANKINCTL_B0 Fld(4, 4) //[7:4] + #define B0_RXDVS0_R_DVS_SW_UP_B0 Fld(1, 8) //[8:8] + #define B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0 Fld(1, 9) //[9:9] + #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B0 Fld(1, 10) //[10:10] + #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B0 Fld(1, 11) //[11:11] + #define B0_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B0 Fld(2, 12) //[13:12] + #define B0_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B0 Fld(3, 16) //[18:16] + #define B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0 Fld(1, 19) //[19:19] + #define B0_RXDVS0_R_RX_DLY_RK_OPT_B0 Fld(2, 20) //[21:20] + #define B0_RXDVS0_R_HWRESTORE_ENA_B0 Fld(1, 22) //[22:22] + #define B0_RXDVS0_R_HWSAVE_MODE_ENA_B0 Fld(1, 24) //[24:24] + #define B0_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B0 Fld(1, 26) //[26:26] + #define B0_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B0 Fld(1, 27) //[27:27] + #define B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 Fld(1, 28) //[28:28] + #define B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0 Fld(1, 29) //[29:29] + #define B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0 Fld(1, 30) //[30:30] + #define B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B0_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x0168) + #define B0_RXDVS1_B0_RXDVS1_RFU Fld(15, 0) //[14:0] + #define B0_RXDVS1_F_LEADLAG_TRACK_B0 Fld(1, 15) //[15:15] + #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B0 Fld(1, 16) //[16:16] + #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_B0_DLL_ARPI0 (DDRPHY_AO_BASE_ADDRESS + 0x016C) + #define B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0 Fld(1, 1) //[1:1] + #define B0_DLL_ARPI0_RG_ARPI_RESETB_B0 Fld(1, 3) //[3:3] + #define B0_DLL_ARPI0_RG_ARPI_LS_EN_B0 Fld(1, 4) //[4:4] + #define B0_DLL_ARPI0_RG_ARPI_LS_SEL_B0 Fld(1, 5) //[5:5] + #define B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0 Fld(1, 6) //[6:6] + +#define DDRPHY_REG_B0_DLL_ARPI1 (DDRPHY_AO_BASE_ADDRESS + 0x0170) + #define B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0 Fld(1, 11) //[11:11] + #define B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0 Fld(1, 13) //[13:13] + #define B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0 Fld(1, 14) //[14:14] + #define B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0 Fld(1, 15) //[15:15] + #define B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0 Fld(1, 17) //[17:17] + #define B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0 Fld(1, 19) //[19:19] + #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT Fld(1, 20) //[20:20] + #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0 Fld(1, 21) //[21:21] + #define B0_DLL_ARPI1_RG_ARPI_SET_UPDN_B0 Fld(3, 28) //[30:28] + +#define DDRPHY_REG_B0_DLL_ARPI4 (DDRPHY_AO_BASE_ADDRESS + 0x0174) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0 Fld(1, 8) //[8:8] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0 Fld(1, 9) //[9:9] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B0 Fld(1, 11) //[11:11] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B0 Fld(1, 13) //[13:13] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B0 Fld(1, 14) //[14:14] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B0 Fld(1, 15) //[15:15] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_FB_B0 Fld(1, 17) //[17:17] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B0 Fld(1, 19) //[19:19] + +#define DDRPHY_REG_B0_DLL_ARPI5 (DDRPHY_AO_BASE_ADDRESS + 0x0178) + #define B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0 Fld(4, 4) //[7:4] + #define B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0 Fld(1, 8) //[8:8] + #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0 Fld(1, 25) //[25:25] + #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0 Fld(1, 26) //[26:26] + #define B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0 Fld(1, 28) //[28:28] + #define B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_B0_DQ2 (DDRPHY_AO_BASE_ADDRESS + 0x017C) + #define B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0 Fld(1, 0) //[0:0] + #define B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0 Fld(1, 1) //[1:1] + #define B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0 Fld(1, 2) //[2:2] + #define B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0 Fld(1, 3) //[3:3] + #define B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 Fld(1, 8) //[8:8] + #define B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0 Fld(1, 9) //[9:9] + #define B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0 Fld(1, 10) //[10:10] + #define B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0 Fld(1, 11) //[11:11] + #define B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0 Fld(1, 12) //[12:12] + #define B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0 Fld(1, 13) //[13:13] + #define B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0 Fld(1, 14) //[14:14] + #define B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0 Fld(1, 15) //[15:15] + #define B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0 Fld(1, 20) //[20:20] + #define B0_DQ2_RG_TX_ARDQ_OE_DIS_B0 Fld(1, 21) //[21:21] + #define B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0 Fld(1, 22) //[22:22] + #define B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_B0_DQ3 (DDRPHY_AO_BASE_ADDRESS + 0x0180) + #define B0_DQ3_RG_ARDQ_ATPG_EN_B0 Fld(1, 0) //[0:0] + #define B0_DQ3_RG_RX_ARDQ_SMT_EN_B0 Fld(1, 1) //[1:1] + #define B0_DQ3_RG_TX_ARDQ_EN_B0 Fld(1, 2) //[2:2] + #define B0_DQ3_RG_ARDQ_RESETB_B0 Fld(1, 3) //[3:3] + #define B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0 Fld(1, 5) //[5:5] + #define B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B0 Fld(1, 6) //[6:6] + #define B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0 Fld(1, 7) //[7:7] + #define B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0 Fld(1, 10) //[10:10] + #define B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0 Fld(1, 11) //[11:11] + #define B0_DQ3_RG_RX_ARDQS0_SWAP_EN_B0 Fld(1, 15) //[15:15] + #define B0_DQ3_RG_ARPI_ASYNC_EN_B0 Fld(1, 23) //[23:23] + #define B0_DQ3_RG_ARPI_LAT_EN_B0 Fld(1, 24) //[24:24] + #define B0_DQ3_RG_ARPI_MCK_FB_SEL_B0 Fld(2, 26) //[27:26] + +#define DDRPHY_REG_B0_DQ4 (DDRPHY_AO_BASE_ADDRESS + 0x0184) + #define B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0 Fld(7, 0) //[6:0] + #define B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0 Fld(7, 8) //[14:8] + #define B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0 Fld(6, 16) //[21:16] + #define B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_B0_DQ5 (DDRPHY_AO_BASE_ADDRESS + 0x0188) + #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0 Fld(6, 8) //[13:8] + #define B0_DQ5_RG_RX_ARDQ_VREF_EN_B0 Fld(1, 16) //[16:16] + #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0 Fld(1, 17) //[17:17] + #define B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0 Fld(4, 20) //[23:20] + #define B0_DQ5_RG_RX_ARDQ_EYE_EN_B0 Fld(1, 24) //[24:24] + #define B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0 Fld(1, 25) //[25:25] + #define B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B0_DQ6 (DDRPHY_AO_BASE_ADDRESS + 0x018C) + #define B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0 Fld(2, 0) //[1:0] + #define B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0 Fld(1, 2) //[2:2] + #define B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0 Fld(1, 3) //[3:3] + #define B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0 Fld(1, 5) //[5:5] + #define B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0 Fld(1, 6) //[6:6] + #define B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0 Fld(1, 7) //[7:7] + #define B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0 Fld(1, 8) //[8:8] + #define B0_DQ6_RG_RX_ARDQ_O1_SEL_B0 Fld(1, 9) //[9:9] + #define B0_DQ6_RG_RX_ARDQ_JM_SEL_B0 Fld(1, 11) //[11:11] + #define B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0 Fld(1, 12) //[12:12] + #define B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0 Fld(2, 14) //[15:14] + #define B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0 Fld(1, 16) //[16:16] + #define B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0 Fld(1, 17) //[17:17] + #define B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0 Fld(1, 18) //[18:18] + #define B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0 Fld(1, 19) //[19:19] + #define B0_DQ6_RG_TX_ARDQ_LP5_SEL_B0 Fld(1, 20) //[20:20] + #define B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0 Fld(1, 21) //[21:21] + #define B0_DQ6_RG_TX_ARDQ_CAP_EN_B0 Fld(1, 24) //[24:24] + #define B0_DQ6_RG_TX_ARDQ_DATA_SWAP_EN_B0 Fld(1, 25) //[25:25] + #define B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0 Fld(2, 26) //[27:26] + #define B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0 Fld(1, 28) //[28:28] + #define B0_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B0 Fld(1, 29) //[29:29] + #define B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B0_DQ7 (DDRPHY_AO_BASE_ADDRESS + 0x0190) + #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0 Fld(1, 0) //[0:0] + #define B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0 Fld(1, 1) //[1:1] + #define B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0 Fld(1, 2) //[2:2] + #define B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0 Fld(1, 3) //[3:3] + #define B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0 Fld(1, 4) //[4:4] + #define B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0 Fld(1, 5) //[5:5] + #define B0_DQ7_RG_TX_ARDQ_PULL_DN_B0 Fld(1, 6) //[6:6] + #define B0_DQ7_RG_TX_ARDQ_PULL_UP_B0 Fld(1, 7) //[7:7] + #define B0_DQ7_RG_TX_ARWCKB_PULL_DN_B0 Fld(1, 8) //[8:8] + #define B0_DQ7_RG_TX_ARWCKB_PULL_UP_B0 Fld(1, 9) //[9:9] + #define B0_DQ7_RG_TX_ARWCK_PULL_DN_B0 Fld(1, 10) //[10:10] + #define B0_DQ7_RG_TX_ARWCK_PULL_UP_B0 Fld(1, 11) //[11:11] + #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y Fld(1, 16) //[16:16] + +#define DDRPHY_REG_B0_DQ8 (DDRPHY_AO_BASE_ADDRESS + 0x0194) + #define B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0 Fld(1, 0) //[0:0] + #define B0_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B0 Fld(1, 1) //[1:1] + #define B0_DQ8_RG_TX_ARDQ_CAP_DET_B0 Fld(1, 2) //[2:2] + #define B0_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B0 Fld(2, 3) //[4:3] + #define B0_DQ8_RG_RX_ARDQS_BURST_E1_EN_B0 Fld(1, 8) //[8:8] + #define B0_DQ8_RG_RX_ARDQS_BURST_E2_EN_B0 Fld(1, 9) //[9:9] + #define B0_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B0 Fld(1, 12) //[12:12] + #define B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0 Fld(1, 13) //[13:13] + #define B0_DQ8_RG_ARDLL_RESETB_B0 Fld(1, 15) //[15:15] + +#define DDRPHY_REG_B0_DQ9 (DDRPHY_AO_BASE_ADDRESS + 0x0198) + #define B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0 Fld(1, 0) //[0:0] + #define B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0 Fld(1, 4) //[4:4] + #define B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 Fld(1, 5) //[5:5] + #define B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 Fld(1, 6) //[6:6] + #define B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0 Fld(1, 7) //[7:7] + #define B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 Fld(8, 8) //[15:8] + #define B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 Fld(3, 16) //[18:16] + #define B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 Fld(3, 20) //[22:20] + #define B0_DQ9_R_DMRXDVS_VALID_LAT_B0 Fld(3, 24) //[26:24] + #define B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0 Fld(3, 28) //[30:28] + +#define DDRPHY_REG_B0_DQ10 (DDRPHY_AO_BASE_ADDRESS + 0x019C) + #define B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_B0_DQ11 (DDRPHY_AO_BASE_ADDRESS + 0x01A0) + #define B0_DQ11_DMY_DQ11_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_B0_PHY2 (DDRPHY_AO_BASE_ADDRESS + 0x01A4) + #define B0_PHY2_RG_RX_ARDQS_SE_SWAP_EN_B0 Fld(1, 0) //[0:0] + #define B0_PHY2_RG_RX_ARDQS_JM_SEL_B0 Fld(4, 4) //[7:4] + #define B0_PHY2_RG_RX_ARDQS_JM_EN_B0 Fld(1, 8) //[8:8] + #define B0_PHY2_RG_RX_ARDQS_JM_DLY_B0 Fld(9, 16) //[24:16] + #define B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0 Fld(1, 28) //[28:28] + #define B0_PHY2_RG_RX_ARDQS_DQSIEN_TIE_GATE_EN_B0 Fld(1, 29) //[29:29] + #define B0_PHY2_RG_RX_ARDQSB_SE_SWAP_EN_B0 Fld(1, 30) //[30:30] + +#define DDRPHY_REG_B0_PHY3 (DDRPHY_AO_BASE_ADDRESS + 0x01A8) + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0 Fld(7, 8) //[14:8] + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0 Fld(4, 16) //[19:16] + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_EN_B0 Fld(1, 20) //[20:20] + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B0 Fld(2, 24) //[25:24] + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_RC_SEL_B0 Fld(2, 26) //[27:26] + #define B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0 Fld(1, 28) //[28:28] + +#define DDRPHY_REG_B0_TX_MCK (DDRPHY_AO_BASE_ADDRESS + 0x01AC) + #define B0_TX_MCK_DMY_TX_MCK_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_RK_B1_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x01E0) + #define RK_B1_RXDVS0_R_RK0_B1_DVS_LEAD_LAG_CNT_CLR Fld(1, 26) //[26:26] + #define RK_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_CLR Fld(1, 27) //[27:27] + #define RK_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_ENA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_RK_B1_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x01E4) + #define RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG Fld(16, 0) //[15:0] + #define RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_RK_B1_RXDVS2 (DDRPHY_AO_BASE_ADDRESS + 0x01E8) + #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1 Fld(2, 16) //[17:16] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1 Fld(2, 18) //[19:18] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1 Fld(1, 23) //[23:23] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1 Fld(2, 24) //[25:24] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1 Fld(2, 26) //[27:26] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1 Fld(1, 28) //[28:28] + #define RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1 Fld(1, 29) //[29:29] + #define RK_B1_RXDVS2_R_RK0_DVS_MODE_B1 Fld(2, 30) //[31:30] + +#define DDRPHY_REG_RK_B1_RXDVS3 (DDRPHY_AO_BASE_ADDRESS + 0x01EC) + #define RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1 Fld(8, 0) //[7:0] + #define RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_RK_B1_RXDVS4 (DDRPHY_AO_BASE_ADDRESS + 0x01F0) + #define RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1 Fld(9, 0) //[8:0] + #define RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_B1_LP_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x02E0) + #define B1_LP_CTRL0_RG_ARDMSUS_10_B1 Fld(1, 0) //[0:0] + #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_3_1 Fld(3, 1) //[3:1] + #define B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL Fld(1, 4) //[4:4] + #define B1_LP_CTRL0_RG_DA_PICG_B1_CTRL_LOW_BY_LPC Fld(1, 5) //[5:5] + #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_6_6 Fld(1, 6) //[6:6] + #define B1_LP_CTRL0_RG_TX_ARDQ_RESETB_B1_LP_SEL Fld(1, 7) //[7:7] + #define B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL Fld(1, 8) //[8:8] + #define B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL Fld(1, 9) //[9:9] + #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_11_10 Fld(2, 10) //[11:10] + #define B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL Fld(1, 12) //[12:12] + #define B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL Fld(1, 13) //[13:13] + #define B1_LP_CTRL0_RG_B1_DLL_EN_OP_SEQ_LP_SEL Fld(1, 14) //[14:14] + #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_15 Fld(1, 15) //[15:15] + #define B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL Fld(1, 16) //[16:16] + #define B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL Fld(1, 17) //[17:17] + #define B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL Fld(1, 18) //[18:18] + #define B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL Fld(1, 19) //[19:19] + #define B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL Fld(1, 20) //[20:20] + #define B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL Fld(1, 21) //[21:21] + #define B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL Fld(1, 22) //[22:22] + #define B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL Fld(1, 23) //[23:23] + #define B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL Fld(1, 24) //[24:24] + #define B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL Fld(1, 25) //[25:25] + #define B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL Fld(1, 26) //[26:26] + #define B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL Fld(1, 27) //[27:27] + #define B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL Fld(1, 28) //[28:28] + #define B1_LP_CTRL0_RG_ARPI_DDR400_EN_B1_LP_SEL Fld(1, 29) //[29:29] + #define B1_LP_CTRL0_RG_MIDPI_EN_B1_OP_LP_SEL Fld(1, 30) //[30:30] + #define B1_LP_CTRL0_RG_MIDPI_CKDIV4_EN_B1_OP_LP_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B1_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x02E4) + #define B1_RXDVS0_R_RX_RANKINSEL_B1 Fld(1, 0) //[0:0] + #define B1_RXDVS0_B1_RXDVS0_RFU Fld(3, 1) //[3:1] + #define B1_RXDVS0_R_RX_RANKINCTL_B1 Fld(4, 4) //[7:4] + #define B1_RXDVS0_R_DVS_SW_UP_B1 Fld(1, 8) //[8:8] + #define B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1 Fld(1, 9) //[9:9] + #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B1 Fld(1, 10) //[10:10] + #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B1 Fld(1, 11) //[11:11] + #define B1_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B1 Fld(2, 12) //[13:12] + #define B1_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B1 Fld(3, 16) //[18:16] + #define B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1 Fld(1, 19) //[19:19] + #define B1_RXDVS0_R_RX_DLY_RK_OPT_B1 Fld(2, 20) //[21:20] + #define B1_RXDVS0_R_HWRESTORE_ENA_B1 Fld(1, 22) //[22:22] + #define B1_RXDVS0_R_HWSAVE_MODE_ENA_B1 Fld(1, 24) //[24:24] + #define B1_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B1 Fld(1, 26) //[26:26] + #define B1_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B1 Fld(1, 27) //[27:27] + #define B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 Fld(1, 28) //[28:28] + #define B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1 Fld(1, 29) //[29:29] + #define B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1 Fld(1, 30) //[30:30] + #define B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B1_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x02E8) + #define B1_RXDVS1_B1_RXDVS1_RFU Fld(15, 0) //[14:0] + #define B1_RXDVS1_F_LEADLAG_TRACK_B1 Fld(1, 15) //[15:15] + #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B1 Fld(1, 16) //[16:16] + #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_B1_DLL_ARPI0 (DDRPHY_AO_BASE_ADDRESS + 0x02EC) + #define B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1 Fld(1, 1) //[1:1] + #define B1_DLL_ARPI0_RG_ARPI_RESETB_B1 Fld(1, 3) //[3:3] + #define B1_DLL_ARPI0_RG_ARPI_LS_EN_B1 Fld(1, 4) //[4:4] + #define B1_DLL_ARPI0_RG_ARPI_LS_SEL_B1 Fld(1, 5) //[5:5] + #define B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1 Fld(1, 6) //[6:6] + +#define DDRPHY_REG_B1_DLL_ARPI1 (DDRPHY_AO_BASE_ADDRESS + 0x02F0) + #define B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1 Fld(1, 11) //[11:11] + #define B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1 Fld(1, 13) //[13:13] + #define B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1 Fld(1, 14) //[14:14] + #define B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1 Fld(1, 15) //[15:15] + #define B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1 Fld(1, 17) //[17:17] + #define B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1 Fld(1, 19) //[19:19] + #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT Fld(1, 20) //[20:20] + #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1 Fld(1, 21) //[21:21] + #define B1_DLL_ARPI1_RG_ARPI_SET_UPDN_B1 Fld(3, 28) //[30:28] + +#define DDRPHY_REG_B1_DLL_ARPI4 (DDRPHY_AO_BASE_ADDRESS + 0x02F4) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1 Fld(1, 8) //[8:8] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1 Fld(1, 9) //[9:9] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B1 Fld(1, 11) //[11:11] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B1 Fld(1, 13) //[13:13] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B1 Fld(1, 14) //[14:14] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B1 Fld(1, 15) //[15:15] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_FB_B1 Fld(1, 17) //[17:17] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B1 Fld(1, 19) //[19:19] + +#define DDRPHY_REG_B1_DLL_ARPI5 (DDRPHY_AO_BASE_ADDRESS + 0x02F8) + #define B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1 Fld(4, 4) //[7:4] + #define B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1 Fld(1, 8) //[8:8] + #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1 Fld(1, 25) //[25:25] + #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1 Fld(1, 26) //[26:26] + #define B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1 Fld(1, 28) //[28:28] + #define B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_B1_DQ2 (DDRPHY_AO_BASE_ADDRESS + 0x02FC) + #define B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1 Fld(1, 0) //[0:0] + #define B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1 Fld(1, 1) //[1:1] + #define B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1 Fld(1, 2) //[2:2] + #define B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1 Fld(1, 3) //[3:3] + #define B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 Fld(1, 8) //[8:8] + #define B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1 Fld(1, 9) //[9:9] + #define B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1 Fld(1, 10) //[10:10] + #define B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1 Fld(1, 11) //[11:11] + #define B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1 Fld(1, 12) //[12:12] + #define B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1 Fld(1, 13) //[13:13] + #define B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1 Fld(1, 14) //[14:14] + #define B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1 Fld(1, 15) //[15:15] + #define B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1 Fld(1, 20) //[20:20] + #define B1_DQ2_RG_TX_ARDQ_OE_DIS_B1 Fld(1, 21) //[21:21] + #define B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1 Fld(1, 22) //[22:22] + #define B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_B1_DQ3 (DDRPHY_AO_BASE_ADDRESS + 0x0300) + #define B1_DQ3_RG_ARDQ_ATPG_EN_B1 Fld(1, 0) //[0:0] + #define B1_DQ3_RG_RX_ARDQ_SMT_EN_B1 Fld(1, 1) //[1:1] + #define B1_DQ3_RG_TX_ARDQ_EN_B1 Fld(1, 2) //[2:2] + #define B1_DQ3_RG_ARDQ_RESETB_B1 Fld(1, 3) //[3:3] + #define B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1 Fld(1, 5) //[5:5] + #define B1_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B1 Fld(1, 6) //[6:6] + #define B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1 Fld(1, 7) //[7:7] + #define B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1 Fld(1, 10) //[10:10] + #define B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1 Fld(1, 11) //[11:11] + #define B1_DQ3_RG_RX_ARDQS0_SWAP_EN_B1 Fld(1, 15) //[15:15] + #define B1_DQ3_RG_ARPI_ASYNC_EN_B1 Fld(1, 23) //[23:23] + #define B1_DQ3_RG_ARPI_LAT_EN_B1 Fld(1, 24) //[24:24] + #define B1_DQ3_RG_ARPI_MCK_FB_SEL_B1 Fld(2, 26) //[27:26] + +#define DDRPHY_REG_B1_DQ4 (DDRPHY_AO_BASE_ADDRESS + 0x0304) + #define B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1 Fld(7, 0) //[6:0] + #define B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1 Fld(7, 8) //[14:8] + #define B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1 Fld(6, 16) //[21:16] + #define B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_B1_DQ5 (DDRPHY_AO_BASE_ADDRESS + 0x0308) + #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1 Fld(6, 8) //[13:8] + #define B1_DQ5_RG_RX_ARDQ_VREF_EN_B1 Fld(1, 16) //[16:16] + #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1 Fld(1, 17) //[17:17] + #define B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1 Fld(4, 20) //[23:20] + #define B1_DQ5_RG_RX_ARDQ_EYE_EN_B1 Fld(1, 24) //[24:24] + #define B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1 Fld(1, 25) //[25:25] + #define B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B1_DQ6 (DDRPHY_AO_BASE_ADDRESS + 0x030C) + #define B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1 Fld(2, 0) //[1:0] + #define B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1 Fld(1, 2) //[2:2] + #define B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1 Fld(1, 3) //[3:3] + #define B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1 Fld(1, 5) //[5:5] + #define B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1 Fld(1, 6) //[6:6] + #define B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1 Fld(1, 7) //[7:7] + #define B1_DQ6_RG_RX_ARDQ_LPBK_EN_B1 Fld(1, 8) //[8:8] + #define B1_DQ6_RG_RX_ARDQ_O1_SEL_B1 Fld(1, 9) //[9:9] + #define B1_DQ6_RG_RX_ARDQ_JM_SEL_B1 Fld(1, 11) //[11:11] + #define B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1 Fld(1, 12) //[12:12] + #define B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1 Fld(2, 14) //[15:14] + #define B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1 Fld(1, 16) //[16:16] + #define B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1 Fld(1, 17) //[17:17] + #define B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1 Fld(1, 18) //[18:18] + #define B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1 Fld(1, 19) //[19:19] + #define B1_DQ6_RG_TX_ARDQ_LP5_SEL_B1 Fld(1, 20) //[20:20] + #define B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1 Fld(1, 21) //[21:21] + #define B1_DQ6_RG_TX_ARDQ_CAP_EN_B1 Fld(1, 24) //[24:24] + #define B1_DQ6_RG_TX_ARDQ_DATA_SWAP_EN_B1 Fld(1, 25) //[25:25] + #define B1_DQ6_RG_TX_ARDQ_DATA_SWAP_B1 Fld(2, 26) //[27:26] + #define B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1 Fld(1, 28) //[28:28] + #define B1_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B1 Fld(1, 29) //[29:29] + #define B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B1_DQ7 (DDRPHY_AO_BASE_ADDRESS + 0x0310) + #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1 Fld(1, 0) //[0:0] + #define B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1 Fld(1, 1) //[1:1] + #define B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1 Fld(1, 2) //[2:2] + #define B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1 Fld(1, 3) //[3:3] + #define B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1 Fld(1, 4) //[4:4] + #define B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 Fld(1, 5) //[5:5] + #define B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 Fld(1, 6) //[6:6] + #define B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 Fld(1, 7) //[7:7] + #define B1_DQ7_RG_TX_ARWCKB_PULL_DN_B1 Fld(1, 8) //[8:8] + #define B1_DQ7_RG_TX_ARWCKB_PULL_UP_B1 Fld(1, 9) //[9:9] + #define B1_DQ7_RG_TX_ARWCK_PULL_DN_B1 Fld(1, 10) //[10:10] + #define B1_DQ7_RG_TX_ARWCK_PULL_UP_B1 Fld(1, 11) //[11:11] + #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y Fld(1, 16) //[16:16] + +#define DDRPHY_REG_B1_DQ8 (DDRPHY_AO_BASE_ADDRESS + 0x0314) + #define B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1 Fld(1, 0) //[0:0] + #define B1_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B1 Fld(1, 1) //[1:1] + #define B1_DQ8_RG_TX_ARDQ_CAP_DET_B1 Fld(1, 2) //[2:2] + #define B1_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B1 Fld(2, 3) //[4:3] + #define B1_DQ8_RG_RX_ARDQS_BURST_E1_EN_B1 Fld(1, 8) //[8:8] + #define B1_DQ8_RG_RX_ARDQS_BURST_E2_EN_B1 Fld(1, 9) //[9:9] + #define B1_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B1 Fld(1, 12) //[12:12] + #define B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1 Fld(1, 13) //[13:13] + #define B1_DQ8_RG_ARDLL_RESETB_B1 Fld(1, 15) //[15:15] + +#define DDRPHY_REG_B1_DQ9 (DDRPHY_AO_BASE_ADDRESS + 0x0318) + #define B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1 Fld(1, 0) //[0:0] + #define B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1 Fld(1, 4) //[4:4] + #define B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 Fld(1, 5) //[5:5] + #define B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 Fld(1, 6) //[6:6] + #define B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 Fld(1, 7) //[7:7] + #define B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 Fld(8, 8) //[15:8] + #define B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 Fld(3, 16) //[18:16] + #define B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 Fld(3, 20) //[22:20] + #define B1_DQ9_R_DMRXDVS_VALID_LAT_B1 Fld(3, 24) //[26:24] + #define B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1 Fld(3, 28) //[30:28] + +#define DDRPHY_REG_B1_DQ10 (DDRPHY_AO_BASE_ADDRESS + 0x031C) + #define B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_B1_DQ11 (DDRPHY_AO_BASE_ADDRESS + 0x0320) + #define B1_DQ11_DMY_DQ11_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_B1_PHY2 (DDRPHY_AO_BASE_ADDRESS + 0x0324) + #define B1_PHY2_RG_RX_ARDQS_SE_SWAP_EN_B1 Fld(1, 0) //[0:0] + #define B1_PHY2_RG_RX_ARDQS_JM_SEL_B1 Fld(4, 4) //[7:4] + #define B1_PHY2_RG_RX_ARDQS_JM_EN_B1 Fld(1, 8) //[8:8] + #define B1_PHY2_RG_RX_ARDQS_JM_DLY_B1 Fld(9, 16) //[24:16] + #define B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1 Fld(1, 28) //[28:28] + #define B1_PHY2_RG_RX_ARDQS_DQSIEN_TIE_GATE_EN_B1 Fld(1, 29) //[29:29] + #define B1_PHY2_RG_RX_ARDQSB_SE_SWAP_EN_B1 Fld(1, 30) //[30:30] + +#define DDRPHY_REG_B1_PHY3 (DDRPHY_AO_BASE_ADDRESS + 0x0328) + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B1 Fld(7, 8) //[14:8] + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1 Fld(4, 16) //[19:16] + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_EN_B1 Fld(1, 20) //[20:20] + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B1 Fld(2, 24) //[25:24] + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_RC_SEL_B1 Fld(2, 26) //[27:26] + #define B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1 Fld(1, 28) //[28:28] + +#define DDRPHY_REG_B1_TX_MCK (DDRPHY_AO_BASE_ADDRESS + 0x032C) + #define B1_TX_MCK_DMY_TX_MCK_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_RK_CA_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0360) + #define RK_CA_RXDVS0_R_RK0_CA_DVS_LEAD_LAG_CNT_CLR Fld(1, 26) //[26:26] + #define RK_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_CLR Fld(1, 27) //[27:27] + #define RK_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_ENA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_RK_CA_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x0364) + #define RK_CA_RXDVS1_R_RK0_CA_DVS_TH_LAG Fld(16, 0) //[15:0] + #define RK_CA_RXDVS1_R_RK0_CA_DVS_TH_LEAD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_RK_CA_RXDVS2 (DDRPHY_AO_BASE_ADDRESS + 0x0368) + #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_CA Fld(2, 16) //[17:16] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_CA Fld(2, 18) //[19:18] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_CA Fld(1, 23) //[23:23] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_CA Fld(2, 24) //[25:24] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_CA Fld(2, 26) //[27:26] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_CA Fld(1, 28) //[28:28] + #define RK_CA_RXDVS2_R_RK0_DVS_FDLY_MODE_CA Fld(1, 29) //[29:29] + #define RK_CA_RXDVS2_R_RK0_DVS_MODE_CA Fld(2, 30) //[31:30] + +#define DDRPHY_REG_RK_CA_RXDVS3 (DDRPHY_AO_BASE_ADDRESS + 0x036C) + #define RK_CA_RXDVS3_RG_RK0_ARCMD_MIN_DLY Fld(6, 0) //[5:0] + #define RK_CA_RXDVS3_RG_RK0_ARCMD_MIN_DLY_RFU Fld(2, 6) //[7:6] + #define RK_CA_RXDVS3_RG_RK0_ARCMD_MAX_DLY Fld(6, 8) //[13:8] + #define RK_CA_RXDVS3_RG_RK0_ARCMD_MAX_DLY_RFU Fld(2, 14) //[15:14] + +#define DDRPHY_REG_RK_CA_RXDVS4 (DDRPHY_AO_BASE_ADDRESS + 0x0370) + #define RK_CA_RXDVS4_RG_RK0_ARCLK_MIN_DLY Fld(7, 0) //[6:0] + #define RK_CA_RXDVS4_RG_RK0_ARCLK_MIN_DLY_RFU Fld(1, 7) //[7:7] + #define RK_CA_RXDVS4_RG_RK0_ARCLK_MAX_DLY Fld(7, 8) //[14:8] + #define RK_CA_RXDVS4_RG_RK0_ARCLK_MAX_DLY_RFU Fld(1, 15) //[15:15] + +#define DDRPHY_REG_CA_LP_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0460) + #define CA_LP_CTRL0_RG_ARDMSUS_10_CA Fld(1, 0) //[0:0] + #define CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL Fld(1, 1) //[1:1] + #define CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL Fld(1, 2) //[2:2] + #define CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL Fld(1, 3) //[3:3] + #define CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL Fld(1, 4) //[4:4] + #define CA_LP_CTRL0_RG_DA_PICG_CA_CTRL_LOW_BY_LPC Fld(1, 5) //[5:5] + #define CA_LP_CTRL0_RESERVED_CA_LP_CTRL0_6_6 Fld(1, 6) //[6:6] + #define CA_LP_CTRL0_RG_TX_ARCMD_RESETB_LP_SEL Fld(1, 7) //[7:7] + #define CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL Fld(1, 8) //[8:8] + #define CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL Fld(1, 9) //[9:9] + #define CA_LP_CTRL0_RESERVED_CA_LP_CTRL0_11_10 Fld(2, 10) //[11:10] + #define CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL Fld(1, 12) //[12:12] + #define CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL Fld(1, 13) //[13:13] + #define CA_LP_CTRL0_RG_CA_DLL_EN_OP_SEQ_LP_SEL Fld(1, 14) //[14:14] + #define CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL Fld(1, 15) //[15:15] + #define CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL Fld(1, 16) //[16:16] + #define CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL Fld(1, 17) //[17:17] + #define CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL Fld(1, 18) //[18:18] + #define CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL Fld(1, 19) //[19:19] + #define CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL Fld(1, 20) //[20:20] + #define CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL Fld(1, 21) //[21:21] + #define CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL Fld(1, 22) //[22:22] + #define CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL Fld(1, 23) //[23:23] + #define CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL Fld(1, 24) //[24:24] + #define CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL Fld(1, 25) //[25:25] + #define CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL Fld(1, 26) //[26:26] + #define CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL Fld(1, 27) //[27:27] + #define CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL Fld(1, 28) //[28:28] + #define CA_LP_CTRL0_RG_ARPI_DDR400_EN_CA_LP_SEL Fld(1, 29) //[29:29] + #define CA_LP_CTRL0_RG_MIDPI_EN_CA_OP_LP_SEL Fld(1, 30) //[30:30] + #define CA_LP_CTRL0_RG_MIDPI_CKDIV4_EN_CA_OP_LP_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_CA_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0464) + #define CA_RXDVS0_R_RX_RANKINSEL_CA Fld(1, 0) //[0:0] + #define CA_RXDVS0_CA_RXDVS0_RFU Fld(3, 1) //[3:1] + #define CA_RXDVS0_R_RX_RANKINCTL_CA Fld(4, 4) //[7:4] + #define CA_RXDVS0_R_DVS_SW_UP_CA Fld(1, 8) //[8:8] + #define CA_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_CA Fld(1, 9) //[9:9] + #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_CA Fld(1, 10) //[10:10] + #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_CA Fld(1, 11) //[11:11] + #define CA_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_CA Fld(2, 12) //[13:12] + #define CA_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_CA Fld(3, 16) //[18:16] + #define CA_RXDVS0_R_DMRXDVS_CNTCMP_OPT_CA Fld(1, 19) //[19:19] + #define CA_RXDVS0_R_RX_DLY_RK_OPT_CA Fld(2, 20) //[21:20] + #define CA_RXDVS0_R_HWRESTORE_ENA_CA Fld(1, 22) //[22:22] + #define CA_RXDVS0_R_HWSAVE_MODE_ENA_CA Fld(1, 24) //[24:24] + #define CA_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_CA Fld(1, 26) //[26:26] + #define CA_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_CA Fld(1, 27) //[27:27] + #define CA_RXDVS0_R_RX_DLY_TRACK_CG_EN_CA Fld(1, 28) //[28:28] + #define CA_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_CA Fld(1, 29) //[29:29] + #define CA_RXDVS0_R_RX_DLY_TRACK_CLR_CA Fld(1, 30) //[30:30] + #define CA_RXDVS0_R_RX_DLY_TRACK_ENA_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_CA_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x0468) + #define CA_RXDVS1_CA_RXDVS1_RFU Fld(16, 0) //[15:0] + #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_CA Fld(1, 16) //[16:16] + #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_CA Fld(1, 17) //[17:17] + +#define DDRPHY_REG_CA_DLL_ARPI0 (DDRPHY_AO_BASE_ADDRESS + 0x046C) + #define CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA Fld(1, 1) //[1:1] + #define CA_DLL_ARPI0_RG_ARPI_RESETB_CA Fld(1, 3) //[3:3] + #define CA_DLL_ARPI0_RG_ARPI_LS_EN_CA Fld(1, 4) //[4:4] + #define CA_DLL_ARPI0_RG_ARPI_LS_SEL_CA Fld(1, 5) //[5:5] + #define CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA Fld(1, 6) //[6:6] + +#define DDRPHY_REG_CA_DLL_ARPI1 (DDRPHY_AO_BASE_ADDRESS + 0x0470) + #define CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN Fld(1, 11) //[11:11] + #define CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN Fld(1, 13) //[13:13] + #define CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN Fld(1, 15) //[15:15] + #define CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN Fld(1, 16) //[16:16] + #define CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA Fld(1, 17) //[17:17] + #define CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA Fld(1, 19) //[19:19] + #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT Fld(1, 20) //[20:20] + #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA Fld(1, 21) //[21:21] + #define CA_DLL_ARPI1_RG_ARPI_SET_UPDN_CA Fld(3, 28) //[30:28] + +#define DDRPHY_REG_CA_DLL_ARPI4 (DDRPHY_AO_BASE_ADDRESS + 0x0474) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA Fld(1, 8) //[8:8] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA Fld(1, 9) //[9:9] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLKIEN Fld(1, 11) //[11:11] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CMD Fld(1, 13) //[13:13] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLK Fld(1, 15) //[15:15] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CS Fld(1, 16) //[16:16] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_FB_CA Fld(1, 17) //[17:17] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_CA Fld(1, 19) //[19:19] + +#define DDRPHY_REG_CA_DLL_ARPI5 (DDRPHY_AO_BASE_ADDRESS + 0x0478) + #define CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA Fld(4, 4) //[7:4] + #define CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA Fld(1, 8) //[8:8] + #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA Fld(1, 25) //[25:25] + #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA Fld(1, 26) //[26:26] + #define CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA Fld(1, 28) //[28:28] + #define CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA Fld(3, 29) //[31:29] + +#define DDRPHY_REG_CA_CMD2 (DDRPHY_AO_BASE_ADDRESS + 0x047C) + #define CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA Fld(1, 0) //[0:0] + #define CA_CMD2_RG_TX_ARCLK_OE_DIS_CA Fld(1, 1) //[1:1] + #define CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA Fld(1, 2) //[2:2] + #define CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA Fld(1, 3) //[3:3] + #define CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA Fld(1, 14) //[14:14] + #define CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA Fld(1, 15) //[15:15] + #define CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA Fld(1, 20) //[20:20] + #define CA_CMD2_RG_TX_ARCMD_OE_DIS_CA Fld(1, 21) //[21:21] + #define CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA Fld(1, 22) //[22:22] + #define CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA Fld(8, 24) //[31:24] + +#define DDRPHY_REG_CA_CMD3 (DDRPHY_AO_BASE_ADDRESS + 0x0480) + #define CA_CMD3_RG_ARCMD_ATPG_EN Fld(1, 0) //[0:0] + #define CA_CMD3_RG_RX_ARCMD_SMT_EN Fld(1, 1) //[1:1] + #define CA_CMD3_RG_TX_ARCMD_EN Fld(1, 2) //[2:2] + #define CA_CMD3_RG_ARCMD_RESETB Fld(1, 3) //[3:3] + #define CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN Fld(1, 5) //[5:5] + #define CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN Fld(1, 7) //[7:7] + #define CA_CMD3_RG_RX_ARCMD_STBENCMP_EN Fld(1, 10) //[10:10] + #define CA_CMD3_RG_RX_ARCMD_OFFC_EN Fld(1, 11) //[11:11] + #define CA_CMD3_RG_RX_ARCLK_SWAP_EN Fld(1, 15) //[15:15] + #define CA_CMD3_RG_ARPI_ASYNC_EN_CA Fld(1, 23) //[23:23] + #define CA_CMD3_RG_ARPI_LAT_EN_CA Fld(1, 24) //[24:24] + #define CA_CMD3_RG_ARPI_MCK_FB_SEL_CA Fld(2, 26) //[27:26] + +#define DDRPHY_REG_CA_CMD4 (DDRPHY_AO_BASE_ADDRESS + 0x0484) + #define CA_CMD4_RG_RX_ARCLK_EYE_R_DLY Fld(7, 0) //[6:0] + #define CA_CMD4_RG_RX_ARCLK_EYE_F_DLY Fld(7, 8) //[14:8] + #define CA_CMD4_RG_RX_ARCMD_EYE_R_DLY Fld(6, 16) //[21:16] + #define CA_CMD4_RG_RX_ARCMD_EYE_F_DLY Fld(6, 24) //[29:24] + +#define DDRPHY_REG_CA_CMD5 (DDRPHY_AO_BASE_ADDRESS + 0x0488) + #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL Fld(6, 8) //[13:8] + #define CA_CMD5_RG_RX_ARCMD_VREF_EN Fld(1, 16) //[16:16] + #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN Fld(1, 17) //[17:17] + #define CA_CMD5_RG_RX_ARCMD_EYE_SEL Fld(4, 20) //[23:20] + #define CA_CMD5_RG_RX_ARCMD_EYE_EN Fld(1, 24) //[24:24] + #define CA_CMD5_RG_RX_ARCMD_EYE_STBEN_RESETB Fld(1, 25) //[25:25] + #define CA_CMD5_RG_RX_ARCLK_DVS_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_CA_CMD6 (DDRPHY_AO_BASE_ADDRESS + 0x048C) + #define CA_CMD6_RG_RX_ARCMD_BIAS_PS Fld(2, 0) //[1:0] + #define CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS Fld(1, 2) //[2:2] + #define CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS Fld(1, 3) //[3:3] + #define CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN Fld(1, 5) //[5:5] + #define CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN Fld(1, 6) //[6:6] + #define CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN Fld(1, 7) //[7:7] + #define CA_CMD6_RG_RX_ARCMD_LPBK_EN Fld(1, 8) //[8:8] + #define CA_CMD6_RG_RX_ARCMD_O1_SEL Fld(1, 9) //[9:9] + #define CA_CMD6_RG_RX_ARCMD_JM_SEL Fld(1, 11) //[11:11] + #define CA_CMD6_RG_RX_ARCMD_BIAS_EN Fld(1, 12) //[12:12] + #define CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL Fld(2, 14) //[15:14] + #define CA_CMD6_RG_RX_ARCMD_DDR4_SEL Fld(1, 16) //[16:16] + #define CA_CMD6_RG_TX_ARCMD_DDR4_SEL Fld(1, 17) //[17:17] + #define CA_CMD6_RG_RX_ARCMD_DDR3_SEL Fld(1, 18) //[18:18] + #define CA_CMD6_RG_TX_ARCMD_DDR3_SEL Fld(1, 19) //[19:19] + #define CA_CMD6_RG_TX_ARCMD_LP5_SEL Fld(1, 20) //[20:20] + #define CA_CMD6_RG_TX_ARCMD_LP4_SEL Fld(1, 21) //[21:21] + #define CA_CMD6_RG_TX_ARCMD_CAP_EN Fld(1, 24) //[24:24] + #define CA_CMD6_RG_TX_ARCMD_DATA_SWAP_EN Fld(1, 25) //[25:25] + #define CA_CMD6_RG_TX_ARCMD_DATA_SWAP Fld(2, 26) //[27:26] + #define CA_CMD6_RG_RX_ARCMD_EYE_DLY_DQS_BYPASS Fld(1, 28) //[28:28] + #define CA_CMD6_RG_RX_ARCMD_EYE_OE_GATE_EN Fld(1, 29) //[29:29] + #define CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_CA_CMD7 (DDRPHY_AO_BASE_ADDRESS + 0x0490) + #define CA_CMD7_RG_TX_ARCLKB_PULL_DN Fld(1, 0) //[0:0] + #define CA_CMD7_RG_TX_ARCLKB_PULL_UP Fld(1, 1) //[1:1] + #define CA_CMD7_RG_TX_ARCLK_PULL_DN Fld(1, 2) //[2:2] + #define CA_CMD7_RG_TX_ARCLK_PULL_UP Fld(1, 3) //[3:3] + #define CA_CMD7_RG_TX_ARCS0_PULL_DN Fld(1, 4) //[4:4] + #define CA_CMD7_RG_TX_ARCS0_PULL_UP Fld(1, 5) //[5:5] + #define CA_CMD7_RG_TX_ARCMD_PULL_DN Fld(1, 6) //[6:6] + #define CA_CMD7_RG_TX_ARCMD_PULL_UP Fld(1, 7) //[7:7] + #define CA_CMD7_RG_TX_ARCS1_PULL_DN Fld(1, 8) //[8:8] + #define CA_CMD7_RG_TX_ARCS1_PULL_UP Fld(1, 9) //[9:9] + #define CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y Fld(1, 16) //[16:16] + +#define DDRPHY_REG_CA_CMD8 (DDRPHY_AO_BASE_ADDRESS + 0x0494) + #define CA_CMD8_RG_TX_ARCMD_EN_LP4P Fld(1, 0) //[0:0] + #define CA_CMD8_RG_TX_ARCMD_EN_CAP_LP4P Fld(1, 1) //[1:1] + #define CA_CMD8_RG_TX_ARCMD_CAP_DET Fld(1, 2) //[2:2] + #define CA_CMD8_RG_TX_ARCMD_CKE_MCK4X_SEL Fld(2, 3) //[4:3] + #define CA_CMD8_RG_RX_ARCLK_DQSIEN_BURST_E1_EN Fld(1, 8) //[8:8] + #define CA_CMD8_RG_RX_ARCLK_DQSIEN_BURST_E2_EN Fld(1, 9) //[9:9] + #define CA_CMD8_RG_RX_ARCLK_GATE_EN_MODE Fld(1, 12) //[12:12] + #define CA_CMD8_RG_RX_ARCLK_SER_RST_MODE Fld(1, 13) //[13:13] + #define CA_CMD8_RG_ARDLL_RESETB_CA Fld(1, 15) //[15:15] + #define CA_CMD8_RG_TX_ARCMD_LP3_CKE_SEL Fld(1, 16) //[16:16] + #define CA_CMD8_RG_TX_ARCMD_LP4_CKE_SEL Fld(1, 17) //[17:17] + #define CA_CMD8_RG_TX_ARCMD_LP4X_CKE_SEL Fld(1, 18) //[18:18] + #define CA_CMD8_RG_TX_ARCMD_LSH_DQM_CG_EN Fld(1, 20) //[20:20] + #define CA_CMD8_RG_TX_ARCMD_LSH_DQS_CG_EN Fld(1, 21) //[21:21] + #define CA_CMD8_RG_TX_ARCMD_LSH_DQ_CG_EN Fld(1, 22) //[22:22] + #define CA_CMD8_RG_TX_ARCMD_OE_SUS_EN Fld(1, 24) //[24:24] + #define CA_CMD8_RG_TX_ARCMD_ODTEN_OE_SUS_EN Fld(1, 25) //[25:25] + +#define DDRPHY_REG_CA_CMD9 (DDRPHY_AO_BASE_ADDRESS + 0x0498) + #define CA_CMD9_RG_RX_ARCMD_STBEN_RESETB Fld(1, 0) //[0:0] + #define CA_CMD9_RG_RX_ARCLK_STBEN_RESETB Fld(1, 4) //[4:4] + #define CA_CMD9_RG_RX_ARCLK_DQSIENMODE Fld(1, 5) //[5:5] + #define CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT Fld(1, 6) //[6:6] + #define CA_CMD9_R_DMRXFIFO_STBENCMP_EN_CA Fld(1, 7) //[7:7] + #define CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA Fld(8, 8) //[15:8] + #define CA_CMD9_R_DMDQSIEN_VALID_LAT_CA Fld(3, 16) //[18:16] + #define CA_CMD9_R_DMDQSIEN_RDSEL_LAT_CA Fld(3, 20) //[22:20] + #define CA_CMD9_R_DMRXDVS_VALID_LAT_CA Fld(3, 24) //[26:24] + #define CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA Fld(3, 28) //[30:28] + +#define DDRPHY_REG_CA_CMD10 (DDRPHY_AO_BASE_ADDRESS + 0x049C) + #define CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA Fld(1, 0) //[0:0] + +#define DDRPHY_REG_CA_CMD11 (DDRPHY_AO_BASE_ADDRESS + 0x04A0) + #define CA_CMD11_RG_RRESETB_DRVP Fld(5, 0) //[4:0] + #define CA_CMD11_RG_RRESETB_DRVN Fld(5, 8) //[12:8] + #define CA_CMD11_RG_RX_RRESETB_SMT_EN Fld(1, 16) //[16:16] + #define CA_CMD11_RG_TX_RRESETB_SCAN_IN_EN Fld(1, 17) //[17:17] + #define CA_CMD11_RG_TX_RRESETB_DDR4_SEL Fld(1, 18) //[18:18] + #define CA_CMD11_RG_TX_RRESETB_DDR3_SEL Fld(1, 19) //[19:19] + #define CA_CMD11_RG_TX_RRESETB_PULL_DN Fld(1, 20) //[20:20] + #define CA_CMD11_RG_TX_RRESETB_PULL_UP Fld(1, 21) //[21:21] + #define CA_CMD11_RG_RRESETB_OPEN_DRAIN_EN Fld(1, 22) //[22:22] + +#define DDRPHY_REG_CA_PHY2 (DDRPHY_AO_BASE_ADDRESS + 0x04A4) + #define CA_PHY2_RG_RX_ARCLK_SE_SWAP_EN_CA Fld(1, 0) //[0:0] + #define CA_PHY2_RG_RX_ARCLK_JM_SEL_CA Fld(4, 4) //[7:4] + #define CA_PHY2_RG_RX_ARCLK_JM_EN_CA Fld(1, 8) //[8:8] + #define CA_PHY2_RG_RX_ARCLK_JM_DLY_CA Fld(9, 16) //[24:16] + #define CA_PHY2_RG_RX_ARCLK_DQSIEN_UI_LEAD_LAG_EN_CA Fld(1, 28) //[28:28] + #define CA_PHY2_RG_RX_ARCLK_DQSIEN_TIE_GATE_EN_CA Fld(1, 29) //[29:29] + #define CA_PHY2_RG_RX_ARCLKB_SE_SWAP_EN_CA Fld(1, 30) //[30:30] + +#define DDRPHY_REG_CA_PHY3 (DDRPHY_AO_BASE_ADDRESS + 0x04A8) + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_VREF_SEL_CA Fld(7, 8) //[14:8] + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA Fld(4, 16) //[19:16] + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_EN_CA Fld(1, 20) //[20:20] + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_CLK_SEL_CA Fld(2, 24) //[25:24] + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_CLK_RC_SEL_CA Fld(2, 26) //[27:26] + #define CA_PHY3_RG_RX_ARCA_BUFF_EN_SEL_CA Fld(1, 28) //[28:28] + +#define DDRPHY_REG_CA_TX_MCK (DDRPHY_AO_BASE_ADDRESS + 0x04AC) + #define CA_TX_MCK_R_DMRESETB_DRVP_FRPHY Fld(5, 21) //[25:21] + #define CA_TX_MCK_R_DMRESETB_DRVN_FRPHY Fld(5, 26) //[30:26] + #define CA_TX_MCK_R_DMRESET_FRPHY_OPT Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_STBCAL (DDRPHY_AO_BASE_ADDRESS + 0x04E0) + #define MISC_STBCAL_PIMASK_RKCHG_OPT Fld(1, 0) //[0:0] + #define MISC_STBCAL_PIMASK_RKCHG_EXT Fld(3, 1) //[3:1] + #define MISC_STBCAL_STBDLELAST_OPT Fld(1, 4) //[4:4] + #define MISC_STBCAL_STBDLELAST_PULSE Fld(4, 8) //[11:8] + #define MISC_STBCAL_STBDLELAST_FILTER Fld(1, 12) //[12:12] + #define MISC_STBCAL_STBUPDSTOP Fld(1, 13) //[13:13] + #define MISC_STBCAL_CG_RKEN Fld(1, 14) //[14:14] + #define MISC_STBCAL_STBSTATE_OPT Fld(1, 15) //[15:15] + #define MISC_STBCAL_PHYVALID_IG Fld(1, 16) //[16:16] + #define MISC_STBCAL_SREF_DQSGUPD Fld(1, 17) //[17:17] + #define MISC_STBCAL_RKCHGMASKDIS Fld(1, 19) //[19:19] + #define MISC_STBCAL_PICGEN Fld(1, 20) //[20:20] + #define MISC_STBCAL_REFUICHG Fld(1, 21) //[21:21] + #define MISC_STBCAL_STBCAL2R Fld(1, 23) //[23:23] + #define MISC_STBCAL_STBDLYOUT_OPT Fld(1, 25) //[25:25] + #define MISC_STBCAL_PICHGBLOCK_NORD Fld(1, 26) //[26:26] + #define MISC_STBCAL_STB_DQIEN_IG Fld(1, 27) //[27:27] + #define MISC_STBCAL_DQSIENCG_CHG_EN Fld(1, 28) //[28:28] + #define MISC_STBCAL_DQSIENCG_NORMAL_EN Fld(1, 29) //[29:29] + #define MISC_STBCAL_DQSIENMODE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_STBCAL1 (DDRPHY_AO_BASE_ADDRESS + 0x04E4) + #define MISC_STBCAL1_STBCNT_SHU_RST_EN Fld(1, 0) //[0:0] + #define MISC_STBCAL1_RKUICHG_EN Fld(1, 1) //[1:1] + #define MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD Fld(1, 2) //[2:2] + #define MISC_STBCAL1_STBCNT_MODESEL Fld(1, 4) //[4:4] + #define MISC_STBCAL1_DQSIEN_7UI_EN Fld(1, 5) //[5:5] + #define MISC_STBCAL1_STB_SHIFT_DTCOUT_IG Fld(1, 6) //[6:6] + #define MISC_STBCAL1_STB_FLAGCLR_OPT Fld(1, 8) //[8:8] + #define MISC_STBCAL1_STB_DLLFRZ_IG Fld(1, 9) //[9:9] + #define MISC_STBCAL1_STBCNT_SW_RST Fld(1, 15) //[15:15] + #define MISC_STBCAL1_STBCAL_FILTER Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_STBCAL2 (DDRPHY_AO_BASE_ADDRESS + 0x04E8) + #define MISC_STBCAL2_STB_PIDLYCG_IG Fld(1, 0) //[0:0] + #define MISC_STBCAL2_STB_UIDLYCG_IG Fld(1, 1) //[1:1] + #define MISC_STBCAL2_STBENCMPEN Fld(1, 2) //[2:2] + #define MISC_STBCAL2_STB_DBG_EN Fld(4, 4) //[7:4] + #define MISC_STBCAL2_STB_DBG_CG_AO Fld(1, 8) //[8:8] + #define MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT Fld(1, 9) //[9:9] + #define MISC_STBCAL2_DQSGCNT_BYP_REF Fld(1, 10) //[10:10] + #define MISC_STBCAL2_STB_DRS_MASK_HW_SAVE Fld(1, 12) //[12:12] + #define MISC_STBCAL2_STB_DRS_RK1_FLAG_SYNC_RK0_EN Fld(1, 13) //[13:13] + #define MISC_STBCAL2_STB_PICG_EARLY_1T_EN Fld(1, 16) //[16:16] + #define MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN Fld(1, 17) //[17:17] + #define MISC_STBCAL2_STB_IG_XRANK_CG_RST Fld(1, 18) //[18:18] + #define MISC_STBCAL2_STB_RST_BY_RANK Fld(1, 19) //[19:19] + #define MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN Fld(1, 20) //[20:20] + #define MISC_STBCAL2_DQSG_CNT_EN Fld(1, 21) //[21:21] + #define MISC_STBCAL2_DQSG_CNT_RST Fld(1, 22) //[22:22] + #define MISC_STBCAL2_STB_DBG_STATUS Fld(4, 24) //[27:24] + #define MISC_STBCAL2_STB_GERRSTOP Fld(1, 28) //[28:28] + #define MISC_STBCAL2_STB_GERR_RST Fld(1, 29) //[29:29] + #define MISC_STBCAL2_STB_GERR_B01 Fld(1, 30) //[30:30] + #define MISC_STBCAL2_STB_GERR_B23 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CG_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x04EC) + #define MISC_CG_CTRL0_W_CHG_MEM Fld(1, 0) //[0:0] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1 Fld(3, 1) //[3:1] + #define MISC_CG_CTRL0_CLK_MEM_SEL Fld(2, 4) //[5:4] + #define MISC_CG_CTRL0_CLK_MEM_INV Fld(1, 6) //[6:6] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7 Fld(1, 7) //[7:7] + #define MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE Fld(1, 8) //[8:8] + #define MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE Fld(1, 9) //[9:9] + #define MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE Fld(1, 10) //[10:10] + #define MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE Fld(1, 11) //[11:11] + #define MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE Fld(1, 12) //[12:12] + #define MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE Fld(1, 13) //[13:13] + #define MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE Fld(1, 14) //[14:14] + #define MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE Fld(1, 15) //[15:15] + #define MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE Fld(1, 16) //[16:16] + #define MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE Fld(1, 17) //[17:17] + #define MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN Fld(1, 18) //[18:18] + #define MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE Fld(1, 19) //[19:19] + #define MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF Fld(1, 20) //[20:20] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT21 Fld(1, 21) //[21:21] + #define MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF Fld(1, 22) //[22:22] + #define MISC_CG_CTRL0_RG_DBG_OUT_SEL Fld(2, 23) //[24:23] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT27_25 Fld(3, 25) //[27:25] + #define MISC_CG_CTRL0_RG_DA_RREF_CK_SEL Fld(1, 28) //[28:28] + #define MISC_CG_CTRL0_RG_FREERUN_MCK_CG Fld(1, 29) //[29:29] + #define MISC_CG_CTRL0_RG_FREERUN_MCK_SEL Fld(1, 30) //[30:30] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT31 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CG_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x04F0) + #define MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CG_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x04F4) + #define MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG Fld(1, 0) //[0:0] + #define MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL Fld(5, 1) //[5:1] + #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON Fld(1, 6) //[6:6] + #define MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN Fld(1, 7) //[7:7] + #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN Fld(1, 8) //[8:8] + #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT Fld(7, 9) //[15:9] + #define MISC_CG_CTRL2_RG_MEM_DCM_FSEL Fld(5, 16) //[20:16] + #define MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL Fld(5, 21) //[25:21] + #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF Fld(1, 26) //[26:26] + #define MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27 Fld(1, 27) //[27:27] + #define MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE Fld(1, 28) //[28:28] + #define MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE Fld(1, 29) //[29:29] + #define MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30 Fld(1, 30) //[30:30] + #define MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CG_CTRL3 (DDRPHY_AO_BASE_ADDRESS + 0x04F8) + #define MISC_CG_CTRL3_R_LBK_CG_CTRL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CG_CTRL5 (DDRPHY_AO_BASE_ADDRESS + 0x0500) + #define MISC_CG_CTRL5_RESERVE Fld(16, 0) //[15:0] + #define MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN Fld(1, 16) //[16:16] + #define MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN Fld(1, 17) //[17:17] + #define MISC_CG_CTRL5_R_CA_DLY_DCM_EN Fld(1, 18) //[18:18] + #define MISC_CG_CTRL5_R_DQ1_PI_DCM_EN Fld(1, 20) //[20:20] + #define MISC_CG_CTRL5_R_DQ0_PI_DCM_EN Fld(1, 21) //[21:21] + #define MISC_CG_CTRL5_R_CA_PI_DCM_EN Fld(1, 22) //[22:22] + #define MISC_CG_CTRL5_R_PICG_MON_CLR Fld(1, 23) //[23:23] + #define MISC_CG_CTRL5_R_PICG_MON_EN Fld(1, 24) //[24:24] + +#define DDRPHY_REG_MISC_CG_CTRL7 (DDRPHY_AO_BASE_ADDRESS + 0x0504) + #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT3_0 Fld(4, 0) //[3:0] + #define MISC_CG_CTRL7_FMEM_CK_CG_PINMUX Fld(2, 4) //[5:4] + #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT10_6 Fld(5, 6) //[10:6] + #define MISC_CG_CTRL7_CK_BFE_DCM_EN Fld(1, 11) //[11:11] + #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT15_12 Fld(4, 12) //[15:12] + #define MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL Fld(1, 16) //[16:16] + #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT31_17 Fld(15, 17) //[31:17] + +#define DDRPHY_REG_MISC_CG_CTRL9 (DDRPHY_AO_BASE_ADDRESS + 0x0508) + #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT3_0 Fld(4, 0) //[3:0] + #define MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN Fld(1, 4) //[4:4] + #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT7_5 Fld(3, 5) //[7:5] + #define MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN Fld(1, 8) //[8:8] + #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF Fld(1, 9) //[9:9] + #define MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON Fld(1, 10) //[10:10] + #define MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF Fld(1, 11) //[11:11] + #define MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN Fld(1, 12) //[12:12] + #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF Fld(1, 13) //[13:13] + #define MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON Fld(1, 14) //[14:14] + #define MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF Fld(1, 15) //[15:15] + #define MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN Fld(1, 16) //[16:16] + #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF Fld(1, 17) //[17:17] + #define MISC_CG_CTRL9_RG_DDR400_MCK4X_O_FORCE_ON Fld(1, 18) //[18:18] + #define MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF Fld(1, 19) //[19:19] + #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT31_20 Fld(12, 20) //[31:20] + +#define DDRPHY_REG_MISC_CG_CTRL10 (DDRPHY_AO_BASE_ADDRESS + 0x050C) + #define MISC_CG_CTRL10_RESERVED_MISC_CG_CTRL10_BIT31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DVFSCTL (DDRPHY_AO_BASE_ADDRESS + 0x0510) + #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW Fld(4, 0) //[3:0] + #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW Fld(4, 4) //[7:4] + #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW Fld(4, 8) //[11:8] + #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW Fld(4, 12) //[15:12] + #define MISC_DVFSCTL_R_DVFS_MCK_CG_EN_FT_EN Fld(1, 16) //[16:16] + #define MISC_DVFSCTL_R_DVFS_MCK_CG_EN_FT_IN Fld(1, 17) //[17:17] + #define MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT Fld(1, 18) //[18:18] + #define MISC_DVFSCTL_R_NEW_SHU_MUX_SPM Fld(1, 19) //[19:19] + #define MISC_DVFSCTL_R_MPDIV_SHU_GP Fld(3, 20) //[22:20] + #define MISC_DVFSCTL_R_OTHER_SHU_GP Fld(2, 24) //[25:24] + #define MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE Fld(1, 26) //[26:26] + #define MISC_DVFSCTL_R_DVFS_PICG_POSTPONE Fld(1, 27) //[27:27] + #define MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_DVFSCTL2 (DDRPHY_AO_BASE_ADDRESS + 0x0514) + #define MISC_DVFSCTL2_DLL_LOCK_SHU_EN Fld(1, 0) //[0:0] + #define MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHA Fld(1, 1) //[1:1] + #define MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHB Fld(1, 2) //[2:2] + #define MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS Fld(1, 3) //[3:3] + #define MISC_DVFSCTL2_RG_DLL_SHUFFLE Fld(1, 4) //[4:4] + #define MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE Fld(1, 5) //[5:5] + #define MISC_DVFSCTL2_R_DVFS_DDRPHY_FSM_CLR Fld(1, 7) //[7:7] + #define MISC_DVFSCTL2_RG_MRW_AFTER_DFS Fld(1, 8) //[8:8] + #define MISC_DVFSCTL2_R_DVFS_CDC_OPTION Fld(1, 9) //[9:9] + #define MISC_DVFSCTL2_R_DVFS_PICG_MARGIN Fld(2, 10) //[11:10] + #define MISC_DVFSCTL2_R_DVFS_DLL_CHA Fld(1, 12) //[12:12] + #define MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION Fld(1, 13) //[13:13] + #define MISC_DVFSCTL2_R_DVFS_PARK_N Fld(1, 14) //[14:14] + #define MISC_DVFSCTL2_R_DVFS_OPTION Fld(1, 15) //[15:15] + #define MISC_DVFSCTL2_RG_PHY_ST_DELAY_BYPASS_CK_CHG_TO_MCLK Fld(1, 16) //[16:16] + #define MISC_DVFSCTL2_RG_PHY_ST_DELAY_BYPASS_CK_CHG_TO_BCLK Fld(1, 17) //[17:17] + #define MISC_DVFSCTL2_RG_PS_CLK_FREERUN Fld(1, 18) //[18:18] + #define MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY Fld(1, 19) //[19:19] + #define MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY Fld(1, 20) //[20:20] + #define MISC_DVFSCTL2_GTDMW_SYNC_MASK_FOR_PHY Fld(1, 21) //[21:21] + #define MISC_DVFSCTL2_R_DVFS_RG_CDC_TX_SEL Fld(1, 26) //[26:26] + #define MISC_DVFSCTL2_R_DVFS_RG_CDC_SYNC_ENABLE Fld(1, 27) //[27:27] + #define MISC_DVFSCTL2_R_SHU_RESTORE Fld(1, 28) //[28:28] + #define MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL Fld(1, 29) //[29:29] + #define MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DVFSCTL3 (DDRPHY_AO_BASE_ADDRESS + 0x0518) + #define MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN Fld(1, 0) //[0:0] + #define MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN Fld(1, 1) //[1:1] + #define MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN Fld(1, 2) //[2:2] + #define MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN Fld(1, 3) //[3:3] + #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK Fld(1, 4) //[4:4] + #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK Fld(1, 5) //[5:5] + #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK Fld(1, 6) //[6:6] + #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK Fld(1, 7) //[7:7] + #define MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI Fld(2, 8) //[9:8] + #define MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE Fld(2, 10) //[11:10] + #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK Fld(6, 12) //[17:12] + #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_MCLK Fld(4, 18) //[21:18] + #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK Fld(6, 22) //[27:22] + #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_CKMUX_SEL (DDRPHY_AO_BASE_ADDRESS + 0x051C) + #define MISC_CKMUX_SEL_R_PHYCTRLMUX Fld(1, 0) //[0:0] + #define MISC_CKMUX_SEL_R_PHYCTRLDCM Fld(1, 1) //[1:1] + #define MISC_CKMUX_SEL_R_DMMCTLPLL_CKSEL Fld(2, 4) //[5:4] + #define MISC_CKMUX_SEL_BCLK_SHU_SEL Fld(1, 8) //[8:8] + #define MISC_CKMUX_SEL_RG_52M_104M_SEL Fld(1, 12) //[12:12] + #define MISC_CKMUX_SEL_RG_104M_208M_SEL Fld(1, 13) //[13:13] + #define MISC_CKMUX_SEL_RG_FMEM_CK_OCC_FRC_EN Fld(1, 14) //[14:14] + #define MISC_CKMUX_SEL_RG_MEM_CLKMUX_REFCLK_SEL Fld(1, 15) //[15:15] + #define MISC_CKMUX_SEL_FB_CK_MUX Fld(2, 16) //[17:16] + #define MISC_CKMUX_SEL_FMEM_CK_MUX Fld(2, 18) //[19:18] + +#define DDRPHY_REG_MISC_CLK_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0520) + #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN Fld(1, 0) //[0:0] + #define MISC_CLK_CTRL_DVFS_CLK_MEM_SEL Fld(1, 1) //[1:1] + #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE Fld(1, 8) //[8:8] + #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL Fld(2, 9) //[10:9] + #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE Fld(2, 12) //[13:12] + #define MISC_CLK_CTRL_RESERVED_MISC_CLK_CTRL_BIT31_4 Fld(18, 14) //[31:14] + +#define DDRPHY_REG_MISC_DQSG_RETRY1 (DDRPHY_AO_BASE_ADDRESS + 0x0524) + #define MISC_DQSG_RETRY1_R_RETRY_SAV_MSK Fld(1, 24) //[24:24] + #define MISC_DQSG_RETRY1_RETRY_DEBUG_RANK_SEL Fld(2, 28) //[29:28] + #define MISC_DQSG_RETRY1_RETRY_DEBUG_BYTE_SEL Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_RDSEL_TRACK (DDRPHY_AO_BASE_ADDRESS + 0x0528) + #define MISC_RDSEL_TRACK_RDSEL_SW_RST Fld(1, 0) //[0:0] + +#define DDRPHY_REG_MISC_PRE_TDQSCK1 (DDRPHY_AO_BASE_ADDRESS + 0x052C) + #define MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL Fld(1, 22) //[22:22] + #define MISC_PRE_TDQSCK1_TDQSCK_SW_UP_CASE Fld(1, 23) //[23:23] + #define MISC_PRE_TDQSCK1_TDQSCK_SW_SAVE Fld(1, 24) //[24:24] + #define MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS Fld(1, 25) //[25:25] + #define MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW Fld(1, 26) //[26:26] + #define MISC_PRE_TDQSCK1_TDQSCK_PRECAL_START Fld(1, 27) //[27:27] + +#define DDRPHY_REG_MISC_CDC_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0530) + #define MISC_CDC_CTRL_RESERVED_MISC_CDC_CTRL_30_0 Fld(31, 0) //[30:0] + #define MISC_CDC_CTRL_REG_CDC_BYPASS_DBG Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_LP_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0534) + #define MISC_LP_CTRL_RG_ARDMSUS_10 Fld(1, 0) //[0:0] + #define MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL Fld(1, 1) //[1:1] + #define MISC_LP_CTRL_RG_RIMP_DMSUS_10 Fld(1, 2) //[2:2] + #define MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL Fld(1, 3) //[3:3] + #define MISC_LP_CTRL_RG_RRESETB_LP_SEL Fld(1, 4) //[4:4] + #define MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL Fld(1, 5) //[5:5] + #define MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL Fld(1, 6) //[6:6] + #define MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL Fld(1, 7) //[7:7] + #define MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL Fld(1, 8) //[8:8] + #define MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL Fld(1, 9) //[9:9] + #define MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL Fld(1, 10) //[10:10] + #define MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL Fld(1, 11) //[11:11] + #define MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL Fld(1, 12) //[12:12] + #define MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL Fld(1, 13) //[13:13] + #define MISC_LP_CTRL_RG_ADA_MCK8X_OP_LP_SEL Fld(1, 14) //[14:14] + #define MISC_LP_CTRL_RG_AD_MCK8X_OP_LP_SEL Fld(1, 15) //[15:15] + #define MISC_LP_CTRL_RG_RPHYPLL_DDR400_EN_LP_SEL Fld(1, 16) //[16:16] + #define MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL Fld(1, 17) //[17:17] + #define MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL Fld(1, 18) //[18:18] + #define MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL Fld(1, 19) //[19:19] + #define MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL Fld(1, 20) //[20:20] + #define MISC_LP_CTRL_RG_TX_RESETB_CTRL_OPT Fld(1, 21) //[21:21] + #define MISC_LP_CTRL_RESERVED_MISC_LP_CTRL_31_20 Fld(10, 22) //[31:22] + +#define DDRPHY_REG_MISC_RG_DFS_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0538) + #define MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL Fld(1, 0) //[0:0] + #define MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS Fld(1, 1) //[1:1] + #define MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN Fld(1, 2) //[2:2] + #define MISC_RG_DFS_CTRL_RG_DPY_PRECAL_UP Fld(1, 3) //[3:3] + #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM Fld(4, 4) //[7:4] + #define MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE Fld(1, 8) //[8:8] + #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH Fld(1, 9) //[9:9] + #define MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD Fld(1, 10) //[10:10] + #define MISC_RG_DFS_CTRL_RESERVED_MISC_RG_DFS_CTRL_11_11 Fld(1, 11) //[11:11] + #define MISC_RG_DFS_CTRL_RG_DPHY_RESERVED Fld(4, 12) //[15:12] + #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL Fld(2, 16) //[17:16] + #define MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN Fld(1, 18) //[18:18] + #define MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN Fld(1, 19) //[19:19] + #define MISC_RG_DFS_CTRL_RG_PHYPLL_MODE_SW Fld(1, 20) //[20:20] + #define MISC_RG_DFS_CTRL_RG_PHYPLL2_MODE_SW Fld(1, 21) //[21:21] + #define MISC_RG_DFS_CTRL_RG_DR_SHORT_QUEUE Fld(1, 22) //[22:22] + #define MISC_RG_DFS_CTRL_RG_DR_SHU_EN Fld(1, 23) //[23:23] + #define MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN Fld(1, 24) //[24:24] + #define MISC_RG_DFS_CTRL_RG_TX_TRACKING_RETRY_EN Fld(1, 25) //[25:25] + #define MISC_RG_DFS_CTRL_RG_RX_GATING_RETRY_EN Fld(1, 26) //[26:26] + #define MISC_RG_DFS_CTRL_RESERVED_MISC_RG_DFS_CTRL_31_27 Fld(5, 27) //[31:27] + +#define DDRPHY_REG_MISC_DDR_RESERVE (DDRPHY_AO_BASE_ADDRESS + 0x053C) + #define MISC_DDR_RESERVE_WDT_CONF_ISO_CNT Fld(8, 0) //[7:0] + #define MISC_DDR_RESERVE_WDT_ISO_CNT Fld(8, 8) //[15:8] + #define MISC_DDR_RESERVE_WDT_SREF_CNT Fld(8, 16) //[23:16] + #define MISC_DDR_RESERVE_WDT_SM_CLR Fld(1, 24) //[24:24] + #define MISC_DDR_RESERVE_WDT_LITE_EN Fld(1, 25) //[25:25] + +#define DDRPHY_REG_MISC_IMP_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x0540) + #define MISC_IMP_CTRL1_RG_IMP_OCD_PUCMP_EN Fld(1, 0) //[0:0] + #define MISC_IMP_CTRL1_RG_IMP_EN Fld(1, 1) //[1:1] + #define MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL Fld(1, 2) //[2:2] + #define MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL Fld(1, 3) //[3:3] + #define MISC_IMP_CTRL1_RG_RIMP_BIAS_EN Fld(1, 4) //[4:4] + #define MISC_IMP_CTRL1_RG_RIMP_ODT_EN Fld(1, 5) //[5:5] + #define MISC_IMP_CTRL1_RG_RIMP_PRE_EN Fld(1, 6) //[6:6] + #define MISC_IMP_CTRL1_RG_RIMP_VREF_EN Fld(1, 7) //[7:7] + #define MISC_IMP_CTRL1_IMP_DIFF_THD Fld(5, 8) //[12:8] + #define MISC_IMP_CTRL1_IMP_ABN_LAT_CLR Fld(1, 14) //[14:14] + #define MISC_IMP_CTRL1_IMP_ABN_LAT_EN Fld(1, 15) //[15:15] + #define MISC_IMP_CTRL1_IMP_ABN_PRD Fld(12, 16) //[27:16] + #define MISC_IMP_CTRL1_IMP_CG_EN Fld(1, 30) //[30:30] + #define MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_IMPCAL (DDRPHY_AO_BASE_ADDRESS + 0x0544) + #define MISC_IMPCAL_DRVCGWREF Fld(1, 2) //[2:2] + #define MISC_IMPCAL_DQDRVSWUPD Fld(1, 3) //[3:3] + #define MISC_IMPCAL_IMPSRCEXT Fld(1, 4) //[4:4] + #define MISC_IMPCAL_IMPBINARY Fld(1, 5) //[5:5] + #define MISC_IMPCAL_DRV_ECO_OPT Fld(1, 10) //[10:10] + #define MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT Fld(1, 11) //[11:11] + #define MISC_IMPCAL_IMPCAL_SM_ECO_OPT Fld(1, 12) //[12:12] + #define MISC_IMPCAL_IMPCAL_ECO_OPT Fld(1, 13) //[13:13] + #define MISC_IMPCAL_DIS_SUS_CH1_DRV Fld(1, 14) //[14:14] + #define MISC_IMPCAL_DIS_SUS_CH0_DRV Fld(1, 15) //[15:15] + #define MISC_IMPCAL_DIS_SHU_DRV Fld(1, 16) //[16:16] + #define MISC_IMPCAL_IMPCAL_DRVUPDOPT Fld(1, 17) //[17:17] + #define MISC_IMPCAL_IMPCAL_USING_SYNC Fld(1, 18) //[18:18] + #define MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV Fld(1, 19) //[19:19] + #define MISC_IMPCAL_IMPCAL_HWSAVE_EN Fld(1, 20) //[20:20] + #define MISC_IMPCAL_IMPCAL_CALI_ENN Fld(1, 21) //[21:21] + #define MISC_IMPCAL_IMPCAL_CALI_ENP Fld(1, 22) //[22:22] + #define MISC_IMPCAL_IMPCAL_CALI_EN Fld(1, 23) //[23:23] + #define MISC_IMPCAL_IMPCAL_IMPPDN Fld(1, 24) //[24:24] + #define MISC_IMPCAL_IMPCAL_IMPPDP Fld(1, 25) //[25:25] + #define MISC_IMPCAL_IMPCAL_NEW_OLD_SL Fld(1, 26) //[26:26] + #define MISC_IMPCAL_IMPCAL_CMP_DIREC Fld(2, 27) //[28:27] + #define MISC_IMPCAL_IMPCAL_SWVALUE_EN Fld(1, 29) //[29:29] + #define MISC_IMPCAL_IMPCAL_EN Fld(1, 30) //[30:30] + #define MISC_IMPCAL_IMPCAL_HW Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_IMPCAL1 (DDRPHY_AO_BASE_ADDRESS + 0x0548) + #define MISC_IMPCAL1_IMPCAL_RSV Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x054C) + #define MISC_IMPEDAMCE_CTRL1_DQS1_OFF Fld(10, 0) //[9:0] + #define MISC_IMPEDAMCE_CTRL1_DOS2_OFF Fld(10, 10) //[19:10] + #define MISC_IMPEDAMCE_CTRL1_DQS1_OFF_SUB Fld(2, 28) //[29:28] + #define MISC_IMPEDAMCE_CTRL1_DQS2_OFF_SUB Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x0550) + #define MISC_IMPEDAMCE_CTRL2_DQ1_OFF Fld(10, 0) //[9:0] + #define MISC_IMPEDAMCE_CTRL2_DQ2_OFF Fld(10, 10) //[19:10] + #define MISC_IMPEDAMCE_CTRL2_DQ1_OFF_SUB Fld(2, 28) //[29:28] + #define MISC_IMPEDAMCE_CTRL2_DQ2_OFF_SUB Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL3 (DDRPHY_AO_BASE_ADDRESS + 0x0554) + #define MISC_IMPEDAMCE_CTRL3_CMD1_OFF Fld(10, 0) //[9:0] + #define MISC_IMPEDAMCE_CTRL3_CMD2_OFF Fld(10, 10) //[19:10] + #define MISC_IMPEDAMCE_CTRL3_CMD1_OFF_SUB Fld(2, 28) //[29:28] + #define MISC_IMPEDAMCE_CTRL3_CMD2_OFF_SUB Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL4 (DDRPHY_AO_BASE_ADDRESS + 0x0558) + #define MISC_IMPEDAMCE_CTRL4_DQC1_OFF Fld(10, 0) //[9:0] + #define MISC_IMPEDAMCE_CTRL4_DQC2_OFF Fld(10, 10) //[19:10] + #define MISC_IMPEDAMCE_CTRL4_DQC1_OFF_SUB Fld(2, 28) //[29:28] + #define MISC_IMPEDAMCE_CTRL4_DQC2_OFF_SUB Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_PERIPHER_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x055C) + #define MISC_PERIPHER_CTRL2_APB_WRITE_MASK_EN Fld(1, 0) //[0:0] + #define MISC_PERIPHER_CTRL2_R_SW_RXFIFO_RDSEL_BUS Fld(4, 27) //[30:27] + #define MISC_PERIPHER_CTRL2_R_SW_RXFIFO_RDSEL_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_APB (DDRPHY_AO_BASE_ADDRESS + 0x0560) + #define MISC_APB_APB_ARB_SW_KEEP Fld(1, 30) //[30:30] + #define MISC_APB_SRAM_ARB_SW_KEEP Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_EXTLB0 (DDRPHY_AO_BASE_ADDRESS + 0x0564) + #define MISC_EXTLB0_EXTLB_LFSR_INI_1 Fld(16, 16) //[31:16] + #define MISC_EXTLB0_EXTLB_LFSR_INI_0 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB1 (DDRPHY_AO_BASE_ADDRESS + 0x0568) + #define MISC_EXTLB1_EXTLB_LFSR_INI_3 Fld(16, 16) //[31:16] + #define MISC_EXTLB1_EXTLB_LFSR_INI_2 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB2 (DDRPHY_AO_BASE_ADDRESS + 0x056C) + #define MISC_EXTLB2_EXTLB_LFSR_INI_5 Fld(16, 16) //[31:16] + #define MISC_EXTLB2_EXTLB_LFSR_INI_4 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB3 (DDRPHY_AO_BASE_ADDRESS + 0x0570) + #define MISC_EXTLB3_EXTLB_LFSR_INI_7 Fld(16, 16) //[31:16] + #define MISC_EXTLB3_EXTLB_LFSR_INI_6 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB4 (DDRPHY_AO_BASE_ADDRESS + 0x0574) + #define MISC_EXTLB4_EXTLB_LFSR_INI_9 Fld(16, 16) //[31:16] + #define MISC_EXTLB4_EXTLB_LFSR_INI_8 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB5 (DDRPHY_AO_BASE_ADDRESS + 0x0578) + #define MISC_EXTLB5_EXTLB_LFSR_INI_11 Fld(16, 16) //[31:16] + #define MISC_EXTLB5_EXTLB_LFSR_INI_10 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB6 (DDRPHY_AO_BASE_ADDRESS + 0x057C) + #define MISC_EXTLB6_EXTLB_LFSR_INI_13 Fld(16, 16) //[31:16] + #define MISC_EXTLB6_EXTLB_LFSR_INI_12 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB7 (DDRPHY_AO_BASE_ADDRESS + 0x0580) + #define MISC_EXTLB7_EXTLB_LFSR_INI_15 Fld(16, 16) //[31:16] + #define MISC_EXTLB7_EXTLB_LFSR_INI_14 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB8 (DDRPHY_AO_BASE_ADDRESS + 0x0584) + #define MISC_EXTLB8_EXTLB_LFSR_INI_17 Fld(16, 16) //[31:16] + #define MISC_EXTLB8_EXTLB_LFSR_INI_16 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB9 (DDRPHY_AO_BASE_ADDRESS + 0x0588) + #define MISC_EXTLB9_EXTLB_LFSR_INI_19 Fld(16, 16) //[31:16] + #define MISC_EXTLB9_EXTLB_LFSR_INI_18 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB10 (DDRPHY_AO_BASE_ADDRESS + 0x058C) + #define MISC_EXTLB10_EXTLB_LFSR_INI_21 Fld(16, 16) //[31:16] + #define MISC_EXTLB10_EXTLB_LFSR_INI_20 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB11 (DDRPHY_AO_BASE_ADDRESS + 0x0590) + #define MISC_EXTLB11_EXTLB_LFSR_INI_23 Fld(16, 16) //[31:16] + #define MISC_EXTLB11_EXTLB_LFSR_INI_22 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB12 (DDRPHY_AO_BASE_ADDRESS + 0x0594) + #define MISC_EXTLB12_EXTLB_LFSR_INI_25 Fld(16, 16) //[31:16] + #define MISC_EXTLB12_EXTLB_LFSR_INI_24 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB13 (DDRPHY_AO_BASE_ADDRESS + 0x0598) + #define MISC_EXTLB13_EXTLB_LFSR_INI_27 Fld(16, 16) //[31:16] + #define MISC_EXTLB13_EXTLB_LFSR_INI_26 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB14 (DDRPHY_AO_BASE_ADDRESS + 0x059C) + #define MISC_EXTLB14_EXTLB_LFSR_INI_29 Fld(16, 16) //[31:16] + #define MISC_EXTLB14_EXTLB_LFSR_INI_28 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB15 (DDRPHY_AO_BASE_ADDRESS + 0x05A0) + #define MISC_EXTLB15_EXTLB_LFSR_INI_30 Fld(16, 0) //[15:0] + #define MISC_EXTLB15_EXTLB_LFSR_INI_31 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EXTLB16 (DDRPHY_AO_BASE_ADDRESS + 0x05A4) + #define MISC_EXTLB16_EXTLB_ODTEN_DQS1_ON Fld(1, 27) //[27:27] + #define MISC_EXTLB16_EXTLB_ODTEN_DQM1_ON Fld(1, 26) //[26:26] + #define MISC_EXTLB16_EXTLB_ODTEN_DQB1_ON Fld(1, 25) //[25:25] + #define MISC_EXTLB16_EXTLB_ODTEN_DQS0_ON Fld(1, 24) //[24:24] + #define MISC_EXTLB16_EXTLB_ODTEN_DQM0_ON Fld(1, 23) //[23:23] + #define MISC_EXTLB16_EXTLB_ODTEN_DQB0_ON Fld(1, 22) //[22:22] + #define MISC_EXTLB16_EXTLB_OE_DQS1_ON Fld(1, 21) //[21:21] + #define MISC_EXTLB16_EXTLB_OE_DQM1_ON Fld(1, 20) //[20:20] + #define MISC_EXTLB16_EXTLB_OE_DQB1_ON Fld(1, 19) //[19:19] + #define MISC_EXTLB16_EXTLB_OE_DQS0_ON Fld(1, 18) //[18:18] + #define MISC_EXTLB16_EXTLB_OE_DQM0_ON Fld(1, 17) //[17:17] + #define MISC_EXTLB16_EXTLB_OE_DQB0_ON Fld(1, 16) //[16:16] + #define MISC_EXTLB16_EXTLB_LFSR_TAP Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB17 (DDRPHY_AO_BASE_ADDRESS + 0x05A8) + #define MISC_EXTLB17_EXTLB_RX_LENGTH_M1 Fld(24, 8) //[31:8] + #define MISC_EXTLB17_EXTLB_TX_PRE_ON Fld(1, 7) //[7:7] + #define MISC_EXTLB17_INTLB_DRDF_CA_MUXSEL Fld(1, 5) //[5:5] + #define MISC_EXTLB17_INTLB_ARCLK_MUXSEL Fld(1, 4) //[4:4] + #define MISC_EXTLB17_EXTLB_TX_EN_OTHERCH_SEL Fld(1, 3) //[3:3] + #define MISC_EXTLB17_EXTLB_TX_EN Fld(1, 2) //[2:2] + #define MISC_EXTLB17_EXTLB_RX_SWRST Fld(1, 1) //[1:1] + #define MISC_EXTLB17_EXTLB Fld(1, 0) //[0:0] + +#define DDRPHY_REG_MISC_EXTLB18 (DDRPHY_AO_BASE_ADDRESS + 0x05AC) + #define MISC_EXTLB18_TX_EN_SRC_SEL Fld(1, 0) //[0:0] + #define MISC_EXTLB18_OTH_TX_EN_SRC_SEL Fld(1, 1) //[1:1] + #define MISC_EXTLB18_LPBK_DQ_MODE_FOCA Fld(1, 3) //[3:3] + #define MISC_EXTLB18_LPBK_DQ_TX_MODE Fld(1, 4) //[4:4] + #define MISC_EXTLB18_LPBK_CA_TX_MODE Fld(1, 5) //[5:5] + #define MISC_EXTLB18_LPBK_DQ_RX_MODE Fld(1, 8) //[8:8] + #define MISC_EXTLB18_LPBK_CA_RX_MODE Fld(1, 9) //[9:9] + #define MISC_EXTLB18_TX_TRIG_SRC_SEL Fld(4, 16) //[19:16] + #define MISC_EXTLB18_OTH_TX_TRIG_SRC_SEL Fld(4, 20) //[23:20] + +#define DDRPHY_REG_MISC_EXTLB19 (DDRPHY_AO_BASE_ADDRESS + 0x05B0) + #define MISC_EXTLB19_EXTLB_LFSR_ENABLE Fld(1, 0) //[0:0] + #define MISC_EXTLB19_EXTLB_SSO_ENABLE Fld(1, 1) //[1:1] + #define MISC_EXTLB19_EXTLB_XTALK_ENABLE Fld(1, 2) //[2:2] + #define MISC_EXTLB19_EXTLB_LEADLAG_DBG_ENABLE Fld(1, 3) //[3:3] + #define MISC_EXTLB19_EXTLB_DBG_SEL Fld(5, 16) //[20:16] + #define MISC_EXTLB19_EXTLB_LFSR_EXTEND_INV Fld(1, 21) //[21:21] + #define MISC_EXTLB19_LPBK_DC_TOG_MODE Fld(1, 23) //[23:23] + #define MISC_EXTLB19_LPBK_DC_TOG_TIMER Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_EXTLB20 (DDRPHY_AO_BASE_ADDRESS + 0x05B4) + #define MISC_EXTLB20_XTALK_TX_00_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB20_XTALK_TX_01_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB20_XTALK_TX_02_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB20_XTALK_TX_03_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB20_XTALK_TX_04_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB20_XTALK_TX_05_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB20_XTALK_TX_06_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB20_XTALK_TX_07_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB21 (DDRPHY_AO_BASE_ADDRESS + 0x05B8) + #define MISC_EXTLB21_XTALK_TX_08_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB21_XTALK_TX_09_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB21_XTALK_TX_10_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB21_XTALK_TX_11_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB21_XTALK_TX_12_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB21_XTALK_TX_13_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB21_XTALK_TX_14_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB21_XTALK_TX_15_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB22 (DDRPHY_AO_BASE_ADDRESS + 0x05BC) + #define MISC_EXTLB22_XTALK_TX_16_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB22_XTALK_TX_17_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB22_XTALK_TX_18_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB22_XTALK_TX_19_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB22_XTALK_TX_20_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB22_XTALK_TX_21_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB22_XTALK_TX_22_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB22_XTALK_TX_23_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB23 (DDRPHY_AO_BASE_ADDRESS + 0x05C0) + #define MISC_EXTLB23_XTALK_TX_24_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB23_XTALK_TX_25_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB23_XTALK_TX_26_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB23_XTALK_TX_27_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB23_XTALK_TX_28_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB23_XTALK_TX_29_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB23_XTALK_TX_30_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB23_XTALK_TX_31_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB_RX0 (DDRPHY_AO_BASE_ADDRESS + 0x05C4) + #define MISC_EXTLB_RX0_EXTLB_LFSR_RX_INI_1 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX0_EXTLB_LFSR_RX_INI_0 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX1 (DDRPHY_AO_BASE_ADDRESS + 0x05C8) + #define MISC_EXTLB_RX1_EXTLB_LFSR_RX_INI_3 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX1_EXTLB_LFSR_RX_INI_2 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX2 (DDRPHY_AO_BASE_ADDRESS + 0x05CC) + #define MISC_EXTLB_RX2_EXTLB_LFSR_RX_INI_5 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX2_EXTLB_LFSR_RX_INI_4 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX3 (DDRPHY_AO_BASE_ADDRESS + 0x05D0) + #define MISC_EXTLB_RX3_EXTLB_LFSR_RX_INI_7 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX3_EXTLB_LFSR_RX_INI_6 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX4 (DDRPHY_AO_BASE_ADDRESS + 0x05D4) + #define MISC_EXTLB_RX4_EXTLB_LFSR_RX_INI_9 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX4_EXTLB_LFSR_RX_INI_8 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX5 (DDRPHY_AO_BASE_ADDRESS + 0x05D8) + #define MISC_EXTLB_RX5_EXTLB_LFSR_RX_INI_11 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX5_EXTLB_LFSR_RX_INI_10 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX6 (DDRPHY_AO_BASE_ADDRESS + 0x05DC) + #define MISC_EXTLB_RX6_EXTLB_LFSR_RX_INI_13 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX6_EXTLB_LFSR_RX_INI_12 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX7 (DDRPHY_AO_BASE_ADDRESS + 0x05E0) + #define MISC_EXTLB_RX7_EXTLB_LFSR_RX_INI_15 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX7_EXTLB_LFSR_RX_INI_14 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX8 (DDRPHY_AO_BASE_ADDRESS + 0x05E4) + #define MISC_EXTLB_RX8_EXTLB_LFSR_RX_INI_17 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX8_EXTLB_LFSR_RX_INI_16 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX9 (DDRPHY_AO_BASE_ADDRESS + 0x05E8) + #define MISC_EXTLB_RX9_EXTLB_LFSR_RX_INI_19 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX9_EXTLB_LFSR_RX_INI_18 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX10 (DDRPHY_AO_BASE_ADDRESS + 0x05EC) + #define MISC_EXTLB_RX10_EXTLB_LFSR_RX_INI_21 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX10_EXTLB_LFSR_RX_INI_20 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX11 (DDRPHY_AO_BASE_ADDRESS + 0x05F0) + #define MISC_EXTLB_RX11_EXTLB_LFSR_RX_INI_23 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX11_EXTLB_LFSR_RX_INI_22 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX12 (DDRPHY_AO_BASE_ADDRESS + 0x05F4) + #define MISC_EXTLB_RX12_EXTLB_LFSR_RX_INI_25 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX12_EXTLB_LFSR_RX_INI_24 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX13 (DDRPHY_AO_BASE_ADDRESS + 0x05F8) + #define MISC_EXTLB_RX13_EXTLB_LFSR_RX_INI_27 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX13_EXTLB_LFSR_RX_INI_26 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX14 (DDRPHY_AO_BASE_ADDRESS + 0x05FC) + #define MISC_EXTLB_RX14_EXTLB_LFSR_RX_INI_29 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX14_EXTLB_LFSR_RX_INI_28 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX15 (DDRPHY_AO_BASE_ADDRESS + 0x0600) + #define MISC_EXTLB_RX15_EXTLB_LFSR_RX_INI_30 Fld(16, 0) //[15:0] + #define MISC_EXTLB_RX15_EXTLB_LFSR_RX_INI_31 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EXTLB_RX16 (DDRPHY_AO_BASE_ADDRESS + 0x0604) + #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_DQB0 Fld(7, 0) //[6:0] + #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_DQB1 Fld(7, 8) //[14:8] + #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_CA Fld(7, 16) //[22:16] + +#define DDRPHY_REG_MISC_EXTLB_RX17 (DDRPHY_AO_BASE_ADDRESS + 0x0608) + #define MISC_EXTLB_RX17_XTALK_RX_00_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB_RX17_XTALK_RX_01_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB_RX17_XTALK_RX_02_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB_RX17_XTALK_RX_03_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB_RX17_XTALK_RX_04_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB_RX17_XTALK_RX_05_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB_RX17_XTALK_RX_06_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB_RX17_XTALK_RX_07_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB_RX18 (DDRPHY_AO_BASE_ADDRESS + 0x060C) + #define MISC_EXTLB_RX18_XTALK_RX_08_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB_RX18_XTALK_RX_09_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB_RX18_XTALK_RX_10_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB_RX18_XTALK_RX_11_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB_RX18_XTALK_RX_12_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB_RX18_XTALK_RX_13_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB_RX18_XTALK_RX_14_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB_RX18_XTALK_RX_15_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB_RX19 (DDRPHY_AO_BASE_ADDRESS + 0x0610) + #define MISC_EXTLB_RX19_XTALK_RX_16_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB_RX19_XTALK_RX_17_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB_RX19_XTALK_RX_18_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB_RX19_XTALK_RX_19_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB_RX19_XTALK_RX_20_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB_RX19_XTALK_RX_21_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB_RX19_XTALK_RX_22_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB_RX19_XTALK_RX_23_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB_RX20 (DDRPHY_AO_BASE_ADDRESS + 0x0614) + #define MISC_EXTLB_RX20_XTALK_RX_24_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB_RX20_XTALK_RX_25_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB_RX20_XTALK_RX_26_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB_RX20_XTALK_RX_27_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB_RX20_XTALK_RX_28_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB_RX20_XTALK_RX_29_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB_RX20_XTALK_RX_30_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB_RX20_XTALK_RX_31_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_SRAM_DMA0 (DDRPHY_AO_BASE_ADDRESS + 0x0618) + #define MISC_SRAM_DMA0_SW_DMA_FIRE Fld(1, 0) //[0:0] + #define MISC_SRAM_DMA0_SW_MODE Fld(1, 1) //[1:1] + #define MISC_SRAM_DMA0_APB_WR_MODE Fld(1, 2) //[2:2] + #define MISC_SRAM_DMA0_SRAM_WR_MODE Fld(1, 3) //[3:3] + #define MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM Fld(4, 4) //[7:4] + #define MISC_SRAM_DMA0_SW_SHU_LEVEL_APB Fld(4, 8) //[11:8] + #define MISC_SRAM_DMA0_PENABLE_LAT_RD Fld(2, 12) //[13:12] + #define MISC_SRAM_DMA0_PENABLE_LAT_WR Fld(2, 14) //[15:14] + #define MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA Fld(1, 16) //[16:16] + #define MISC_SRAM_DMA0_KEEP_APB_ARB_ENA Fld(1, 17) //[17:17] + #define MISC_SRAM_DMA0_DMA_TIMER_EN Fld(1, 18) //[18:18] + #define MISC_SRAM_DMA0_EARLY_ACK_ENA Fld(1, 20) //[20:20] + #define MISC_SRAM_DMA0_SPM_CTR_APB_LEVEL Fld(1, 21) //[21:21] + #define MISC_SRAM_DMA0_SPM_CTR_RESTORE Fld(1, 22) //[22:22] + #define MISC_SRAM_DMA0_SW_STEP_EN_MODE Fld(1, 23) //[23:23] + #define MISC_SRAM_DMA0_DMA_CLK_FORCE_ON Fld(1, 24) //[24:24] + #define MISC_SRAM_DMA0_DMA_CLK_FORCE_OFF Fld(1, 25) //[25:25] + #define MISC_SRAM_DMA0_APB_SLV_SEL Fld(2, 28) //[29:28] + +#define DDRPHY_REG_MISC_SRAM_DMA1 (DDRPHY_AO_BASE_ADDRESS + 0x061C) + #define MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN Fld(17, 0) //[16:0] + #define MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS Fld(1, 19) //[19:19] + #define MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL Fld(4, 20) //[23:20] + #define MISC_SRAM_DMA1_PLL_REG_LENGTH Fld(7, 24) //[30:24] + +#define DDRPHY_REG_MISC_SRAM_DMA2 (DDRPHY_AO_BASE_ADDRESS + 0x0620) + #define MISC_SRAM_DMA2_SW_DMA_STEP_EN Fld(17, 0) //[16:0] + +#define DDRPHY_REG_MISC_DUTYSCAN1 (DDRPHY_AO_BASE_ADDRESS + 0x0624) + #define MISC_DUTYSCAN1_REG_SW_RST Fld(1, 0) //[0:0] + #define MISC_DUTYSCAN1_RX_EYE_SCAN_EN Fld(1, 1) //[1:1] + #define MISC_DUTYSCAN1_RX_MIOCK_JIT_EN Fld(1, 2) //[2:2] + #define MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN Fld(1, 3) //[3:3] + #define MISC_DUTYSCAN1_EYESCAN_RD_SEL_OPT Fld(1, 4) //[4:4] + #define MISC_DUTYSCAN1_DMDQ4BMUX Fld(1, 5) //[5:5] + #define MISC_DUTYSCAN1_EYESCAN_CHK_OPT Fld(1, 6) //[6:6] + #define MISC_DUTYSCAN1_EYESCAN_TOG_OPT Fld(1, 7) //[7:7] + #define MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN Fld(1, 8) //[8:8] + #define MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN Fld(1, 9) //[9:9] + #define MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN Fld(1, 10) //[10:10] + #define MISC_DUTYSCAN1_EYESCAN_DQS_OPT Fld(1, 11) //[11:11] + #define MISC_DUTYSCAN1_DCBLNCEN Fld(1, 12) //[12:12] + #define MISC_DUTYSCAN1_DCBLNCINS Fld(1, 13) //[13:13] + #define MISC_DUTYSCAN1_DQSERRCNT_DIS Fld(1, 14) //[14:14] + #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL Fld(4, 16) //[19:16] + #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B1 Fld(4, 20) //[23:20] + #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B2 Fld(4, 24) //[27:24] + #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B3 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_MIOCK_JIT_MTR (DDRPHY_AO_BASE_ADDRESS + 0x0628) + #define MISC_MIOCK_JIT_MTR_RX_MIOCK_JIT_LIMIT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_JMETER (DDRPHY_AO_BASE_ADDRESS + 0x062C) + #define MISC_JMETER_JMTR_EN Fld(1, 0) //[0:0] + #define MISC_JMETER_JMTRCNT Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_DVFS_EMI_CLK (DDRPHY_AO_BASE_ADDRESS + 0x0630) + #define MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY Fld(1, 24) //[24:24] + #define MISC_DVFS_EMI_CLK_GATING_EMI_NEW Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0634) + #define MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT Fld(1, 0) //[0:0] + #define MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN Fld(1, 1) //[1:1] + #define MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN Fld(4, 8) //[11:8] + #define MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN Fld(4, 12) //[15:12] + +#define DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0638) + #define MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT Fld(1, 0) //[0:0] + #define MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN Fld(1, 1) //[1:1] + #define MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN Fld(4, 8) //[11:8] + #define MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN Fld(4, 12) //[15:12] + +#define DDRPHY_REG_MISC_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x063C) + #define MISC_CTRL0_R_DMDQSIEN_FIFO_EN Fld(1, 0) //[0:0] + #define MISC_CTRL0_R_DMDQSIEN_DEPTH_HALF Fld(1, 1) //[1:1] + #define MISC_CTRL0_R_DMSTBEN_SYNCOPT Fld(1, 2) //[2:2] + #define MISC_CTRL0_R_DMVALID_DLY_OPT Fld(1, 4) //[4:4] + #define MISC_CTRL0_R_DMVALID_NARROW_IG Fld(1, 5) //[5:5] + #define MISC_CTRL0_R_DMVALID_DLY Fld(3, 8) //[10:8] + #define MISC_CTRL0_IMPCAL_CHAB_EN Fld(1, 12) //[12:12] + #define MISC_CTRL0_IMPCAL_TRACK_DISABLE Fld(1, 13) //[13:13] + #define MISC_CTRL0_IMPCAL_LP_ECO_OPT Fld(1, 18) //[18:18] + #define MISC_CTRL0_IMPCAL_CDC_ECO_OPT Fld(1, 19) //[19:19] + #define MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT Fld(1, 20) //[20:20] + #define MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF Fld(1, 27) //[27:27] + #define MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL Fld(1, 28) //[28:28] + #define MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL Fld(1, 29) //[29:29] + #define MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL Fld(1, 30) //[30:30] + #define MISC_CTRL0_R_STBENCMP_DIV4CK_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x0640) + #define MISC_CTRL1_R_RK_PINMUXSWAP_EN Fld(1, 0) //[0:0] + #define MISC_CTRL1_R_DMPHYRST Fld(1, 1) //[1:1] + #define MISC_CTRL1_R_DM_TX_ARCLK_OE Fld(1, 2) //[2:2] + #define MISC_CTRL1_R_DM_TX_ARCMD_OE Fld(1, 3) //[3:3] + #define MISC_CTRL1_R_DMMUXCA Fld(1, 6) //[6:6] + #define MISC_CTRL1_R_DMARPIDQ_SW Fld(1, 7) //[7:7] + #define MISC_CTRL1_R_DMPINMUX Fld(2, 8) //[9:8] + #define MISC_CTRL1_R_DMARPICA_SW_UPDX Fld(1, 10) //[10:10] + #define MISC_CTRL1_R_DMRRESETB_I_OPT Fld(1, 12) //[12:12] + #define MISC_CTRL1_R_DMDA_RRESETB_I Fld(1, 13) //[13:13] + #define MISC_CTRL1_R_DQ2DM_SWAP Fld(1, 15) //[15:15] + #define MISC_CTRL1_R_DMDRAMCLKEN0 Fld(4, 16) //[19:16] + #define MISC_CTRL1_R_DMDRAMCLKEN1 Fld(4, 20) //[23:20] + #define MISC_CTRL1_R_DMDQSIENCG_EN Fld(1, 24) //[24:24] + #define MISC_CTRL1_R_DMSTBENCMP_RK_OPT Fld(1, 25) //[25:25] + #define MISC_CTRL1_R_WL_DOWNSP Fld(1, 26) //[26:26] + #define MISC_CTRL1_R_DMODTDISOE_A Fld(1, 27) //[27:27] + #define MISC_CTRL1_R_DMODTDISOE_B Fld(1, 28) //[28:28] + #define MISC_CTRL1_R_DMODTDISOE_C Fld(1, 29) //[29:29] + #define MISC_CTRL1_R_DMDA_RRESETB_E Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x0644) + #define MISC_CTRL2_CLRPLL_SHU_GP Fld(2, 0) //[1:0] + #define MISC_CTRL2_PHYPLL_SHU_GP Fld(2, 2) //[3:2] + +#define DDRPHY_REG_MISC_CTRL3 (DDRPHY_AO_BASE_ADDRESS + 0x0648) + #define MISC_CTRL3_ARPI_CG_CMD_OPT Fld(2, 0) //[1:0] + #define MISC_CTRL3_ARPI_CG_CLK_OPT Fld(2, 2) //[3:2] + #define MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT Fld(1, 4) //[4:4] + #define MISC_CTRL3_ARPI_CG_MCK_CA_OPT Fld(1, 5) //[5:5] + #define MISC_CTRL3_ARPI_CG_MCTL_CA_OPT Fld(1, 6) //[6:6] + #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_CA_SEL Fld(2, 8) //[9:8] + #define MISC_CTRL3_DRAM_CLK_NEW_CA_EN_SEL Fld(4, 12) //[15:12] + #define MISC_CTRL3_ARPI_CG_DQ_OPT Fld(2, 16) //[17:16] + #define MISC_CTRL3_ARPI_CG_DQS_OPT Fld(2, 18) //[19:18] + #define MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT Fld(1, 20) //[20:20] + #define MISC_CTRL3_ARPI_CG_MCK_DQ_OPT Fld(1, 21) //[21:21] + #define MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT Fld(1, 22) //[22:22] + #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_DQ_SEL Fld(2, 24) //[25:24] + #define MISC_CTRL3_R_DDRPHY_COMB_CG_IG Fld(1, 26) //[26:26] + #define MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG Fld(1, 27) //[27:27] + #define MISC_CTRL3_DRAM_CLK_NEW_DQ_EN_SEL Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_CTRL4 (DDRPHY_AO_BASE_ADDRESS + 0x064C) + #define MISC_CTRL4_R_OPT2_MPDIV_CG Fld(1, 0) //[0:0] + #define MISC_CTRL4_R_OPT2_CG_MCK Fld(1, 1) //[1:1] + #define MISC_CTRL4_R_OPT2_CG_DQM Fld(1, 2) //[2:2] + #define MISC_CTRL4_R_OPT2_CG_DQS Fld(1, 3) //[3:3] + #define MISC_CTRL4_R_OPT2_CG_DQ Fld(1, 4) //[4:4] + #define MISC_CTRL4_R_OPT2_CG_DQSIEN Fld(1, 5) //[5:5] + #define MISC_CTRL4_R_OPT2_CG_CMD Fld(1, 6) //[6:6] + #define MISC_CTRL4_R_OPT2_CG_CLK Fld(1, 7) //[7:7] + #define MISC_CTRL4_R_OPT2_CG_CS Fld(1, 8) //[8:8] + +#define DDRPHY_REG_MISC_CTRL5 (DDRPHY_AO_BASE_ADDRESS + 0x0650) + #define MISC_CTRL5_R_SRAM_DELSEL Fld(10, 0) //[9:0] + #define MISC_CTRL5_R_MBIST_RPREG_LOAD Fld(1, 10) //[10:10] + #define MISC_CTRL5_R_MBIST_RPREG_SEL Fld(1, 11) //[11:11] + #define MISC_CTRL5_R_MBIST_RPRSTB Fld(1, 12) //[12:12] + #define MISC_CTRL5_R_MBIST_MODE Fld(1, 13) //[13:13] + #define MISC_CTRL5_R_MBIST_BACKGROUND Fld(3, 14) //[16:14] + #define MISC_CTRL5_R_SLEEP_W Fld(1, 17) //[17:17] + #define MISC_CTRL5_R_SLEEP_R Fld(1, 18) //[18:18] + #define MISC_CTRL5_R_SLEEP_INV Fld(1, 19) //[19:19] + #define MISC_CTRL5_R_SLEEP_TEST Fld(1, 20) //[20:20] + #define MISC_CTRL5_R_MBIST_HOLDB Fld(1, 21) //[21:21] + #define MISC_CTRL5_R_CS_MARK Fld(1, 22) //[22:22] + #define MISC_CTRL5_MBIST_RSTB Fld(1, 23) //[23:23] + #define MISC_CTRL5_R_SPM_SRAM_SLP_MSK Fld(1, 24) //[24:24] + #define MISC_CTRL5_R_SRAM_HDEN Fld(1, 25) //[25:25] + #define MISC_CTRL5_R_SRAM_ISOINTB Fld(1, 26) //[26:26] + #define MISC_CTRL5_R_SRAM_SLEEPB Fld(1, 27) //[27:27] + +#define DDRPHY_REG_MISC_CTRL6 (DDRPHY_AO_BASE_ADDRESS + 0x0654) + #define MISC_CTRL6_RG_PHDET_EN_SHU_OPT Fld(1, 0) //[0:0] + #define MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT Fld(1, 1) //[1:1] + #define MISC_CTRL6_R_SRAM_DELSEL_1 Fld(10, 16) //[25:16] + +#define DDRPHY_REG_MISC_VREF_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0658) + #define MISC_VREF_CTRL_VREF_CTRL_RFU Fld(15, 16) //[30:16] + #define MISC_VREF_CTRL_RG_RVREF_VREF_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_SHU_OPT (DDRPHY_AO_BASE_ADDRESS + 0x065C) + #define MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN Fld(1, 0) //[0:0] + #define MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN Fld(2, 2) //[3:2] + #define MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN Fld(1, 8) //[8:8] + #define MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN Fld(2, 10) //[11:10] + #define MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN Fld(1, 16) //[16:16] + #define MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN Fld(2, 18) //[19:18] + +#define DDRPHY_REG_MISC_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0660) + #define MISC_RXDVS0_R_RX_DLY_TRACK_RO_SEL Fld(3, 0) //[2:0] + #define MISC_RXDVS0_R_DA_DQX_R_DLY_RO_SEL Fld(4, 8) //[11:8] + #define MISC_RXDVS0_R_DA_CAX_R_DLY_RO_SEL Fld(4, 12) //[15:12] + +#define DDRPHY_REG_MISC_RXDVS2 (DDRPHY_AO_BASE_ADDRESS + 0x0664) + #define MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF Fld(1, 0) //[0:0] + #define MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG Fld(1, 8) //[8:8] + #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN Fld(1, 16) //[16:16] + #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR Fld(1, 17) //[17:17] + #define MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN Fld(1, 18) //[18:18] + +#define DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0 (DDRPHY_AO_BASE_ADDRESS + 0x0668) + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO Fld(1, 0) //[0:0] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B0_EN Fld(1, 1) //[1:1] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B1_EN Fld(1, 2) //[2:2] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CA_EN Fld(1, 3) //[3:3] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_DEBUG_MODE_EN Fld(1, 4) //[4:4] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_EARLY_BREAK_EN Fld(1, 5) //[5:5] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CUR_RANK Fld(1, 6) //[6:6] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_PI_OFFSET Fld(2, 8) //[9:8] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_BURST_LENGTH Fld(2, 10) //[11:10] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST Fld(1, 12) //[12:12] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST Fld(1, 13) //[13:13] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST Fld(1, 14) //[14:14] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END__UI Fld(4, 16) //[19:16] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END_MCK Fld(4, 20) //[23:20] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI__UI Fld(4, 24) //[27:24] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI_MCK Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_DLINE_MON_CFG (DDRPHY_AO_BASE_ADDRESS + 0x066C) + #define MISC_DLINE_MON_CFG_DLINE_MON_TRACK_EN Fld(1, 0) //[0:0] + #define MISC_DLINE_MON_CFG_FORCE_DLINE_MON_EN Fld(1, 1) //[1:1] + #define MISC_DLINE_MON_CFG_FORCE_UDP_DLY_VAL Fld(1, 2) //[2:2] + #define MISC_DLINE_MON_CFG_MON_DLY_OUT Fld(4, 4) //[7:4] + #define MISC_DLINE_MON_CFG_RX_UDP_EN Fld(1, 8) //[8:8] + #define MISC_DLINE_MON_CFG_TX_UDP_EN Fld(1, 9) //[9:9] + #define MISC_DLINE_MON_CFG_DLINE_MON_TRACK_CG_EN Fld(1, 10) //[10:10] + +#define DDRPHY_REG_MISC_RX_AUTOK_CFG0 (DDRPHY_AO_BASE_ADDRESS + 0x0670) + #define MISC_RX_AUTOK_CFG0_RX_CAL_START Fld(1, 0) //[0:0] + #define MISC_RX_AUTOK_CFG0_RX_CAL_BREAK Fld(1, 1) //[1:1] + #define MISC_RX_AUTOK_CFG0_RX_CAL_CLEAR Fld(1, 2) //[2:2] + #define MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN Fld(1, 3) //[3:3] + #define MISC_RX_AUTOK_CFG0_RX_CAL_BEGIN Fld(11, 4) //[14:4] + #define MISC_RX_AUTOK_CFG0_RX_CAL_LEN Fld(10, 16) //[25:16] + #define MISC_RX_AUTOK_CFG0_RX_CAL_STEP Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_RX_AUTOK_CFG1 (DDRPHY_AO_BASE_ADDRESS + 0x0674) + #define MISC_RX_AUTOK_CFG1_RX_CAL_OUT_DBG_EN Fld(1, 0) //[0:0] + #define MISC_RX_AUTOK_CFG1_RX_CAL_OUT_DBG_SEL Fld(4, 4) //[7:4] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0680) + #define MISC_DBG_IRQ_CTRL0_DBG_DB_SW_RST Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL0_DBG_DB_IRQ_RST_EN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL0_IRQ_CK_FRUN Fld(1, 4) //[4:4] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x0684) + #define MISC_DBG_IRQ_CTRL1_REFRATE_EN Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL1_REFPENDING_EN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL1_PRE_REFRATE_EN Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL1_RTMRW_ABNORMAL_STOP_EN Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL1_SREF_REQ_NO_ACK_EN Fld(1, 6) //[6:6] + #define MISC_DBG_IRQ_CTRL1_SREF_REQ_SHORT_EN Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL1_SREF_REQ_DTRIG_EN Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL1_RTSWCMD_NONVALIDCMD_EN Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL1_TX_TRACKING1_EN Fld(1, 16) //[16:16] + #define MISC_DBG_IRQ_CTRL1_TX_TRACKING2_EN Fld(1, 17) //[17:17] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x0688) + #define MISC_DBG_IRQ_CTRL2_REFRATE_POL Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL2_REFPENDING_POL Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL2_PRE_REFRATE_POL Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL2_RTMRW_ABNORMAL_STOP_POL Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL2_SREF_REQ_NO_ACK_POL Fld(1, 6) //[6:6] + #define MISC_DBG_IRQ_CTRL2_SREF_REQ_SHORT_POL Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL2_SREF_REQ_DTRIG_POL Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL2_RTSWCMD_NONVALIDCMD_POL Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL2_TX_TRACKING1_POL Fld(1, 16) //[16:16] + #define MISC_DBG_IRQ_CTRL2_TX_TRACKING2_POL Fld(1, 17) //[17:17] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL3 (DDRPHY_AO_BASE_ADDRESS + 0x068C) + #define MISC_DBG_IRQ_CTRL3_REFRATE_CLEAN Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL3_REFPENDING_CLEAN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL3_PRE_REFRATE_CLEAN Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL3_RTMRW_ABNORMAL_STOP_CLEAN Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL3_SREF_REQ_NO_ACK_CLEAN Fld(1, 6) //[6:6] + #define MISC_DBG_IRQ_CTRL3_SREF_REQ_SHORT_CLEAN Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL3_SREF_REQ_DTRIG_CLEAN Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL3_RTSWCMD_NONVALIDCMD_CLEAN Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL3_TX_TRACKING1_CLEAN Fld(1, 16) //[16:16] + #define MISC_DBG_IRQ_CTRL3_TX_TRACKING2_CLEAN Fld(1, 17) //[17:17] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL4 (DDRPHY_AO_BASE_ADDRESS + 0x0690) + #define MISC_DBG_IRQ_CTRL4_DBG_DRAMC_IRQ_EN_1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL5 (DDRPHY_AO_BASE_ADDRESS + 0x0694) + #define MISC_DBG_IRQ_CTRL5_DBG_DRAMC_IRQ_POL_1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL6 (DDRPHY_AO_BASE_ADDRESS + 0x0698) + #define MISC_DBG_IRQ_CTRL6_DBG_DRAMC_IRQ_CLEAN_1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL7 (DDRPHY_AO_BASE_ADDRESS + 0x069C) + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_B0_EN Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_B0_EN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_B1_EN Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_B1_EN Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_CA_EN Fld(1, 4) //[4:4] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_CA_EN Fld(1, 5) //[5:5] + #define MISC_DBG_IRQ_CTRL7_STB_GATTING_ERR_EN Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL7_RX_ARDQ0_FIFO_STBEN_ERR_B0_EN Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL7_RX_ARDQ4_FIFO_STBEN_ERR_B0_EN Fld(1, 9) //[9:9] + #define MISC_DBG_IRQ_CTRL7_RX_ARDQ0_FIFO_STBEN_ERR_B1_EN Fld(1, 10) //[10:10] + #define MISC_DBG_IRQ_CTRL7_RX_ARDQ4_FIFO_STBEN_ERR_B1_EN Fld(1, 11) //[11:11] + #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R1_B1_EN Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R1_B0_EN Fld(1, 13) //[13:13] + #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R0_B1_EN Fld(1, 14) //[14:14] + #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R0_B0_EN Fld(1, 15) //[15:15] + #define MISC_DBG_IRQ_CTRL7_IMP_CLK_ERR_EN Fld(1, 24) //[24:24] + #define MISC_DBG_IRQ_CTRL7_IMP_CMD_ERR_EN Fld(1, 25) //[25:25] + #define MISC_DBG_IRQ_CTRL7_IMP_DQ1_ERR_EN Fld(1, 26) //[26:26] + #define MISC_DBG_IRQ_CTRL7_IMP_DQ0_ERR_EN Fld(1, 27) //[27:27] + #define MISC_DBG_IRQ_CTRL7_IMP_DQS_ERR_EN Fld(1, 28) //[28:28] + #define MISC_DBG_IRQ_CTRL7_IMP_ODTN_ERR_EN Fld(1, 29) //[29:29] + #define MISC_DBG_IRQ_CTRL7_IMP_DRVN_ERR_EN Fld(1, 30) //[30:30] + #define MISC_DBG_IRQ_CTRL7_IMP_DRVP_ERR_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL8 (DDRPHY_AO_BASE_ADDRESS + 0x06A0) + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_B0_POL Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_B0_POL Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_B1_POL Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_B1_POL Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_CA_POL Fld(1, 4) //[4:4] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_CA_POL Fld(1, 5) //[5:5] + #define MISC_DBG_IRQ_CTRL8_STB_GATTING_ERR_POL Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL8_RX_ARDQ0_FIFO_STBEN_ERR_B0_POL Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL8_RX_ARDQ4_FIFO_STBEN_ERR_B0_POL Fld(1, 9) //[9:9] + #define MISC_DBG_IRQ_CTRL8_RX_ARDQ0_FIFO_STBEN_ERR_B1_POL Fld(1, 10) //[10:10] + #define MISC_DBG_IRQ_CTRL8_RX_ARDQ4_FIFO_STBEN_ERR_B1_POL Fld(1, 11) //[11:11] + #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R1_B1_POL Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R1_B0_POL Fld(1, 13) //[13:13] + #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R0_B1_POL Fld(1, 14) //[14:14] + #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R0_B0_POL Fld(1, 15) //[15:15] + #define MISC_DBG_IRQ_CTRL8_IMP_CLK_ERR_POL Fld(1, 24) //[24:24] + #define MISC_DBG_IRQ_CTRL8_IMP_CMD_ERR_POL Fld(1, 25) //[25:25] + #define MISC_DBG_IRQ_CTRL8_IMP_DQ1_ERR_POL Fld(1, 26) //[26:26] + #define MISC_DBG_IRQ_CTRL8_IMP_DQ0_ERR_POL Fld(1, 27) //[27:27] + #define MISC_DBG_IRQ_CTRL8_IMP_DQS_ERR_POL Fld(1, 28) //[28:28] + #define MISC_DBG_IRQ_CTRL8_IMP_ODTN_ERR_POL Fld(1, 29) //[29:29] + #define MISC_DBG_IRQ_CTRL8_IMP_DRVN_ERR_POL Fld(1, 30) //[30:30] + #define MISC_DBG_IRQ_CTRL8_IMP_DRVP_ERR_POL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL9 (DDRPHY_AO_BASE_ADDRESS + 0x06A4) + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_B0_CLEAN Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_B0_CLEAN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_B1_CLEAN Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_B1_CLEAN Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_CA_CLEAN Fld(1, 4) //[4:4] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_CA_CLEAN Fld(1, 5) //[5:5] + #define MISC_DBG_IRQ_CTRL9_STB_GATTING_ERR_CLEAN Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL9_RX_ARDQ0_FIFO_STBEN_ERR_B0_CLEAN Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL9_RX_ARDQ4_FIFO_STBEN_ERR_B0_CLEAN Fld(1, 9) //[9:9] + #define MISC_DBG_IRQ_CTRL9_RX_ARDQ0_FIFO_STBEN_ERR_B1_CLEAN Fld(1, 10) //[10:10] + #define MISC_DBG_IRQ_CTRL9_RX_ARDQ4_FIFO_STBEN_ERR_B1_CLEAN Fld(1, 11) //[11:11] + #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R1_B1_CLEAN Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R1_B0_CLEAN Fld(1, 13) //[13:13] + #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R0_B1_CLEAN Fld(1, 14) //[14:14] + #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R0_B0_CLEAN Fld(1, 15) //[15:15] + #define MISC_DBG_IRQ_CTRL9_IMP_CLK_ERR_CLEAN Fld(1, 24) //[24:24] + #define MISC_DBG_IRQ_CTRL9_IMP_CMD_ERR_CLEAN Fld(1, 25) //[25:25] + #define MISC_DBG_IRQ_CTRL9_IMP_DQ1_ERR_CLEAN Fld(1, 26) //[26:26] + #define MISC_DBG_IRQ_CTRL9_IMP_DQ0_ERR_CLEAN Fld(1, 27) //[27:27] + #define MISC_DBG_IRQ_CTRL9_IMP_DQS_ERR_CLEAN Fld(1, 28) //[28:28] + #define MISC_DBG_IRQ_CTRL9_IMP_ODTN_ERR_CLEAN Fld(1, 29) //[29:29] + #define MISC_DBG_IRQ_CTRL9_IMP_DRVN_ERR_CLEAN Fld(1, 30) //[30:30] + #define MISC_DBG_IRQ_CTRL9_IMP_DRVP_ERR_CLEAN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x06B0) + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0 Fld(4, 0) //[3:0] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1 Fld(4, 4) //[7:4] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2 Fld(4, 8) //[11:8] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3 Fld(4, 12) //[15:12] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4 Fld(4, 16) //[19:16] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5 Fld(4, 20) //[23:20] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6 Fld(4, 24) //[27:24] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x06B4) + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8 Fld(4, 0) //[3:0] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9 Fld(4, 4) //[7:4] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10 Fld(4, 8) //[11:8] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11 Fld(4, 12) //[15:12] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12 Fld(4, 16) //[19:16] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13 Fld(4, 20) //[23:20] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14 Fld(4, 24) //[27:24] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_BIST_LPBK_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x06C0) + #define MISC_BIST_LPBK_CTRL0_BIST_EN Fld(1, 0) //[0:0] + #define MISC_BIST_LPBK_CTRL0_BIST_TA2_LPBK_MODE Fld(1, 1) //[1:1] + #define MISC_BIST_LPBK_CTRL0_BIST_RX_LPBK_MODE Fld(1, 2) //[2:2] + #define MISC_BIST_LPBK_CTRL0_BIST_DSEL_MODE Fld(1, 3) //[3:3] + #define MISC_BIST_LPBK_CTRL0_BIST_TX_DQSINCTL Fld(4, 12) //[15:12] + #define MISC_BIST_LPBK_CTRL0_BIST_SEDA_LPBK_DSEL_RW Fld(5, 16) //[20:16] + #define MISC_BIST_LPBK_CTRL0_BIST_SEDA_LPBK_DLE_RW Fld(5, 24) //[28:24] + +#define DDRPHY_REG_SHU_PHYPLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0700) + #define SHU_PHYPLL0_RG_RPHYPLL_RESERVED Fld(16, 0) //[15:0] + #define SHU_PHYPLL0_RG_RPHYPLL_FS Fld(2, 18) //[19:18] + #define SHU_PHYPLL0_RG_RPHYPLL_BW Fld(3, 20) //[22:20] + #define SHU_PHYPLL0_RG_RPHYPLL_ICHP Fld(2, 24) //[25:24] + #define SHU_PHYPLL0_RG_RPHYPLL_IBIAS Fld(2, 26) //[27:26] + #define SHU_PHYPLL0_RG_RPHYPLL_BLP Fld(1, 29) //[29:29] + #define SHU_PHYPLL0_RG_RPHYPLL_BR Fld(1, 30) //[30:30] + #define SHU_PHYPLL0_RG_RPHYPLL_BP Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_PHYPLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0704) + #define SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN Fld(1, 0) //[0:0] + #define SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG Fld(1, 1) //[1:1] + #define SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_PHYPLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0708) + #define SHU_PHYPLL2_RG_RPHYPLL_POSDIV Fld(3, 0) //[2:0] + #define SHU_PHYPLL2_RG_RPHYPLL_PREDIV Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_PHYPLL3 (DDRPHY_AO_BASE_ADDRESS + 0x070C) + #define SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL Fld(1, 0) //[0:0] + #define SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN Fld(1, 1) //[1:1] + #define SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL Fld(2, 2) //[3:2] + #define SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN Fld(1, 4) //[4:4] + #define SHU_PHYPLL3_RG_RPHYPLL_FS_EN Fld(1, 5) //[5:5] + #define SHU_PHYPLL3_RG_RPHYPLL_FBKSEL Fld(1, 6) //[6:6] + #define SHU_PHYPLL3_RG_RPHYPLL_RST_DLY Fld(2, 8) //[9:8] + #define SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN Fld(1, 12) //[12:12] + #define SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN Fld(1, 13) //[13:13] + #define SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN Fld(2, 14) //[15:14] + #define SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN Fld(1, 16) //[16:16] + +#define DDRPHY_REG_SHU_PHYPLL4 (DDRPHY_AO_BASE_ADDRESS + 0x0710) + #define SHU_PHYPLL4_RG_RPHYPLL_EXT_FBDIV Fld(6, 0) //[5:0] + #define SHU_PHYPLL4_RG_RPHYPLL_EXTFBDIV_EN Fld(1, 8) //[8:8] + +#define DDRPHY_REG_SHU_PHYPLL5 (DDRPHY_AO_BASE_ADDRESS + 0x0714) + #define SHU_PHYPLL5_RG_RPHYPLL_FB_DL Fld(6, 0) //[5:0] + #define SHU_PHYPLL5_RG_RPHYPLL_REF_DL Fld(6, 8) //[13:8] + +#define DDRPHY_REG_SHU_PHYPLL6 (DDRPHY_AO_BASE_ADDRESS + 0x0718) + #define SHU_PHYPLL6_RG_RPHYPLL_SDM_HREN Fld(1, 0) //[0:0] + #define SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PH_INIT Fld(1, 1) //[1:1] + #define SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PRD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_PHYPLL7 (DDRPHY_AO_BASE_ADDRESS + 0x071C) + #define SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA Fld(16, 0) //[15:0] + #define SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_CLRPLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0720) + #define SHU_CLRPLL0_RG_RCLRPLL_RESERVED Fld(16, 0) //[15:0] + #define SHU_CLRPLL0_RG_RCLRPLL_FS Fld(2, 18) //[19:18] + #define SHU_CLRPLL0_RG_RCLRPLL_BW Fld(3, 20) //[22:20] + #define SHU_CLRPLL0_RG_RCLRPLL_ICHP Fld(2, 24) //[25:24] + #define SHU_CLRPLL0_RG_RCLRPLL_IBIAS Fld(2, 26) //[27:26] + #define SHU_CLRPLL0_RG_RCLRPLL_BLP Fld(1, 29) //[29:29] + #define SHU_CLRPLL0_RG_RCLRPLL_BR Fld(1, 30) //[30:30] + #define SHU_CLRPLL0_RG_RCLRPLL_BP Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CLRPLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0724) + #define SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN Fld(1, 0) //[0:0] + #define SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG Fld(1, 1) //[1:1] + #define SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_CLRPLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0728) + #define SHU_CLRPLL2_RG_RCLRPLL_POSDIV Fld(3, 0) //[2:0] + #define SHU_CLRPLL2_RG_RCLRPLL_PREDIV Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_CLRPLL3 (DDRPHY_AO_BASE_ADDRESS + 0x072C) + #define SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL Fld(1, 0) //[0:0] + #define SHU_CLRPLL3_RG_RCLRPLL_GLITCH_FREE_EN Fld(1, 1) //[1:1] + #define SHU_CLRPLL3_RG_RCLRPLL_LVR_REFSEL Fld(2, 2) //[3:2] + #define SHU_CLRPLL3_RG_RCLRPLL_DIV3_EN Fld(1, 4) //[4:4] + #define SHU_CLRPLL3_RG_RCLRPLL_FS_EN Fld(1, 5) //[5:5] + #define SHU_CLRPLL3_RG_RCLRPLL_FBKSEL Fld(1, 6) //[6:6] + #define SHU_CLRPLL3_RG_RCLRPLL_RST_DLY Fld(2, 8) //[9:8] + #define SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN Fld(1, 12) //[12:12] + #define SHU_CLRPLL3_RG_RCLRPLL_MONREF_EN Fld(1, 13) //[13:13] + #define SHU_CLRPLL3_RG_RCLRPLL_MONVC_EN Fld(2, 14) //[15:14] + #define SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN Fld(1, 16) //[16:16] + +#define DDRPHY_REG_SHU_CLRPLL4 (DDRPHY_AO_BASE_ADDRESS + 0x0730) + #define SHU_CLRPLL4_RG_RCLRPLL_EXT_PODIV Fld(6, 0) //[5:0] + #define SHU_CLRPLL4_RG_RCLRPLL_BYPASS Fld(1, 8) //[8:8] + #define SHU_CLRPLL4_RG_RCLRPLL_EXTPODIV_EN Fld(1, 12) //[12:12] + #define SHU_CLRPLL4_RG_RCLRPLL_EXT_FBDIV Fld(6, 16) //[21:16] + #define SHU_CLRPLL4_RG_RCLRPLL_EXTFBDIV_EN Fld(1, 24) //[24:24] + +#define DDRPHY_REG_SHU_CLRPLL5 (DDRPHY_AO_BASE_ADDRESS + 0x0734) + #define SHU_CLRPLL5_RG_RCLRPLL_FB_DL Fld(6, 0) //[5:0] + #define SHU_CLRPLL5_RG_RCLRPLL_REF_DL Fld(6, 8) //[13:8] + +#define DDRPHY_REG_SHU_CLRPLL6 (DDRPHY_AO_BASE_ADDRESS + 0x0738) + #define SHU_CLRPLL6_RG_RCLRPLL_SDM_HREN Fld(1, 0) //[0:0] + #define SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PH_INIT Fld(1, 1) //[1:1] + #define SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PRD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_CLRPLL7 (DDRPHY_AO_BASE_ADDRESS + 0x073C) + #define SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA Fld(16, 0) //[15:0] + #define SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_PLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0740) + #define SHU_PLL0_RG_RPHYPLL_TOP_REV Fld(16, 0) //[15:0] + #define SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE Fld(1, 16) //[16:16] + #define SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN Fld(1, 17) //[17:17] + #define SHU_PLL0_RG_RPLLGP_SOPEN_EN Fld(1, 18) //[18:18] + #define SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT Fld(2, 20) //[21:20] + #define SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV Fld(2, 22) //[23:22] + #define SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY Fld(7, 24) //[30:24] + #define SHU_PLL0_RG_RPLLGP_DLINE_MON_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_PLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0744) + #define SHU_PLL1_RG_RPHYPLLGP_CK_SEL Fld(1, 0) //[0:0] + #define SHU_PLL1_RG_RPLLGP_PLLCK_VSEL Fld(1, 1) //[1:1] + #define SHU_PLL1_R_SHU_AUTO_PLL_MUX Fld(1, 4) //[4:4] + #define SHU_PLL1_RG_RPHYPLL_DDR400_EN Fld(1, 8) //[8:8] + +#define DDRPHY_REG_SHU_PLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0748) + #define SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x0760) + #define SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x0764) + #define SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x0768) + #define SHU_R0_B0_TXDLY2_TX_ARDQS0_DLYB_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_TXDLY2_TX_ARDQS0B_DLYB_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_TXDLY2_TX_ARDQS0_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_TXDLY2_TX_ARDQS0B_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x076C) + #define SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0770) + #define SHU_R0_B0_TXDLY4_DMY_TXDLY4_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x0774) + #define SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x0778) + #define SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x077C) + #define SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x0780) + #define SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0784) + #define SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY5 (DDRPHY_AO_BASE_ADDRESS + 0x0788) + #define SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0 Fld(9, 0) //[8:0] + #define SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0 Fld(9, 16) //[24:16] + +#if 0 +#define DDRPHY_REG_SHU_R0_B0_RXDLY6 (DDRPHY_AO_BASE_ADDRESS + 0x078C) + #define SHU_R0_B0_RXDLY6_DMY_RXDLY6_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY7 (DDRPHY_AO_BASE_ADDRESS + 0x0790) + #define SHU_R0_B0_RXDLY7_DMY_RXDLY7_B0 Fld(1, 0) //[0:0] +#else +#define DDRPHY_REG_SHU_RK_B0_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x078C) + #define SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0 Fld(4, 0) //[3:0] + +#define DDRPHY_REG_SHU_B0_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x0790) + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0 Fld(7, 0) //[6:0] + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0 Fld(7, 8) //[14:8] +#endif + +#define DDRPHY_REG_SHU_R0_B0_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x0794) + #define SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY Fld(3, 0) //[2:0] + #define SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY Fld(3, 4) //[6:4] + #define SHU_R0_B0_DQ0_SW_ARPI_DQ_B0 Fld(6, 8) //[13:8] + #define SHU_R0_B0_DQ0_SW_ARPI_DQM_B0 Fld(6, 16) //[21:16] + #define SHU_R0_B0_DQ0_ARPI_PBYTE_B0 Fld(6, 24) //[29:24] + #define SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0 Fld(1, 30) //[30:30] + #define SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_R0_B0_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x0798) + #define SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0 Fld(7, 0) //[6:0] + #define SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x079C) + #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0 Fld(7, 0) //[6:0] + #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x07A0) + #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0 Fld(4, 0) //[3:0] + #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0 Fld(4, 4) //[7:4] + #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0 Fld(4, 16) //[19:16] + #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0 Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x07A4) + #define SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0 Fld(7, 0) //[6:0] + +#define DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x07A8) + #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0 Fld(3, 0) //[2:0] + #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0 Fld(3, 4) //[6:4] + #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0 Fld(3, 16) //[18:16] + #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0 Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_RK_B0_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x07AC) + #define SHU_RK_B0_DQ0_RG_RX_ARDQ0_OFFC_B0 Fld(4, 0) //[3:0] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ1_OFFC_B0 Fld(4, 4) //[7:4] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ2_OFFC_B0 Fld(4, 8) //[11:8] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ3_OFFC_B0 Fld(4, 12) //[15:12] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ4_OFFC_B0 Fld(4, 16) //[19:16] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ5_OFFC_B0 Fld(4, 20) //[23:20] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ6_OFFC_B0 Fld(4, 24) //[27:24] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ7_OFFC_B0 Fld(4, 28) //[31:28] + +#if 0 +#define DDRPHY_REG_SHU_RK_B0_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x07B0) + #define SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0 Fld(4, 0) //[3:0] + +#define DDRPHY_REG_SHU_B0_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x07B4) + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0 Fld(7, 0) //[6:0] + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0 Fld(7, 8) //[14:8] +#endif + +#define DDRPHY_REG_SHU_RK_B0_BIST_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x07C0) + #define SHU_RK_B0_BIST_CTRL_BIST_TX_DQS_UI_DLY_B0 Fld(8, 0) //[7:0] + +#define DDRPHY_REG_SHU_B0_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x0860) + #define SHU_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 Fld(3, 8) //[10:8] + #define SHU_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 Fld(3, 12) //[14:12] + #define SHU_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 Fld(3, 24) //[26:24] + #define SHU_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 Fld(3, 28) //[30:28] + #define SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B0_DQ3 (DDRPHY_AO_BASE_ADDRESS + 0x0864) + #define SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0 Fld(2, 0) //[1:0] + #define SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 Fld(2, 2) //[3:2] + #define SHU_B0_DQ3_RG_TX_ARDQS0_PDB_B0 Fld(2, 4) //[5:4] + #define SHU_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 Fld(2, 6) //[7:6] + #define SHU_B0_DQ3_RG_TX_ARDQ_PU_B0 Fld(2, 8) //[9:8] + #define SHU_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 Fld(2, 10) //[11:10] + #define SHU_B0_DQ3_RG_TX_ARDQ_PDB_B0 Fld(2, 12) //[13:12] + #define SHU_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 Fld(2, 14) //[15:14] + #define SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0 Fld(9, 23) //[31:23] + +#define DDRPHY_REG_SHU_B0_DQ4 (DDRPHY_AO_BASE_ADDRESS + 0x0868) + #define SHU_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 Fld(6, 0) //[5:0] + #define SHU_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 Fld(6, 8) //[13:8] + #define SHU_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 Fld(6, 16) //[21:16] + +#define DDRPHY_REG_SHU_B0_DQ5 (DDRPHY_AO_BASE_ADDRESS + 0x086C) + #define SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 Fld(6, 0) //[5:0] + #define SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ5_RG_ARPI_FB_B0 Fld(6, 8) //[13:8] + #define SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 Fld(3, 16) //[18:16] + #define SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 Fld(4, 20) //[23:20] + #define SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_B0_DQ6 (DDRPHY_AO_BASE_ADDRESS + 0x0870) + #define SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 Fld(6, 0) //[5:0] + #define SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0 Fld(6, 6) //[11:6] + #define SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0 Fld(7, 12) //[18:12] + #define SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0 Fld(1, 21) //[21:21] + #define SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0 Fld(2, 22) //[23:22] + #define SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0 Fld(1, 25) //[25:25] + #define SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0 Fld(1, 26) //[26:26] + #define SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0 Fld(1, 27) //[27:27] + #define SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0 Fld(1, 28) //[28:28] + #define SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0 Fld(1, 29) //[29:29] + +#define DDRPHY_REG_SHU_B0_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x0874) + #define SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0 Fld(5, 8) //[12:8] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0 Fld(2, 16) //[17:16] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0 Fld(2, 22) //[23:22] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0 Fld(2, 24) //[25:24] + #define SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0 Fld(1, 26) //[26:26] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0 Fld(1, 27) //[27:27] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B0_DQ2 (DDRPHY_AO_BASE_ADDRESS + 0x0878) + #define SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0 Fld(1, 5) //[5:5] + #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0 Fld(1, 8) //[8:8] + #define SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0 Fld(1, 9) //[9:9] + #define SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0 Fld(1, 10) //[10:10] + #define SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU Fld(1, 12) //[12:12] + #define SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_SHU_B0_DQ10 (DDRPHY_AO_BASE_ADDRESS + 0x087C) + #define SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0 Fld(1, 3) //[3:3] + #define SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0 Fld(3, 8) //[10:8] + #define SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0 Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_B0_DQ11 (DDRPHY_AO_BASE_ADDRESS + 0x0880) + #define SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0 Fld(1, 3) //[3:3] + #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0 Fld(1, 5) //[5:5] + #define SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0 Fld(1, 7) //[7:7] + #define SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0 Fld(4, 8) //[11:8] + #define SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0 Fld(2, 16) //[17:16] + #define SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0 Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_B0_DQ7 (DDRPHY_AO_BASE_ADDRESS + 0x0884) + #define SHU_B0_DQ7_R_DMRANKRXDVS_B0 Fld(4, 0) //[3:0] + #define SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ7_R_DMDQMDBI_SHU_B0 Fld(1, 7) //[7:7] + #define SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 Fld(4, 8) //[11:8] + #define SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 Fld(1, 12) //[12:12] + #define SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DQ7_R_DMRODTEN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 Fld(1, 17) //[17:17] + #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 Fld(1, 18) //[18:18] + #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 Fld(3, 25) //[27:25] + #define SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0 Fld(1, 28) //[28:28] + #define SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_B0_DQ8 (DDRPHY_AO_BASE_ADDRESS + 0x0888) + #define SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 Fld(15, 0) //[14:0] + #define SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 Fld(1, 21) //[21:21] + #define SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 Fld(1, 22) //[22:22] + #define SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 Fld(1, 23) //[23:23] + #define SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 Fld(1, 26) //[26:26] + #define SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 Fld(1, 27) //[27:27] + #define SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 Fld(1, 28) //[28:28] + #define SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 Fld(1, 29) //[29:29] + #define SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 Fld(1, 30) //[30:30] + #define SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B0_DQ9 (DDRPHY_AO_BASE_ADDRESS + 0x088C) + #define SHU_B0_DQ9_RG_ARPI_RESERVE_B0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_B0_DQ12 (DDRPHY_AO_BASE_ADDRESS + 0x0890) + #define SHU_B0_DQ12_DMY_DQ12_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_B0_DLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0894) + #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0 Fld(3, 0) //[2:0] + #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0 Fld(3, 4) //[6:4] + #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0 Fld(1, 8) //[8:8] + #define SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0 Fld(4, 12) //[15:12] + #define SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0 Fld(3, 17) //[19:17] + #define SHU_B0_DLL0_RG_ARDLL_GAIN_B0 Fld(4, 20) //[23:20] + #define SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 Fld(1, 25) //[25:25] + #define SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0 Fld(1, 26) //[26:26] + #define SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0 Fld(1, 27) //[27:27] + +#define DDRPHY_REG_SHU_B0_DLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0898) + #define SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0 Fld(2, 2) //[3:2] + #define SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0 Fld(1, 5) //[5:5] + #define SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0 Fld(1, 7) //[7:7] + #define SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0 Fld(2, 8) //[9:8] + #define SHU_B0_DLL1_RG_ARDLL_PS_EN_B0 Fld(1, 10) //[10:10] + #define SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DLL1_RG_ARDLL_PHDIV_B0 Fld(1, 12) //[12:12] + #define SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0 Fld(2, 18) //[19:18] + #define SHU_B0_DLL1_RG_ARDLL_PGAIN_B0 Fld(4, 20) //[23:20] + #define SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 Fld(1, 24) //[24:24] + +#define DDRPHY_REG_SHU_B0_DLL2 (DDRPHY_AO_BASE_ADDRESS + 0x089C) + #define SHU_B0_DLL2_RG_ARDQ_REV_B0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x08A0) + #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B0 Fld(3, 0) //[2:0] + #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B0 Fld(3, 4) //[6:4] + #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0 Fld(3, 16) //[18:16] + #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0 Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_B0_DLL_ARPI2 (DDRPHY_AO_BASE_ADDRESS + 0x08A4) + #define SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 Fld(1, 10) //[10:10] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 Fld(1, 17) //[17:17] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0 Fld(1, 27) //[27:27] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B0_DLL_ARPI3 (DDRPHY_AO_BASE_ADDRESS + 0x08A8) + #define SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0 Fld(1, 17) //[17:17] + #define SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0 Fld(1, 19) //[19:19] + +#define DDRPHY_REG_SHU_B0_TXDUTY (DDRPHY_AO_BASE_ADDRESS + 0x08AC) + #define SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0 Fld(6, 0) //[5:0] + #define SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0 Fld(6, 8) //[13:8] + #define SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0 Fld(6, 16) //[21:16] + #define SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_SHU_B0_VREF (DDRPHY_AO_BASE_ADDRESS + 0x08B0) + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_SEL_DQS_B0 Fld(7, 0) //[6:0] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_UB_RK1_B0 Fld(1, 17) //[17:17] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_UB_RK0_B0 Fld(1, 18) //[18:18] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_LB_RK1_B0 Fld(1, 19) //[19:19] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_LB_RK0_B0 Fld(1, 20) //[20:20] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_DQS_B0 Fld(1, 21) //[21:21] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0 Fld(1, 22) //[22:22] + +#define DDRPHY_REG_SHU_B0_DQ13 (DDRPHY_AO_BASE_ADDRESS + 0x08B4) + #define SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 Fld(1, 3) //[3:3] + #define SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0 Fld(1, 5) //[5:5] + #define SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0 Fld(1, 7) //[7:7] + #define SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0 Fld(1, 8) //[8:8] + #define SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0 Fld(2, 12) //[13:12] + #define SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0 Fld(1, 17) //[17:17] + #define SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0 Fld(1, 18) //[18:18] + #define SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0 Fld(1, 25) //[25:25] + +#define DDRPHY_REG_SHU_B0_DQ14 (DDRPHY_AO_BASE_ADDRESS + 0x08B8) + #define SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0 Fld(2, 4) //[5:4] + #define SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0 Fld(1, 9) //[9:9] + #define SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0 Fld(1, 10) //[10:10] + #define SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0 Fld(8, 16) //[23:16] + +#define DDRPHY_REG_B0_SHU_MIDPI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x08BC) + #define B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0 Fld(1, 0) //[0:0] + #define B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0 Fld(1, 1) //[1:1] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x08E0) + #define SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x08E4) + #define SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x08E8) + #define SHU_R0_B1_TXDLY2_TX_ARDQS0_DLYB_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_TXDLY2_TX_ARDQS0B_DLYB_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_TXDLY2_TX_ARDQS0_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_TXDLY2_TX_ARDQS0B_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x08EC) + #define SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x08F0) + #define SHU_R0_B1_TXDLY4_DMY_TXDLY4_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x08F4) + #define SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x08F8) + #define SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x08FC) + #define SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x0900) + #define SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0904) + #define SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY5 (DDRPHY_AO_BASE_ADDRESS + 0x0908) + #define SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1 Fld(9, 0) //[8:0] + #define SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1 Fld(9, 16) //[24:16] + +#if 0 +#define DDRPHY_REG_SHU_R0_B1_RXDLY6 (DDRPHY_AO_BASE_ADDRESS + 0x090C) + #define SHU_R0_B1_RXDLY6_DMY_RXDLY6_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY7 (DDRPHY_AO_BASE_ADDRESS + 0x0910) + #define SHU_R0_B1_RXDLY7_DMY_RXDLY7_B1 Fld(1, 0) //[0:0] +#else +#define DDRPHY_REG_SHU_RK_B1_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x090C) + #define SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1 Fld(4, 0) //[3:0] + +#define DDRPHY_REG_SHU_B1_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x0910) + #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1 Fld(7, 0) //[6:0] + #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1 Fld(7, 8) //[14:8] +#endif + +#define DDRPHY_REG_SHU_R0_B1_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x0914) + #define SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY Fld(3, 0) //[2:0] + #define SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY Fld(3, 4) //[6:4] + #define SHU_R0_B1_DQ0_SW_ARPI_DQ_B1 Fld(6, 8) //[13:8] + #define SHU_R0_B1_DQ0_SW_ARPI_DQM_B1 Fld(6, 16) //[21:16] + #define SHU_R0_B1_DQ0_ARPI_PBYTE_B1 Fld(6, 24) //[29:24] + #define SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1 Fld(1, 30) //[30:30] + #define SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_R0_B1_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x0918) + #define SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1 Fld(7, 0) //[6:0] + #define SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x091C) + #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1 Fld(7, 0) //[6:0] + #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0920) + #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1 Fld(4, 0) //[3:0] + #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1 Fld(4, 4) //[7:4] + #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1 Fld(4, 16) //[19:16] + #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1 Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0924) + #define SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1 Fld(7, 0) //[6:0] + +#define DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0928) + #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1 Fld(3, 0) //[2:0] + #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1 Fld(3, 4) //[6:4] + #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1 Fld(3, 16) //[18:16] + #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1 Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_RK_B1_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x092C) + #define SHU_RK_B1_DQ0_RG_RX_ARDQ0_OFFC_B1 Fld(4, 0) //[3:0] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ1_OFFC_B1 Fld(4, 4) //[7:4] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ2_OFFC_B1 Fld(4, 8) //[11:8] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ3_OFFC_B1 Fld(4, 12) //[15:12] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ4_OFFC_B1 Fld(4, 16) //[19:16] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ5_OFFC_B1 Fld(4, 20) //[23:20] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ6_OFFC_B1 Fld(4, 24) //[27:24] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ7_OFFC_B1 Fld(4, 28) //[31:28] + +#if 0 +#define DDRPHY_REG_SHU_RK_B1_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x0930) + #define SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1 Fld(4, 0) //[3:0] + +#define DDRPHY_REG_SHU_B1_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x0934) + #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1 Fld(7, 0) //[6:0] + #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1 Fld(7, 8) //[14:8] +#endif + +#define DDRPHY_REG_SHU_RK_B1_BIST_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0940) + #define SHU_RK_B1_BIST_CTRL_BIST_TX_DQS_UI_DLY_B1 Fld(8, 0) //[7:0] + +#define DDRPHY_REG_SHU_B1_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x09E0) + #define SHU_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 Fld(3, 8) //[10:8] + #define SHU_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 Fld(3, 12) //[14:12] + #define SHU_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 Fld(3, 24) //[26:24] + #define SHU_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 Fld(3, 28) //[30:28] + #define SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B1_DQ3 (DDRPHY_AO_BASE_ADDRESS + 0x09E4) + #define SHU_B1_DQ3_RG_TX_ARDQS0_PU_B1 Fld(2, 0) //[1:0] + #define SHU_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 Fld(2, 2) //[3:2] + #define SHU_B1_DQ3_RG_TX_ARDQS0_PDB_B1 Fld(2, 4) //[5:4] + #define SHU_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 Fld(2, 6) //[7:6] + #define SHU_B1_DQ3_RG_TX_ARDQ_PU_B1 Fld(2, 8) //[9:8] + #define SHU_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 Fld(2, 10) //[11:10] + #define SHU_B1_DQ3_RG_TX_ARDQ_PDB_B1 Fld(2, 12) //[13:12] + #define SHU_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 Fld(2, 14) //[15:14] + #define SHU_B1_DQ3_RG_ARDQ_DUTYREV_B1 Fld(9, 23) //[31:23] + +#define DDRPHY_REG_SHU_B1_DQ4 (DDRPHY_AO_BASE_ADDRESS + 0x09E8) + #define SHU_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 Fld(6, 0) //[5:0] + #define SHU_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 Fld(6, 8) //[13:8] + #define SHU_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 Fld(6, 16) //[21:16] + +#define DDRPHY_REG_SHU_B1_DQ5 (DDRPHY_AO_BASE_ADDRESS + 0x09EC) + #define SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 Fld(6, 0) //[5:0] + #define SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ5_RG_ARPI_FB_B1 Fld(6, 8) //[13:8] + #define SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 Fld(3, 16) //[18:16] + #define SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 Fld(4, 20) //[23:20] + #define SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_B1_DQ6 (DDRPHY_AO_BASE_ADDRESS + 0x09F0) + #define SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 Fld(6, 0) //[5:0] + #define SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1 Fld(6, 6) //[11:6] + #define SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1 Fld(7, 12) //[18:12] + #define SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1 Fld(1, 21) //[21:21] + #define SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1 Fld(2, 22) //[23:22] + #define SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1 Fld(1, 25) //[25:25] + #define SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1 Fld(1, 26) //[26:26] + #define SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1 Fld(1, 27) //[27:27] + #define SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1 Fld(1, 28) //[28:28] + #define SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1 Fld(1, 29) //[29:29] + +#define DDRPHY_REG_SHU_B1_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x09F4) + #define SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1 Fld(5, 8) //[12:8] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1 Fld(2, 16) //[17:16] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1 Fld(2, 22) //[23:22] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1 Fld(2, 24) //[25:24] + #define SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1 Fld(1, 26) //[26:26] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1 Fld(1, 27) //[27:27] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B1_DQ2 (DDRPHY_AO_BASE_ADDRESS + 0x09F8) + #define SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1 Fld(1, 5) //[5:5] + #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1 Fld(1, 8) //[8:8] + #define SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1 Fld(1, 9) //[9:9] + #define SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1 Fld(1, 10) //[10:10] + #define SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU Fld(1, 12) //[12:12] + #define SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_SHU_B1_DQ10 (DDRPHY_AO_BASE_ADDRESS + 0x09FC) + #define SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1 Fld(1, 3) //[3:3] + #define SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1 Fld(3, 8) //[10:8] + #define SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1 Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_B1_DQ11 (DDRPHY_AO_BASE_ADDRESS + 0x0A00) + #define SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1 Fld(1, 3) //[3:3] + #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1 Fld(1, 5) //[5:5] + #define SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1 Fld(1, 7) //[7:7] + #define SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1 Fld(4, 8) //[11:8] + #define SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1 Fld(2, 16) //[17:16] + #define SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1 Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_B1_DQ7 (DDRPHY_AO_BASE_ADDRESS + 0x0A04) + #define SHU_B1_DQ7_R_DMRANKRXDVS_B1 Fld(4, 0) //[3:0] + #define SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ7_R_DMDQMDBI_SHU_B1 Fld(1, 7) //[7:7] + #define SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 Fld(4, 8) //[11:8] + #define SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 Fld(1, 12) //[12:12] + #define SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DQ7_R_DMRODTEN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 Fld(1, 17) //[17:17] + #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 Fld(1, 18) //[18:18] + #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 Fld(3, 25) //[27:25] + #define SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1 Fld(1, 28) //[28:28] + #define SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_B1_DQ8 (DDRPHY_AO_BASE_ADDRESS + 0x0A08) + #define SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 Fld(15, 0) //[14:0] + #define SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 Fld(1, 21) //[21:21] + #define SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 Fld(1, 22) //[22:22] + #define SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 Fld(1, 23) //[23:23] + #define SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 Fld(1, 26) //[26:26] + #define SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 Fld(1, 27) //[27:27] + #define SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 Fld(1, 28) //[28:28] + #define SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 Fld(1, 29) //[29:29] + #define SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 Fld(1, 30) //[30:30] + #define SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B1_DQ9 (DDRPHY_AO_BASE_ADDRESS + 0x0A0C) + #define SHU_B1_DQ9_RG_ARPI_RESERVE_B1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_B1_DQ12 (DDRPHY_AO_BASE_ADDRESS + 0x0A10) + #define SHU_B1_DQ12_DMY_DQ12_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_B1_DLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0A14) + #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1 Fld(3, 0) //[2:0] + #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1 Fld(3, 4) //[6:4] + #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1 Fld(1, 8) //[8:8] + #define SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1 Fld(4, 12) //[15:12] + #define SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1 Fld(3, 17) //[19:17] + #define SHU_B1_DLL0_RG_ARDLL_GAIN_B1 Fld(4, 20) //[23:20] + #define SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 Fld(1, 25) //[25:25] + #define SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1 Fld(1, 26) //[26:26] + #define SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1 Fld(1, 27) //[27:27] + +#define DDRPHY_REG_SHU_B1_DLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0A18) + #define SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1 Fld(2, 2) //[3:2] + #define SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1 Fld(1, 5) //[5:5] + #define SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1 Fld(1, 7) //[7:7] + #define SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1 Fld(2, 8) //[9:8] + #define SHU_B1_DLL1_RG_ARDLL_PS_EN_B1 Fld(1, 10) //[10:10] + #define SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DLL1_RG_ARDLL_PHDIV_B1 Fld(1, 12) //[12:12] + #define SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1 Fld(2, 18) //[19:18] + #define SHU_B1_DLL1_RG_ARDLL_PGAIN_B1 Fld(4, 20) //[23:20] + #define SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 Fld(1, 24) //[24:24] + +#define DDRPHY_REG_SHU_B1_DLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0A1C) + #define SHU_B1_DLL2_RG_ARDQ_REV_B1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0A20) + #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B1 Fld(3, 0) //[2:0] + #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B1 Fld(3, 4) //[6:4] + #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1 Fld(3, 16) //[18:16] + #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1 Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_B1_DLL_ARPI2 (DDRPHY_AO_BASE_ADDRESS + 0x0A24) + #define SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 Fld(1, 10) //[10:10] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1 Fld(1, 17) //[17:17] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1 Fld(1, 27) //[27:27] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B1_DLL_ARPI3 (DDRPHY_AO_BASE_ADDRESS + 0x0A28) + #define SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1 Fld(1, 17) //[17:17] + #define SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 Fld(1, 19) //[19:19] + +#define DDRPHY_REG_SHU_B1_TXDUTY (DDRPHY_AO_BASE_ADDRESS + 0x0A2C) + #define SHU_B1_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B1 Fld(6, 0) //[5:0] + #define SHU_B1_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B1 Fld(6, 8) //[13:8] + #define SHU_B1_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B1 Fld(6, 16) //[21:16] + #define SHU_B1_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B1 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_SHU_B1_VREF (DDRPHY_AO_BASE_ADDRESS + 0x0A30) + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_SEL_DQS_B1 Fld(7, 0) //[6:0] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_UB_RK1_B1 Fld(1, 17) //[17:17] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_UB_RK0_B1 Fld(1, 18) //[18:18] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_LB_RK1_B1 Fld(1, 19) //[19:19] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_LB_RK0_B1 Fld(1, 20) //[20:20] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_DQS_B1 Fld(1, 21) //[21:21] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1 Fld(1, 22) //[22:22] + +#define DDRPHY_REG_SHU_B1_DQ13 (DDRPHY_AO_BASE_ADDRESS + 0x0A34) + #define SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 Fld(1, 3) //[3:3] + #define SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1 Fld(1, 5) //[5:5] + #define SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1 Fld(1, 7) //[7:7] + #define SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1 Fld(1, 8) //[8:8] + #define SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1 Fld(2, 12) //[13:12] + #define SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1 Fld(1, 17) //[17:17] + #define SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1 Fld(1, 18) //[18:18] + #define SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1 Fld(1, 25) //[25:25] + +#define DDRPHY_REG_SHU_B1_DQ14 (DDRPHY_AO_BASE_ADDRESS + 0x0A38) + #define SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1 Fld(2, 4) //[5:4] + #define SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1 Fld(1, 9) //[9:9] + #define SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1 Fld(1, 10) //[10:10] + #define SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1 Fld(8, 16) //[23:16] + +#define DDRPHY_REG_B1_SHU_MIDPI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0A3C) + #define B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1 Fld(1, 0) //[0:0] + #define B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1 Fld(1, 1) //[1:1] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x0A60) + #define SHU_R0_CA_TXDLY0_TX_ARCA0_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY0_TX_ARCA1_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_TXDLY0_TX_ARCA2_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_TXDLY0_TX_ARCA3_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x0A64) + #define SHU_R0_CA_TXDLY1_TX_ARCA4_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY1_TX_ARCA5_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_TXDLY1_TX_ARCA6_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_TXDLY1_TX_ARCA7_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x0A68) + #define SHU_R0_CA_TXDLY2_TX_ARCKE0_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY2_TX_ARCKE1_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_TXDLY2_TX_ARCKE2_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_TXDLY2_TX_ARCS0_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x0A6C) + #define SHU_R0_CA_TXDLY3_TX_ARCS1_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY3_TX_ARCS2_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_TXDLY3_TX_ARCLK_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_TXDLY3_TX_ARCLKB_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0A70) + #define SHU_R0_CA_TXDLY4_TX_ARCLK_DLYB Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY4_TX_ARCLKB_DLYB Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x0A74) + #define SHU_R0_CA_RXDLY0_RG_RX_ARCA0_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY0_RG_RX_ARCA0_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY0_RG_RX_ARCA1_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY0_RG_RX_ARCA1_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x0A78) + #define SHU_R0_CA_RXDLY1_RG_RX_ARCA2_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY1_RG_RX_ARCA2_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY1_RG_RX_ARCA3_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY1_RG_RX_ARCA3_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x0A7C) + #define SHU_R0_CA_RXDLY2_RG_RX_ARCA4_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY2_RG_RX_ARCA4_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY2_RG_RX_ARCA5_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY2_RG_RX_ARCA5_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY6 (DDRPHY_AO_BASE_ADDRESS + 0x0A80) + #define SHU_R0_CA_RXDLY6_RG_RX_ARCA6_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY6_RG_RX_ARCA6_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY6_RG_RX_ARCA7_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY6_RG_RX_ARCA7_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x0A84) + #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE0_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE0_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE1_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE1_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0A88) + #define SHU_R0_CA_RXDLY4_RG_RX_ARCKE2_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY4_RG_RX_ARCKE2_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY4_RG_RX_ARCS0_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY4_RG_RX_ARCS0_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY5 (DDRPHY_AO_BASE_ADDRESS + 0x0A8C) + #define SHU_R0_CA_RXDLY5_RG_RX_ARCS1_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY5_RG_RX_ARCS1_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY5_RG_RX_ARCS2_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY5_RG_RX_ARCS2_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY7 (DDRPHY_AO_BASE_ADDRESS + 0x0A90) + #define SHU_R0_CA_RXDLY7_RG_RX_ARCLK_R_DLY Fld(9, 0) //[8:0] + #define SHU_R0_CA_RXDLY7_RG_RX_ARCLK_F_DLY Fld(9, 16) //[24:16] + +#define DDRPHY_REG_SHU_R0_CA_CMD0 (DDRPHY_AO_BASE_ADDRESS + 0x0A94) + #define SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY Fld(3, 0) //[2:0] + #define SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY Fld(3, 4) //[6:4] + #define SHU_R0_CA_CMD0_RG_ARPI_CS Fld(6, 8) //[13:8] + #define SHU_R0_CA_CMD0_RG_ARPI_CMD Fld(6, 16) //[21:16] + #define SHU_R0_CA_CMD0_RG_ARPI_CLK Fld(6, 24) //[29:24] + #define SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA Fld(1, 30) //[30:30] + #define SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_R0_CA_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x0A98) + #define SHU_R0_CA_INI_UIPI_CURR_INI_PI_CA Fld(7, 0) //[6:0] + #define SHU_R0_CA_INI_UIPI_CURR_INI_UI_CA Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_CA_NEXT_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x0A9C) + #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_PI_CA Fld(7, 0) //[6:0] + #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_UI_CA Fld(8, 8) //[15:8] + #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_UI_P1_CA Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_RK_CA_DQSIEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0AA0) + #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_CA Fld(4, 0) //[3:0] + #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_CA Fld(4, 4) //[7:4] + #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_CA Fld(4, 16) //[19:16] + #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_CA Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_RK_CA_DQSIEN_PI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0AA4) + #define SHU_RK_CA_DQSIEN_PI_DLY_DQSIEN_PI_CA Fld(7, 0) //[6:0] + +#define DDRPHY_REG_SHU_RK_CA_RODTEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0AA8) + #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_CA Fld(3, 0) //[2:0] + #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_CA Fld(3, 4) //[6:4] + #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_CA Fld(3, 16) //[18:16] + #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_CA Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_RK_CA_CMD0 (DDRPHY_AO_BASE_ADDRESS + 0x0AAC) + #define SHU_RK_CA_CMD0_RG_RX_ARCA0_OFFC Fld(4, 0) //[3:0] + #define SHU_RK_CA_CMD0_RG_RX_ARCA1_OFFC Fld(4, 4) //[7:4] + #define SHU_RK_CA_CMD0_RG_RX_ARCA2_OFFC Fld(4, 8) //[11:8] + #define SHU_RK_CA_CMD0_RG_RX_ARCA3_OFFC Fld(4, 12) //[15:12] + #define SHU_RK_CA_CMD0_RG_RX_ARCA4_OFFC Fld(4, 16) //[19:16] + #define SHU_RK_CA_CMD0_RG_RX_ARCA5_OFFC Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_RK_CA_CMD1 (DDRPHY_AO_BASE_ADDRESS + 0x0AB0) + #define SHU_RK_CA_CMD1_RG_RX_ARCS0_OFFC Fld(4, 0) //[3:0] + #define SHU_RK_CA_CMD1_RG_RX_ARCS1_OFFC Fld(4, 4) //[7:4] + #define SHU_RK_CA_CMD1_RG_RX_ARCS2_OFFC Fld(4, 8) //[11:8] + #define SHU_RK_CA_CMD1_RG_RX_ARCKE0_OFFC Fld(4, 12) //[15:12] + #define SHU_RK_CA_CMD1_RG_RX_ARCKE1_OFFC Fld(4, 16) //[19:16] + #define SHU_RK_CA_CMD1_RG_RX_ARCKE2_OFFC Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_CA_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x0AB4) + #define SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB Fld(7, 0) //[6:0] + #define SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB Fld(7, 8) //[14:8] + +#define DDRPHY_REG_SHU_CA_CMD0 (DDRPHY_AO_BASE_ADDRESS + 0x0B60) + #define SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN Fld(1, 4) //[4:4] + #define SHU_CA_CMD0_RG_TX_ARCLK_DRVP_PRE Fld(3, 8) //[10:8] + #define SHU_CA_CMD0_RG_TX_ARCLK_DRVN_PRE Fld(3, 12) //[14:12] + #define SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN Fld(1, 20) //[20:20] + #define SHU_CA_CMD0_RG_TX_ARCMD_DRVP_PRE Fld(3, 24) //[26:24] + #define SHU_CA_CMD0_RG_TX_ARCMD_DRVN_PRE Fld(3, 28) //[30:28] + #define SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_CMD3 (DDRPHY_AO_BASE_ADDRESS + 0x0B64) + #define SHU_CA_CMD3_RG_TX_ARCLK_PU Fld(2, 0) //[1:0] + #define SHU_CA_CMD3_RG_TX_ARCLK_PU_PRE Fld(2, 2) //[3:2] + #define SHU_CA_CMD3_RG_TX_ARCLK_PDB Fld(2, 4) //[5:4] + #define SHU_CA_CMD3_RG_TX_ARCLK_PDB_PRE Fld(2, 6) //[7:6] + #define SHU_CA_CMD3_RG_TX_ARCMD_PU Fld(2, 8) //[9:8] + #define SHU_CA_CMD3_RG_TX_ARCMD_PU_PRE Fld(2, 10) //[11:10] + #define SHU_CA_CMD3_RG_TX_ARCMD_PDB Fld(2, 12) //[13:12] + #define SHU_CA_CMD3_RG_TX_ARCMD_PDB_PRE Fld(2, 14) //[15:14] + +#define DDRPHY_REG_SHU_CA_CMD4 (DDRPHY_AO_BASE_ADDRESS + 0x0B68) + #define SHU_CA_CMD4_RG_ARPI_AA_MCK_DL_CA Fld(6, 0) //[5:0] + #define SHU_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA Fld(6, 8) //[13:8] + #define SHU_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA Fld(6, 16) //[21:16] + +#define DDRPHY_REG_SHU_CA_CMD5 (DDRPHY_AO_BASE_ADDRESS + 0x0B6C) + #define SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL Fld(6, 0) //[5:0] + #define SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS Fld(1, 6) //[6:6] + #define SHU_CA_CMD5_RG_ARPI_FB_CA Fld(6, 8) //[13:8] + #define SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY Fld(3, 16) //[18:16] + #define SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY Fld(1, 19) //[19:19] + #define SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY Fld(4, 20) //[23:20] + #define SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_CA_CMD6 (DDRPHY_AO_BASE_ADDRESS + 0x0B70) + #define SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA Fld(6, 0) //[5:0] + #define SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA Fld(6, 6) //[11:6] + #define SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA Fld(7, 12) //[18:12] + #define SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA Fld(1, 20) //[20:20] + #define SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA Fld(1, 21) //[21:21] + #define SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA Fld(2, 22) //[23:22] + #define SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA Fld(1, 24) //[24:24] + #define SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA Fld(1, 25) //[25:25] + #define SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA Fld(1, 26) //[26:26] + #define SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA Fld(1, 27) //[27:27] + #define SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA Fld(1, 28) //[28:28] + #define SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE Fld(1, 29) //[29:29] + +#define DDRPHY_REG_SHU_CA_CMD1 (DDRPHY_AO_BASE_ADDRESS + 0x0B74) + #define SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA Fld(1, 1) //[1:1] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA Fld(1, 2) //[2:2] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA Fld(5, 8) //[12:8] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA Fld(2, 16) //[17:16] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA Fld(2, 22) //[23:22] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA Fld(2, 24) //[25:24] + #define SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA Fld(1, 26) //[26:26] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA Fld(1, 27) //[27:27] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_CMD2 (DDRPHY_AO_BASE_ADDRESS + 0x0B78) + #define SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA Fld(1, 4) //[4:4] + #define SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA Fld(1, 5) //[5:5] + #define SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA Fld(1, 6) //[6:6] + #define SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA Fld(1, 8) //[8:8] + #define SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA Fld(1, 9) //[9:9] + #define SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA Fld(1, 10) //[10:10] + #define SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA Fld(1, 11) //[11:11] + #define SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU Fld(1, 12) //[12:12] + #define SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA Fld(1, 13) //[13:13] + #define SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA Fld(1, 17) //[17:17] + +#define DDRPHY_REG_SHU_CA_CMD10 (DDRPHY_AO_BASE_ADDRESS + 0x0B7C) + #define SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_CG_EN_CA Fld(1, 1) //[1:1] + #define SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA Fld(1, 2) //[2:2] + #define SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA Fld(1, 3) //[3:3] + #define SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_RPST_HS_EN_CA Fld(1, 4) //[4:4] + #define SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA Fld(3, 8) //[10:8] + #define SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA Fld(1, 15) //[15:15] + #define SHU_CA_CMD10_RG_RX_ARCLK_DIFF_SWAP_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_CA_CMD11 (DDRPHY_AO_BASE_ADDRESS + 0x0B80) + #define SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA Fld(1, 1) //[1:1] + #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA Fld(1, 2) //[2:2] + #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA Fld(1, 3) //[3:3] + #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA Fld(1, 4) //[4:4] + #define SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA Fld(1, 5) //[5:5] + #define SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA Fld(1, 6) //[6:6] + #define SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA Fld(1, 7) //[7:7] + #define SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA Fld(4, 8) //[11:8] + #define SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA Fld(2, 16) //[17:16] + #define SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_CA_CMD7 (DDRPHY_AO_BASE_ADDRESS + 0x0B84) + #define SHU_CA_CMD7_R_DMRANKRXDVS_CA Fld(4, 0) //[3:0] + #define SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA Fld(1, 12) //[12:12] + #define SHU_CA_CMD7_R_DMRODTEN_CA Fld(1, 15) //[15:15] + #define SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW Fld(1, 17) //[17:17] + #define SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW Fld(1, 19) //[19:19] + #define SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK Fld(1, 20) //[20:20] + #define SHU_CA_CMD7_R_DMRXRANK_CMD_EN Fld(1, 24) //[24:24] + #define SHU_CA_CMD7_R_DMRXRANK_CMD_LAT Fld(3, 25) //[27:25] + #define SHU_CA_CMD7_R_DMRXRANK_CLK_EN Fld(1, 28) //[28:28] + #define SHU_CA_CMD7_R_DMRXRANK_CLK_LAT Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_CA_CMD8 (DDRPHY_AO_BASE_ADDRESS + 0x0B88) + #define SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA Fld(15, 0) //[14:0] + #define SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA Fld(1, 15) //[15:15] + #define SHU_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA Fld(1, 19) //[19:19] + #define SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA Fld(1, 20) //[20:20] + #define SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA Fld(1, 21) //[21:21] + #define SHU_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA Fld(1, 22) //[22:22] + #define SHU_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA Fld(1, 23) //[23:23] + #define SHU_CA_CMD8_R_DMRXDLY_CG_IG_CA Fld(1, 24) //[24:24] + #define SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA Fld(1, 26) //[26:26] + #define SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA Fld(1, 27) //[27:27] + #define SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA Fld(1, 28) //[28:28] + #define SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA Fld(1, 29) //[29:29] + #define SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA Fld(1, 30) //[30:30] + #define SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_CMD9 (DDRPHY_AO_BASE_ADDRESS + 0x0B8C) + #define SHU_CA_CMD9_RG_ARPI_RESERVE_CA Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_CA_CMD12 (DDRPHY_AO_BASE_ADDRESS + 0x0B90) + #define SHU_CA_CMD12_RG_RIMP_REV Fld(8, 0) //[7:0] + #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN Fld(7, 8) //[14:8] + #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN Fld(7, 16) //[22:16] + #define SHU_CA_CMD12_RG_RIMP_DRV05 Fld(1, 23) //[23:23] + #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP Fld(7, 24) //[30:24] + #define SHU_CA_CMD12_RG_RIMP_UNTERM_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_DLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0B94) + #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA Fld(3, 0) //[2:0] + #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA Fld(3, 4) //[6:4] + #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA Fld(1, 8) //[8:8] + #define SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA Fld(4, 12) //[15:12] + #define SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA Fld(3, 17) //[19:17] + #define SHU_CA_DLL0_RG_ARDLL_GAIN_CA Fld(4, 20) //[23:20] + #define SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA Fld(1, 24) //[24:24] + #define SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA Fld(1, 25) //[25:25] + #define SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA Fld(1, 26) //[26:26] + #define SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA Fld(1, 27) //[27:27] + +#define DDRPHY_REG_SHU_CA_DLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0B98) + #define SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA Fld(1, 0) //[0:0] + #define SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA Fld(2, 2) //[3:2] + #define SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA Fld(1, 4) //[4:4] + #define SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA Fld(1, 5) //[5:5] + #define SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA Fld(1, 6) //[6:6] + #define SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA Fld(1, 7) //[7:7] + #define SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA Fld(2, 8) //[9:8] + #define SHU_CA_DLL1_RG_ARDLL_PS_EN_CA Fld(1, 10) //[10:10] + #define SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA Fld(1, 11) //[11:11] + #define SHU_CA_DLL1_RG_ARDLL_PHDIV_CA Fld(1, 12) //[12:12] + #define SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA Fld(1, 13) //[13:13] + #define SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA Fld(1, 14) //[14:14] + #define SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA Fld(2, 18) //[19:18] + #define SHU_CA_DLL1_RG_ARDLL_PGAIN_CA Fld(4, 20) //[23:20] + #define SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA Fld(1, 24) //[24:24] + +#define DDRPHY_REG_SHU_CA_DLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0B9C) + #define SHU_CA_DLL2_RG_ARCMD_REV Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_CA_RANK_SELPH_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0BA0) + #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_CA Fld(3, 0) //[2:0] + #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_CA Fld(3, 4) //[6:4] + #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_CA Fld(3, 16) //[18:16] + #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_CA Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_CA_DLL_ARPI2 (DDRPHY_AO_BASE_ADDRESS + 0x0BA4) + #define SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA Fld(1, 10) //[10:10] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN Fld(1, 11) //[11:11] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD Fld(1, 13) //[13:13] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK Fld(1, 15) //[15:15] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS Fld(1, 16) //[16:16] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA Fld(1, 17) //[17:17] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA Fld(1, 19) //[19:19] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA Fld(1, 27) //[27:27] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_DLL_ARPI3 (DDRPHY_AO_BASE_ADDRESS + 0x0BA8) + #define SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN Fld(1, 11) //[11:11] + #define SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN Fld(1, 13) //[13:13] + #define SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN Fld(1, 15) //[15:15] + #define SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN Fld(1, 16) //[16:16] + #define SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA Fld(1, 17) //[17:17] + #define SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA Fld(1, 19) //[19:19] + +#define DDRPHY_REG_SHU_CA_TXDUTY (DDRPHY_AO_BASE_ADDRESS + 0x0BAC) + #define SHU_CA_TXDUTY_DA_TX_ARCA_DUTY_DLY Fld(6, 0) //[5:0] + #define SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY Fld(6, 8) //[13:8] + #define SHU_CA_TXDUTY_DA_TX_ARCS_DUTY_DLY Fld(6, 16) //[21:16] + +#define DDRPHY_REG_SHU_CA_VREF (DDRPHY_AO_BASE_ADDRESS + 0x0BB0) + #define SHU_CA_VREF_RG_RX_ARCA_VREF_SEL_CLK_CA Fld(7, 0) //[6:0] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_RANK_SEL_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_UB_RK1_CA Fld(1, 17) //[17:17] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_UB_RK0_CA Fld(1, 18) //[18:18] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_LB_RK1_CA Fld(1, 19) //[19:19] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_LB_RK0_CA Fld(1, 20) //[20:20] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_CLK_CA Fld(1, 21) //[21:21] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA Fld(1, 22) //[22:22] + +#define DDRPHY_REG_SHU_CA_CMD13 (DDRPHY_AO_BASE_ADDRESS + 0x0BB4) + #define SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA Fld(1, 1) //[1:1] + #define SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA Fld(1, 2) //[2:2] + #define SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA Fld(1, 3) //[3:3] + #define SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA Fld(1, 5) //[5:5] + #define SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA Fld(1, 6) //[6:6] + #define SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA Fld(1, 7) //[7:7] + #define SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA Fld(1, 8) //[8:8] + #define SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA Fld(2, 12) //[13:12] + #define SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA Fld(1, 14) //[14:14] + #define SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA Fld(1, 15) //[15:15] + #define SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA Fld(1, 17) //[17:17] + #define SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA Fld(1, 18) //[18:18] + #define SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA Fld(1, 19) //[19:19] + #define SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA Fld(1, 20) //[20:20] + #define SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA Fld(1, 24) //[24:24] + #define SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA Fld(1, 25) //[25:25] + +#define DDRPHY_REG_SHU_CA_CMD14 (DDRPHY_AO_BASE_ADDRESS + 0x0BB8) + #define SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA Fld(2, 4) //[5:4] + #define SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA Fld(1, 6) //[6:6] + #define SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA Fld(1, 9) //[9:9] + #define SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA Fld(1, 10) //[10:10] + #define SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA Fld(1, 11) //[11:11] + #define SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA Fld(8, 16) //[23:16] + +#define DDRPHY_REG_CA_SHU_MIDPI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0BBC) + #define CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA Fld(1, 0) //[0:0] + #define CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA Fld(1, 1) //[1:1] + +#define DDRPHY_REG_MISC_SHU_RK_DQSCTL (DDRPHY_AO_BASE_ADDRESS + 0x0BE0) + #define MISC_SHU_RK_DQSCTL_DQSINCTL Fld(4, 0) //[3:0] + +#define DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0BE4) + #define MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT Fld(3, 0) //[2:0] + #define MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT Fld(3, 4) //[6:4] + +#define DDRPHY_REG_MISC_SHU_RK_DQSCAL (DDRPHY_AO_BASE_ADDRESS + 0x0BE8) + #define MISC_SHU_RK_DQSCAL_DQSIENLLMT Fld(7, 0) //[6:0] + #define MISC_SHU_RK_DQSCAL_DQSIENLLMTEN Fld(1, 7) //[7:7] + #define MISC_SHU_RK_DQSCAL_DQSIENHLMT Fld(7, 8) //[14:8] + #define MISC_SHU_RK_DQSCAL_DQSIENHLMTEN Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_SHU_DRVING7 (DDRPHY_AO_BASE_ADDRESS + 0x0CE0) + #define MISC_SHU_DRVING7_WCK0_DRVN Fld(5, 0) //[4:0] + #define MISC_SHU_DRVING7_WCK0_DRVP Fld(5, 8) //[12:8] + #define MISC_SHU_DRVING7_WCK1_DRVN Fld(5, 16) //[20:16] + #define MISC_SHU_DRVING7_WCK1_DRVP Fld(5, 24) //[28:24] + +#define DDRPHY_REG_MISC_SHU_DRVING8 (DDRPHY_AO_BASE_ADDRESS + 0x0CE4) + #define MISC_SHU_DRVING8_CS_DRVN Fld(5, 0) //[4:0] + #define MISC_SHU_DRVING8_CS_DRVP Fld(5, 8) //[12:8] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET1 (DDRPHY_AO_BASE_ADDRESS + 0x0CE8) + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET2 (DDRPHY_AO_BASE_ADDRESS + 0x0CEC) + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET3 (DDRPHY_AO_BASE_ADDRESS + 0x0CF0) + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET4 (DDRPHY_AO_BASE_ADDRESS + 0x0CF4) + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET5 (DDRPHY_AO_BASE_ADDRESS + 0x0CF8) + #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVN_OFF_SUB Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET6 (DDRPHY_AO_BASE_ADDRESS + 0x0CFC) + #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVN_OFF_SUB Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET7 (DDRPHY_AO_BASE_ADDRESS + 0x0D00) + #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVN_OFF_SUB Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET8 (DDRPHY_AO_BASE_ADDRESS + 0x0D04) + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET9 (DDRPHY_AO_BASE_ADDRESS + 0x0D08) + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1 (DDRPHY_AO_BASE_ADDRESS + 0x0D0C) + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS Fld(1, 0) //[0:0] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS Fld(1, 1) //[1:1] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS Fld(1, 2) //[2:2] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS Fld(1, 4) //[4:4] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS Fld(1, 5) //[5:5] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS Fld(1, 6) //[6:6] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS Fld(1, 8) //[8:8] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS Fld(1, 9) //[9:9] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS Fld(1, 10) //[10:10] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS Fld(1, 12) //[12:12] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS Fld(1, 13) //[13:13] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS Fld(1, 14) //[14:14] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS Fld(1, 16) //[16:16] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS Fld(1, 17) //[17:17] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS Fld(1, 18) //[18:18] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS Fld(1, 20) //[20:20] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS Fld(1, 21) //[21:21] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS Fld(1, 22) //[22:22] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS Fld(1, 28) //[28:28] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS Fld(1, 29) //[29:29] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS Fld(1, 30) //[30:30] + +#define DDRPHY_REG_SHU_MISC_SW_IMPCAL (DDRPHY_AO_BASE_ADDRESS + 0x0D10) + #define SHU_MISC_SW_IMPCAL_IMPODTN Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_SHU_STBCAL (DDRPHY_AO_BASE_ADDRESS + 0x0D14) + #define MISC_SHU_STBCAL_DMSTBLAT Fld(4, 0) //[3:0] + #define MISC_SHU_STBCAL_PICGLAT Fld(3, 4) //[6:4] + #define MISC_SHU_STBCAL_DQSG_MODE Fld(1, 8) //[8:8] + #define MISC_SHU_STBCAL_DQSIEN_PICG_MODE Fld(1, 9) //[9:9] + #define MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE Fld(2, 12) //[13:12] + #define MISC_SHU_STBCAL_DQSIEN_BURST_MODE Fld(1, 14) //[14:14] + #define MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN Fld(1, 15) //[15:15] + #define MISC_SHU_STBCAL_STBCALEN Fld(1, 16) //[16:16] + #define MISC_SHU_STBCAL_STB_SELPHCALEN Fld(1, 17) //[17:17] + #define MISC_SHU_STBCAL_DQSIEN_4TO1_EN Fld(1, 20) //[20:20] + #define MISC_SHU_STBCAL_DQSIEN_8TO1_EN Fld(1, 21) //[21:21] + #define MISC_SHU_STBCAL_DQSIEN_16TO1_EN Fld(1, 22) //[22:22] + +#define DDRPHY_REG_MISC_SHU_STBCAL1 (DDRPHY_AO_BASE_ADDRESS + 0x0D18) + #define MISC_SHU_STBCAL1_DLLFRZRFCOPT Fld(2, 0) //[1:0] + #define MISC_SHU_STBCAL1_DLLFRZWROPT Fld(2, 4) //[5:4] + #define MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT Fld(3, 8) //[10:8] + #define MISC_SHU_STBCAL1_STB_UPDMASK_EN Fld(1, 11) //[11:11] + #define MISC_SHU_STBCAL1_STB_UPDMASKCYC Fld(4, 12) //[15:12] + #define MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL Fld(1, 16) //[16:16] + #define MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO Fld(6, 20) //[25:20] + +#define DDRPHY_REG_MISC_SHU_DVFSDLL (DDRPHY_AO_BASE_ADDRESS + 0x0D1C) + #define MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL Fld(1, 0) //[0:0] + #define MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL Fld(1, 1) //[1:1] + #define MISC_SHU_DVFSDLL_R_DLL_IDLE Fld(7, 4) //[10:4] + #define MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE Fld(7, 16) //[22:16] + +#define DDRPHY_REG_MISC_SHU_RANKCTL (DDRPHY_AO_BASE_ADDRESS + 0x0D20) + #define MISC_SHU_RANKCTL_RANKINCTL_RXDLY Fld(4, 0) //[3:0] + #define MISC_SHU_RANKCTL_RANK_RXDLY_OPT Fld(1, 4) //[4:4] + #define MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN Fld(1, 15) //[15:15] + #define MISC_SHU_RANKCTL_RANKINCTL_STB Fld(4, 16) //[19:16] + #define MISC_SHU_RANKCTL_RANKINCTL Fld(4, 20) //[23:20] + #define MISC_SHU_RANKCTL_RANKINCTL_ROOT1 Fld(4, 24) //[27:24] + #define MISC_SHU_RANKCTL_RANKINCTL_PHY Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_SHU_PHY_RX_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D24) + #define MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN Fld(1, 8) //[8:8] + #define MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET Fld(3, 9) //[11:9] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET Fld(2, 14) //[15:14] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD Fld(3, 16) //[18:16] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL Fld(3, 20) //[22:20] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD Fld(3, 24) //[26:24] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL Fld(3, 28) //[30:28] + +#define DDRPHY_REG_MISC_SHU_ODTCTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D28) + #define MISC_SHU_ODTCTRL_RODTEN Fld(1, 0) //[0:0] + #define MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG Fld(1, 1) //[1:1] + #define MISC_SHU_ODTCTRL_RODT_LAT Fld(4, 4) //[7:4] + #define MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN Fld(1, 15) //[15:15] + #define MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT Fld(2, 24) //[25:24] + #define MISC_SHU_ODTCTRL_FIXRODT Fld(1, 27) //[27:27] + #define MISC_SHU_ODTCTRL_RODTEN_OPT Fld(1, 29) //[29:29] + #define MISC_SHU_ODTCTRL_RODTE2 Fld(1, 30) //[30:30] + #define MISC_SHU_ODTCTRL_RODTE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_SHU_RODTENSTB (DDRPHY_AO_BASE_ADDRESS + 0x0D2C) + #define MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN Fld(1, 0) //[0:0] + #define MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE Fld(1, 1) //[1:1] + #define MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN Fld(1, 2) //[2:2] + #define MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL Fld(1, 3) //[3:3] + #define MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE Fld(1, 4) //[4:4] + #define MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME Fld(1, 5) //[5:5] + #define MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET Fld(4, 8) //[11:8] + #define MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET Fld(4, 12) //[15:12] + #define MISC_SHU_RODTENSTB_RODTENSTB_EXT Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_SHU_RODTENSTB1 (DDRPHY_AO_BASE_ADDRESS + 0x0D30) + #define MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD Fld(2, 4) //[5:4] + #define MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL Fld(2, 6) //[7:6] + +#define DDRPHY_REG_MISC_SHU_DQSG_RETRY1 (DDRPHY_AO_BASE_ADDRESS + 0x0D34) + #define MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET Fld(1, 0) //[0:0] + #define MISC_SHU_DQSG_RETRY1_RETRY_SW_EN Fld(1, 1) //[1:1] + #define MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS Fld(1, 2) //[2:2] + #define MISC_SHU_DQSG_RETRY1_RETRY_ONCE Fld(1, 3) //[3:3] + #define MISC_SHU_DQSG_RETRY1_RETRY_3TIMES Fld(1, 4) //[4:4] + #define MISC_SHU_DQSG_RETRY1_RETRY_1RANK Fld(1, 5) //[5:5] + #define MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK Fld(1, 6) //[6:6] + #define MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE Fld(1, 7) //[7:7] + #define MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT Fld(4, 8) //[11:8] + #define MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE Fld(1, 12) //[12:12] + #define MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN Fld(1, 13) //[13:13] + #define MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE Fld(1, 14) //[14:14] + #define MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA Fld(1, 15) //[15:15] + #define MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK Fld(1, 20) //[20:20] + #define MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE Fld(1, 21) //[21:21] + #define MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND Fld(1, 22) //[22:22] + #define MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING Fld(1, 23) //[23:23] + #define MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM Fld(2, 24) //[25:24] + #define MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY Fld(1, 28) //[28:28] + #define MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE Fld(1, 29) //[29:29] + #define MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK Fld(1, 30) //[30:30] + #define MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_SHU_RDAT (DDRPHY_AO_BASE_ADDRESS + 0x0D38) + #define MISC_SHU_RDAT_DATLAT Fld(5, 0) //[4:0] + #define MISC_SHU_RDAT_DATLAT_DSEL Fld(5, 8) //[12:8] + #define MISC_SHU_RDAT_DATLAT_DSEL_PHY Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_SHU_RDAT1 (DDRPHY_AO_BASE_ADDRESS + 0x0D3C) + #define MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT Fld(1, 0) //[0:0] + #define MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT Fld(1, 1) //[1:1] + #define MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT Fld(1, 2) //[2:2] + #define MISC_SHU_RDAT1_RDATDIV2 Fld(1, 4) //[4:4] + #define MISC_SHU_RDAT1_RDATDIV4 Fld(1, 5) //[5:5] + +#define DDRPHY_REG_SHU_MISC_CLK_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0D40) + #define SHU_MISC_CLK_CTRL0_FMEM_CK_CG_DRAMC_DLL_DIS Fld(1, 0) //[0:0] + #define SHU_MISC_CLK_CTRL0_RESERVED_MISC_CLK_CTRL0_BIT3_1 Fld(3, 1) //[3:1] + #define SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL Fld(1, 4) //[4:4] + #define SHU_MISC_CLK_CTRL0_RESERVED_MISC_CLK_CTRL0_BIT31_5 Fld(27, 5) //[31:5] + +#define DDRPHY_REG_SHU_MISC_IMPCAL1 (DDRPHY_AO_BASE_ADDRESS + 0x0D44) + #define SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE Fld(3, 0) //[2:0] + #define SHU_MISC_IMPCAL1_IMPDRVP Fld(5, 4) //[8:4] + #define SHU_MISC_IMPCAL1_IMPDRVN Fld(5, 12) //[16:12] + #define SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE Fld(3, 17) //[19:17] + #define SHU_MISC_IMPCAL1_IMPCALCNT Fld(8, 20) //[27:20] + #define SHU_MISC_IMPCAL1_IMPCAL_CALICNT Fld(4, 28) //[31:28] + +#define DDRPHY_REG_SHU_MISC_DRVING1 (DDRPHY_AO_BASE_ADDRESS + 0x0D48) + #define SHU_MISC_DRVING1_DQDRVN2 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING1_DQDRVP2 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING1_DQSDRVN1 Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING1_DQSDRVP1 Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING1_DQSDRVN2 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING1_DQSDRVP2 Fld(5, 25) //[29:25] + #define SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK Fld(1, 30) //[30:30] + #define SHU_MISC_DRVING1_DIS_IMPCAL_HW Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_MISC_DRVING2 (DDRPHY_AO_BASE_ADDRESS + 0x0D4C) + #define SHU_MISC_DRVING2_CMDDRVN1 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING2_CMDDRVP1 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING2_CMDDRVN2 Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING2_CMDDRVP2 Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING2_DQDRVN1 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING2_DQDRVP1 Fld(5, 25) //[29:25] + #define SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_MISC_DRVING3 (DDRPHY_AO_BASE_ADDRESS + 0x0D50) + #define SHU_MISC_DRVING3_DQODTN2 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING3_DQODTP2 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING3_DQSODTN Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING3_DQSODTP Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING3_DQSODTN2 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING3_DQSODTP2 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_SHU_MISC_DRVING4 (DDRPHY_AO_BASE_ADDRESS + 0x0D54) + #define SHU_MISC_DRVING4_CMDODTN1 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING4_CMDODTP1 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING4_CMDODTN2 Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING4_CMDODTP2 Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING4_DQODTN1 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING4_DQODTP1 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_SHU_MISC_DRVING5 (DDRPHY_AO_BASE_ADDRESS + 0x0D58) + #define SHU_MISC_DRVING5_DQCODTN2 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING5_DQCODTP2 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING5_DQCDRVN1 Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING5_DQCDRVP1 Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING5_DQCDRVN2 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING5_DQCDRVP2 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_SHU_MISC_DRVING6 (DDRPHY_AO_BASE_ADDRESS + 0x0D5C) + #define SHU_MISC_DRVING6_IMP_TXDLY_CMD Fld(6, 0) //[5:0] + #define SHU_MISC_DRVING6_DQCODTN1 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING6_DQCODTP1 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_SHU_MISC_DUTY_SCAN (DDRPHY_AO_BASE_ADDRESS + 0x0D60) + #define SHU_MISC_DUTY_SCAN_R_DMFREQDIV2 Fld(1, 0) //[0:0] + #define SHU_MISC_DUTY_SCAN_R_DM64BITEN Fld(1, 1) //[1:1] + +#define DDRPHY_REG_SHU_MISC_DMA (DDRPHY_AO_BASE_ADDRESS + 0x0D64) + #define SHU_MISC_DMA_SRAM_RL_2T Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_MISC_RVREF (DDRPHY_AO_BASE_ADDRESS + 0x0D68) + #define SHU_MISC_RVREF_RG_RVREF_SEL_DQ Fld(6, 16) //[21:16] + #define SHU_MISC_RVREF_RG_RVREF_DDR4_SEL Fld(1, 22) //[22:22] + #define SHU_MISC_RVREF_RG_RVREF_DDR3_SEL Fld(1, 23) //[23:23] + #define SHU_MISC_RVREF_RG_RVREF_SEL_CMD Fld(6, 24) //[29:24] + +#define DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D6C) + #define SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D70) + #define SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN Fld(1, 0) //[0:0] + #define SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN Fld(1, 1) //[1:1] + #define SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN Fld(1, 2) //[2:2] + #define SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN Fld(1, 3) //[3:3] + #define SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS Fld(1, 8) //[8:8] + +#define DDRPHY_REG_SHU_MISC_EMI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D74) + #define SHU_MISC_EMI_CTRL_DR_EMI_RESERVE Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_MISC_RANK_SEL_STB (DDRPHY_AO_BASE_ADDRESS + 0x0D78) + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN Fld(1, 0) //[0:0] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23 Fld(1, 1) //[1:1] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE Fld(2, 2) //[3:2] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK Fld(1, 4) //[4:4] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK Fld(1, 5) //[5:5] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN Fld(1, 7) //[7:7] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL Fld(4, 8) //[11:8] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS Fld(4, 16) //[19:16] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS Fld(4, 20) //[23:20] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS Fld(4, 24) //[27:24] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS Fld(4, 28) //[31:28] + +#define DDRPHY_REG_SHU_MISC_RDSEL_TRACK (DDRPHY_AO_BASE_ADDRESS + 0x0D7C) + #define SHU_MISC_RDSEL_TRACK_DMDATLAT_I Fld(5, 0) //[4:0] + #define SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK Fld(1, 6) //[6:6] + #define SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN Fld(1, 7) //[7:7] + #define SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG Fld(12, 8) //[19:8] + #define SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS Fld(12, 20) //[31:20] + +#define DDRPHY_REG_SHU_MISC_PRE_TDQSCK (DDRPHY_AO_BASE_ADDRESS + 0x0D80) + #define SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_MISC_ASYNC_FIFO_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D84) + #define SHU_MISC_ASYNC_FIFO_CTRL_ASYNC_EN Fld(1, 0) //[0:0] + #define SHU_MISC_ASYNC_FIFO_CTRL_AFIFO_SYNCDEPTH Fld(2, 4) //[5:4] + +#define DDRPHY_REG_MISC_SHU_RX_SELPH_MODE (DDRPHY_AO_BASE_ADDRESS + 0x0D88) + #define MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE Fld(2, 0) //[1:0] + #define MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE Fld(2, 4) //[5:4] + #define MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE Fld(2, 6) //[7:6] + +#define DDRPHY_REG_MISC_SHU_RANK_SEL_LAT (DDRPHY_AO_BASE_ADDRESS + 0x0D8C) + #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0 Fld(4, 0) //[3:0] + #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1 Fld(4, 4) //[7:4] + #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA Fld(4, 8) //[11:8] + +#define DDRPHY_REG_MISC_SHU_DLINE_MON_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D90) + #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_TSHIFT Fld(2, 0) //[1:0] + #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_DIV Fld(2, 2) //[3:2] + #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_DLY Fld(7, 8) //[14:8] + #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_EN Fld(1, 16) //[16:16] + +#define DDRPHY_REG_MISC_SHU_DLINE_MON_CNT (DDRPHY_AO_BASE_ADDRESS + 0x0D94) + #define MISC_SHU_DLINE_MON_CNT_TRIG_DLINE_MON_CNT Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_SHU_MIDPI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D98) + #define MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE Fld(1, 0) //[0:0] + #define MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE Fld(1, 1) //[1:1] + +#define DDRPHY_REG_MISC_SHU_RX_CG_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0DA0) + #define MISC_SHU_RX_CG_CTRL_RX_DCM_OPT Fld(1, 0) //[0:0] + #define MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT Fld(1, 1) //[1:1] + #define MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT Fld(1, 2) //[2:2] + #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN Fld(1, 4) //[4:4] + #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN Fld(1, 5) //[5:5] + #define MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN Fld(1, 8) //[8:8] + #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN Fld(1, 9) //[9:9] + #define MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN Fld(1, 10) //[10:10] + #define MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY Fld(4, 16) //[19:16] + #define MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY Fld(4, 20) //[23:20] + +#define DDRPHY_REG_MISC_SHU_CG_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0DA4) + #define MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STBERR_ALL (DDRPHY_AO_BASE_ADDRESS + 0x1500) + #define MISC_STBERR_ALL_GATING_ERROR_ALL_RK0 Fld(1, 0) //[0:0] + #define MISC_STBERR_ALL_GATING_ERROR_B0_RK0 Fld(1, 1) //[1:1] + #define MISC_STBERR_ALL_GATING_ERROR_B1_RK0 Fld(1, 2) //[2:2] + #define MISC_STBERR_ALL_GATING_ERROR_CA_RK0 Fld(1, 3) //[3:3] + #define MISC_STBERR_ALL_GATING_ERROR_ALL_RK1 Fld(1, 4) //[4:4] + #define MISC_STBERR_ALL_GATING_ERROR_B0_RK1 Fld(1, 5) //[5:5] + #define MISC_STBERR_ALL_GATING_ERROR_B1_RK1 Fld(1, 6) //[6:6] + #define MISC_STBERR_ALL_GATING_ERROR_CA_RK1 Fld(1, 7) //[7:7] + #define MISC_STBERR_ALL_STBENERR_ALL Fld(1, 16) //[16:16] + #define MISC_STBERR_ALL_RX_ARDQ0_FIFO_STBEN_ERR_B0 Fld(1, 24) //[24:24] + #define MISC_STBERR_ALL_RX_ARDQ4_FIFO_STBEN_ERR_B0 Fld(1, 25) //[25:25] + #define MISC_STBERR_ALL_RX_ARDQ0_FIFO_STBEN_ERR_B1 Fld(1, 26) //[26:26] + #define MISC_STBERR_ALL_RX_ARDQ4_FIFO_STBEN_ERR_B1 Fld(1, 27) //[27:27] + #define MISC_STBERR_ALL_RX_ARCA0_FIFO_STBEN_ERR Fld(1, 28) //[28:28] + #define MISC_STBERR_ALL_RX_ARCA4_FIFO_STBEN_ERR Fld(1, 29) //[29:29] + +#define DDRPHY_REG_MISC_STBERR_RK0_R (DDRPHY_AO_BASE_ADDRESS + 0x1504) + #define MISC_STBERR_RK0_R_STBENERR_B0_RK0_R Fld(8, 0) //[7:0] + #define MISC_STBERR_RK0_R_STBENERR_B1_RK0_R Fld(8, 8) //[15:8] + #define MISC_STBERR_RK0_R_STBENERR_CA_RK0_R Fld(8, 16) //[23:16] + +#define DDRPHY_REG_MISC_STBERR_RK0_F (DDRPHY_AO_BASE_ADDRESS + 0x1508) + #define MISC_STBERR_RK0_F_STBENERR_B0_RK0_F Fld(8, 0) //[7:0] + #define MISC_STBERR_RK0_F_STBENERR_B1_RK0_F Fld(8, 8) //[15:8] + #define MISC_STBERR_RK0_F_STBENERR_CA_RK0_F Fld(8, 16) //[23:16] + +#define DDRPHY_REG_MISC_STBERR_RK1_R (DDRPHY_AO_BASE_ADDRESS + 0x150C) + #define MISC_STBERR_RK1_R_STBENERR_B0_RK1_R Fld(8, 0) //[7:0] + #define MISC_STBERR_RK1_R_STBENERR_B1_RK1_R Fld(8, 8) //[15:8] + #define MISC_STBERR_RK1_R_STBENERR_CA_RK1_R Fld(8, 16) //[23:16] + +#define DDRPHY_REG_MISC_STBERR_RK1_F (DDRPHY_AO_BASE_ADDRESS + 0x1510) + #define MISC_STBERR_RK1_F_STBENERR_B0_RK1_F Fld(8, 0) //[7:0] + #define MISC_STBERR_RK1_F_STBENERR_B1_RK1_F Fld(8, 8) //[15:8] + #define MISC_STBERR_RK1_F_STBENERR_CA_RK1_F Fld(8, 16) //[23:16] + +#define DDRPHY_REG_MISC_DDR_RESERVE_STATE (DDRPHY_AO_BASE_ADDRESS + 0x1520) + #define MISC_DDR_RESERVE_STATE_WDT_SM Fld(4, 0) //[3:0] + +#define DDRPHY_REG_MISC_IRQ_STATUS0 (DDRPHY_AO_BASE_ADDRESS + 0x1530) + #define MISC_IRQ_STATUS0_REFRATE_EN Fld(1, 0) //[0:0] + #define MISC_IRQ_STATUS0_REFPENDING_EN Fld(1, 1) //[1:1] + #define MISC_IRQ_STATUS0_PRE_REFRATE_EN Fld(1, 2) //[2:2] + #define MISC_IRQ_STATUS0_RTMRW_ABNORMAL_STOP_EN Fld(1, 3) //[3:3] + #define MISC_IRQ_STATUS0_SREF_REQ_NO_ACK_EN Fld(1, 6) //[6:6] + #define MISC_IRQ_STATUS0_SREF_REQ_SHORT_EN Fld(1, 7) //[7:7] + #define MISC_IRQ_STATUS0_SREF_REQ_DTRIG_EN Fld(1, 8) //[8:8] + #define MISC_IRQ_STATUS0_RTSWCMD_NONVALIDCMD_EN Fld(1, 12) //[12:12] + #define MISC_IRQ_STATUS0_TX_TRACKING1_EN Fld(1, 16) //[16:16] + #define MISC_IRQ_STATUS0_TX_TRACKING2_EN Fld(1, 17) //[17:17] + +#define DDRPHY_REG_MISC_IRQ_STATUS1 (DDRPHY_AO_BASE_ADDRESS + 0x1534) + #define MISC_IRQ_STATUS1_DRAMC_IRQ_OUT_1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_IRQ_STATUS2 (DDRPHY_AO_BASE_ADDRESS + 0x1538) + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_B0_EN Fld(1, 0) //[0:0] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_B0_EN Fld(1, 1) //[1:1] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_B1_EN Fld(1, 2) //[2:2] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_B1_EN Fld(1, 3) //[3:3] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_CA_EN Fld(1, 4) //[4:4] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_CA_EN Fld(1, 5) //[5:5] + #define MISC_IRQ_STATUS2_STB_GATTING_ERR_EN Fld(1, 7) //[7:7] + #define MISC_IRQ_STATUS2_RX_ARDQ0_FIFO_STBEN_ERR_B0_EN Fld(1, 8) //[8:8] + #define MISC_IRQ_STATUS2_RX_ARDQ4_FIFO_STBEN_ERR_B0_EN Fld(1, 9) //[9:9] + #define MISC_IRQ_STATUS2_RX_ARDQ0_FIFO_STBEN_ERR_B1_EN Fld(1, 10) //[10:10] + #define MISC_IRQ_STATUS2_RX_ARDQ4_FIFO_STBEN_ERR_B1_EN Fld(1, 11) //[11:11] + #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R1_B1_EN Fld(1, 12) //[12:12] + #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R1_B0_EN Fld(1, 13) //[13:13] + #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R0_B1_EN Fld(1, 14) //[14:14] + #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R0_B0_EN Fld(1, 15) //[15:15] + #define MISC_IRQ_STATUS2_IMP_CLK_ERR_EN Fld(1, 24) //[24:24] + #define MISC_IRQ_STATUS2_IMP_CMD_ERR_EN Fld(1, 25) //[25:25] + #define MISC_IRQ_STATUS2_IMP_DQ1_ERR_EN Fld(1, 26) //[26:26] + #define MISC_IRQ_STATUS2_IMP_DQ0_ERR_EN Fld(1, 27) //[27:27] + #define MISC_IRQ_STATUS2_IMP_DQS_ERR_EN Fld(1, 28) //[28:28] + #define MISC_IRQ_STATUS2_IMP_ODTN_ERR_EN Fld(1, 29) //[29:29] + #define MISC_IRQ_STATUS2_IMP_DRVN_ERR_EN Fld(1, 30) //[30:30] + #define MISC_IRQ_STATUS2_IMP_DRVP_ERR_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE0 (DDRPHY_AO_BASE_ADDRESS + 0x1600) + #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_RATE Fld(5, 0) //[4:0] + #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_QUEUE_CNT Fld(4, 8) //[11:8] + #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_RATE_CHG_QUEUE_CNT Fld(4, 12) //[15:12] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE1 (DDRPHY_AO_BASE_ADDRESS + 0x1604) + #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK0 Fld(5, 0) //[4:0] + #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK1 Fld(5, 8) //[12:8] + #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK0_B1 Fld(5, 16) //[20:16] + #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK1_B1 Fld(5, 24) //[28:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE2 (DDRPHY_AO_BASE_ADDRESS + 0x1608) + #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_DEC_ACC_CNT_RK0_B0 Fld(6, 0) //[5:0] + #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_INC_ACC_CNT_RK0_B0 Fld(6, 8) //[13:8] + #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_DEC_ACC_CNT_RK1_B0 Fld(6, 16) //[21:16] + #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_INC_ACC_CNT_RK1_B0 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE3 (DDRPHY_AO_BASE_ADDRESS + 0x160C) + #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_INI_PI_RK0_B0 Fld(7, 0) //[6:0] + #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_INI_UI_RK0_B0 Fld(8, 8) //[15:8] + #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_CUR_PI_RK0_B0 Fld(7, 16) //[22:16] + #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_CUR_UI_RK0_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE4 (DDRPHY_AO_BASE_ADDRESS + 0x1610) + #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_INI_PI_RK1_B0 Fld(7, 0) //[6:0] + #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_INI_UI_RK1_B0 Fld(8, 8) //[15:8] + #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_CUR_PI_RK1_B0 Fld(7, 16) //[22:16] + #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_CUR_UI_RK1_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE5 (DDRPHY_AO_BASE_ADDRESS + 0x1614) + #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_DEC_ACC_CNT_RK0_B1 Fld(6, 0) //[5:0] + #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_INC_ACC_CNT_RK0_B1 Fld(6, 8) //[13:8] + #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_DEC_ACC_CNT_RK1_B1 Fld(6, 16) //[21:16] + #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_INC_ACC_CNT_RK1_B1 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE6 (DDRPHY_AO_BASE_ADDRESS + 0x1618) + #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_INI_PI_RK0_B1 Fld(7, 0) //[6:0] + #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_INI_UI_RK0_B1 Fld(8, 8) //[15:8] + #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_CUR_PI_RK0_B1 Fld(7, 16) //[22:16] + #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_CUR_UI_RK0_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE7 (DDRPHY_AO_BASE_ADDRESS + 0x161C) + #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_INI_PI_RK1_B1 Fld(7, 0) //[6:0] + #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_INI_UI_RK1_B1 Fld(8, 8) //[15:8] + #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_CUR_PI_RK1_B1 Fld(7, 16) //[22:16] + #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_CUR_UI_RK1_B1 Fld(8, 24) //[31:24] + +#endif // __DDRPHY_AO_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h new file mode 100644 index 0000000000..726aecb7f5 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h @@ -0,0 +1,2900 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_MD32_REGS_H__ +#define __DDRPHY_MD32_REGS_H__ + +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x10940000 + +#define DDRPHY_MD32_BASE_ADDRESS Channel_A_DDRPHY_DPM_BASE_VIRTUAL + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN (DDRPHY_MD32_BASE_ADDRESS + 0x0000) + #define SSPM_CFGREG_SW_RSTN_SW_RSTN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RESOURCE_CTL (DDRPHY_MD32_BASE_ADDRESS + 0x0004) + #define SSPM_CFGREG_RESOURCE_CTL_APSRC_REQ Fld(1, 0) //[0:0] + #define SSPM_CFGREG_RESOURCE_CTL_APSRC_ACK Fld(1, 4) //[4:4] + #define SSPM_CFGREG_RESOURCE_CTL_INFRA_REQ Fld(1, 8) //[8:8] + #define SSPM_CFGREG_RESOURCE_CTL_INFRA_ACK Fld(1, 12) //[12:12] + #define SSPM_CFGREG_RESOURCE_CTL_SRCLKENA_REQ Fld(1, 16) //[16:16] + #define SSPM_CFGREG_RESOURCE_CTL_SRCLKENA_ACK Fld(1, 20) //[20:20] + #define SSPM_CFGREG_RESOURCE_CTL_DCS_ULTRA_REQ Fld(1, 24) //[24:24] + #define SSPM_CFGREG_RESOURCE_CTL_DCS_ULTRA_REQ_ACK Fld(1, 28) //[28:28] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SYS_RMAP (DDRPHY_MD32_BASE_ADDRESS + 0x0008) + #define SSPM_CFGREG_SYS_RMAP_SYS_RMAP Fld(4, 0) //[3:0] + #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP0 Fld(6, 4) //[9:4] + #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP1 Fld(6, 10) //[15:10] + #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP2 Fld(6, 16) //[21:16] + #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP3 Fld(6, 22) //[27:22] + #define SSPM_CFGREG_SYS_RMAP_BUS_ARB_POLICY Fld(1, 28) //[28:28] + #define SSPM_CFGREG_SYS_RMAP_H2H_POSTWRITE_DIS Fld(1, 29) //[29:29] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_OCD_BYPASS (DDRPHY_MD32_BASE_ADDRESS + 0x000C) + #define SSPM_CFGREG_OCD_BYPASS_OCD_BYPASS Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD2HOST_IPC (DDRPHY_MD32_BASE_ADDRESS + 0x0010) + #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC Fld(1, 0) //[0:0] + #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC1 Fld(1, 1) //[1:1] + #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC_INT Fld(1, 8) //[8:8] + #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC_INT1 Fld(1, 9) //[9:9] + #define SSPM_CFGREG_MD2HOST_IPC_WDT_INT Fld(1, 10) //[10:10] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD2SPM_IPC (DDRPHY_MD32_BASE_ADDRESS + 0x0014) + #define SSPM_CFGREG_MD2SPM_IPC_MD2SPM_IPC Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_HOST2MD_IPC (DDRPHY_MD32_BASE_ADDRESS + 0x0018) + #define SSPM_CFGREG_HOST2MD_IPC_HOST2MD_IPC Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SPM2MD_IPC (DDRPHY_MD32_BASE_ADDRESS + 0x001C) + #define SSPM_CFGREG_SPM2MD_IPC_SPM2MD_IPC Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR0 (DDRPHY_MD32_BASE_ADDRESS + 0x0020) + #define SSPM_CFGREG_GPR0_GPR0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR1 (DDRPHY_MD32_BASE_ADDRESS + 0x0024) + #define SSPM_CFGREG_GPR1_GPR1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR2 (DDRPHY_MD32_BASE_ADDRESS + 0x0028) + #define SSPM_CFGREG_GPR2_GPR2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR3 (DDRPHY_MD32_BASE_ADDRESS + 0x002C) + #define SSPM_CFGREG_GPR3_GPR3 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR4 (DDRPHY_MD32_BASE_ADDRESS + 0x0030) + #define SSPM_CFGREG_GPR4_GPR4 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR5 (DDRPHY_MD32_BASE_ADDRESS + 0x0034) + #define SSPM_CFGREG_GPR5_GPR5 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO (DDRPHY_MD32_BASE_ADDRESS + 0x0038) + #define SSPM_CFGREG_DVFS_INFO_DVFS_INFO_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TEMPERATURE (DDRPHY_MD32_BASE_ADDRESS + 0x003C) + #define SSPM_CFGREG_TEMPERATURE_TEMPERATURE Fld(15, 0) //[14:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_WDT_CFG (DDRPHY_MD32_BASE_ADDRESS + 0x0040) + #define SSPM_CFGREG_WDT_CFG_WDT_VAL Fld(20, 0) //[19:0] + #define SSPM_CFGREG_WDT_CFG_WDT_EN Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_WDT_KICK (DDRPHY_MD32_BASE_ADDRESS + 0x0044) + #define SSPM_CFGREG_WDT_KICK_WDT_KICK Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SEMAPHORE (DDRPHY_MD32_BASE_ADDRESS + 0x0048) + #define SSPM_CFGREG_SEMAPHORE_SEMA_0_M Fld(1, 0) //[0:0] + #define SSPM_CFGREG_SEMAPHORE_SEMA_0_H Fld(1, 1) //[1:1] + #define SSPM_CFGREG_SEMAPHORE_SEMA_1_M Fld(1, 2) //[2:2] + #define SSPM_CFGREG_SEMAPHORE_SEMA_1_H Fld(1, 3) //[3:3] + #define SSPM_CFGREG_SEMAPHORE_SEMA_2_M Fld(1, 4) //[4:4] + #define SSPM_CFGREG_SEMAPHORE_SEMA_2_H Fld(1, 5) //[5:5] + #define SSPM_CFGREG_SEMAPHORE_SEMA_3_M Fld(1, 6) //[6:6] + #define SSPM_CFGREG_SEMAPHORE_SEMA_3_H Fld(1, 7) //[7:7] + #define SSPM_CFGREG_SEMAPHORE_SEMA_4_M Fld(1, 8) //[8:8] + #define SSPM_CFGREG_SEMAPHORE_SEMA_4_H Fld(1, 9) //[9:9] + #define SSPM_CFGREG_SEMAPHORE_SEMA_5_M Fld(1, 10) //[10:10] + #define SSPM_CFGREG_SEMAPHORE_SEMA_5_H Fld(1, 11) //[11:11] + #define SSPM_CFGREG_SEMAPHORE_SEMA_6_M Fld(1, 12) //[12:12] + #define SSPM_CFGREG_SEMAPHORE_SEMA_6_H Fld(1, 13) //[13:13] + #define SSPM_CFGREG_SEMAPHORE_SEMA_7_M Fld(1, 14) //[14:14] + #define SSPM_CFGREG_SEMAPHORE_SEMA_7_H Fld(1, 15) //[15:15] + #define SSPM_CFGREG_SEMAPHORE_SEMA_8_M Fld(1, 16) //[16:16] + #define SSPM_CFGREG_SEMAPHORE_SEMA_8_H Fld(1, 17) //[17:17] + #define SSPM_CFGREG_SEMAPHORE_SEMA_9_M Fld(1, 18) //[18:18] + #define SSPM_CFGREG_SEMAPHORE_SEMA_9_H Fld(1, 19) //[19:19] + #define SSPM_CFGREG_SEMAPHORE_SEMA_10_M Fld(1, 20) //[20:20] + #define SSPM_CFGREG_SEMAPHORE_SEMA_10_H Fld(1, 21) //[21:21] + #define SSPM_CFGREG_SEMAPHORE_SEMA_11_M Fld(1, 22) //[22:22] + #define SSPM_CFGREG_SEMAPHORE_SEMA_11_H Fld(1, 23) //[23:23] + #define SSPM_CFGREG_SEMAPHORE_SEMA_12_M Fld(1, 24) //[24:24] + #define SSPM_CFGREG_SEMAPHORE_SEMA_12_H Fld(1, 25) //[25:25] + #define SSPM_CFGREG_SEMAPHORE_SEMA_13_M Fld(1, 26) //[26:26] + #define SSPM_CFGREG_SEMAPHORE_SEMA_13_H Fld(1, 27) //[27:27] + #define SSPM_CFGREG_SEMAPHORE_SEMA_14_M Fld(1, 28) //[28:28] + #define SSPM_CFGREG_SEMAPHORE_SEMA_14_H Fld(1, 29) //[29:29] + #define SSPM_CFGREG_SEMAPHORE_SEMA_15_M Fld(1, 30) //[30:30] + #define SSPM_CFGREG_SEMAPHORE_SEMA_15_H Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_TBUF_WPTR (DDRPHY_MD32_BASE_ADDRESS + 0x004C) + #define SSPM_CFGREG_MD32_TBUF_WPTR_MON_TBUF_WPTR Fld(4, 0) //[3:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_CCNT (DDRPHY_MD32_BASE_ADDRESS + 0x0050) + #define SSPM_CFGREG_MD32_CCNT_MON_CCNT Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT0 (DDRPHY_MD32_BASE_ADDRESS + 0x0054) + #define SSPM_CFGREG_MD32_PCNT0_MON_PCNT0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT1 (DDRPHY_MD32_BASE_ADDRESS + 0x0058) + #define SSPM_CFGREG_MD32_PCNT1_MON_PCNT1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT2 (DDRPHY_MD32_BASE_ADDRESS + 0x005C) + #define SSPM_CFGREG_MD32_PCNT2_MON_PCNT2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_CONTID (DDRPHY_MD32_BASE_ADDRESS + 0x0060) + #define SSPM_CFGREG_MD32_CONTID_MON_CONTID Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PC (DDRPHY_MD32_BASE_ADDRESS + 0x0064) + #define SSPM_CFGREG_MD32_PC_MON_PC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PC_MON (DDRPHY_MD32_BASE_ADDRESS + 0x0068) + #define SSPM_CFGREG_MD32_PC_MON_MON_PC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_BUS_STATUS (DDRPHY_MD32_BASE_ADDRESS + 0x006C) + #define SSPM_CFGREG_MD32_BUS_STATUS_BUS_STATUS Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_AHB_M0_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x0070) + #define SSPM_CFGREG_MD32_AHB_M0_ADDR_AHB_M0_ADDR Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_AHB_M1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x0074) + #define SSPM_CFGREG_MD32_AHB_M1_ADDR_AHB_M1_ADDR Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_ONE_TIME_LOCK (DDRPHY_MD32_BASE_ADDRESS + 0x0078) + #define SSPM_CFGREG_ONE_TIME_LOCK_ONE_TIME_LOCK Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SECURE_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x007C) + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_0 Fld(1, 0) //[0:0] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_1 Fld(1, 1) //[1:1] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_2 Fld(1, 2) //[2:2] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_3 Fld(1, 3) //[3:3] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_4 Fld(1, 4) //[4:4] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_5 Fld(1, 5) //[5:5] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_6 Fld(1, 6) //[6:6] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_7 Fld(1, 7) //[7:7] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_8 Fld(1, 8) //[8:8] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_9 Fld(1, 9) //[9:9] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_10 Fld(1, 10) //[10:10] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_11 Fld(1, 11) //[11:11] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_12 Fld(1, 12) //[12:12] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_13 Fld(1, 13) //[13:13] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_14 Fld(1, 14) //[14:14] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_24 Fld(1, 24) //[24:24] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_28 Fld(1, 28) //[28:28] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TCM_LOCK_CNT (DDRPHY_MD32_BASE_ADDRESS + 0x0080) + #define SSPM_CFGREG_TCM_LOCK_CNT_TCM_LOCK_CNT Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SLPP_S_EN (DDRPHY_MD32_BASE_ADDRESS + 0x0088) + #define SSPM_CFGREG_SLPP_S_EN_SLPP_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_P2P_TOEN (DDRPHY_MD32_BASE_ADDRESS + 0x008C) + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_0 Fld(1, 0) //[0:0] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_1 Fld(1, 1) //[1:1] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_2 Fld(1, 2) //[2:2] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_3 Fld(1, 3) //[3:3] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_4 Fld(1, 4) //[4:4] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_5 Fld(1, 5) //[5:5] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_6 Fld(1, 6) //[6:6] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00A0) + #define SSPM_CFGREG_MBOX0_IN_IRQ_MBOX0_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00A4) + #define SSPM_CFGREG_MBOX1_IN_IRQ_MBOX1_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00A8) + #define SSPM_CFGREG_MBOX2_IN_IRQ_MBOX2_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00AC) + #define SSPM_CFGREG_MBOX3_IN_IRQ_MBOX3_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00B0) + #define SSPM_CFGREG_MBOX4_IN_IRQ_MBOX4_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00C0) + #define SSPM_CFGREG_MBOX0_OUT_IRQ_MBOX0_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00C4) + #define SSPM_CFGREG_MBOX1_OUT_IRQ_MBOX1_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00C8) + #define SSPM_CFGREG_MBOX2_OUT_IRQ_MBOX2_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00CC) + #define SSPM_CFGREG_MBOX3_OUT_IRQ_MBOX3_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00D0) + #define SSPM_CFGREG_MBOX4_OUT_IRQ_MBOX4_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_ACAO_INT_SET (DDRPHY_MD32_BASE_ADDRESS + 0x00D8) + #define SSPM_CFGREG_ACAO_INT_SET_ACAO_INT_SET Fld(17, 0) //[16:0] + #define SSPM_CFGREG_ACAO_INT_SET_RSV0 Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_ACAO_INT_CLR (DDRPHY_MD32_BASE_ADDRESS + 0x00DC) + #define SSPM_CFGREG_ACAO_INT_CLR_ACAO_INT_CLR Fld(17, 0) //[16:0] + #define SSPM_CFGREG_ACAO_INT_CLR_RSV0 Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00E0) + #define SSPM_CFGREG_MBOX0_BASE_MBOX0_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00E4) + #define SSPM_CFGREG_MBOX1_BASE_MBOX1_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00E8) + #define SSPM_CFGREG_MBOX2_BASE_MBOX2_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00EC) + #define SSPM_CFGREG_MBOX3_BASE_MBOX3_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00F0) + #define SSPM_CFGREG_MBOX4_BASE_MBOX4_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX8_7B_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00F4) + #define SSPM_CFGREG_MBOX8_7B_BASE_MBOX5_7B_4 Fld(5, 0) //[4:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO_1 (DDRPHY_MD32_BASE_ADDRESS + 0x00F8) + #define SSPM_CFGREG_DVFS_INFO_1_DVFS_INFO_1 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO_2 (DDRPHY_MD32_BASE_ADDRESS + 0x00FC) + #define SSPM_CFGREG_DVFS_INFO_2_DVFS_INFO_2 Fld(5, 0) //[4:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RW_REG0 (DDRPHY_MD32_BASE_ADDRESS + 0x0100) + #define SSPM_CFGREG_RSV_RW_REG0_GICNIRQOUT_IRQ Fld(8, 0) //[7:0] + #define SSPM_CFGREG_RSV_RW_REG0_STANDBYWFI_INQ Fld(8, 8) //[15:8] + #define SSPM_CFGREG_RSV_RW_REG0_SPM_WAKEUP_IRQ Fld(1, 16) //[16:16] + #define SSPM_CFGREG_RSV_RW_REG0_RSV0 Fld(1, 17) //[17:17] + #define SSPM_CFGREG_RSV_RW_REG0_RSV_RW_REG0 Fld(14, 18) //[31:18] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RW_REG1 (DDRPHY_MD32_BASE_ADDRESS + 0x0104) + #define SSPM_CFGREG_RSV_RW_REG1_RSV_RW_REG1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RO_REG0 (DDRPHY_MD32_BASE_ADDRESS + 0x0108) + #define SSPM_CFGREG_RSV_RO_REG0_RSV_RO_REG0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RO_REG1 (DDRPHY_MD32_BASE_ADDRESS + 0x010C) + #define SSPM_CFGREG_RSV_RO_REG1_RSV_RO_REG1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR6 (DDRPHY_MD32_BASE_ADDRESS + 0x0110) + #define SSPM_CFGREG_GPR6_GPR6 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR7 (DDRPHY_MD32_BASE_ADDRESS + 0x0114) + #define SSPM_CFGREG_GPR7_GPR7 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR8 (DDRPHY_MD32_BASE_ADDRESS + 0x0118) + #define SSPM_CFGREG_GPR8_GPR8 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR9 (DDRPHY_MD32_BASE_ADDRESS + 0x011C) + #define SSPM_CFGREG_GPR9_GPR9 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR10 (DDRPHY_MD32_BASE_ADDRESS + 0x0120) + #define SSPM_CFGREG_GPR10_GPR10 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR11 (DDRPHY_MD32_BASE_ADDRESS + 0x0124) + #define SSPM_CFGREG_GPR11_GPR11 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR12 (DDRPHY_MD32_BASE_ADDRESS + 0x0128) + #define SSPM_CFGREG_GPR12_GPR12 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR13 (DDRPHY_MD32_BASE_ADDRESS + 0x012C) + #define SSPM_CFGREG_GPR13_GPR13 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR14 (DDRPHY_MD32_BASE_ADDRESS + 0x0130) + #define SSPM_CFGREG_GPR14_GPR14 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR15 (DDRPHY_MD32_BASE_ADDRESS + 0x0134) + #define SSPM_CFGREG_GPR15_GPR15 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHA (DDRPHY_MD32_BASE_ADDRESS + 0x013C) + #define SSPM_CFGREG_PC_DRAM_CHA_PC_DRAM_CHA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHB (DDRPHY_MD32_BASE_ADDRESS + 0x0140) + #define SSPM_CFGREG_PC_DRAM_CHB_PC_DRAM_CHB Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHC (DDRPHY_MD32_BASE_ADDRESS + 0x0144) + #define SSPM_CFGREG_PC_DRAM_CHC_PC_DRAM_CHC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHD (DDRPHY_MD32_BASE_ADDRESS + 0x0148) + #define SSPM_CFGREG_PC_DRAM_CHD_PC_DRAM_CHD Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_SP (DDRPHY_MD32_BASE_ADDRESS + 0x014C) + #define SSPM_CFGREG_MD32_SP_MON_SP Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_LR (DDRPHY_MD32_BASE_ADDRESS + 0x0150) + #define SSPM_CFGREG_MD32_LR_MON_LR Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL0 (DDRPHY_MD32_BASE_ADDRESS + 0x0168) + #define SSPM_CFGREG_BUS_CTRL0_BUS_CTRL0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL1 (DDRPHY_MD32_BASE_ADDRESS + 0x016C) + #define SSPM_CFGREG_BUS_CTRL1_BUS_CTRL1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL2 (DDRPHY_MD32_BASE_ADDRESS + 0x0170) + #define SSPM_CFGREG_BUS_CTRL2_BUS_CTRL2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_DR_APBP2P_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x0174) + #define SSPM_CFGREG_DR_APBP2P_CTRL_R_APB_BROADCAST_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUF_MON_SEL (DDRPHY_MD32_BASE_ADDRESS + 0x0178) + #define SSPM_CFGREG_TBUF_MON_SEL_TBU_MON_SEL Fld(4, 0) //[3:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUFL (DDRPHY_MD32_BASE_ADDRESS + 0x017C) + #define SSPM_CFGREG_TBUFL_TBUFL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUFH (DDRPHY_MD32_BASE_ADDRESS + 0x0180) + #define SSPM_CFGREG_TBUFH_TBUFH Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBIST_CFG (DDRPHY_MD32_BASE_ADDRESS + 0x0190) + #define SSPM_CFGREG_MBIST_CFG_DM_MD32_MBIST_CFG Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SRAM_DELSEL (DDRPHY_MD32_BASE_ADDRESS + 0x0194) + #define SSPM_CFGREG_SRAM_DELSEL_DM_MD32_SRAM_DELSEL_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER0_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1000) + #define SSPM_TIMER0_CON_TIMER0_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER0_CON_TIMER0_RTC Fld(2, 4) //[5:4] + +#define DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1004) + #define SSPM_TIMER0_RESET_VAL_TIMER0_RST_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER0_CUR_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1008) + #define SSPM_TIMER0_CUR_VAL_TIMER0_CUR_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER0_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x100C) + #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_TIMER1_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1010) + #define SSPM_TIMER1_CON_TIMER1_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER1_CON_TIMER1_RTC Fld(2, 4) //[5:4] + +#define DDRPHY_MD32_REG_SSPM_TIMER1_RESET_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1014) + #define SSPM_TIMER1_RESET_VAL_TIMER1_RST_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER1_CUR_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1018) + #define SSPM_TIMER1_CUR_VAL_TIMER1_CUR_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER1_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x101C) + #define SSPM_TIMER1_IRQ_ACK_TIMER1_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER1_IRQ_ACK_TIMER1_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_TIMER1_IRQ_ACK_TIMER2_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_TIMER2_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1020) + #define SSPM_TIMER2_CON_TIMER2_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER2_CON_TIMER2_RTC Fld(2, 4) //[5:4] + +#define DDRPHY_MD32_REG_SSPM_TIMER2_RESET_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1024) + #define SSPM_TIMER2_RESET_VAL_TIMER2_RST_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER2_CUR_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1028) + #define SSPM_TIMER2_CUR_VAL_TIMER2_CUR_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER2_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x102C) + #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_TIMER3_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1030) + #define SSPM_TIMER3_CON_TIMER3_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER3_CON_TIMER3_RTC Fld(2, 4) //[5:4] + +#define DDRPHY_MD32_REG_SSPM_TIMER3_RESET_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1034) + #define SSPM_TIMER3_RESET_VAL_TIMER3_RST_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER3_CUR_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1038) + #define SSPM_TIMER3_CUR_VAL_TIMER3_CUR_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER3_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x103C) + #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1080) + #define SSPM_OS_TIMER_CON_OS_TIMER_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CNT_L (DDRPHY_MD32_BASE_ADDRESS + 0x108C) + #define SSPM_OS_TIMER_CNT_L_OS_TIMER_CNT_L Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CNT_H (DDRPHY_MD32_BASE_ADDRESS + 0x1090) + #define SSPM_OS_TIMER_CNT_H_OS_TIMER_CNT_H Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_TVAL (DDRPHY_MD32_BASE_ADDRESS + 0x1094) + #define SSPM_OS_TIMER_TVAL_OS_TIMER_TVAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x1098) + #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_RAW_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2000) + #define SSPM_INTC_IRQ_RAW_STA0_IRQ_RAW_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_RAW_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2004) + #define SSPM_INTC_IRQ_RAW_STA1_IRQ_RAW_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2010) + #define SSPM_INTC_IRQ_STA0_IRQ_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2014) + #define SSPM_INTC_IRQ_STA1_IRQ_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_EN0 (DDRPHY_MD32_BASE_ADDRESS + 0x2020) + #define SSPM_INTC_IRQ_EN0_IRQ_EN0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_EN1 (DDRPHY_MD32_BASE_ADDRESS + 0x2024) + #define SSPM_INTC_IRQ_EN1_IRQ_EN1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_WAKE_EN0 (DDRPHY_MD32_BASE_ADDRESS + 0x2030) + #define SSPM_INTC_IRQ_WAKE_EN0_IRQ_WAKE_EN0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_WAKE_EN1 (DDRPHY_MD32_BASE_ADDRESS + 0x2034) + #define SSPM_INTC_IRQ_WAKE_EN1_IRQ_WAKE_EN1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_POL0 (DDRPHY_MD32_BASE_ADDRESS + 0x2040) + #define SSPM_INTC_IRQ_POL0_IRQ_POL0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_POL1 (DDRPHY_MD32_BASE_ADDRESS + 0x2044) + #define SSPM_INTC_IRQ_POL1_IRQ_POL1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2050) + #define SSPM_INTC_IRQ_GRP0_0_IRQ_GRP0_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2054) + #define SSPM_INTC_IRQ_GRP0_1_IRQ_GRP0_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2060) + #define SSPM_INTC_IRQ_GRP1_0_IRQ_GRP1_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2064) + #define SSPM_INTC_IRQ_GRP1_1_IRQ_GRP1_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2070) + #define SSPM_INTC_IRQ_GRP2_0_IRQ_GRP2_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2074) + #define SSPM_INTC_IRQ_GRP2_1_IRQ_GRP2_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2080) + #define SSPM_INTC_IRQ_GRP3_0_IRQ_GRP3_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2084) + #define SSPM_INTC_IRQ_GRP3_1_IRQ_GRP3_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2090) + #define SSPM_INTC_IRQ_GRP4_0_IRQ_GRP4_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2094) + #define SSPM_INTC_IRQ_GRP4_1_IRQ_GRP4_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20A0) + #define SSPM_INTC_IRQ_GRP5_0_IRQ_GRP5_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20A4) + #define SSPM_INTC_IRQ_GRP5_1_IRQ_GRP5_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20B0) + #define SSPM_INTC_IRQ_GRP6_0_IRQ_GRP6_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20B4) + #define SSPM_INTC_IRQ_GRP6_1_IRQ_GRP6_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20C0) + #define SSPM_INTC_IRQ_GRP7_0_IRQ_GRP7_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20C4) + #define SSPM_INTC_IRQ_GRP7_1_IRQ_GRP7_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20D0) + #define SSPM_INTC_IRQ_GRP8_0_IRQ_GRP8_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20D4) + #define SSPM_INTC_IRQ_GRP8_1_IRQ_GRP8_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20E0) + #define SSPM_INTC_IRQ_GRP9_0_IRQ_GRP9_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20E4) + #define SSPM_INTC_IRQ_GRP9_1_IRQ_GRP9_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20F0) + #define SSPM_INTC_IRQ_GRP10_0_IRQ_GRP10_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20F4) + #define SSPM_INTC_IRQ_GRP10_1_IRQ_GRP10_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2100) + #define SSPM_INTC_IRQ_GRP11_0_IRQ_GRP11_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2104) + #define SSPM_INTC_IRQ_GRP11_1_IRQ_GRP11_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2110) + #define SSPM_INTC_IRQ_GRP12_0_IRQ_GRP12_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2114) + #define SSPM_INTC_IRQ_GRP12_1_IRQ_GRP12_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2120) + #define SSPM_INTC_IRQ_GRP13_0_IRQ_GRP13_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2124) + #define SSPM_INTC_IRQ_GRP13_1_IRQ_GRP13_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2130) + #define SSPM_INTC_IRQ_GRP14_0_IRQ_GRP14_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2134) + #define SSPM_INTC_IRQ_GRP14_1_IRQ_GRP14_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2150) + #define SSPM_INTC_IRQ_GRP0_STA0_IRQ_GRP0_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2154) + #define SSPM_INTC_IRQ_GRP0_STA1_IRQ_GRP0_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2160) + #define SSPM_INTC_IRQ_GRP1_STA0_IRQ_GRP1_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2164) + #define SSPM_INTC_IRQ_GRP1_STA1_IRQ_GRP1_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2170) + #define SSPM_INTC_IRQ_GRP2_STA0_IRQ_GRP2_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2174) + #define SSPM_INTC_IRQ_GRP2_STA1_IRQ_GRP2_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2180) + #define SSPM_INTC_IRQ_GRP3_STA0_IRQ_GRP3_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2184) + #define SSPM_INTC_IRQ_GRP3_STA1_IRQ_GRP3_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2190) + #define SSPM_INTC_IRQ_GRP4_STA0_IRQ_GRP4_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2194) + #define SSPM_INTC_IRQ_GRP4_STA1_IRQ_GRP4_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21A0) + #define SSPM_INTC_IRQ_GRP5_STA0_IRQ_GRP5_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21A4) + #define SSPM_INTC_IRQ_GRP5_STA1_IRQ_GRP5_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21B0) + #define SSPM_INTC_IRQ_GRP6_STA0_IRQ_GRP6_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21B4) + #define SSPM_INTC_IRQ_GRP6_STA1_IRQ_GRP6_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21C0) + #define SSPM_INTC_IRQ_GRP7_STA0_IRQ_GRP7_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21C4) + #define SSPM_INTC_IRQ_GRP7_STA1_IRQ_GRP7_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21D0) + #define SSPM_INTC_IRQ_GRP8_STA0_IRQ_GRP8_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21D4) + #define SSPM_INTC_IRQ_GRP8_STA1_IRQ_GRP8_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21E0) + #define SSPM_INTC_IRQ_GRP9_STA0_IRQ_GRP9_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21E4) + #define SSPM_INTC_IRQ_GRP9_STA1_IRQ_GRP9_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21F0) + #define SSPM_INTC_IRQ_GRP10_STA0_IRQ_GRP10_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21F4) + #define SSPM_INTC_IRQ_GRP10_STA1_IRQ_GRP10_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2200) + #define SSPM_INTC_IRQ_GRP11_STA0_IRQ_GRP11_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2204) + #define SSPM_INTC_IRQ_GRP11_STA1_IRQ_GRP11_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2210) + #define SSPM_INTC_IRQ_GRP12_STA0_IRQ_GRP12_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2214) + #define SSPM_INTC_IRQ_GRP12_STA1_IRQ_GRP12_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2220) + #define SSPM_INTC_IRQ_GRP13_STA0_IRQ_GRP13_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2224) + #define SSPM_INTC_IRQ_GRP13_STA1_IRQ_GRP13_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2230) + #define SSPM_INTC_IRQ_GRP14_STA0_IRQ_GRP14_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2234) + #define SSPM_INTC_IRQ_GRP14_STA1_IRQ_GRP14_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP15_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2240) + #define SSPM_INTC_IRQ_GRP15_STA0_IRQ_GRP15_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP15_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2244) + #define SSPM_INTC_IRQ_GRP15_STA1_IRQ_GRP15_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_OUT (DDRPHY_MD32_BASE_ADDRESS + 0x2250) + #define SSPM_INTC_IRQ_OUT_IRQ_OUT Fld(15, 0) //[14:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_CLR_TRG (DDRPHY_MD32_BASE_ADDRESS + 0x2254) + #define SSPM_INTC_IRQ_CLR_TRG_IRQ_CLR_TRG Fld(15, 0) //[14:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_UART_RX_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x2258) + #define SSPM_INTC_UART_RX_IRQ_UART_RX_IRQ Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CK_EN (DDRPHY_MD32_BASE_ADDRESS + 0x3000) + #define SSPM_CK_EN_R_CLK_EN Fld(12, 0) //[11:0] + #define SSPM_CK_EN_R_LPIF_CLK_FR Fld(1, 12) //[12:12] + #define SSPM_CK_EN_R_DCM_MCLK_DIV Fld(2, 13) //[14:13] + #define SSPM_CK_EN_R_LPIF_CLK_26M Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_MCLK_DIV (DDRPHY_MD32_BASE_ADDRESS + 0x3004) + #define SSPM_MCLK_DIV_MCLK_DIV Fld(2, 0) //[1:0] + #define SSPM_MCLK_DIV_RSV0 Fld(2, 2) //[3:2] + #define SSPM_MCLK_DIV_MCLK_SRC Fld(2, 4) //[5:4] + #define SSPM_MCLK_DIV_RSV1 Fld(2, 6) //[7:6] + #define SSPM_MCLK_DIV_MCLK_DCM_EN Fld(1, 8) //[8:8] + #define SSPM_MCLK_DIV_RSV2 Fld(7, 9) //[15:9] + #define SSPM_MCLK_DIV_DIVSW_SEL_O Fld(4, 16) //[19:16] + #define SSPM_MCLK_DIV_CKSRC_SEL_O Fld(4, 20) //[23:20] + #define SSPM_MCLK_DIV_RSV3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_SSPM_DCM_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x3008) + #define SSPM_DCM_CTRL_R_DCM_EN Fld(12, 0) //[11:0] + #define SSPM_DCM_CTRL_WAKEUP_TYPE Fld(1, 28) //[28:28] + #define SSPM_DCM_CTRL_MD32_GATED Fld(1, 30) //[30:30] + #define SSPM_DCM_CTRL_CLK_OFF Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_SSPM_WAKE_INT (DDRPHY_MD32_BASE_ADDRESS + 0x300C) + #define SSPM_WAKE_INT_WAKEUP_INT Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x3010) + #define SSPM_UART_CTRL_UART_BCLK_CG Fld(1, 0) //[0:0] + #define SSPM_UART_CTRL_UART_CLK_SEL Fld(2, 1) //[2:1] + #define SSPM_UART_CTRL_UART_RST_N Fld(1, 3) //[3:3] + +#define DDRPHY_MD32_REG_SSPM_DMA_GLBSTA (DDRPHY_MD32_BASE_ADDRESS + 0x4000) + #define SSPM_DMA_GLBSTA_RUN_1 Fld(1, 0) //[0:0] + #define SSPM_DMA_GLBSTA_INTSTA_1 Fld(1, 1) //[1:1] + #define SSPM_DMA_GLBSTA_RUN_2 Fld(1, 2) //[2:2] + #define SSPM_DMA_GLBSTA_INTSTA_2 Fld(1, 3) //[3:3] + #define SSPM_DMA_GLBSTA_RUN_3 Fld(1, 4) //[4:4] + #define SSPM_DMA_GLBSTA_INTSTA_3 Fld(1, 5) //[5:5] + #define SSPM_DMA_GLBSTA_RUN_4 Fld(1, 6) //[6:6] + #define SSPM_DMA_GLBSTA_INTSTA_4 Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_DMA_GLBSTA2 (DDRPHY_MD32_BASE_ADDRESS + 0x4004) + #define SSPM_DMA_GLBSTA2_RUN_1 Fld(1, 0) //[0:0] + #define SSPM_DMA_GLBSTA2_INTSTA_1 Fld(1, 1) //[1:1] + #define SSPM_DMA_GLBSTA2_RUN_2 Fld(1, 2) //[2:2] + #define SSPM_DMA_GLBSTA2_INTSTA_2 Fld(1, 3) //[3:3] + #define SSPM_DMA_GLBSTA2_RUN_3 Fld(1, 4) //[4:4] + #define SSPM_DMA_GLBSTA2_INTSTA_3 Fld(1, 5) //[5:5] + #define SSPM_DMA_GLBSTA2_RUN_4 Fld(1, 6) //[6:6] + #define SSPM_DMA_GLBSTA2_INTSTA_4 Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_DMA_GLBLIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4028) + #define SSPM_DMA_GLBLIMITER_GLBLIMITER Fld(4, 0) //[3:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_SRC (DDRPHY_MD32_BASE_ADDRESS + 0x4100) + #define SSPM_DMA1_SRC_SRC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_DST (DDRPHY_MD32_BASE_ADDRESS + 0x4104) + #define SSPM_DMA1_DST_DST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_WPPT (DDRPHY_MD32_BASE_ADDRESS + 0x4108) + #define SSPM_DMA1_WPPT_WPPT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_WPTO (DDRPHY_MD32_BASE_ADDRESS + 0x410C) + #define SSPM_DMA1_WPTO_WPTO Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_COUNT (DDRPHY_MD32_BASE_ADDRESS + 0x4110) + #define SSPM_DMA1_COUNT_COUNT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_CON (DDRPHY_MD32_BASE_ADDRESS + 0x4114) + #define SSPM_DMA1_CON_SIZE Fld(2, 0) //[1:0] + #define SSPM_DMA1_CON_SRC_BEN Fld(1, 2) //[2:2] + #define SSPM_DMA1_CON_DST_BEN Fld(1, 3) //[3:3] + #define SSPM_DMA1_CON_DRQ Fld(1, 4) //[4:4] + #define SSPM_DMA1_CON_BRUST_TYPE Fld(2, 8) //[9:8] + #define SSPM_DMA1_CON_INTEN Fld(1, 15) //[15:15] + #define SSPM_DMA1_CON_WPSD Fld(1, 16) //[16:16] + #define SSPM_DMA1_CON_WPEN Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_DMA1_START (DDRPHY_MD32_BASE_ADDRESS + 0x4118) + #define SSPM_DMA1_START_START Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA1_INTSTA (DDRPHY_MD32_BASE_ADDRESS + 0x411C) + #define SSPM_DMA1_INTSTA_INTSTA Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA1_ACKINT (DDRPHY_MD32_BASE_ADDRESS + 0x4120) + #define SSPM_DMA1_ACKINT_ACKINT Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA1_RLCT (DDRPHY_MD32_BASE_ADDRESS + 0x4124) + #define SSPM_DMA1_RLCT_RLCT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_LIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4128) + #define SSPM_DMA1_LIMITER_LIMITER Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_SRC (DDRPHY_MD32_BASE_ADDRESS + 0x4200) + #define SSPM_DMA2_SRC_SRC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_DST (DDRPHY_MD32_BASE_ADDRESS + 0x4204) + #define SSPM_DMA2_DST_DST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_WPPT (DDRPHY_MD32_BASE_ADDRESS + 0x4208) + #define SSPM_DMA2_WPPT_WPPT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_WPTO (DDRPHY_MD32_BASE_ADDRESS + 0x420C) + #define SSPM_DMA2_WPTO_WPTO Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_COUNT (DDRPHY_MD32_BASE_ADDRESS + 0x4210) + #define SSPM_DMA2_COUNT_COUNT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_CON (DDRPHY_MD32_BASE_ADDRESS + 0x4214) + #define SSPM_DMA2_CON_SIZE Fld(2, 0) //[1:0] + #define SSPM_DMA2_CON_SRC_BEN Fld(1, 2) //[2:2] + #define SSPM_DMA2_CON_DST_BEN Fld(1, 3) //[3:3] + #define SSPM_DMA2_CON_DRQ Fld(1, 4) //[4:4] + #define SSPM_DMA2_CON_BRUST_TYPE Fld(2, 8) //[9:8] + #define SSPM_DMA2_CON_INTEN Fld(1, 15) //[15:15] + #define SSPM_DMA2_CON_WPSD Fld(1, 16) //[16:16] + #define SSPM_DMA2_CON_WPEN Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_DMA2_START (DDRPHY_MD32_BASE_ADDRESS + 0x4218) + #define SSPM_DMA2_START_START Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA2_INTSTA (DDRPHY_MD32_BASE_ADDRESS + 0x421C) + #define SSPM_DMA2_INTSTA_INTSTA Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA2_ACKINT (DDRPHY_MD32_BASE_ADDRESS + 0x4220) + #define SSPM_DMA2_ACKINT_ACKINT Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA2_RLCT (DDRPHY_MD32_BASE_ADDRESS + 0x4224) + #define SSPM_DMA2_RLCT_RLCT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_LIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4228) + #define SSPM_DMA2_LIMITER_LIMITER Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_SRC (DDRPHY_MD32_BASE_ADDRESS + 0x4300) + #define SSPM_DMA3_SRC_SRC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_DST (DDRPHY_MD32_BASE_ADDRESS + 0x4304) + #define SSPM_DMA3_DST_DST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_WPPT (DDRPHY_MD32_BASE_ADDRESS + 0x4308) + #define SSPM_DMA3_WPPT_WPPT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_WPTO (DDRPHY_MD32_BASE_ADDRESS + 0x430C) + #define SSPM_DMA3_WPTO_WPTO Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_COUNT (DDRPHY_MD32_BASE_ADDRESS + 0x4310) + #define SSPM_DMA3_COUNT_COUNT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_CON (DDRPHY_MD32_BASE_ADDRESS + 0x4314) + #define SSPM_DMA3_CON_SIZE Fld(2, 0) //[1:0] + #define SSPM_DMA3_CON_SRC_BEN Fld(1, 2) //[2:2] + #define SSPM_DMA3_CON_DST_BEN Fld(1, 3) //[3:3] + #define SSPM_DMA3_CON_DRQ Fld(1, 4) //[4:4] + #define SSPM_DMA3_CON_BRUST_TYPE Fld(2, 8) //[9:8] + #define SSPM_DMA3_CON_INTEN Fld(1, 15) //[15:15] + #define SSPM_DMA3_CON_WPSD Fld(1, 16) //[16:16] + #define SSPM_DMA3_CON_WPEN Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_DMA3_START (DDRPHY_MD32_BASE_ADDRESS + 0x4318) + #define SSPM_DMA3_START_START Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA3_INTSTA (DDRPHY_MD32_BASE_ADDRESS + 0x431C) + #define SSPM_DMA3_INTSTA_INTSTA Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA3_ACKINT (DDRPHY_MD32_BASE_ADDRESS + 0x4320) + #define SSPM_DMA3_ACKINT_ACKINT Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA3_RLCT (DDRPHY_MD32_BASE_ADDRESS + 0x4324) + #define SSPM_DMA3_RLCT_RLCT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_LIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4328) + #define SSPM_DMA3_LIMITER_LIMITER Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_SRC (DDRPHY_MD32_BASE_ADDRESS + 0x4400) + #define SSPM_DMA4_SRC_SRC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_DST (DDRPHY_MD32_BASE_ADDRESS + 0x4404) + #define SSPM_DMA4_DST_DST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_WPPT (DDRPHY_MD32_BASE_ADDRESS + 0x4408) + #define SSPM_DMA4_WPPT_WPPT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_WPTO (DDRPHY_MD32_BASE_ADDRESS + 0x440C) + #define SSPM_DMA4_WPTO_WPTO Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_COUNT (DDRPHY_MD32_BASE_ADDRESS + 0x4410) + #define SSPM_DMA4_COUNT_COUNT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_CON (DDRPHY_MD32_BASE_ADDRESS + 0x4414) + #define SSPM_DMA4_CON_SIZE Fld(2, 0) //[1:0] + #define SSPM_DMA4_CON_SRC_BEN Fld(1, 2) //[2:2] + #define SSPM_DMA4_CON_DST_BEN Fld(1, 3) //[3:3] + #define SSPM_DMA4_CON_DRQ Fld(1, 4) //[4:4] + #define SSPM_DMA4_CON_BRUST_TYPE Fld(2, 8) //[9:8] + #define SSPM_DMA4_CON_INTEN Fld(1, 15) //[15:15] + #define SSPM_DMA4_CON_WPSD Fld(1, 16) //[16:16] + #define SSPM_DMA4_CON_WPEN Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_DMA4_START (DDRPHY_MD32_BASE_ADDRESS + 0x4418) + #define SSPM_DMA4_START_START Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA4_INTSTA (DDRPHY_MD32_BASE_ADDRESS + 0x441C) + #define SSPM_DMA4_INTSTA_INTSTA Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA4_ACKINT (DDRPHY_MD32_BASE_ADDRESS + 0x4420) + #define SSPM_DMA4_ACKINT_ACKINT Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA4_RLCT (DDRPHY_MD32_BASE_ADDRESS + 0x4424) + #define SSPM_DMA4_RLCT_RLCT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_LIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4428) + #define SSPM_DMA4_LIMITER_LIMITER Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_RBR_THR_DLL_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5000) + #define SSPM_UART_RBR_THR_DLL_ADDR_RBR Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_IER_DLM_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5004) + #define SSPM_UART_IER_DLM_ADDR_RHRI Fld(1, 0) //[0:0] + #define SSPM_UART_IER_DLM_ADDR_THRI Fld(1, 1) //[1:1] + #define SSPM_UART_IER_DLM_ADDR_LINT_STSI Fld(1, 2) //[2:2] + #define SSPM_UART_IER_DLM_ADDR_MODEM_STSI Fld(1, 3) //[3:3] + #define SSPM_UART_IER_DLM_ADDR_RESERVED Fld(1, 4) //[4:4] + #define SSPM_UART_IER_DLM_ADDR_XOFFI Fld(1, 5) //[5:5] + #define SSPM_UART_IER_DLM_ADDR_RTSI Fld(1, 6) //[6:6] + #define SSPM_UART_IER_DLM_ADDR_CTSI Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_IIR_FCR_EFR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5008) + #define SSPM_UART_IIR_FCR_EFR_ADDR_ID Fld(6, 0) //[5:0] + #define SSPM_UART_IIR_FCR_EFR_ADDR_FIFOE Fld(2, 6) //[7:6] + +#define DDRPHY_MD32_REG_SSPM_UART_LCR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x500C) + #define SSPM_UART_LCR_ADDR_CHAR_LENGTH Fld(2, 0) //[1:0] + #define SSPM_UART_LCR_ADDR_STB Fld(1, 2) //[2:2] + #define SSPM_UART_LCR_ADDR_PEN Fld(1, 3) //[3:3] + #define SSPM_UART_LCR_ADDR_EPS Fld(1, 4) //[4:4] + #define SSPM_UART_LCR_ADDR_SP Fld(1, 5) //[5:5] + #define SSPM_UART_LCR_ADDR_SB Fld(1, 6) //[6:6] + #define SSPM_UART_LCR_ADDR_DLAB Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_MCR_XON1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5010) + #define SSPM_UART_MCR_XON1_ADDR_RTS Fld(1, 1) //[1:1] + #define SSPM_UART_MCR_XON1_ADDR_LOOPBACK_EN Fld(1, 4) //[4:4] + #define SSPM_UART_MCR_XON1_ADDR_XOFF_STATUS Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_LSR_XON2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5014) + #define SSPM_UART_LSR_XON2_ADDR_DR Fld(1, 0) //[0:0] + #define SSPM_UART_LSR_XON2_ADDR_OE Fld(1, 1) //[1:1] + #define SSPM_UART_LSR_XON2_ADDR_PE Fld(1, 2) //[2:2] + #define SSPM_UART_LSR_XON2_ADDR_FE Fld(1, 3) //[3:3] + #define SSPM_UART_LSR_XON2_ADDR_BI Fld(1, 4) //[4:4] + #define SSPM_UART_LSR_XON2_ADDR_THRE Fld(1, 5) //[5:5] + #define SSPM_UART_LSR_XON2_ADDR_TEMT Fld(1, 6) //[6:6] + #define SSPM_UART_LSR_XON2_ADDR_FIFOERR Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_MSR_XOFF1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5018) + #define SSPM_UART_MSR_XOFF1_ADDR_DCTS Fld(1, 0) //[0:0] + #define SSPM_UART_MSR_XOFF1_ADDR_CTS Fld(1, 4) //[4:4] + +#define DDRPHY_MD32_REG_SSPM_UART_SCR_XOFF2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x501C) + #define SSPM_UART_SCR_XOFF2_ADDR_SCR Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_EN_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5020) + #define SSPM_UART_AUTOBAUD_EN_ADDR_AUTOBAUD_EN Fld(1, 0) //[0:0] + #define SSPM_UART_AUTOBAUD_EN_ADDR_AUTOBAUD_SEL Fld(1, 1) //[1:1] + #define SSPM_UART_AUTOBAUD_EN_ADDR_SLEEP_ACK_SEL Fld(1, 2) //[2:2] + +#define DDRPHY_MD32_REG_SSPM_UART_RATE_STEP_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5024) + #define SSPM_UART_RATE_STEP_ADDR_SPEED Fld(2, 0) //[1:0] + +#define DDRPHY_MD32_REG_SSPM_UART_STEP_COUNT_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5028) + #define SSPM_UART_STEP_COUNT_ADDR_SAMPLECOUNT Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SAMPLE_COUNT_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x502C) + #define SSPM_UART_SAMPLE_COUNT_ADDR_SAMPLEPOINT Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_DATA_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5030) + #define SSPM_UART_AUTOBAUD_DATA_ADDR_BAUD_RATE Fld(4, 0) //[3:0] + #define SSPM_UART_AUTOBAUD_DATA_ADDR_BAUD_STAT Fld(4, 4) //[7:4] + +#define DDRPHY_MD32_REG_SSPM_UART_RATE_FIX_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5034) + #define SSPM_UART_RATE_FIX_ADDR_RATE_FIX Fld(1, 0) //[0:0] + #define SSPM_UART_RATE_FIX_ADDR_AUTOBAUD_RATE_FIX Fld(1, 1) //[1:1] + #define SSPM_UART_RATE_FIX_ADDR_FREQ_SEL Fld(1, 2) //[2:2] + +#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_RATE_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5038) + #define SSPM_UART_AUTOBAUD_RATE_ADDR_AUTOBAUDSAMPLE Fld(6, 0) //[5:0] + +#define DDRPHY_MD32_REG_SSPM_UART_GUARD_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x503C) + #define SSPM_UART_GUARD_ADDR_GUARD_CNT Fld(4, 0) //[3:0] + #define SSPM_UART_GUARD_ADDR_GUARD_EN Fld(1, 4) //[4:4] + +#define DDRPHY_MD32_REG_SSPM_UART_ESC_CHAR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5040) + #define SSPM_UART_ESC_CHAR_ADDR_ESC_CHAR Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_ESC_EN_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5044) + #define SSPM_UART_ESC_EN_ADDR_ESC_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_EN_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5048) + #define SSPM_UART_SLEEP_EN_ADDR_SLEEP_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_RXDMA_EN_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x504C) + #define SSPM_UART_RXDMA_EN_ADDR_RX_DMA_EN Fld(1, 0) //[0:0] + #define SSPM_UART_RXDMA_EN_ADDR_TX_DMA_EN Fld(1, 1) //[1:1] + #define SSPM_UART_RXDMA_EN_ADDR_TO_CNT_AUTORST Fld(1, 2) //[2:2] + #define SSPM_UART_RXDMA_EN_ADDR_FIFO_LSR_SEL Fld(1, 3) //[3:3] + +#define DDRPHY_MD32_REG_SSPM_UART_RXTRIG_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5050) + #define SSPM_UART_RXTRIG_ADDR_RXTRIG Fld(4, 0) //[3:0] + +#define DDRPHY_MD32_REG_SSPM_UART_FRACDIV_L_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5054) + #define SSPM_UART_FRACDIV_L_ADDR_FRACDIV_L Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_FRACDIV_M_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5058) + #define SSPM_UART_FRACDIV_M_ADDR_FRACDIV_M Fld(2, 0) //[1:0] + +#define DDRPHY_MD32_REG_SSPM_UART_FCR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x505C) + #define SSPM_UART_FCR_ADDR_FIFO_EN Fld(1, 0) //[0:0] + #define SSPM_UART_FCR_ADDR_RXFIFO_CLR Fld(1, 1) //[1:1] + #define SSPM_UART_FCR_ADDR_TXFIFO_CLR Fld(1, 2) //[2:2] + #define SSPM_UART_FCR_ADDR_RESERVED Fld(1, 3) //[3:3] + #define SSPM_UART_FCR_ADDR_TFTL1_TFTL0 Fld(2, 4) //[5:4] + #define SSPM_UART_FCR_ADDR_RFTL1_RFTL0 Fld(2, 6) //[7:6] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5060) + #define SSPM_UART_DEBUG_ADDR_ACC_SEL Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5064) + #define SSPM_UART_DEBUG_1_ADDR_TXSTATE Fld(5, 0) //[4:0] + #define SSPM_UART_DEBUG_1_ADDR_XCSTATE Fld(3, 5) //[7:5] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5068) + #define SSPM_UART_DEBUG_2_ADDR_RXSTATE Fld(4, 0) //[3:0] + #define SSPM_UART_DEBUG_2_ADDR_IP_TX_DMA0 Fld(4, 4) //[7:4] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_3_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x506C) + #define SSPM_UART_DEBUG_3_ADDR_IP_TX_DMA1 Fld(2, 0) //[1:0] + #define SSPM_UART_DEBUG_3_ADDR_TOFFSET_TX_DMA Fld(6, 2) //[7:2] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_4_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5070) + #define SSPM_UART_DEBUG_4_ADDR_TX_WOFFSET Fld(6, 0) //[5:0] + #define SSPM_UART_DEBUG_4_ADDR_TX_ROFFSET0 Fld(2, 6) //[7:6] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_5_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5074) + #define SSPM_UART_DEBUG_5_ADDR_TX_ROFFSET1 Fld(4, 0) //[3:0] + #define SSPM_UART_DEBUG_5_ADDR_OP_RX_REQ0 Fld(4, 4) //[7:4] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_6_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5078) + #define SSPM_UART_DEBUG_6_ADDR_OP_RX_REQ1 Fld(2, 0) //[1:0] + #define SSPM_UART_DEBUG_6_ADDR_ROFFSET_RXDMA Fld(6, 2) //[7:2] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_7_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x507C) + #define SSPM_UART_DEBUG_7_ADDR_RX_WOFFSET Fld(6, 0) //[5:0] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_8_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5080) + #define SSPM_UART_DEBUG_8_ADDR_XON_DET Fld(1, 0) //[0:0] + #define SSPM_UART_DEBUG_8_ADDR_XOFF_DET Fld(1, 1) //[1:1] + #define SSPM_UART_DEBUG_8_ADDR_SUPPLOAD Fld(1, 2) //[2:2] + #define SSPM_UART_DEBUG_8_ADDR_SW_TX_DIS Fld(1, 3) //[3:3] + #define SSPM_UART_DEBUG_8_ADDR_HW_TX_DIS Fld(1, 4) //[4:4] + #define SSPM_UART_DEBUG_8_ADDR_SLEEPING Fld(1, 5) //[5:5] + #define SSPM_UART_DEBUG_8_ADDR_VFIFO_LIMIT Fld(1, 6) //[6:6] + #define SSPM_UART_DEBUG_8_ADDR_HWFIFO_LIMIT Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_SEL (DDRPHY_MD32_BASE_ADDRESS + 0x5084) + #define SSPM_UART_DEBUG_SEL_UART_DBG_SEL Fld(3, 0) //[2:0] + +#define DDRPHY_MD32_REG_SSPM_UART_DLL_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5090) + #define SSPM_UART_DLL_ADDR_DLL Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_DLM_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5094) + #define SSPM_UART_DLM_ADDR_DLM Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_EFR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5098) + #define SSPM_UART_EFR_ADDR_SW_FLOW_CONTROL Fld(4, 0) //[3:0] + #define SSPM_UART_EFR_ADDR_ENHANCED_EN Fld(1, 4) //[4:4] + #define SSPM_UART_EFR_ADDR_AUTO_RTS_EN Fld(1, 6) //[6:6] + #define SSPM_UART_EFR_ADDR_AUTO_CTS_EN Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_FEATURE_SEL (DDRPHY_MD32_BASE_ADDRESS + 0x509C) + #define SSPM_UART_FEATURE_SEL_FEATURE_SEL Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_XON1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50A0) + #define SSPM_UART_XON1_ADDR_XON1 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_XON2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50A4) + #define SSPM_UART_XON2_ADDR_XON2 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_XOFF1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50A8) + #define SSPM_UART_XOFF1_ADDR_XOFF1 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_XOFF2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50AC) + #define SSPM_UART_XOFF2_ADDR_XOFF2 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_UART_RX_SEL_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50B0) + #define SSPM_UART_UART_RX_SEL_ADDR_USB_RX_SEL Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_REQ_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50B4) + #define SSPM_UART_SLEEP_REQ_ADDR_SLEEP_REQ Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_ACK_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50B8) + #define SSPM_UART_SLEEP_ACK_ADDR_SLEEP_ACK Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SPM_SEL (DDRPHY_MD32_BASE_ADDRESS + 0x50BC) + #define SSPM_UART_SPM_SEL_SPM_SEL Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_TWAM_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x6000) + #define SSPM_TWAM_CTRL_TWAM_SW_RST Fld(1, 0) //[0:0] + #define SSPM_TWAM_CTRL_TWAM_EN Fld(1, 1) //[1:1] + #define SSPM_TWAM_CTRL_SPEED_MODE_EN Fld(1, 2) //[2:2] + +#define DDRPHY_MD32_REG_SSPM_TWAM_WINDOW_LEN (DDRPHY_MD32_BASE_ADDRESS + 0x6004) + #define SSPM_TWAM_WINDOW_LEN_TWAM_WINDOW_LEN Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TWAM_MON_TYPE (DDRPHY_MD32_BASE_ADDRESS + 0x6008) + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE0 Fld(2, 0) //[1:0] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE1 Fld(2, 2) //[3:2] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE2 Fld(2, 4) //[5:4] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE3 Fld(2, 6) //[7:6] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE4 Fld(2, 8) //[9:8] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE5 Fld(2, 10) //[11:10] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE6 Fld(2, 12) //[13:12] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE7 Fld(2, 14) //[15:14] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE8 Fld(2, 16) //[17:16] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE9 Fld(2, 18) //[19:18] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE10 Fld(2, 20) //[21:20] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE11 Fld(2, 22) //[23:22] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE12 Fld(2, 24) //[25:24] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE13 Fld(2, 26) //[27:26] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE14 Fld(2, 28) //[29:28] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE15 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL0 (DDRPHY_MD32_BASE_ADDRESS + 0x600C) + #define SSPM_TWAM_SIG_SEL0_TWAM_CH0_SIG_SEL Fld(5, 0) //[4:0] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH1_SIG_SEL Fld(5, 5) //[9:5] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH2_SIG_SEL Fld(5, 10) //[14:10] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH3_SIG_SEL Fld(5, 15) //[19:15] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH4_SIG_SEL Fld(5, 20) //[24:20] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH5_SIG_SEL Fld(5, 25) //[29:25] + +#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL1 (DDRPHY_MD32_BASE_ADDRESS + 0x6010) + #define SSPM_TWAM_SIG_SEL1_TWAM_CH6_SIG_SEL Fld(5, 0) //[4:0] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH7_SIG_SEL Fld(5, 5) //[9:5] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH8_SIG_SEL Fld(5, 10) //[14:10] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH9_SIG_SEL Fld(5, 15) //[19:15] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH10_SIG_SEL Fld(5, 20) //[24:20] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH11_SIG_SEL Fld(5, 25) //[29:25] + +#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL2 (DDRPHY_MD32_BASE_ADDRESS + 0x6014) + #define SSPM_TWAM_SIG_SEL2_TWAM_CH12_SIG_SEL Fld(5, 0) //[4:0] + #define SSPM_TWAM_SIG_SEL2_TWAM_CH13_SIG_SEL Fld(5, 5) //[9:5] + #define SSPM_TWAM_SIG_SEL2_TWAM_CH14_SIG_SEL Fld(5, 10) //[14:10] + #define SSPM_TWAM_SIG_SEL2_TWAM_CH15_SIG_SEL Fld(5, 15) //[19:15] + +#define DDRPHY_MD32_REG_SSPM_TWAM_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x6018) + #define SSPM_TWAM_IRQ_TIRQ Fld(1, 0) //[0:0] + #define SSPM_TWAM_IRQ_IRQ_CLR Fld(1, 7) //[7:7] + #define SSPM_TWAM_IRQ_IRQ_CLR_FLAG Fld(1, 8) //[8:8] + +#define DDRPHY_MD32_REG_SSPM_TWAM_TIMER (DDRPHY_MD32_BASE_ADDRESS + 0x601C) + #define SSPM_TWAM_TIMER_TWAM_TIMER Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_WFI_WFE (DDRPHY_MD32_BASE_ADDRESS + 0x6020) + #define SSPM_WFI_WFE_WFI_WFE Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT0 (DDRPHY_MD32_BASE_ADDRESS + 0x6030) + #define SSPM_CUR_IDLE_CNT0_CUR_IDLE_CNT0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT1 (DDRPHY_MD32_BASE_ADDRESS + 0x6034) + #define SSPM_CUR_IDLE_CNT1_CUR_IDLE_CNT1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT2 (DDRPHY_MD32_BASE_ADDRESS + 0x6038) + #define SSPM_CUR_IDLE_CNT2_CUR_IDLE_CNT2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT3 (DDRPHY_MD32_BASE_ADDRESS + 0x603C) + #define SSPM_CUR_IDLE_CNT3_CUR_IDLE_CNT3 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT4 (DDRPHY_MD32_BASE_ADDRESS + 0x6040) + #define SSPM_CUR_IDLE_CNT4_CUR_IDLE_CNT4 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT5 (DDRPHY_MD32_BASE_ADDRESS + 0x6044) + #define SSPM_CUR_IDLE_CNT5_CUR_IDLE_CNT5 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT6 (DDRPHY_MD32_BASE_ADDRESS + 0x6048) + #define SSPM_CUR_IDLE_CNT6_CUR_IDLE_CNT6 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT7 (DDRPHY_MD32_BASE_ADDRESS + 0x604C) + #define SSPM_CUR_IDLE_CNT7_CUR_IDLE_CNT7 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT8 (DDRPHY_MD32_BASE_ADDRESS + 0x6050) + #define SSPM_CUR_IDLE_CNT8_CUR_IDLE_CNT8 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT9 (DDRPHY_MD32_BASE_ADDRESS + 0x6054) + #define SSPM_CUR_IDLE_CNT9_CUR_IDLE_CNT9 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT10 (DDRPHY_MD32_BASE_ADDRESS + 0x6058) + #define SSPM_CUR_IDLE_CNT10_CUR_IDLE_CNT10 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT11 (DDRPHY_MD32_BASE_ADDRESS + 0x605C) + #define SSPM_CUR_IDLE_CNT11_CUR_IDLE_CNT11 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT12 (DDRPHY_MD32_BASE_ADDRESS + 0x6060) + #define SSPM_CUR_IDLE_CNT12_CUR_IDLE_CNT12 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT13 (DDRPHY_MD32_BASE_ADDRESS + 0x6064) + #define SSPM_CUR_IDLE_CNT13_CUR_IDLE_CNT13 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT14 (DDRPHY_MD32_BASE_ADDRESS + 0x6068) + #define SSPM_CUR_IDLE_CNT14_CUR_IDLE_CNT14 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT15 (DDRPHY_MD32_BASE_ADDRESS + 0x606C) + #define SSPM_CUR_IDLE_CNT15_CUR_IDLE_CNT15 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT0 (DDRPHY_MD32_BASE_ADDRESS + 0x6080) + #define SSPM_LAST_IDLE_CNT0_LAST_IDEL_CNT0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT1 (DDRPHY_MD32_BASE_ADDRESS + 0x6084) + #define SSPM_LAST_IDLE_CNT1_LAST_IDEL_CNT1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT2 (DDRPHY_MD32_BASE_ADDRESS + 0x6088) + #define SSPM_LAST_IDLE_CNT2_LAST_IDEL_CNT2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT3 (DDRPHY_MD32_BASE_ADDRESS + 0x608C) + #define SSPM_LAST_IDLE_CNT3_LAST_IDEL_CNT3 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT4 (DDRPHY_MD32_BASE_ADDRESS + 0x6090) + #define SSPM_LAST_IDLE_CNT4_LAST_IDEL_CNT4 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT5 (DDRPHY_MD32_BASE_ADDRESS + 0x6094) + #define SSPM_LAST_IDLE_CNT5_LAST_IDEL_CNT5 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT6 (DDRPHY_MD32_BASE_ADDRESS + 0x6098) + #define SSPM_LAST_IDLE_CNT6_LAST_IDEL_CNT6 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT7 (DDRPHY_MD32_BASE_ADDRESS + 0x609C) + #define SSPM_LAST_IDLE_CNT7_LAST_IDEL_CNT7 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT8 (DDRPHY_MD32_BASE_ADDRESS + 0x60A0) + #define SSPM_LAST_IDLE_CNT8_LAST_IDEL_CNT8 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT9 (DDRPHY_MD32_BASE_ADDRESS + 0x60A4) + #define SSPM_LAST_IDLE_CNT9_LAST_IDEL_CNT9 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT10 (DDRPHY_MD32_BASE_ADDRESS + 0x60A8) + #define SSPM_LAST_IDLE_CNT10_LAST_IDEL_CNT10 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT11 (DDRPHY_MD32_BASE_ADDRESS + 0x60AC) + #define SSPM_LAST_IDLE_CNT11_LAST_IDEL_CNT11 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT12 (DDRPHY_MD32_BASE_ADDRESS + 0x60B0) + #define SSPM_LAST_IDLE_CNT12_LAST_IDEL_CNT12 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT13 (DDRPHY_MD32_BASE_ADDRESS + 0x60B4) + #define SSPM_LAST_IDLE_CNT13_LAST_IDEL_CNT13 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT14 (DDRPHY_MD32_BASE_ADDRESS + 0x60B8) + #define SSPM_LAST_IDLE_CNT14_LAST_IDEL_CNT14 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT15 (DDRPHY_MD32_BASE_ADDRESS + 0x60BC) + #define SSPM_LAST_IDLE_CNT15_LAST_IDEL_CNT15 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_FSM_CFG (DDRPHY_MD32_BASE_ADDRESS + 0x7000) + #define LPIF_FSM_CFG_LPIF_FMS_SW_RSTB Fld(1, 0) //[0:0] + #define LPIF_FSM_CFG_LPIF_INTERNAL_TEST Fld(1, 1) //[1:1] + #define LPIF_FSM_CFG_LPIF_DFS_RUNTIME_MRW_EN Fld(1, 2) //[2:2] + #define LPIF_FSM_CFG_LPIF_FSM_VAL_LOAD_FROM_CFG Fld(1, 3) //[3:3] + #define LPIF_FSM_CFG_LPIF_FSM_CTRL_SINGLE_CH Fld(1, 4) //[4:4] + #define LPIF_FSM_CFG_LPIF_SPM_IN_SYNC_BYPASS Fld(1, 5) //[5:5] + #define LPIF_FSM_CFG_LPIF_FSM_CONTROL_SINGLE_CH_HYBRID_S1 Fld(1, 6) //[6:6] + #define LPIF_FSM_CFG_LPIF_PLL_CONTROL_SINGLE_CHANNEL Fld(1, 7) //[7:7] + #define LPIF_FSM_CFG_LPIF_LP_NEW_8X Fld(1, 8) //[8:8] + #define LPIF_FSM_CFG_LPIF_SHU_SRAM_BASED Fld(1, 9) //[9:9] + #define LPIF_FSM_CFG_LPIF_SHU_INDEX Fld(1, 10) //[10:10] + #define LPIF_FSM_CFG_DBG_LATENCY_CNT_EN Fld(1, 11) //[11:11] + #define LPIF_FSM_CFG_LPIF_FSM Fld(10, 12) //[21:12] + #define LPIF_FSM_CFG_SR_DEBON_EN Fld(1, 22) //[22:22] + #define LPIF_FSM_CFG_SR_MIN_PLS_DEBON_EN Fld(1, 23) //[23:23] + #define LPIF_FSM_CFG_DELAY_PST_ACK_OUTPUT_SEL Fld(4, 24) //[27:24] + #define LPIF_FSM_CFG_DELAY_PST_ABOUT_OUTPUT_SEL Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7004) + #define LPIF_LOW_POWER_CFG_0_DMSUS_OFF Fld(2, 0) //[1:0] + #define LPIF_LOW_POWER_CFG_0_PHYPLL_EN Fld(2, 2) //[3:2] + #define LPIF_LOW_POWER_CFG_0_DPY_DLL_EN Fld(2, 4) //[5:4] + #define LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN Fld(2, 6) //[7:6] + #define LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN Fld(2, 8) //[9:8] + #define LPIF_LOW_POWER_CFG_0_DPY_VREF_EN Fld(2, 10) //[11:10] + #define LPIF_LOW_POWER_CFG_0_EMI_CLK_OFF_REQ Fld(2, 12) //[13:12] + #define LPIF_LOW_POWER_CFG_0_MEM_CK_OFF Fld(2, 14) //[15:14] + #define LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN Fld(2, 16) //[17:16] + #define LPIF_LOW_POWER_CFG_0_DR_GATE_RETRY_EN Fld(2, 18) //[19:18] + #define LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN Fld(2, 20) //[21:20] + #define LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW Fld(2, 22) //[23:22] + #define LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN Fld(2, 24) //[25:24] + #define LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW Fld(2, 26) //[27:26] + #define LPIF_LOW_POWER_CFG_0_DR_SHU_EN Fld(2, 28) //[29:28] + #define LPIF_LOW_POWER_CFG_0_DR_SHORT_QUEUE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7008) + #define LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL Fld(4, 0) //[3:0] + #define LPIF_LOW_POWER_CFG_1_DPY_BCLK_ENABLE Fld(2, 4) //[5:4] + #define LPIF_LOW_POWER_CFG_1_SHU_RESTORE Fld(2, 6) //[7:6] + #define LPIF_LOW_POWER_CFG_1_DPHY_PRECAL_UP Fld(2, 8) //[9:8] + #define LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN Fld(2, 10) //[11:10] + #define LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL Fld(2, 12) //[13:12] + #define LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL Fld(2, 14) //[15:14] + #define LPIF_LOW_POWER_CFG_1_DMYRD_EN Fld(2, 16) //[17:16] + #define LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS Fld(2, 18) //[19:18] + #define LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN Fld(2, 20) //[21:20] + #define LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL Fld(8, 22) //[29:22] + #define LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2 (DDRPHY_MD32_BASE_ADDRESS + 0x700C) + #define LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE Fld(2, 0) //[1:0] + #define LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH Fld(2, 2) //[3:2] + #define LPIF_LOW_POWER_CFG_2_DPY_MODE_SW Fld(2, 4) //[5:4] + #define LPIF_LOW_POWER_CFG_2_EMI_SLEEP_PROT_EN Fld(1, 6) //[6:6] + #define LPIF_LOW_POWER_CFG_2_MPLLOUT_OFF Fld(1, 7) //[7:7] + #define LPIF_LOW_POWER_CFG_2_DPY_RESERVED Fld(8, 8) //[15:8] + #define LPIF_LOW_POWER_CFG_2_DRAMC_DFS_STA Fld(13, 16) //[28:16] + #define LPIF_LOW_POWER_CFG_2_MPLL_S_OFF Fld(1, 29) //[29:29] + #define LPIF_LOW_POWER_CFG_2_FHC_PAUSE_MPLL Fld(1, 30) //[30:30] + #define LPIF_LOW_POWER_CFG_2_FHC_PAUSE_MEM Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7010) + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMSUS_OFF Fld(1, 0) //[0:0] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN Fld(1, 1) //[1:1] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN Fld(1, 2) //[2:2] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN Fld(1, 3) //[3:3] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN Fld(1, 4) //[4:4] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN Fld(1, 5) //[5:5] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_EMI_CLK_OFF_REQ Fld(1, 6) //[6:6] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_MEM_CK_OFF Fld(1, 7) //[7:7] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DDRPHY_FB_CK_EN Fld(1, 8) //[8:8] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_GATE_RETRY_EN Fld(1, 9) //[9:9] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN Fld(1, 10) //[10:10] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW Fld(1, 11) //[11:11] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL2_SHU_EN Fld(1, 12) //[12:12] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL2_MODE_SW Fld(1, 13) //[13:13] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_EN Fld(1, 14) //[14:14] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHORT_QUEUE Fld(1, 15) //[15:15] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_LEVEL Fld(1, 16) //[16:16] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_BCLK_ENABLE Fld(1, 17) //[17:17] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_SHU_RESTORE Fld(1, 18) //[18:18] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPHY_PRECAL_UP Fld(1, 19) //[19:19] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPHY_RXDLY_TRACK_EN Fld(1, 20) //[20:20] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMY_EN_MOD_SEL Fld(1, 21) //[21:21] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMYRD_INTV_SEL Fld(1, 22) //[22:22] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMYRD_EN Fld(1, 23) //[23:23] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_TX_TRACKING_DIS Fld(1, 24) //[24:24] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_TX_TRACKING_RETRY_EN Fld(1, 25) //[25:25] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_SRAM_LEVEL Fld(1, 26) //[26:26] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SRAM_LOAD Fld(1, 27) //[27:27] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SRAM_RESTORE Fld(1, 28) //[28:28] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_LEVEL_SRAM_LATCH Fld(1, 29) //[29:29] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_RESERVED Fld(1, 30) //[30:30] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DRAMC_DFS_STA Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7014) + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MODE_SW Fld(1, 0) //[0:0] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_MPLL_S_OFF Fld(1, 1) //[1:1] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_FHC_PAUSE_MPLL Fld(1, 2) //[2:2] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_FHC_PAUSE_MEM Fld(1, 3) //[3:3] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MCK8X_EN Fld(1, 4) //[4:4] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MIDPI_EN Fld(1, 5) //[5:5] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_PI_RESETB_EN Fld(1, 6) //[6:6] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DVFS_MEM_CK_MUX_UPDATE Fld(1, 7) //[7:7] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DVFS_MEM_CK_MUX_SEL Fld(1, 8) //[8:8] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_DSM_EN Fld(1, 9) //[9:9] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_PICG_FREE Fld(1, 10) //[10:10] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_FASTK_RDDQS_EN Fld(1, 11) //[11:11] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CS_PULL_UP_EN Fld(1, 12) //[12:12] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CS_PULL_DN_EN Fld(1, 13) //[13:13] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CA_PULL_UP_EN Fld(1, 14) //[14:14] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CA_PULL_DN_EN Fld(1, 15) //[15:15] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_MPLLOUT_OFF Fld(1, 16) //[16:16] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_EMI_S1_MODE_ASYNC Fld(1, 17) //[17:17] + #define LPIF_FSM_OUT_CTRL_1_RESERVED_X14_31_16 Fld(14, 18) //[31:18] + +#define DDRPHY_MD32_REG_LPIF_IPC_MASK_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7018) + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0 Fld(1, 0) //[0:0] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_01 Fld(1, 1) //[1:1] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_02 Fld(1, 2) //[2:2] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_03 Fld(1, 3) //[3:3] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_04 Fld(1, 4) //[4:4] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_05 Fld(1, 5) //[5:5] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_06 Fld(1, 6) //[6:6] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_07 Fld(1, 7) //[7:7] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_08 Fld(1, 8) //[8:8] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_09 Fld(1, 9) //[9:9] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0A Fld(1, 10) //[10:10] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0B Fld(1, 11) //[11:11] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0C Fld(1, 12) //[12:12] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0D Fld(1, 13) //[13:13] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0E Fld(1, 14) //[14:14] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0F Fld(1, 15) //[15:15] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_10 Fld(1, 16) //[16:16] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_11 Fld(1, 17) //[17:17] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_12 Fld(1, 18) //[18:18] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_13 Fld(1, 19) //[19:19] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_14 Fld(1, 20) //[20:20] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_15 Fld(1, 21) //[21:21] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_16 Fld(1, 22) //[22:22] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_17 Fld(1, 23) //[23:23] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_18 Fld(1, 24) //[24:24] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_19 Fld(1, 25) //[25:25] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1A Fld(1, 26) //[26:26] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1B Fld(1, 27) //[27:27] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1C Fld(1, 28) //[28:28] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1D Fld(1, 29) //[29:29] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1E Fld(1, 30) //[30:30] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1F Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_IPC_MASK_1 (DDRPHY_MD32_BASE_ADDRESS + 0x701C) + #define LPIF_IPC_MASK_1_PWR_STATE_IPC_MASK_RESERVED Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7020) + #define LPIF_FSM_CTRL_0_LPIF_SW_DDR_PST_ABORT_ACK Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_0_LPIF_SW_DDR_PST_ACK Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_0_RELEASE_LPIF_IRQ Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_0_RELEASE_DDR_PST_ACK Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_0_DFS_STATUS_RECORD Fld(4, 4) //[7:4] + #define LPIF_FSM_CTRL_0_DVS_STATUS_RECORD Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_0_RUN_TIME_STATUS_RECORD Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_0_RESERVED_X20_11_10 Fld(2, 10) //[11:10] + #define LPIF_FSM_CTRL_0_DFS_STATUS_RECORD_UPDATE Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_0_DVS_STATUS_RECORD_UPDATE Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_0_RUN_TIME_STATUS_RECORD_UPDATE Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_0_RESERVED_X20_15_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_0_JUMP_TO_SIDLE Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_0_JUMP_TO_SR Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_0_JUMP_TO_S1 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_0_JUMP_TO_S0 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_0_JUMP_TO_HYBRID_S1 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_0_JUMP_TO_DFS Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_0_JUMP_TO_DVS_ENTR Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_0_JUMP_TO_DVS_EXIT Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_0_JUMP_TO_EN_RUNTIME Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_0_JUMP_TO_DIS_RUNTIME Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_0_DRAMC_S0_STATUS Fld(2, 26) //[27:26] + #define LPIF_FSM_CTRL_0_RESERVED_X20_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7024) + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_0 Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_1 Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_2 Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_3 Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_4 Fld(1, 4) //[4:4] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_5 Fld(1, 5) //[5:5] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_6 Fld(1, 6) //[6:6] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_7 Fld(1, 7) //[7:7] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_8 Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_9 Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_10 Fld(1, 10) //[10:10] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_11 Fld(1, 11) //[11:11] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_12 Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_13 Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_14 Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_1_DMYRD_EN_0 Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_1_DMYRD_EN_1 Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_1_DMYRD_EN_2 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_1_DMYRD_EN_3 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_1_DMYRD_EN_4 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_1_DMYRD_EN_5 Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_1_DMYRD_EN_6 Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_1_DMYRD_EN_7 Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_1_DMYRD_EN_8 Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_1_DMYRD_EN_9 Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_1_DMYRD_EN_10 Fld(1, 26) //[26:26] + #define LPIF_FSM_CTRL_1_DMYRD_EN_11 Fld(1, 27) //[27:27] + #define LPIF_FSM_CTRL_1_DMYRD_EN_12 Fld(1, 28) //[28:28] + #define LPIF_FSM_CTRL_1_DMYRD_EN_13 Fld(1, 29) //[29:29] + #define LPIF_FSM_CTRL_1_DMYRD_EN_14 Fld(1, 30) //[30:30] + #define LPIF_FSM_CTRL_1_DMYRD_EN_15 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7028) + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_0 Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_1 Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_2 Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_3 Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_4 Fld(1, 4) //[4:4] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_5 Fld(1, 5) //[5:5] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_6 Fld(1, 6) //[6:6] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_7 Fld(1, 7) //[7:7] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_8 Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_9 Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_10 Fld(1, 10) //[10:10] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_11 Fld(1, 11) //[11:11] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_12 Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_13 Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_14 Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_0 Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_1 Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_2 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_3 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_4 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_5 Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_6 Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_7 Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_8 Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_9 Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_10 Fld(1, 26) //[26:26] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_11 Fld(1, 27) //[27:27] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_12 Fld(1, 28) //[28:28] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_13 Fld(1, 29) //[29:29] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_14 Fld(1, 30) //[30:30] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_15 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_3 (DDRPHY_MD32_BASE_ADDRESS + 0x702C) + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_0 Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_1 Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_2 Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_3 Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_4 Fld(1, 4) //[4:4] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_5 Fld(1, 5) //[5:5] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_6 Fld(1, 6) //[6:6] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_7 Fld(1, 7) //[7:7] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_8 Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_9 Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_10 Fld(1, 10) //[10:10] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_11 Fld(1, 11) //[11:11] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_12 Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_13 Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_14 Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_0 Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_1 Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_2 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_3 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_4 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_5 Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_6 Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_7 Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_8 Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_9 Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_10 Fld(1, 26) //[26:26] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_11 Fld(1, 27) //[27:27] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_12 Fld(1, 28) //[28:28] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_13 Fld(1, 29) //[29:29] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_14 Fld(1, 30) //[30:30] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_15 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_4 (DDRPHY_MD32_BASE_ADDRESS + 0x7030) + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_0 Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_1 Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_2 Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_3 Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_4 Fld(1, 4) //[4:4] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_5 Fld(1, 5) //[5:5] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_6 Fld(1, 6) //[6:6] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_7 Fld(1, 7) //[7:7] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_8 Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_9 Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_10 Fld(1, 10) //[10:10] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_11 Fld(1, 11) //[11:11] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_12 Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_13 Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_14 Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_0 Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_1 Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_2 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_3 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_4 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_5 Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_6 Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_7 Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_8 Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_9 Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_10 Fld(1, 26) //[26:26] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_11 Fld(1, 27) //[27:27] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_12 Fld(1, 28) //[28:28] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_13 Fld(1, 29) //[29:29] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_14 Fld(1, 30) //[30:30] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_15 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_CFG_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7034) + #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL Fld(1, 0) //[0:0] + #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND Fld(1, 1) //[1:1] + #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR Fld(1, 2) //[2:2] + #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND Fld(1, 3) //[3:3] + #define LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW Fld(1, 4) //[4:4] + #define LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND Fld(1, 5) //[5:5] + #define LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL Fld(1, 6) //[6:6] + #define LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3 (DDRPHY_MD32_BASE_ADDRESS + 0x7038) + #define LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN Fld(2, 0) //[1:0] + #define LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN Fld(2, 4) //[5:4] + #define LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE Fld(2, 6) //[7:6] + #define LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL Fld(4, 8) //[11:8] + #define LPIF_LOW_POWER_CFG_3_DPY_DSM_EN Fld(2, 12) //[13:12] + #define LPIF_LOW_POWER_CFG_3_DPY_FASTK_RDDQS_EN Fld(2, 14) //[15:14] + #define LPIF_LOW_POWER_CFG_3_DPY_CS_PULL_UP_EN Fld(2, 16) //[17:16] + #define LPIF_LOW_POWER_CFG_3_DPY_CS_PULL_DN_EN Fld(2, 18) //[19:18] + #define LPIF_LOW_POWER_CFG_3_DPY_CA_PULL_UP_EN Fld(2, 20) //[21:20] + #define LPIF_LOW_POWER_CFG_3_DPY_CA_PULL_DN_EN Fld(2, 22) //[23:22] + #define LPIF_LOW_POWER_CFG_3_EMI_S1_MODE_ASYNC Fld(1, 24) //[24:24] + #define LPIF_LOW_POWER_CFG_3_RESERVED_X38_25_25 Fld(1, 25) //[25:25] + #define LPIF_LOW_POWER_CFG_3_DPY_PICG_FREE Fld(2, 26) //[27:26] + #define LPIF_LOW_POWER_CFG_3_RESERVED_X38_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 (DDRPHY_MD32_BASE_ADDRESS + 0x703C) + #define LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN Fld(1, 0) //[0:0] + #define LPIF_DFD_DBUG_0_MD32_DRAMC_CKGEN_MCK_CG_EN Fld(1, 1) //[1:1] + #define LPIF_DFD_DBUG_0_RESERVED_X3C_31_2 Fld(30, 2) //[31:2] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_3 (DDRPHY_MD32_BASE_ADDRESS + 0x7040) + #define LPIF_RESERVED_3_RESERVED_X40_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7044) + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_TIME_OUT_CLR Fld(1, 0) //[0:0] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_20US_CLR Fld(1, 1) //[1:1] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_12US_CLR Fld(1, 2) //[2:2] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_DLL_1ST_LOCKING_CLR Fld(1, 3) //[3:3] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_DLL_2ND_LOCKING_CLR Fld(1, 4) //[4:4] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_CK_OFF_TO_DMSUS_CLR Fld(1, 5) //[5:5] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_50NS_CLR Fld(1, 6) //[6:6] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_4US_CLR Fld(1, 7) //[7:7] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_SR_DEBON_CLR Fld(1, 8) //[8:8] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_SR_MIN_PLS_DEBON_CLR Fld(1, 9) //[9:9] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_HW_S1_STEP_CLR Fld(1, 10) //[10:10] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_256MCK_CLR Fld(1, 11) //[11:11] + #define LPIF_TIMING_COUNTER_CTRL_0_RESERVED_X44_31_12 Fld(20, 12) //[31:12] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7048) + #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK2 Fld(4, 0) //[3:0] + #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK1 Fld(4, 4) //[7:4] + #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK0 Fld(4, 8) //[11:8] + #define LPIF_TIMING_COUNTER_CTRL_1_COUNTER_SR_MIN_PLS_DEBON Fld(8, 12) //[19:12] + #define LPIF_TIMING_COUNTER_CTRL_1_COUNTER_SR_DEBON Fld(11, 20) //[30:20] + #define LPIF_TIMING_COUNTER_CTRL_1_RESERVED_X44_31_31 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_2 (DDRPHY_MD32_BASE_ADDRESS + 0x704C) + #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_DLL_1ST_LOCKING_CLK2 Fld(8, 0) //[7:0] + #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_DLL_2ND_LOCKING_CLK2 Fld(8, 8) //[15:8] + #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_CK_OFF_TO_DMSUS_CLK2 Fld(8, 16) //[23:16] + #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_50NS_CLK2 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_3 (DDRPHY_MD32_BASE_ADDRESS + 0x7050) + #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_DLL_1ST_LOCKING_CLK1 Fld(8, 0) //[7:0] + #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_DLL_2ND_LOCKING_CLK1 Fld(8, 8) //[15:8] + #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_CK_OFF_TO_DMSUS_CLK1 Fld(8, 16) //[23:16] + #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_50NS_CLK1 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_4 (DDRPHY_MD32_BASE_ADDRESS + 0x7054) + #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_DLL_1ST_LOCKING_CLK0 Fld(8, 0) //[7:0] + #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_DLL_2ND_LOCKING_CLK0 Fld(8, 8) //[15:8] + #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_CK_OFF_TO_DMSUS_CLK0 Fld(8, 16) //[23:16] + #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_50NS_CLK0 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7058) + #define LPIF_TIMING_COUNTER_CTRL_5_COUNTER_20US_26M Fld(10, 0) //[9:0] + #define LPIF_TIMING_COUNTER_CTRL_5_RESERVED_X58_15_10 Fld(6, 10) //[15:10] + #define LPIF_TIMING_COUNTER_CTRL_5_COUNTER_TIME_OUT_26M Fld(16, 16) //[31:16] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_6 (DDRPHY_MD32_BASE_ADDRESS + 0x705C) + #define LPIF_TIMING_COUNTER_CTRL_6_COUNTER_12US_26M Fld(10, 0) //[9:0] + #define LPIF_TIMING_COUNTER_CTRL_6_RESERVED_X5C_15_11 Fld(2, 10) //[11:10] + #define LPIF_TIMING_COUNTER_CTRL_6_COUNTER_4US_26M Fld(10, 12) //[21:12] + #define LPIF_TIMING_COUNTER_CTRL_6_RESERVED_X5C_31_22 Fld(10, 22) //[31:22] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7060) + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_0 Fld(2, 0) //[1:0] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_1 Fld(2, 2) //[3:2] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_2 Fld(2, 4) //[5:4] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_3 Fld(2, 6) //[7:6] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_4 Fld(2, 8) //[9:8] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_5 Fld(2, 10) //[11:10] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_6 Fld(2, 12) //[13:12] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_7 Fld(2, 14) //[15:14] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_8 Fld(2, 16) //[17:16] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_9 Fld(2, 18) //[19:18] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_10 Fld(2, 20) //[21:20] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_11 Fld(2, 22) //[23:22] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_12 Fld(2, 24) //[25:24] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_13 Fld(2, 26) //[27:26] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_14 Fld(2, 28) //[29:28] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_15 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7064) + #define LPIF_RESERVED_5_COUNTER_HW_S1_STEP Fld(4, 0) //[3:0] + #define LPIF_RESERVED_5_COUNTER_256MCK Fld(9, 4) //[12:4] + #define LPIF_RESERVED_5_RESERVED_X64_31_13 Fld(19, 13) //[31:13] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_6 (DDRPHY_MD32_BASE_ADDRESS + 0x7068) + #define LPIF_RESERVED_6_MAX_CNT_SREF_REQ_HIGH_TO_SREF_ACK Fld(8, 0) //[7:0] + #define LPIF_RESERVED_6_MAX_CNT_SREF_REQ_LOW_TO_SREF_ACK Fld(8, 8) //[15:8] + #define LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK Fld(8, 16) //[23:16] + #define LPIF_RESERVED_6_MAX_CNT_HW_S1_REQ_LOW_TO_SREF_ACK_LOW Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_7 (DDRPHY_MD32_BASE_ADDRESS + 0x706C) + #define LPIF_RESERVED_7_RESERVED_X6C_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_8 (DDRPHY_MD32_BASE_ADDRESS + 0x7070) + #define LPIF_RESERVED_8_RESERVED_X70_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_9 (DDRPHY_MD32_BASE_ADDRESS + 0x7074) + #define LPIF_RESERVED_9_RESERVED_X74_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_10 (DDRPHY_MD32_BASE_ADDRESS + 0x7078) + #define LPIF_RESERVED_10_RESERVED_X78_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_11 (DDRPHY_MD32_BASE_ADDRESS + 0x707C) + #define LPIF_RESERVED_11_RESERVED_X7C_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_SEMA_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7080) + #define LPIF_SEMA_0_SEMA_0_M0 Fld(1, 0) //[0:0] + #define LPIF_SEMA_0_SEMA_1_M0 Fld(1, 1) //[1:1] + #define LPIF_SEMA_0_SEMA_2_M0 Fld(1, 2) //[2:2] + #define LPIF_SEMA_0_SEMA_3_M0 Fld(1, 3) //[3:3] + #define LPIF_SEMA_0_SEMA_4_M0 Fld(1, 4) //[4:4] + #define LPIF_SEMA_0_SEMA_5_M0 Fld(1, 5) //[5:5] + #define LPIF_SEMA_0_SEMA_6_M0 Fld(1, 6) //[6:6] + #define LPIF_SEMA_0_SEMA_7_M0 Fld(1, 7) //[7:7] + #define LPIF_SEMA_0_RESERVED_X80_31_8 Fld(24, 8) //[31:8] + +#define DDRPHY_MD32_REG_LPIF_SEMA_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7084) + #define LPIF_SEMA_1_SEMA_0_M1 Fld(1, 0) //[0:0] + #define LPIF_SEMA_1_SEMA_1_M1 Fld(1, 1) //[1:1] + #define LPIF_SEMA_1_SEMA_2_M1 Fld(1, 2) //[2:2] + #define LPIF_SEMA_1_SEMA_3_M1 Fld(1, 3) //[3:3] + #define LPIF_SEMA_1_SEMA_4_M1 Fld(1, 4) //[4:4] + #define LPIF_SEMA_1_SEMA_5_M1 Fld(1, 5) //[5:5] + #define LPIF_SEMA_1_SEMA_6_M1 Fld(1, 6) //[6:6] + #define LPIF_SEMA_1_SEMA_7_M1 Fld(1, 7) //[7:7] + #define LPIF_SEMA_1_RESERVED_X84_31_8 Fld(24, 8) //[31:8] + +#define DDRPHY_MD32_REG_LPIF_SEMA_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7088) + #define LPIF_SEMA_2_SEMA_0_M2 Fld(1, 0) //[0:0] + #define LPIF_SEMA_2_SEMA_1_M2 Fld(1, 1) //[1:1] + #define LPIF_SEMA_2_SEMA_2_M2 Fld(1, 2) //[2:2] + #define LPIF_SEMA_2_SEMA_3_M2 Fld(1, 3) //[3:3] + #define LPIF_SEMA_2_SEMA_4_M2 Fld(1, 4) //[4:4] + #define LPIF_SEMA_2_SEMA_5_M2 Fld(1, 5) //[5:5] + #define LPIF_SEMA_2_SEMA_6_M2 Fld(1, 6) //[6:6] + #define LPIF_SEMA_2_SEMA_7_M2 Fld(1, 7) //[7:7] + #define LPIF_SEMA_2_RESERVED_X88_31_8 Fld(24, 8) //[31:8] + +#define DDRPHY_MD32_REG_LPIF_SEMA_3 (DDRPHY_MD32_BASE_ADDRESS + 0x708C) + #define LPIF_SEMA_3_SEMA_0_M3 Fld(1, 0) //[0:0] + #define LPIF_SEMA_3_SEMA_1_M3 Fld(1, 1) //[1:1] + #define LPIF_SEMA_3_SEMA_2_M3 Fld(1, 2) //[2:2] + #define LPIF_SEMA_3_SEMA_3_M3 Fld(1, 3) //[3:3] + #define LPIF_SEMA_3_SEMA_4_M3 Fld(1, 4) //[4:4] + #define LPIF_SEMA_3_SEMA_5_M3 Fld(1, 5) //[5:5] + #define LPIF_SEMA_3_SEMA_6_M3 Fld(1, 6) //[6:6] + #define LPIF_SEMA_3_SEMA_7_M3 Fld(1, 7) //[7:7] + #define LPIF_SEMA_3_RESERVED_X8C_31_8 Fld(24, 8) //[31:8] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_16 (DDRPHY_MD32_BASE_ADDRESS + 0x7090) + #define LPIF_RESERVED_16_RESERVED_X90_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_17 (DDRPHY_MD32_BASE_ADDRESS + 0x7094) + #define LPIF_RESERVED_17_RESERVED_X94_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_18 (DDRPHY_MD32_BASE_ADDRESS + 0x7098) + #define LPIF_RESERVED_18_RESERVED_X98_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DUMMY_REG (DDRPHY_MD32_BASE_ADDRESS + 0x709C) + #define LPIF_DUMMY_REG_DUMMY_REG Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_0 (DDRPHY_MD32_BASE_ADDRESS + 0x70A0) + #define LPIF_STATUS_0_LPIF_DDR_PST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_1 (DDRPHY_MD32_BASE_ADDRESS + 0x70A4) + #define LPIF_STATUS_1_DDR_PST_REQ Fld(1, 0) //[0:0] + #define LPIF_STATUS_1_DDR_PST_ABORT_REQ Fld(1, 1) //[1:1] + #define LPIF_STATUS_1_DDR_PST_ABORT_REQ_LATCH Fld(1, 2) //[2:2] + #define LPIF_STATUS_1_LPC_INTERNAL_COUNTER_ABORT_FLAG Fld(1, 3) //[3:3] + #define LPIF_STATUS_1_RESERVED_XA4_31_4 Fld(28, 4) //[31:4] + +#define DDRPHY_MD32_REG_LPIF_STATUS_2 (DDRPHY_MD32_BASE_ADDRESS + 0x70A8) + #define LPIF_STATUS_2_DESTINATION_DDR_PST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_3 (DDRPHY_MD32_BASE_ADDRESS + 0x70AC) + #define LPIF_STATUS_3_CUR_DDR_PST_STA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_4 (DDRPHY_MD32_BASE_ADDRESS + 0x70B0) + #define LPIF_STATUS_4_EMI_CLK_OFF_REQ_ACK Fld(2, 0) //[1:0] + #define LPIF_STATUS_4_RESERVED_XB0_3_2 Fld(2, 2) //[3:2] + #define LPIF_STATUS_4_DRAMC_DFS_STA Fld(4, 4) //[7:4] + #define LPIF_STATUS_4_DQSSOC_REQ Fld(2, 8) //[9:8] + #define LPIF_STATUS_4_RESERVED_XB0_11_10 Fld(2, 10) //[11:10] + #define LPIF_STATUS_4_DR_SHORT_QUEUE_ACK Fld(2, 12) //[13:12] + #define LPIF_STATUS_4_DR_SHU_EN_ACK Fld(2, 14) //[15:14] + #define LPIF_STATUS_4_DR_SRAM_PLL_LOAD_ACK Fld(2, 16) //[17:16] + #define LPIF_STATUS_4_DR_SRAM_LOAD_ACK Fld(2, 18) //[19:18] + #define LPIF_STATUS_4_DR_SRAM_RESTORE_ACK Fld(2, 20) //[21:20] + #define LPIF_STATUS_4_TX_TRACKING_DIS_ACK Fld(2, 22) //[23:22] + #define LPIF_STATUS_4_RESERVED_XB0_27_24 Fld(4, 24) //[27:24] + #define LPIF_STATUS_4_DDR_PST_ACK Fld(1, 28) //[28:28] + #define LPIF_STATUS_4_DDR_PST_ABORT_ACK Fld(1, 29) //[29:29] + #define LPIF_STATUS_4_RESERVED_XB0_31_30 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_5 (DDRPHY_MD32_BASE_ADDRESS + 0x70B4) + #define LPIF_STATUS_5_DDR_PST_STA_D0 Fld(6, 0) //[5:0] + #define LPIF_STATUS_5_DDR_PST_ACK_D0 Fld(1, 6) //[6:6] + #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D0 Fld(1, 7) //[7:7] + #define LPIF_STATUS_5_DDR_PST_STA_D1 Fld(6, 8) //[13:8] + #define LPIF_STATUS_5_DDR_PST_ACK_D1 Fld(1, 14) //[14:14] + #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D1 Fld(1, 15) //[15:15] + #define LPIF_STATUS_5_DDR_PST_STA_D2 Fld(6, 16) //[21:16] + #define LPIF_STATUS_5_DDR_PST_ACK_D2 Fld(1, 22) //[22:22] + #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D2 Fld(1, 23) //[23:23] + #define LPIF_STATUS_5_DDR_PST_STA_D3 Fld(6, 24) //[29:24] + #define LPIF_STATUS_5_DDR_PST_ACK_D3 Fld(1, 30) //[30:30] + #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D3 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_STATUS_6 (DDRPHY_MD32_BASE_ADDRESS + 0x70B8) + #define LPIF_STATUS_6_DDR_PST_STA_D4 Fld(6, 0) //[5:0] + #define LPIF_STATUS_6_DDR_PST_ACK_D4 Fld(1, 6) //[6:6] + #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D4 Fld(1, 7) //[7:7] + #define LPIF_STATUS_6_DDR_PST_STA_D5 Fld(6, 8) //[13:8] + #define LPIF_STATUS_6_DDR_PST_ACK_D5 Fld(1, 14) //[14:14] + #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D5 Fld(1, 15) //[15:15] + #define LPIF_STATUS_6_DDR_PST_STA_D6 Fld(6, 16) //[21:16] + #define LPIF_STATUS_6_DDR_PST_ACK_D6 Fld(1, 22) //[22:22] + #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D6 Fld(1, 23) //[23:23] + #define LPIF_STATUS_6_DDR_PST_STA_D7 Fld(6, 24) //[29:24] + #define LPIF_STATUS_6_DDR_PST_ACK_D7 Fld(1, 30) //[30:30] + #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D7 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_STATUS_7 (DDRPHY_MD32_BASE_ADDRESS + 0x70BC) + #define LPIF_STATUS_7_DDR_PST_STA_D8 Fld(6, 0) //[5:0] + #define LPIF_STATUS_7_DDR_PST_ACK_D8 Fld(1, 6) //[6:6] + #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_D8 Fld(1, 7) //[7:7] + #define LPIF_STATUS_7_DDR_PST_STA_D9 Fld(6, 8) //[13:8] + #define LPIF_STATUS_7_DDR_PST_ACK_D9 Fld(1, 14) //[14:14] + #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_D9 Fld(1, 15) //[15:15] + #define LPIF_STATUS_7_DDR_PST_STA_DA Fld(6, 16) //[21:16] + #define LPIF_STATUS_7_DDR_PST_ACK_DA Fld(1, 22) //[22:22] + #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_DA Fld(1, 23) //[23:23] + #define LPIF_STATUS_7_DDR_PST_STA_DB Fld(6, 24) //[29:24] + #define LPIF_STATUS_7_DDR_PST_ACK_DB Fld(1, 30) //[30:30] + #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_DB Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_STATUS_8 (DDRPHY_MD32_BASE_ADDRESS + 0x70C0) + #define LPIF_STATUS_8_DDR_PST_STA_DC Fld(6, 0) //[5:0] + #define LPIF_STATUS_8_DDR_PST_ACK_DC Fld(1, 6) //[6:6] + #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DC Fld(1, 7) //[7:7] + #define LPIF_STATUS_8_DDR_PST_STA_DD Fld(6, 8) //[13:8] + #define LPIF_STATUS_8_DDR_PST_ACK_DD Fld(1, 14) //[14:14] + #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DD Fld(1, 15) //[15:15] + #define LPIF_STATUS_8_DDR_PST_STA_DE Fld(6, 16) //[21:16] + #define LPIF_STATUS_8_DDR_PST_ACK_DE Fld(1, 22) //[22:22] + #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DE Fld(1, 23) //[23:23] + #define LPIF_STATUS_8_DDR_PST_STA_DF Fld(6, 24) //[29:24] + #define LPIF_STATUS_8_DDR_PST_ACK_DF Fld(1, 30) //[30:30] + #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DF Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_STATUS_9 (DDRPHY_MD32_BASE_ADDRESS + 0x70C4) + #define LPIF_STATUS_9_DRAMC_DMSUS_OFF Fld(2, 0) //[1:0] + #define LPIF_STATUS_9_DRAMC_PHYPLL_EN Fld(2, 2) //[3:2] + #define LPIF_STATUS_9_DRAMC_DPY_DLL_EN Fld(2, 4) //[5:4] + #define LPIF_STATUS_9_DRAMC_DPY_2ND_DLL_EN Fld(2, 6) //[7:6] + #define LPIF_STATUS_9_DRAMC_DPY_DLL_CK_EN Fld(2, 8) //[9:8] + #define LPIF_STATUS_9_DRAMC_DPY_VREF_EN Fld(2, 10) //[11:10] + #define LPIF_STATUS_9_DRAMC_EMI_CLK_OFF_REQ Fld(2, 12) //[13:12] + #define LPIF_STATUS_9_DRAMC_MEM_CK_OFF Fld(2, 14) //[15:14] + #define LPIF_STATUS_9_DRAMC_DDRPHY_FB_CK_EN Fld(2, 16) //[17:16] + #define LPIF_STATUS_9_DRAMC_DR_GATE_RETRY_EN Fld(2, 18) //[19:18] + #define LPIF_STATUS_9_DRAMC_PHYPLL_SHU_EN Fld(2, 20) //[21:20] + #define LPIF_STATUS_9_DRAMC_PHYPLL_MODE_SW Fld(2, 22) //[23:22] + #define LPIF_STATUS_9_DRAMC_PHYPLL2_SHU_EN Fld(2, 24) //[25:24] + #define LPIF_STATUS_9_DRAMC_PHYPLL2_MODE_SW Fld(2, 26) //[27:26] + #define LPIF_STATUS_9_DRAMC_DR_SHU_EN Fld(2, 28) //[29:28] + #define LPIF_STATUS_9_DRAMC_DR_SHORT_QUEUE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_10 (DDRPHY_MD32_BASE_ADDRESS + 0x70C8) + #define LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL Fld(4, 0) //[3:0] + #define LPIF_STATUS_10_DRAMC_DPY_BCLK_ENABLE Fld(2, 4) //[5:4] + #define LPIF_STATUS_10_DRAMC_SHU_RESTORE Fld(2, 6) //[7:6] + #define LPIF_STATUS_10_DRAMC_DPHY_PRECAL_UP Fld(2, 8) //[9:8] + #define LPIF_STATUS_10_DRAMC_DPHY_RXDLY_TRACK_EN Fld(2, 10) //[11:10] + #define LPIF_STATUS_10_DRAMC_DMY_EN_MOD_SEL Fld(2, 12) //[13:12] + #define LPIF_STATUS_10_DRAMC_DMYRD_INTV_SEL Fld(2, 14) //[15:14] + #define LPIF_STATUS_10_DRAMC_DMYRD_EN Fld(2, 16) //[17:16] + #define LPIF_STATUS_10_DRAMC_TX_TRACKING_DIS Fld(2, 18) //[19:18] + #define LPIF_STATUS_10_DRAMC_TX_TRACKING_RETRY_EN Fld(2, 20) //[21:20] + #define LPIF_STATUS_10_DRAMC_DR_SHU_SRAM_LEVEL Fld(8, 22) //[29:22] + #define LPIF_STATUS_10_DRAMC_DR_SRAM_LOAD Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_11 (DDRPHY_MD32_BASE_ADDRESS + 0x70CC) + #define LPIF_STATUS_11_DRAMC_DR_SRAM_RESTORE Fld(2, 0) //[1:0] + #define LPIF_STATUS_11_DRAMC_DR_SHU_LEVEL_SRAM_LATCH Fld(2, 2) //[3:2] + #define LPIF_STATUS_11_DRAMC_DPY_MODE_SW Fld(2, 4) //[5:4] + #define LPIF_STATUS_11_RESERVED_XCC_7_6 Fld(2, 6) //[7:6] + #define LPIF_STATUS_11_DRAMC_DPY_RESERVED Fld(8, 8) //[15:8] + #define LPIF_STATUS_11_DRAMC_DRAMC_DFS_CON Fld(13, 16) //[28:16] + #define LPIF_STATUS_11_RESERVED_XCC_31_27 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_STATUS_12 (DDRPHY_MD32_BASE_ADDRESS + 0x70D0) + #define LPIF_STATUS_12_FSM_TIME_OUT_FLAG Fld(1, 0) //[0:0] + #define LPIF_STATUS_12_EXP_FSM_JUMP Fld(1, 1) //[1:1] + #define LPIF_STATUS_12_IRQ_LPIF_LOW_POWER Fld(1, 2) //[2:2] + #define LPIF_STATUS_12_IRQ_LPIF_OTHERS_STATE Fld(1, 3) //[3:3] + #define LPIF_STATUS_12_DFS_STATUS_RECORD Fld(4, 4) //[7:4] + #define LPIF_STATUS_12_DVS_STATUS_RECORD Fld(1, 8) //[8:8] + #define LPIF_STATUS_12_RUNTIME_STATUS_RECORD Fld(1, 9) //[9:9] + #define LPIF_STATUS_12_RESERVED_XD0_11_10 Fld(2, 10) //[11:10] + #define LPIF_STATUS_12_MUX_LPIF_DPHY_RXDLY_TRACK_EN Fld(1, 12) //[12:12] + #define LPIF_STATUS_12_MUX_LPIF_DMYRD_EN Fld(1, 13) //[13:13] + #define LPIF_STATUS_12_MUX_LPIF_TX_TRACKING_DIS Fld(1, 14) //[14:14] + #define LPIF_STATUS_12_MUX_LPIF_DR_SRAM_RESTORE Fld(1, 15) //[15:15] + #define LPIF_STATUS_12_MUX_LPIF_TX_TRACK_RETRY_EN Fld(1, 16) //[16:16] + #define LPIF_STATUS_12_MUX_LPIF_RX_GATING_RETRY_EN Fld(1, 17) //[17:17] + #define LPIF_STATUS_12_MUX_LPIF_DLL_ALL_SLAVE_EN Fld(1, 18) //[18:18] + #define LPIF_STATUS_12_MUX_LPIF_IMPEDANCE_TRACKING_EN Fld(1, 19) //[19:19] + #define LPIF_STATUS_12_MUX_LPIF_DPHY_RXDLY_TRACK_EN_PREV Fld(1, 20) //[20:20] + #define LPIF_STATUS_12_MUX_LPIF_DMYRD_EN_PREV Fld(1, 21) //[21:21] + #define LPIF_STATUS_12_MUX_LPIF_TX_TRACKING_DIS_PREV Fld(1, 22) //[22:22] + #define LPIF_STATUS_12_MUX_LPIF_DR_SRAM_RESTORE_PREV Fld(1, 23) //[23:23] + #define LPIF_STATUS_12_MUX_LPIF_TX_TRACK_RETRY_EN_PREV Fld(1, 24) //[24:24] + #define LPIF_STATUS_12_MUX_LPIF_RX_GATING_RETRY_EN_PREV Fld(1, 25) //[25:25] + #define LPIF_STATUS_12_MUX_LPIF_DLL_ALL_SLAVE_EN_PREV Fld(1, 26) //[26:26] + #define LPIF_STATUS_12_MUX_LPIF_IMPEDANCE_TRACKING_EN_PREV Fld(1, 27) //[27:27] + #define LPIF_STATUS_12_SHU_INDEX Fld(1, 28) //[28:28] + #define LPIF_STATUS_12_RESERVED_XD0_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_STATUS_13 (DDRPHY_MD32_BASE_ADDRESS + 0x70D4) + #define LPIF_STATUS_13_COUNTER_TIME_OUT_FLAG Fld(1, 0) //[0:0] + #define LPIF_STATUS_13_COUNTER_20US_DONE Fld(1, 1) //[1:1] + #define LPIF_STATUS_13_COUNTER_12US_DONE Fld(1, 2) //[2:2] + #define LPIF_STATUS_13_COUNTER_DLL_1ST_LOCKING_DONE Fld(1, 3) //[3:3] + #define LPIF_STATUS_13_COUNTER_DLL_2ND_LOCKING_DONE Fld(1, 4) //[4:4] + #define LPIF_STATUS_13_COUNTER_CK_OFF_TO_DMSUS_DONE Fld(1, 5) //[5:5] + #define LPIF_STATUS_13_COUNTER_50NS_DONE Fld(1, 6) //[6:6] + #define LPIF_STATUS_13_COUNTER_4US_DONE Fld(1, 7) //[7:7] + #define LPIF_STATUS_13_LPIF_FSM Fld(10, 8) //[17:8] + #define LPIF_STATUS_13_COUNTER_SR_DEBON_DONE Fld(2, 18) //[19:18] + #define LPIF_STATUS_13_COUNTER_SR_MIN_PLS_DEBON_DONE Fld(2, 20) //[21:20] + #define LPIF_STATUS_13_HW_S1_STEP_COUNTER_DONE Fld(1, 22) //[22:22] + #define LPIF_STATUS_13_COUNTER_256MCK_DONE Fld(1, 23) //[23:23] + #define LPIF_STATUS_13_MUX_LPIF_DRAM_PAR_CLOCK_MODE Fld(2, 24) //[25:24] + #define LPIF_STATUS_13_MUX_LPIF_DRAM_PAR_CLOCK_MODE_PREV Fld(2, 26) //[27:26] + #define LPIF_STATUS_13_RESERVED_XD4_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_STATUS_14 (DDRPHY_MD32_BASE_ADDRESS + 0x70D8) + #define LPIF_STATUS_14_DRAMC_DPY_MCK8X_EN Fld(2, 0) //[1:0] + #define LPIF_STATUS_14_DRAMC_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_STATUS_14_DRAMC_DPY_PI_RESETB_EN Fld(2, 4) //[5:4] + #define LPIF_STATUS_14_DRAMC_DVFS_MEM_CK_MUX_UPDATE Fld(2, 6) //[7:6] + #define LPIF_STATUS_14_DRAMC_DVFS_MEM_CK_MUX_SEL Fld(4, 8) //[11:8] + #define LPIF_STATUS_14_DRAMC_DPY_DSM_EN Fld(2, 12) //[13:12] + #define LPIF_STATUS_14_DRAMC_DPY_FASTK_RDDQS_EN Fld(2, 14) //[15:14] + #define LPIF_STATUS_14_DRAMC_DPY_CS_PULL_UP_EN Fld(2, 16) //[17:16] + #define LPIF_STATUS_14_DRAMC_DPY_CS_PULL_DN_EN Fld(2, 18) //[19:18] + #define LPIF_STATUS_14_DRAMC_DPY_CA_PULL_UP_EN Fld(2, 20) //[21:20] + #define LPIF_STATUS_14_DRAMC_DPY_CA_PULL_DN_EN Fld(2, 22) //[23:22] + #define LPIF_STATUS_14_DRAMC_FHC_PAUSE_MEM Fld(1, 24) //[24:24] + #define LPIF_STATUS_14_DRAMC_FHC_PAUSE_MPLL Fld(1, 25) //[25:25] + #define LPIF_STATUS_14_DRAMC_MPLL_S_OFF Fld(1, 26) //[26:26] + #define LPIF_STATUS_14_DRAMC_MPLLOUT_OFF Fld(1, 27) //[27:27] + #define LPIF_STATUS_14_DRAMC_EMI_S1_MODE_ASYNC Fld(1, 28) //[28:28] + #define LPIF_STATUS_14_RESERVED_XD8_29_29 Fld(1, 29) //[29:29] + #define LPIF_STATUS_14_DRAMC_DPY_PICG_FREE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_20 (DDRPHY_MD32_BASE_ADDRESS + 0x70DC) + #define LPIF_RESERVED_20_RESERVED_XDC_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_15 (DDRPHY_MD32_BASE_ADDRESS + 0x70E0) + #define LPIF_STATUS_15_DRAMC_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_STATUS_15_DRAMC_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_STATUS_15_DRAMC_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_STATUS_15_DRAMC_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_STATUS_15_DRAMC_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_STATUS_15_DRAMC_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_STATUS_15_DRAMC_PWR_SRAM_PDN Fld(4, 16) //[19:16] + #define LPIF_STATUS_15_DRAMC_PWR_SC_SRAM_PDN_ACK Fld(1, 20) //[20:20] + #define LPIF_STATUS_15_DRAMC_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_STATUS_15_DRAMC_SHU_SRAM_CKISO Fld(2, 26) //[27:26] + #define LPIF_STATUS_15_DRAMC_SHU_SRAM_ISOINT_B Fld(2, 28) //[29:28] + #define LPIF_STATUS_15_DRAMC_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_16 (DDRPHY_MD32_BASE_ADDRESS + 0x70E4) + #define LPIF_STATUS_16_SC_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_STATUS_16_SC_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_STATUS_16_SC_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_STATUS_16_SC_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_STATUS_16_SC_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_STATUS_16_RESERVED_XE4_11_10 Fld(2, 10) //[11:10] + #define LPIF_STATUS_16_SC_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_STATUS_16_RESERVED_XE4_15_13 Fld(3, 13) //[15:13] + #define LPIF_STATUS_16_SC_PWR_SRAM_PDN Fld(4, 16) //[19:16] + #define LPIF_STATUS_16_RESERVED_XE4_23_20 Fld(4, 20) //[23:20] + #define LPIF_STATUS_16_SC_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_STATUS_16_RESERVED_XE4_26_26 Fld(1, 26) //[26:26] + #define LPIF_STATUS_16_SC_SHU_SRAM_CKISO Fld(1, 27) //[27:27] + #define LPIF_STATUS_16_RESERVED_XE4_28_28 Fld(1, 28) //[28:28] + #define LPIF_STATUS_16_SC_SHU_SRAM_ISOINT_B Fld(1, 29) //[29:29] + #define LPIF_STATUS_16_SC_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_17 (DDRPHY_MD32_BASE_ADDRESS + 0x70E8) + #define LPIF_STATUS_17_LPIF_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_STATUS_17_LPIF_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_STATUS_17_LPIF_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_STATUS_17_LPIF_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_STATUS_17_LPIF_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_STATUS_17_LPIF_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_STATUS_17_LPIF_PWR_SRAM_PDN Fld(8, 16) //[23:16] + #define LPIF_STATUS_17_LPIF_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_STATUS_17_LPIF_SHU_SRAM_CKISO Fld(2, 26) //[27:26] + #define LPIF_STATUS_17_LPIF_SHU_SRAM_ISOINT_B Fld(2, 28) //[29:28] + #define LPIF_STATUS_17_LPIF_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_18 (DDRPHY_MD32_BASE_ADDRESS + 0x70EC) + #define LPIF_STATUS_18_DRAMC_LPIF_COM Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_19 (DDRPHY_MD32_BASE_ADDRESS + 0x70F0) + #define LPIF_STATUS_19_DRAMC_LPIF_STA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_MISC_CTL_0 (DDRPHY_MD32_BASE_ADDRESS + 0x70F4) + #define LPIF_MISC_CTL_0_EMI_SLEEP_IDLE Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_LPIF_MISC_CTL_1 (DDRPHY_MD32_BASE_ADDRESS + 0x70F8) + #define LPIF_MISC_CTL_1_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_MISC_CTL_1_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_MISC_CTL_1_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_MISC_CTL_1_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_MISC_CTL_1_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_MISC_CTL_1_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_MISC_CTL_1_PWR_SRAM_PDN Fld(8, 16) //[23:16] + #define LPIF_MISC_CTL_1_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_MISC_CTL_1_SHU_SRAM_CKISO Fld(2, 26) //[27:26] + #define LPIF_MISC_CTL_1_SHU_SRAM_ISOINT_B Fld(2, 28) //[29:28] + #define LPIF_MISC_CTL_1_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_MISC_STATUS_0 (DDRPHY_MD32_BASE_ADDRESS + 0x70FC) + #define LPIF_MISC_STATUS_0_PWR_ON_ACK Fld(2, 0) //[1:0] + #define LPIF_MISC_STATUS_0_PWR_ON_2ND_ACK Fld(2, 2) //[3:2] + #define LPIF_MISC_STATUS_0_SRAM_PDN_ACK Fld(4, 8) //[11:8] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7100) + #define LPIF_DVFS_CMD_0_DVFS_CMD0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7104) + #define LPIF_DVFS_CMD_1_DVFS_CMD1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7108) + #define LPIF_DVFS_CMD_2_DVFS_CMD2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_3 (DDRPHY_MD32_BASE_ADDRESS + 0x710C) + #define LPIF_DVFS_CMD_3_DVFS_CMD3 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_4 (DDRPHY_MD32_BASE_ADDRESS + 0x7110) + #define LPIF_DVFS_CMD_4_DVFS_CMD4 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7114) + #define LPIF_DVFS_CMD_5_DVFS_CMD5 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_6 (DDRPHY_MD32_BASE_ADDRESS + 0x7118) + #define LPIF_DVFS_CMD_6_DVFS_CMD6 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_7 (DDRPHY_MD32_BASE_ADDRESS + 0x711C) + #define LPIF_DVFS_CMD_7_DVFS_CMD7 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_8 (DDRPHY_MD32_BASE_ADDRESS + 0x7120) + #define LPIF_DVFS_CMD_8_DVFS_CMD8 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_9 (DDRPHY_MD32_BASE_ADDRESS + 0x7124) + #define LPIF_DVFS_CMD_9_DVFS_CMD9 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_10 (DDRPHY_MD32_BASE_ADDRESS + 0x7128) + #define LPIF_DVFS_CMD_10_DVFS_CMD10 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_11 (DDRPHY_MD32_BASE_ADDRESS + 0x712C) + #define LPIF_DVFS_CMD_11_DVFS_CMD11 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_12 (DDRPHY_MD32_BASE_ADDRESS + 0x7130) + #define LPIF_DVFS_CMD_12_DVFS_CMD12 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_13 (DDRPHY_MD32_BASE_ADDRESS + 0x7134) + #define LPIF_DVFS_CMD_13_DVFS_CMD13 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_14 (DDRPHY_MD32_BASE_ADDRESS + 0x7138) + #define LPIF_DVFS_CMD_14_DVFS_CMD14 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_15 (DDRPHY_MD32_BASE_ADDRESS + 0x713C) + #define LPIF_DVFS_CMD_15_DVFS_CMD15 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_16 (DDRPHY_MD32_BASE_ADDRESS + 0x7140) + #define LPIF_DVFS_CMD_16_DVFS_CMD16 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_17 (DDRPHY_MD32_BASE_ADDRESS + 0x7144) + #define LPIF_DVFS_CMD_17_DVFS_CMD17 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_18 (DDRPHY_MD32_BASE_ADDRESS + 0x7148) + #define LPIF_DVFS_CMD_18_DVFS_CMD18 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_19 (DDRPHY_MD32_BASE_ADDRESS + 0x714C) + #define LPIF_DVFS_CMD_19_DVFS_CMD19 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_20 (DDRPHY_MD32_BASE_ADDRESS + 0x7150) + #define LPIF_DVFS_CMD_20_DVFS_CMD20 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_21 (DDRPHY_MD32_BASE_ADDRESS + 0x7154) + #define LPIF_DVFS_CMD_21_DVFS_CMD21 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_22 (DDRPHY_MD32_BASE_ADDRESS + 0x7158) + #define LPIF_DVFS_CMD_22_DVFS_CMD22 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_23 (DDRPHY_MD32_BASE_ADDRESS + 0x715C) + #define LPIF_DVFS_CMD_23_DVFS_CMD23 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CONFIG (DDRPHY_MD32_BASE_ADDRESS + 0x7160) + #define LPIF_DVFS_CONFIG_DVFS_CON Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7164) + #define LPIF_DVFS_STATUS_0_DVFS_CMD_ACK Fld(1, 0) //[0:0] + #define LPIF_DVFS_STATUS_0_DVFS_CMD_REQ Fld(1, 1) //[1:1] + +#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7168) + #define LPIF_DVFS_STATUS_1_DVFS_CMD_DAT Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_2 (DDRPHY_MD32_BASE_ADDRESS + 0x716C) + #define LPIF_DVFS_STATUS_2_DVFS_CON_STA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_170 (DDRPHY_MD32_BASE_ADDRESS + 0x7170) + #define LPIF_RESERVED_170_RESERVED_X170_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_174 (DDRPHY_MD32_BASE_ADDRESS + 0x7174) + #define LPIF_RESERVED_174_RESERVED_X174_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_178 (DDRPHY_MD32_BASE_ADDRESS + 0x7178) + #define LPIF_RESERVED_178_RESERVED_X178_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_17C (DDRPHY_MD32_BASE_ADDRESS + 0x717C) + #define LPIF_RESERVED_17C_RESERVED_X17C_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7180) + #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7184) + #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7188) + #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_3 (DDRPHY_MD32_BASE_ADDRESS + 0x718C) + #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7190) + #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7194) + #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7198) + #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_3 (DDRPHY_MD32_BASE_ADDRESS + 0x719C) + #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71A0) + #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71A4) + #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71A8) + #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71AC) + #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71B0) + #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71B4) + #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71B8) + #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71BC) + #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71C0) + #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71C4) + #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71C8) + #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71CC) + #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71D0) + #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71D4) + #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71D8) + #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71DC) + #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71E0) + #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71E4) + #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71E8) + #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71EC) + #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71F0) + #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71F4) + #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71F8) + #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71FC) + #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7200) + #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7204) + #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7208) + #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_3 (DDRPHY_MD32_BASE_ADDRESS + 0x720C) + #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7210) + #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7214) + #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7218) + #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_3 (DDRPHY_MD32_BASE_ADDRESS + 0x721C) + #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7220) + #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7224) + #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7228) + #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_3 (DDRPHY_MD32_BASE_ADDRESS + 0x722C) + #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7230) + #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7234) + #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7238) + #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_3 (DDRPHY_MD32_BASE_ADDRESS + 0x723C) + #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7240) + #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7244) + #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7248) + #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_3 (DDRPHY_MD32_BASE_ADDRESS + 0x724C) + #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7250) + #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7254) + #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7258) + #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_3 (DDRPHY_MD32_BASE_ADDRESS + 0x725C) + #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7260) + #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7264) + #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7268) + #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_3 (DDRPHY_MD32_BASE_ADDRESS + 0x726C) + #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7270) + #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7274) + #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7278) + #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_3 (DDRPHY_MD32_BASE_ADDRESS + 0x727C) + #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7280) + #define LPIF_INT_PSTA_0_PSTA_CLK_26M_EN Fld(1, 0) //[0:0] + #define LPIF_INT_PSTA_0_PSTA_IN_SYNC_BYPASS Fld(1, 1) //[1:1] + #define LPIF_INT_PSTA_0_PSTA_TEST_TRIGGER_EN Fld(1, 2) //[2:2] + #define LPIF_INT_PSTA_0_PTA_ABORT_CASE_EN Fld(1, 3) //[3:3] + #define LPIF_INT_PSTA_0_PSTA_ABORT_TIME_RAND_EN Fld(1, 4) //[4:4] + #define LPIF_INT_PSTA_0_PSTA_PST_TO_REQ_TIME_RAND_EN Fld(1, 5) //[5:5] + #define LPIF_INT_PSTA_0_PSTA_REQ_TO_NXT_PST_TIME_RAND_EN Fld(1, 6) //[6:6] + #define LPIF_INT_PSTA_0_PSTA_ACK_TO_PST_REQ_LOW_TIME_RAND_EN Fld(1, 7) //[7:7] + #define LPIF_INT_PSTA_0_PSTA_LOOP_MODE_ENABLE Fld(1, 8) //[8:8] + #define LPIF_INT_PSTA_0_PSTA_TEST_CLR Fld(1, 9) //[9:9] + #define LPIF_INT_PSTA_0_RESERVED_XA0_11_10 Fld(2, 10) //[11:10] + #define LPIF_INT_PSTA_0_PSTA_HW_S1_TEST_EN Fld(1, 12) //[12:12] + #define LPIF_INT_PSTA_0_PSTA_HW_S1_HIGH_PERIOD_TIME_RAND_EN Fld(1, 13) //[13:13] + #define LPIF_INT_PSTA_0_PSTA_HW_S1_REQ_INTV_TIME_RAND_EN Fld(1, 14) //[14:14] + #define LPIF_INT_PSTA_0_PSTA_HW_S1_BYPASS_LOW_ACK_CHK Fld(1, 15) //[15:15] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_0_EN Fld(1, 16) //[16:16] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_1_EN Fld(1, 17) //[17:17] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_2_EN Fld(1, 18) //[18:18] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_3_EN Fld(1, 19) //[19:19] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_4_EN Fld(1, 20) //[20:20] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_5_EN Fld(1, 21) //[21:21] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_6_EN Fld(1, 22) //[22:22] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_7_EN Fld(1, 23) //[23:23] + #define LPIF_INT_PSTA_0_RESERVED_XA0_31_24 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7284) + #define LPIF_INT_PSTA_1_PSTA_LOOP_MODE_TIME Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7288) + #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME Fld(10, 0) //[9:0] + #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME_MIN Fld(10, 10) //[19:10] + #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME_MAX Fld(10, 20) //[29:20] + #define LPIF_INT_PSTA_2_RESERVED_XA2_31_30 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_3 (DDRPHY_MD32_BASE_ADDRESS + 0x728C) + #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME Fld(4, 0) //[3:0] + #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME_MIN Fld(4, 4) //[7:4] + #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME_MAX Fld(4, 8) //[11:8] + #define LPIF_INT_PSTA_3_RESERVED_XA3_15_12 Fld(4, 12) //[15:12] + #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME Fld(4, 16) //[19:16] + #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME_MIN Fld(4, 20) //[23:20] + #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME_MAX Fld(4, 24) //[27:24] + #define LPIF_INT_PSTA_3_RESERVED_XA3_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_4 (DDRPHY_MD32_BASE_ADDRESS + 0x7290) + #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME Fld(8, 0) //[7:0] + #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME_MIN Fld(8, 8) //[15:8] + #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME_MAX Fld(8, 16) //[23:16] + #define LPIF_INT_PSTA_4_RESERVED_XA4_31_24 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7294) + #define LPIF_INT_PSTA_5_PSTA_CMD_PST_0 Fld(5, 0) //[4:0] + #define LPIF_INT_PSTA_5_RESERVED_XA5_7_5 Fld(3, 5) //[7:5] + #define LPIF_INT_PSTA_5_PSTA_CMD_PST_1 Fld(5, 8) //[12:8] + #define LPIF_INT_PSTA_5_RESERVED_XA5_15_13 Fld(3, 13) //[15:13] + #define LPIF_INT_PSTA_5_PSTA_CMD_PST_2 Fld(5, 16) //[20:16] + #define LPIF_INT_PSTA_5_RESERVED_XA5_23_21 Fld(3, 21) //[23:21] + #define LPIF_INT_PSTA_5_PSTA_CMD_PST_3 Fld(5, 24) //[28:24] + #define LPIF_INT_PSTA_5_RESERVED_XA5_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_6 (DDRPHY_MD32_BASE_ADDRESS + 0x7298) + #define LPIF_INT_PSTA_6_PSTA_CMD_PST_4 Fld(5, 0) //[4:0] + #define LPIF_INT_PSTA_6_RESERVED_XA6_7_5 Fld(3, 5) //[7:5] + #define LPIF_INT_PSTA_6_PSTA_CMD_PST_5 Fld(5, 8) //[12:8] + #define LPIF_INT_PSTA_6_RESERVED_XA6_15_13 Fld(3, 13) //[15:13] + #define LPIF_INT_PSTA_6_PSTA_CMD_PST_6 Fld(5, 16) //[20:16] + #define LPIF_INT_PSTA_6_RESERVED_XA6_23_21 Fld(3, 21) //[23:21] + #define LPIF_INT_PSTA_6_PSTA_CMD_PST_7 Fld(5, 24) //[28:24] + #define LPIF_INT_PSTA_6_RESERVED_XA6_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_7 (DDRPHY_MD32_BASE_ADDRESS + 0x729C) + #define LPIF_INT_PSTA_7_PSTA_ABORT_TIME_LSFR_POL Fld(20, 0) //[19:0] + #define LPIF_INT_PSTA_7_RESERVED_XA7_23_20 Fld(4, 20) //[23:20] + #define LPIF_INT_PSTA_7_PSTA_ACK_TO_PST_REQ_LOW_TIME_LSFR_POL Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_8 (DDRPHY_MD32_BASE_ADDRESS + 0x72A0) + #define LPIF_INT_PSTA_8_PSTA_REQ_TO_NXT_PST_TIME_LSFR_POL Fld(16, 0) //[15:0] + #define LPIF_INT_PSTA_8_PSTA_PST_TO_REQ_TIME_LSFR_POL Fld(8, 16) //[23:16] + #define LPIF_INT_PSTA_8_RESERVED_XA8_31_24 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_9 (DDRPHY_MD32_BASE_ADDRESS + 0x72A4) + #define LPIF_INT_PSTA_9_PSTA_DDR_PST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_10 (DDRPHY_MD32_BASE_ADDRESS + 0x72A8) + #define LPIF_INT_PSTA_10_PSTA_DDR_PST_REQ Fld(1, 0) //[0:0] + #define LPIF_INT_PSTA_10_PSTA_DDR_PST_ABORT_REQ Fld(1, 1) //[1:1] + #define LPIF_INT_PSTA_10_RESERVED_XAA_3_2 Fld(2, 2) //[3:2] + #define LPIF_INT_PSTA_10_PSTA_DDR_FSM_DONE Fld(1, 4) //[4:4] + #define LPIF_INT_PSTA_10_PSTA_DDR_HW_S1_ACK Fld(1, 5) //[5:5] + #define LPIF_INT_PSTA_10_PSTA_FSM Fld(5, 8) //[12:8] + #define LPIF_INT_PSTA_10_CNT_PSTA_FSM Fld(12, 16) //[27:16] + #define LPIF_INT_PSTA_10_RESERVED_XAA_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_11 (DDRPHY_MD32_BASE_ADDRESS + 0x72AC) + #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME Fld(10, 0) //[9:0] + #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME_MIN Fld(10, 10) //[19:10] + #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME_MAX Fld(10, 20) //[29:20] + #define LPIF_INT_PSTA_11_RESERVED_XAB_31_30 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_12 (DDRPHY_MD32_BASE_ADDRESS + 0x72B0) + #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME Fld(10, 0) //[9:0] + #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME_MIN Fld(10, 10) //[19:10] + #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME_MAX Fld(10, 20) //[29:20] + #define LPIF_INT_PSTA_12_RESERVED_XAC_31_30 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_13 (DDRPHY_MD32_BASE_ADDRESS + 0x72B4) + #define LPIF_INT_PSTA_13_PSTA_HW_S1_REQ_INTV_TIME_LSFR_POL Fld(20, 0) //[19:0] + #define LPIF_INT_PSTA_13_RESERVED_XAD_31_30 Fld(12, 20) //[31:20] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_14 (DDRPHY_MD32_BASE_ADDRESS + 0x72B8) + #define LPIF_INT_PSTA_14_PSTA_HW_S1_HIGH_PERIOD_TIME_LSFR_POL Fld(20, 0) //[19:0] + #define LPIF_INT_PSTA_14_RESERVED_XAE_31_30 Fld(12, 20) //[31:20] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_0 (DDRPHY_MD32_BASE_ADDRESS + 0x72C0) + #define LPIF_HW_S1_0_HW_S1_PS_CHK_RESULT_CLR Fld(1, 0) //[0:0] + #define LPIF_HW_S1_0_HW_S1_LATCH_CLR Fld(1, 1) //[1:1] + #define LPIF_HW_S1_0_HW_S1_TRIG_BY_FSM_EN Fld(1, 2) //[2:2] + #define LPIF_HW_S1_0_HW_S1_TRIG_BY_IRQ_EN Fld(1, 3) //[3:3] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DMSUS_OFF Fld(1, 4) //[4:4] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MODE_SW Fld(1, 5) //[5:5] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_DLL_EN Fld(1, 6) //[6:6] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_2ND_DLL_EN Fld(1, 7) //[7:7] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_DLL_CK_EN Fld(1, 8) //[8:8] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_VREF_EN Fld(1, 9) //[9:9] + #define LPIF_HW_S1_0_HW_S1_BYPASS_EMI_CLK_OFF_REQ Fld(1, 10) //[10:10] + #define LPIF_HW_S1_0_HW_S1_BYPASS_MEM_CK_OFF Fld(1, 11) //[11:11] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DDRPHY_FB_CK_EN Fld(1, 12) //[12:12] + #define LPIF_HW_S1_0_HW_S1_BYPASS_TX_TRACKING_DIS Fld(1, 13) //[13:13] + #define LPIF_HW_S1_0_HW_S1_BYPASS_FHC_PAUSE_MPLL Fld(1, 14) //[14:14] + #define LPIF_HW_S1_0_HW_S1_BYPASS_FHC_PAUSE_MEM Fld(1, 15) //[15:15] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MCK8X_EN Fld(1, 16) //[16:16] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MIDPI_EN Fld(1, 17) //[17:17] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_PI_RESETB_EN Fld(1, 18) //[18:18] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DR_GATE_RETRY_EN Fld(1, 19) //[19:19] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPHY_PRECAL_UP Fld(1, 20) //[20:20] + #define LPIF_HW_S1_0_HW_S1_BYPASS_TX_TRACKING_RETRY_EN Fld(1, 21) //[21:21] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_CS_PULL_DN_EN Fld(1, 22) //[22:22] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_EMI_S1_MODE_ASYNC Fld(1, 23) //[23:23] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_CA_PULL_DN_EN Fld(1, 24) //[24:24] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_PICG_FREE Fld(1, 25) //[25:25] + #define LPIF_HW_S1_0_RESERVED_XB0_31_26 Fld(6, 26) //[31:26] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_1 (DDRPHY_MD32_BASE_ADDRESS + 0x72C4) + #define LPIF_HW_S1_1_HW_S1_PST_CHK Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_2 (DDRPHY_MD32_BASE_ADDRESS + 0x72C8) + #define LPIF_HW_S1_2_HW_S1_PST_CHK_RESULT Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_3 (DDRPHY_MD32_BASE_ADDRESS + 0x72CC) + #define LPIF_HW_S1_3_HW_S1_REQ Fld(1, 0) //[0:0] + #define LPIF_HW_S1_3_HW_S1_ACK Fld(1, 1) //[1:1] + #define LPIF_HW_S1_3_HW_S1_PST_REQ_CHK_RESULT Fld(1, 2) //[2:2] + #define LPIF_HW_S1_3_RESERVED_XB0_3_3 Fld(1, 3) //[3:3] + #define LPIF_HW_S1_3_RISING_HW_S1_REQ_LATCH Fld(1, 4) //[4:4] + #define LPIF_HW_S1_3_FALLING_HW_S1_REQ_LATCH Fld(1, 5) //[5:5] + #define LPIF_HW_S1_3_HW_S1_FSM Fld(6, 6) //[11:6] + #define LPIF_HW_S1_3_RESERVED_XB3_31_12 Fld(20, 12) //[31:12] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_4 (DDRPHY_MD32_BASE_ADDRESS + 0x72D0) + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_PI_RESETB_EN Fld(2, 0) //[1:0] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MCK8X_EN Fld(2, 4) //[5:4] + #define LPIF_HW_S1_4_HW_S1_DRAMC_TX_TRACKING_RETRY_EN Fld(2, 6) //[7:6] + #define LPIF_HW_S1_4_HW_S1_DRAMC_TX_TRACKING_DIS Fld(2, 8) //[9:8] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPHY_PRECAL_UP Fld(2, 10) //[11:10] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DR_GATE_RETRY_EN Fld(2, 12) //[13:12] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DDRPHY_FB_CK_EN Fld(2, 14) //[15:14] + #define LPIF_HW_S1_4_HW_S1_DRAMC_MEM_CK_OFF Fld(2, 16) //[17:16] + #define LPIF_HW_S1_4_HW_S1_DRAMC_EMI_CLK_OFF_REQ Fld(2, 18) //[19:18] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_VREF_EN Fld(2, 20) //[21:20] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_DLL_CK_EN Fld(2, 22) //[23:22] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_2ND_DLL_EN Fld(2, 24) //[25:24] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_DLL_EN Fld(2, 26) //[27:26] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MODE_SW Fld(2, 28) //[29:28] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DMSUS_OFF Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_5 (DDRPHY_MD32_BASE_ADDRESS + 0x72D4) + #define LPIF_HW_S1_5_HW_S1_DRAMC_FHC_PAUSE_MPLL Fld(1, 0) //[0:0] + #define LPIF_HW_S1_5_HW_S1_DRAMC_FHC_PAUSE_MEM Fld(1, 1) //[1:1] + #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_CS_PULL_DN_EN Fld(2, 2) //[3:2] + #define LPIF_HW_S1_5_HW_S1_DRAMC_EMI_S1_MODE_ASYNC Fld(1, 4) //[4:4] + #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_CA_PULL_DN_EN Fld(2, 5) //[6:5] + #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_PICG_FREE Fld(2, 8) //[9:8] + #define LPIF_HW_S1_5_RESERVED_XB5_31_10 Fld(22, 10) //[31:10] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_6 (DDRPHY_MD32_BASE_ADDRESS + 0x72D8) + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DMSUS_OFF Fld(1, 0) //[0:0] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MODE_SW Fld(1, 1) //[1:1] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_DLL_EN Fld(1, 2) //[2:2] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_2ND_DLL_EN Fld(1, 3) //[3:3] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_DLL_CK_EN Fld(1, 4) //[4:4] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_VREF_EN Fld(1, 5) //[5:5] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_EMI_CLK_OFF_REQ Fld(1, 6) //[6:6] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_MEM_CK_OFF Fld(1, 7) //[7:7] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DDRPHY_FB_CK_EN Fld(1, 8) //[8:8] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_TX_TRACKING_DIS Fld(1, 9) //[9:9] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_FHC_PAUSE_MPLL Fld(1, 10) //[10:10] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_FHC_PAUSE_MEM Fld(1, 11) //[11:11] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MCK8X_EN Fld(1, 12) //[12:12] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MIDPI_EN Fld(1, 13) //[13:13] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_PI_RESETB_EN Fld(1, 14) //[14:14] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DR_GATE_RETRY_EN Fld(1, 15) //[15:15] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPHY_PRECAL_UP Fld(1, 16) //[16:16] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_TX_TRACKING_RETRY_EN Fld(1, 17) //[17:17] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_CS_PULL_DN_EN Fld(1, 18) //[18:18] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_CA_PULL_DN_EN Fld(1, 19) //[19:19] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_EMI_S1_MODE_ASYNC Fld(1, 20) //[20:20] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_PICG_FREE Fld(1, 21) //[21:21] + #define LPIF_HW_S1_6_RESERVED_XB6_31_22 Fld(10, 22) //[31:22] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH0 (DDRPHY_MD32_BASE_ADDRESS + 0x7380) + #define LPIF_DBG_LATCH0_LPIF_DDR_PST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH1 (DDRPHY_MD32_BASE_ADDRESS + 0x7384) + #define LPIF_DBG_LATCH1_CUR_LPIF_DDR_PST_STA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH2 (DDRPHY_MD32_BASE_ADDRESS + 0x7388) + #define LPIF_DBG_LATCH2_EMI_CLK_OFF_REQ_ACK Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH2_RESERVED_XE2_3_2 Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH2_DRAMC_DFS_STA Fld(4, 4) //[7:4] + #define LPIF_DBG_LATCH2_DQSSOC_REQ Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH2_RESERVED_XE2_11_10 Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH2_DR_SHORT_QUEUE_ACK Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH2_DR_SHU_EN_ACK Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH2_DR_SRAM_PLL_LOAD_ACK Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH2_DR_SRAM_LOAD_ACK Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH2_DR_SRAM_RESTORE_ACK Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH2_TX_TRACKING_DIS_ACK Fld(2, 22) //[23:22] + #define LPIF_DBG_LATCH2_DDR_PST_ACK Fld(1, 24) //[24:24] + #define LPIF_DBG_LATCH2_DDR_PST_ABORT_ACK Fld(1, 25) //[25:25] + #define LPIF_DBG_LATCH2_EMI_SLEEP_IDLE Fld(1, 26) //[26:26] + #define LPIF_DBG_LATCH2_EMI_SLEEP_PROT_EN Fld(1, 27) //[27:27] + #define LPIF_DBG_LATCH2_DDR_PST_REQ Fld(1, 28) //[28:28] + #define LPIF_DBG_LATCH2_DDR_PST_ABORT_REQ Fld(1, 29) //[29:29] + #define LPIF_DBG_LATCH2_DDR_PST_ABORT_REQ_LATCH Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH2_LPC_INTERNAL_COUNTER_ABORT_FLAG Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH3 (DDRPHY_MD32_BASE_ADDRESS + 0x738C) + #define LPIF_DBG_LATCH3_DDR_PST_STA_D0 Fld(6, 0) //[5:0] + #define LPIF_DBG_LATCH3_DDR_PST_ACK_D0 Fld(1, 6) //[6:6] + #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D0 Fld(1, 7) //[7:7] + #define LPIF_DBG_LATCH3_DDR_PST_STA_D1 Fld(6, 8) //[13:8] + #define LPIF_DBG_LATCH3_DDR_PST_ACK_D1 Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D1 Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH3_DDR_PST_STA_D2 Fld(6, 16) //[21:16] + #define LPIF_DBG_LATCH3_DDR_PST_ACK_D2 Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D2 Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH3_DDR_PST_STA_D3 Fld(6, 24) //[29:24] + #define LPIF_DBG_LATCH3_DDR_PST_ACK_D3 Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D3 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH4 (DDRPHY_MD32_BASE_ADDRESS + 0x7390) + #define LPIF_DBG_LATCH4_DDR_PST_STA_D4 Fld(6, 0) //[5:0] + #define LPIF_DBG_LATCH4_DDR_PST_ACK_D4 Fld(1, 6) //[6:6] + #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D4 Fld(1, 7) //[7:7] + #define LPIF_DBG_LATCH4_DDR_PST_STA_D5 Fld(6, 8) //[13:8] + #define LPIF_DBG_LATCH4_DDR_PST_ACK_D5 Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D5 Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH4_DDR_PST_STA_D6 Fld(6, 16) //[21:16] + #define LPIF_DBG_LATCH4_DDR_PST_ACK_D6 Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D6 Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH4_DDR_PST_STA_D7 Fld(6, 24) //[29:24] + #define LPIF_DBG_LATCH4_DDR_PST_ACK_D7 Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D7 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH5 (DDRPHY_MD32_BASE_ADDRESS + 0x7394) + #define LPIF_DBG_LATCH5_DDR_PST_STA_D8 Fld(6, 0) //[5:0] + #define LPIF_DBG_LATCH5_DDR_PST_ACK_D8 Fld(1, 6) //[6:6] + #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_D8 Fld(1, 7) //[7:7] + #define LPIF_DBG_LATCH5_DDR_PST_STA_D9 Fld(6, 8) //[13:8] + #define LPIF_DBG_LATCH5_DDR_PST_ACK_D9 Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_D9 Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH5_DDR_PST_STA_DA Fld(6, 16) //[21:16] + #define LPIF_DBG_LATCH5_DDR_PST_ACK_DA Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_DA Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH5_DDR_PST_STA_DB Fld(6, 24) //[29:24] + #define LPIF_DBG_LATCH5_DDR_PST_ACK_DB Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_DB Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH6 (DDRPHY_MD32_BASE_ADDRESS + 0x7398) + #define LPIF_DBG_LATCH6_DDR_PST_STA_DC Fld(6, 0) //[5:0] + #define LPIF_DBG_LATCH6_DDR_PST_ACK_DC Fld(1, 6) //[6:6] + #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DC Fld(1, 7) //[7:7] + #define LPIF_DBG_LATCH6_DDR_PST_STA_DD Fld(6, 8) //[13:8] + #define LPIF_DBG_LATCH6_DDR_PST_ACK_DD Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DD Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH6_DDR_PST_STA_DE Fld(6, 16) //[21:16] + #define LPIF_DBG_LATCH6_DDR_PST_ACK_DE Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DE Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH6_DDR_PST_STA_DF Fld(6, 24) //[29:24] + #define LPIF_DBG_LATCH6_DDR_PST_ACK_DF Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DF Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH7 (DDRPHY_MD32_BASE_ADDRESS + 0x739C) + #define LPIF_DBG_LATCH7_DRAMC_DMSUS_OFF Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_EN Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH7_DRAMC_DPY_DLL_EN Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH7_DRAMC_DPY_2ND_DLL_EN Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH7_DRAMC_DPY_DLL_CK_EN Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH7_DRAMC_DPY_VREF_EN Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH7_DRAMC_EMI_CLK_OFF_REQ Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH7_DRAMC_MEM_CK_OFF Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH7_DRAMC_DDRPHY_FB_CK_EN Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH7_DRAMC_DR_GATE_RETRY_EN Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_SHU_EN Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_MODE_SW Fld(2, 22) //[23:22] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL2_SHU_EN Fld(2, 24) //[25:24] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL2_MODE_SW Fld(2, 26) //[27:26] + #define LPIF_DBG_LATCH7_DRAMC_DR_SHU_EN Fld(2, 28) //[29:28] + #define LPIF_DBG_LATCH7_DRAMC_DR_SHORT_QUEUE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH8 (DDRPHY_MD32_BASE_ADDRESS + 0x73A0) + #define LPIF_DBG_LATCH8_DRAMC_DR_SHU_LEVEL Fld(4, 0) //[3:0] + #define LPIF_DBG_LATCH8_DRAMC_DPY_BCLK_ENABLE Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH8_DRAMC_SHU_RESTORE Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH8_DRAMC_DPHY_PRECAL_UP Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH8_DRAMC_DPHY_RXDLY_TRACK_EN Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH8_DRAMC_DMY_EN_MOD_SEL Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH8_DRAMC_DMYRD_INTV_SEL Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH8_DRAMC_DMYRD_EN Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH8_DRAMC_TX_TRACKING_DIS Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH8_DRAMC_TX_TRACKING_RETRY_EN Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH8_DRAMC_DR_SHU_SRAM_LEVEL Fld(8, 22) //[29:22] + #define LPIF_DBG_LATCH8_DRAMC_DR_SRAM_LOAD Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH9 (DDRPHY_MD32_BASE_ADDRESS + 0x73A4) + #define LPIF_DBG_LATCH9_DRAMC_DPY_MCK8X_EN Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH9_DRAMC_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH9_DRAMC_DPY_PI_RESETB_EN Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH9_DRAMC_DVFS_MEM_CK_MUX_UPDATE Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH9_DRAMC_DVFS_MEM_CK_MUX_SEL Fld(4, 8) //[11:8] + #define LPIF_DBG_LATCH9_DRAMC_DPY_DSM_EN Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH9_DRAMC_DPY_FASTK_RDDQS_EN Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH9_DRAMC_DPY_CS_PULL_UP_EN Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH9_DRAMC_DPY_CS_PULL_DN_EN Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH9_DRAMC_DPY_CA_PULL_UP_EN Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH9_DRAMC_DPY_CA_PULL_DN_EN Fld(2, 22) //[23:22] + #define LPIF_DBG_LATCH9_DRAMC_FHC_PAUSE_MEM Fld(1, 24) //[24:24] + #define LPIF_DBG_LATCH9_DRAMC_FHC_PAUSE_MPLL Fld(1, 25) //[25:25] + #define LPIF_DBG_LATCH9_DRAMC_MPLL_S_OFF Fld(1, 26) //[26:26] + #define LPIF_DBG_LATCH9_DRAMC_MPLLOUT_OFF Fld(1, 27) //[27:27] + #define LPIF_DBG_LATCH9_DRAMC_EMI_S1_MODE_ASYNC Fld(1, 28) //[28:28] + #define LPIF_DBG_LATCH9_RESERVED_XE9_29_29 Fld(1, 29) //[29:29] + #define LPIF_DBG_LATCH9_DRAMC_DPY_PICG_FREE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH10 (DDRPHY_MD32_BASE_ADDRESS + 0x73A8) + #define LPIF_DBG_LATCH10_DRAMC_DR_SRAM_RESTORE Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH10_DRAMC_DR_SHU_LEVEL_SRAM_LATCH Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH10_DRAMC_DPY_MODE_SW Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH10_RESERVED_XEA_7_6 Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH10_DRAMC_DPY_RESERVED Fld(8, 8) //[15:8] + #define LPIF_DBG_LATCH10_DRAMC_DRAMC_DFS_CON Fld(13, 16) //[28:16] + #define LPIF_DBG_LATCH10_RESERVED_XEA_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH11 (DDRPHY_MD32_BASE_ADDRESS + 0x73AC) + #define LPIF_DBG_LATCH11_FSM_TIME_OUT_FLAG Fld(1, 0) //[0:0] + #define LPIF_DBG_LATCH11_EXP_FSM_JUMP Fld(1, 1) //[1:1] + #define LPIF_DBG_LATCH11_IRQ_LPIF_LOW_POWER Fld(1, 2) //[2:2] + #define LPIF_DBG_LATCH11_IRQ_LPIF_OTHERS_STATE Fld(1, 3) //[3:3] + #define LPIF_DBG_LATCH11_DFS_STATUS_RECORD Fld(4, 4) //[7:4] + #define LPIF_DBG_LATCH11_DVS_STATUS_RECORD Fld(1, 8) //[8:8] + #define LPIF_DBG_LATCH11_RUNTIME_STATUS_RECORD Fld(1, 9) //[9:9] + #define LPIF_DBG_LATCH11_RESERVED_XEB_11_10 Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH11_MUX_LPIF_DPHY_RXDLY_TRACK_EN Fld(1, 12) //[12:12] + #define LPIF_DBG_LATCH11_MUX_LPIF_DMYRD_EN Fld(1, 13) //[13:13] + #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACKING_DIS Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH11_MUX_LPIF_DR_SRAM_RESTORE Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACK_RETRY_EN Fld(1, 16) //[16:16] + #define LPIF_DBG_LATCH11_MUX_LPIF_RX_GATING_RETRY_EN Fld(1, 17) //[17:17] + #define LPIF_DBG_LATCH11_MUX_LPIF_DLL_ALL_SLAVE_EN Fld(1, 18) //[18:18] + #define LPIF_DBG_LATCH11_MUX_LPIF_IMPEDANCE_TRACKING_EN Fld(1, 19) //[19:19] + #define LPIF_DBG_LATCH11_MUX_LPIF_DPHY_RXDLY_TRACK_EN_PREV Fld(1, 20) //[20:20] + #define LPIF_DBG_LATCH11_MUX_LPIF_DMYRD_EN_PREV Fld(1, 21) //[21:21] + #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACKING_DIS_PREV Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH11_MUX_LPIF_DR_SRAM_RESTORE_PREV Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACK_RETRY_EN_PREV Fld(1, 24) //[24:24] + #define LPIF_DBG_LATCH11_MUX_LPIF_RX_GATING_RETRY_EN_PREV Fld(1, 25) //[25:25] + #define LPIF_DBG_LATCH11_MUX_LPIF_DLL_ALL_SLAVE_EN_PREV Fld(1, 26) //[26:26] + #define LPIF_DBG_LATCH11_MUX_LPIF_IMPEDANCE_TRACKING_EN_PREV Fld(1, 27) //[27:27] + #define LPIF_DBG_LATCH11_SHU_INDEX Fld(1, 28) //[28:28] + #define LPIF_DBG_LATCH11_RESERVED_XEB_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH12 (DDRPHY_MD32_BASE_ADDRESS + 0x73B0) + #define LPIF_DBG_LATCH12_DRAMC_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH12_DRAMC_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH12_DRAMC_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH12_DRAMC_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH12_DRAMC_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH12_DRAMC_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_DBG_LATCH12_DRAMC_PWR_SRAM_PDN Fld(4, 16) //[19:16] + #define LPIF_DBG_LATCH12_DRAMC_PWR_SC_SRAM_PDN_ACK Fld(1, 20) //[20:20] + #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_CKISO Fld(2, 26) //[27:26] + #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_ISOINT_B Fld(2, 28) //[29:28] + #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH13 (DDRPHY_MD32_BASE_ADDRESS + 0x73B4) + #define LPIF_DBG_LATCH13_DRAMC_LPIF_COM Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH14 (DDRPHY_MD32_BASE_ADDRESS + 0x73B8) + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_PI_RESETB_EN Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MCK8X_EN Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_TX_TRACKING_RETRY_EN Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_TX_TRACKING_DIS Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPHY_PRECAL_UP Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DR_GATE_RETRY_EN Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DDRPHY_FB_CK_EN Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_MEM_CK_OFF Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_EMI_CLK_OFF_REQ Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_VREF_EN Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_DLL_CK_EN Fld(2, 22) //[23:22] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_2ND_DLL_EN Fld(2, 24) //[25:24] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_DLL_EN Fld(2, 26) //[27:26] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MODE_SW Fld(2, 28) //[29:28] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DMSUS_OFF Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH15 (DDRPHY_MD32_BASE_ADDRESS + 0x73BC) + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_FHC_PAUSE_MPLL Fld(1, 0) //[0:0] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_FHC_PAUSE_MEM Fld(1, 1) //[1:1] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_CS_PULL_DN_EN Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_EMI_S1_MODE_ASYNC Fld(1, 4) //[4:4] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_CA_PULL_DN_EN Fld(2, 5) //[6:5] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_PICG_FREE Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH15_PWR_ON_ACK Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH15_PWR_ON_2ND_ACK Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH15_SRAM_PDN_ACK Fld(4, 16) //[19:16] + #define LPIF_DBG_LATCH15_HW_S1_REQ Fld(1, 20) //[20:20] + #define LPIF_DBG_LATCH15_HW_S1_ACK Fld(1, 21) //[21:21] + #define LPIF_DBG_LATCH15_HW_S1_PST_REQ_CHK_RESULT Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH15_RESERVED_XEF_31_23 Fld(9, 23) //[31:23] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH16 (DDRPHY_MD32_BASE_ADDRESS + 0x73C0) + #define LPIF_DBG_LATCH16_HW_S1_PST_CHK_RESULT Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH17 (DDRPHY_MD32_BASE_ADDRESS + 0x73C4) + #define LPIF_DBG_LATCH17_MAX_CNT_SREF_REQ_HIGH_TO_SREF_ACK Fld(8, 0) //[7:0] + #define LPIF_DBG_LATCH17_MAX_CNT_SREF_REQ_LOW_TO_SREF_ACK Fld(8, 8) //[15:8] + #define LPIF_DBG_LATCH17_MAX_CNT_SHU_EN_HIGH_TO_ACK Fld(8, 16) //[23:16] + #define LPIF_DBG_LATCH17_MAX_CNT_HW_S1_REQ_LOW_TO_SREF_ACK_LOW Fld(8, 24) //[31:24] + +#endif // __DDRPHY_MD32_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h new file mode 100644 index 0000000000..30c0c2a8f1 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h @@ -0,0 +1,1147 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_NAO_REGS_H__ +#define __DDRPHY_NAO_REGS_H__ + +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x10236000 +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x10246000 + +#define DDRPHY_NAO_BASE_ADDRESS Channel_A_DDRPHY_NAO_BASE_VIRTUAL + +#define DDRPHY_REG_MISC_STA_EXTLB0 (DDRPHY_NAO_BASE_ADDRESS + 0x0000) + #define MISC_STA_EXTLB0_STA_EXTLB_DONE Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB1 (DDRPHY_NAO_BASE_ADDRESS + 0x0004) + #define MISC_STA_EXTLB1_STA_EXTLB_FAIL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB2 (DDRPHY_NAO_BASE_ADDRESS + 0x0008) + #define MISC_STA_EXTLB2_STA_EXTLB_DBG_INFO Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DMA_DEBUG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0010) + #define MISC_DMA_DEBUG0_WPTR Fld(2, 0) //[1:0] + #define MISC_DMA_DEBUG0_RPTR Fld(2, 2) //[3:2] + #define MISC_DMA_DEBUG0_CMD_CNT Fld(3, 4) //[6:4] + #define MISC_DMA_DEBUG0_DATA_CNT Fld(3, 8) //[10:8] + #define MISC_DMA_DEBUG0_FIFO_EMPTY Fld(1, 12) //[12:12] + #define MISC_DMA_DEBUG0_FIFO_FULL Fld(1, 13) //[13:13] + #define MISC_DMA_DEBUG0_DMA_FIRE Fld(1, 14) //[14:14] + #define MISC_DMA_DEBUG0_SHU_REG_PTR Fld(1, 15) //[15:15] + #define MISC_DMA_DEBUG0_SRAM_DONE Fld(1, 16) //[16:16] + #define MISC_DMA_DEBUG0_APB_DONE Fld(1, 17) //[17:17] + #define MISC_DMA_DEBUG0_SRAM_DONE_EARLY Fld(1, 18) //[18:18] + #define MISC_DMA_DEBUG0_APB_DONE_EARLY Fld(1, 19) //[19:19] + #define MISC_DMA_DEBUG0_SRAM_STEP Fld(4, 20) //[23:20] + #define MISC_DMA_DEBUG0_APB_STEP Fld(4, 24) //[27:24] + #define MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK Fld(1, 28) //[28:28] + #define MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK Fld(1, 29) //[29:29] + #define MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK Fld(1, 30) //[30:30] + +#define DDRPHY_REG_MISC_DMA_DEBUG1 (DDRPHY_NAO_BASE_ADDRESS + 0x0014) + #define MISC_DMA_DEBUG1_DMA_TIMER_EARLY Fld(6, 0) //[5:0] + #define MISC_DMA_DEBUG1_DMA_TIMER_ALL Fld(12, 8) //[19:8] + #define MISC_DMA_DEBUG1_PSEL_DDRPHY Fld(1, 20) //[20:20] + #define MISC_DMA_DEBUG1_PSEL_DRAMC Fld(1, 21) //[21:21] + #define MISC_DMA_DEBUG1_PSEL_DDRPHY2 Fld(1, 22) //[22:22] + #define MISC_DMA_DEBUG1_PSEL_DRAMC2 Fld(1, 23) //[23:23] + #define MISC_DMA_DEBUG1_DMA_PENABLE Fld(1, 24) //[24:24] + #define MISC_DMA_DEBUG1_PREADY Fld(1, 25) //[25:25] + #define MISC_DMA_DEBUG1_KEEP_APB_ARB Fld(1, 26) //[26:26] + #define MISC_DMA_DEBUG1_WR_APB Fld(1, 27) //[27:27] + #define MISC_DMA_DEBUG1_SRAM_CS Fld(1, 28) //[28:28] + #define MISC_DMA_DEBUG1_SRAM_GRANT Fld(1, 29) //[29:29] + #define MISC_DMA_DEBUG1_KEEP_SRAM_ARB Fld(1, 30) //[30:30] + #define MISC_DMA_DEBUG1_WR_SRAM Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_RETRY_DBG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0018) + #define MISC_RETRY_DBG0_PRECAL_CONF_CAL_DONE_ALL Fld(1, 0) //[0:0] + #define MISC_RETRY_DBG0_RETRY_DONE_ALL Fld(1, 1) //[1:1] + #define MISC_RETRY_DBG0_RK0_RETRY_DONE0 Fld(1, 4) //[4:4] + #define MISC_RETRY_DBG0_RK0_RETRY_DONE1 Fld(1, 5) //[5:5] + #define MISC_RETRY_DBG0_RK0_RETRY_DONE2 Fld(1, 6) //[6:6] + #define MISC_RETRY_DBG0_RK0_RETRY_FAIL0 Fld(1, 8) //[8:8] + #define MISC_RETRY_DBG0_RK0_RETRY_FAIL1 Fld(1, 9) //[9:9] + #define MISC_RETRY_DBG0_RK0_RETRY_FAIL2 Fld(1, 10) //[10:10] + #define MISC_RETRY_DBG0_RK1_RETRY_DONE0 Fld(1, 12) //[12:12] + #define MISC_RETRY_DBG0_RK1_RETRY_DONE1 Fld(1, 13) //[13:13] + #define MISC_RETRY_DBG0_RK1_RETRY_DONE2 Fld(1, 14) //[14:14] + #define MISC_RETRY_DBG0_RK1_RETRY_FAIL0 Fld(1, 16) //[16:16] + #define MISC_RETRY_DBG0_RK1_RETRY_FAIL1 Fld(1, 17) //[17:17] + #define MISC_RETRY_DBG0_RK1_RETRY_FAIL2 Fld(1, 18) //[18:18] + +#define DDRPHY_REG_MISC_RETRY_DBG1 (DDRPHY_NAO_BASE_ADDRESS + 0x001C) + #define MISC_RETRY_DBG1_DQSG_RETRY_1ST_ST Fld(8, 0) //[7:0] + #define MISC_RETRY_DBG1_DQSG_RETRY_2ND_ST Fld(8, 8) //[15:8] + #define MISC_RETRY_DBG1_DQSG_RETRY_3RD_ST Fld(8, 16) //[23:16] + #define MISC_RETRY_DBG1_DQSG_RETRY_4TH_ST Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_RETRY_DBG2 (DDRPHY_NAO_BASE_ADDRESS + 0x0020) + #define MISC_RETRY_DBG2_DQSG_RETRY_5TH_ST Fld(8, 0) //[7:0] + +#define DDRPHY_REG_MISC_RDSEL_TRACK_DBG (DDRPHY_NAO_BASE_ADDRESS + 0x0024) + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_SLOW_ST Fld(1, 2) //[2:2] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_FAST_ST Fld(1, 3) //[3:3] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_INI2SLOW Fld(1, 4) //[4:4] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_INI2FAST Fld(1, 5) //[5:5] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_SLOW2INI Fld(1, 6) //[6:6] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_FAST2INI Fld(1, 7) //[7:7] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO0 (DDRPHY_NAO_BASE_ADDRESS + 0x0080) + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B0 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B0 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B1 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0084) + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B2 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B2 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B3 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B3 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO2 (DDRPHY_NAO_BASE_ADDRESS + 0x0088) + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B4 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B4 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B5 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B5 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO3 (DDRPHY_NAO_BASE_ADDRESS + 0x008C) + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B6 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B6 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B7 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B7 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO4 (DDRPHY_NAO_BASE_ADDRESS + 0x0090) + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B0 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B1 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B2 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B3 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO5 (DDRPHY_NAO_BASE_ADDRESS + 0x0094) + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B4 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B5 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B6 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B7 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO6 (DDRPHY_NAO_BASE_ADDRESS + 0x0098) + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LAG_CNT_OUT_DQM0 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LEAD_CNT_OUT_DQM0 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_LEAD_LAG_CNT_OUT_DQM0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO7 (DDRPHY_NAO_BASE_ADDRESS + 0x009C) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B0_SW_UP_DONE Fld(1, 0) //[0:0] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B1_SW_UP_DONE Fld(1, 4) //[4:4] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B0_SW_UP_DONE Fld(1, 8) //[8:8] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B1_SW_UP_DONE Fld(1, 12) //[12:12] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B0_SW_UP_DONE Fld(1, 16) //[16:16] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B1_SW_UP_DONE Fld(1, 20) //[20:20] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO8 (DDRPHY_NAO_BASE_ADDRESS + 0x00A0) + #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B0 Fld(9, 0) //[8:0] + #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B1 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO9 (DDRPHY_NAO_BASE_ADDRESS + 0x00A4) + #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B2 Fld(9, 0) //[8:0] + #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B3 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO10 (DDRPHY_NAO_BASE_ADDRESS + 0x00A8) + #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B4 Fld(9, 0) //[8:0] + #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B5 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO11 (DDRPHY_NAO_BASE_ADDRESS + 0x00AC) + #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B6 Fld(9, 0) //[8:0] + #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B7 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO12 (DDRPHY_NAO_BASE_ADDRESS + 0x00B0) + #define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_TH_CNT_OUT_DQM0 Fld(9, 0) //[8:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO13 (DDRPHY_NAO_BASE_ADDRESS + 0x00B4) + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B0_R_DLY Fld(6, 0) //[5:0] + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS0_R_DLY Fld(7, 8) //[14:8] + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B1_R_DLY Fld(6, 16) //[21:16] + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS1_R_DLY Fld(7, 24) //[30:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO14 (DDRPHY_NAO_BASE_ADDRESS + 0x00B8) + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B0_R_DLY Fld(6, 0) //[5:0] + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS0_R_DLY Fld(7, 8) //[14:8] + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B1_R_DLY Fld(6, 16) //[21:16] + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS1_R_DLY Fld(7, 24) //[30:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO15 (DDRPHY_NAO_BASE_ADDRESS + 0x00BC) + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B0_R_DLY Fld(6, 0) //[5:0] + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS0_R_DLY Fld(7, 8) //[14:8] + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B1_R_DLY Fld(6, 16) //[21:16] + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS1_R_DLY Fld(7, 24) //[30:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO16 (DDRPHY_NAO_BASE_ADDRESS + 0x00C0) + #define MISC_DQ_RXDLY_TRRO16_DVS_RXDLY_STS_ERR_CNT_ALL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO17 (DDRPHY_NAO_BASE_ADDRESS + 0x00C4) + #define MISC_DQ_RXDLY_TRRO17_DVS_RXDLY_STS_ERR_CNT_ALL_47_32 Fld(16, 0) //[15:0] + #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B0 Fld(1, 16) //[16:16] + #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B1 Fld(1, 24) //[24:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO18 (DDRPHY_NAO_BASE_ADDRESS + 0x00C8) + #define MISC_DQ_RXDLY_TRRO18_RXDLY_DBG_MON_VALID Fld(1, 0) //[0:0] + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK0_FAIL_LAT Fld(1, 1) //[1:1] + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK1_FAIL_LAT Fld(1, 2) //[2:2] + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK2_FAIL_LAT Fld(1, 3) //[3:3] + #define MISC_DQ_RXDLY_TRRO18_DFS_SHU_GP_FAIL_LAT Fld(2, 4) //[5:4] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO19 (DDRPHY_NAO_BASE_ADDRESS + 0x00CC) + #define MISC_DQ_RXDLY_TRRO19_RESERVED_0X00C Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO20 (DDRPHY_NAO_BASE_ADDRESS + 0x00D0) + #define MISC_DQ_RXDLY_TRRO20_RESERVED_0X0D0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO21 (DDRPHY_NAO_BASE_ADDRESS + 0x00D4) + #define MISC_DQ_RXDLY_TRRO21_RESERVED_0X0D4 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO22 (DDRPHY_NAO_BASE_ADDRESS + 0x00D8) + #define MISC_DQ_RXDLY_TRRO22_RESERVED_0X0D8 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO23 (DDRPHY_NAO_BASE_ADDRESS + 0x00DC) + #define MISC_DQ_RXDLY_TRRO23_RESERVED_0X0DC Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO24 (DDRPHY_NAO_BASE_ADDRESS + 0x00E0) + #define MISC_DQ_RXDLY_TRRO24_RESERVED_0X0E0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO25 (DDRPHY_NAO_BASE_ADDRESS + 0x00E4) + #define MISC_DQ_RXDLY_TRRO25_RESERVED_0X0E4 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO26 (DDRPHY_NAO_BASE_ADDRESS + 0x00E8) + #define MISC_DQ_RXDLY_TRRO26_RESERVED_0X0E8 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO27 (DDRPHY_NAO_BASE_ADDRESS + 0x00EC) + #define MISC_DQ_RXDLY_TRRO27_RESERVED_0X0EC Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO28 (DDRPHY_NAO_BASE_ADDRESS + 0x00F0) + #define MISC_DQ_RXDLY_TRRO28_RESERVED_0X0F0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO29 (DDRPHY_NAO_BASE_ADDRESS + 0x00F4) + #define MISC_DQ_RXDLY_TRRO29_RESERVED_0X0F4 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO30 (DDRPHY_NAO_BASE_ADDRESS + 0x00F8) + #define MISC_DQ_RXDLY_TRRO30_RESERVED_0X0F8 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO31 (DDRPHY_NAO_BASE_ADDRESS + 0x00FC) + #define MISC_DQ_RXDLY_TRRO31_RESERVED_0X0FC Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO20 (DDRPHY_NAO_BASE_ADDRESS + 0x0150) + #define MISC_CA_RXDLY_TRRO20_RESERVED_0X150 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO21 (DDRPHY_NAO_BASE_ADDRESS + 0x0154) + #define MISC_CA_RXDLY_TRRO21_RESERVED_0X154 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO22 (DDRPHY_NAO_BASE_ADDRESS + 0x0158) + #define MISC_CA_RXDLY_TRRO22_RESERVED_0X158 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO23 (DDRPHY_NAO_BASE_ADDRESS + 0x015C) + #define MISC_CA_RXDLY_TRRO23_RESERVED_0X15C Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO24 (DDRPHY_NAO_BASE_ADDRESS + 0x0160) + #define MISC_CA_RXDLY_TRRO24_RESERVED_0X160 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO25 (DDRPHY_NAO_BASE_ADDRESS + 0x0164) + #define MISC_CA_RXDLY_TRRO25_RESERVED_0X164 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO26 (DDRPHY_NAO_BASE_ADDRESS + 0x0168) + #define MISC_CA_RXDLY_TRRO26_RESERVED_0X168 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO27 (DDRPHY_NAO_BASE_ADDRESS + 0x016C) + #define MISC_CA_RXDLY_TRRO27_RESERVED_0X16C Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO28 (DDRPHY_NAO_BASE_ADDRESS + 0x0170) + #define MISC_CA_RXDLY_TRRO28_RESERVED_0X170 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO29 (DDRPHY_NAO_BASE_ADDRESS + 0x0174) + #define MISC_CA_RXDLY_TRRO29_RESERVED_0X174 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO30 (DDRPHY_NAO_BASE_ADDRESS + 0x0178) + #define MISC_CA_RXDLY_TRRO30_RESERVED_0X178 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO31 (DDRPHY_NAO_BASE_ADDRESS + 0x017C) + #define MISC_CA_RXDLY_TRRO31_RESERVED_0X17C Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0180) + #define MISC_DQO1_DQO1_RO Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CAO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0184) + #define MISC_CAO1_DQM0O1_RO Fld(1, 0) //[0:0] + #define MISC_CAO1_DQM1O1_RO Fld(1, 1) //[1:1] + #define MISC_CAO1_DQM2O1_RO Fld(1, 2) //[2:2] + #define MISC_CAO1_DQM3O1_RO Fld(1, 3) //[3:3] + +#define DDRPHY_REG_MISC_AD_RX_DQ_O1 (DDRPHY_NAO_BASE_ADDRESS + 0x0188) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0 Fld(8, 0) //[7:0] + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0 Fld(1, 8) //[8:8] + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1 Fld(8, 16) //[23:16] + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1 Fld(1, 24) //[24:24] + +#define DDRPHY_REG_MISC_AD_RX_CMD_O1 (DDRPHY_NAO_BASE_ADDRESS + 0x018C) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA0_O1 Fld(1, 0) //[0:0] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA1_O1 Fld(1, 1) //[1:1] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA2_O1 Fld(1, 2) //[2:2] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA3_O1 Fld(1, 3) //[3:3] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA4_O1 Fld(1, 4) //[4:4] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA5_O1 Fld(1, 5) //[5:5] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA6_O1 Fld(1, 6) //[6:6] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA7_O1 Fld(1, 7) //[7:7] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA8_O1 Fld(1, 8) //[8:8] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA9_O1 Fld(1, 9) //[9:9] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1 Fld(1, 10) //[10:10] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1 Fld(1, 11) //[11:11] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE2_O1 Fld(1, 12) //[12:12] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1 Fld(1, 13) //[13:13] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1 Fld(1, 14) //[14:14] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS2_O1 Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_PHY_RGS_DQ (DDRPHY_NAO_BASE_ADDRESS + 0x0190) + #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B0 Fld(8, 0) //[7:0] + #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B0 Fld(1, 8) //[8:8] + #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B0 Fld(1, 9) //[9:9] + #define MISC_PHY_RGS_DQ_APB_ARB_M_DEBUG Fld(2, 12) //[13:12] + #define MISC_PHY_RGS_DQ_SRAM_ARB_M_DEBUG Fld(2, 14) //[15:14] + #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B1 Fld(8, 16) //[23:16] + #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B1 Fld(1, 24) //[24:24] + #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B1 Fld(1, 25) //[25:25] + #define MISC_PHY_RGS_DQ_DA_RPHYPLLGP_CK_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_PHY_RGS_CMD (DDRPHY_NAO_BASE_ADDRESS + 0x0194) + #define MISC_PHY_RGS_CMD_RGS_ARCA0_OFFSET_FLAG Fld(1, 0) //[0:0] + #define MISC_PHY_RGS_CMD_RGS_ARCA1_OFFSET_FLAG Fld(1, 1) //[1:1] + #define MISC_PHY_RGS_CMD_RGS_ARCA2_OFFSET_FLAG Fld(1, 2) //[2:2] + #define MISC_PHY_RGS_CMD_RGS_ARCA3_OFFSET_FLAG Fld(1, 3) //[3:3] + #define MISC_PHY_RGS_CMD_RGS_ARCA4_OFFSET_FLAG Fld(1, 4) //[4:4] + #define MISC_PHY_RGS_CMD_RGS_ARCA5_OFFSET_FLAG Fld(1, 5) //[5:5] + #define MISC_PHY_RGS_CMD_RGS_ARCA6_OFFSET_FLAG Fld(1, 6) //[6:6] + #define MISC_PHY_RGS_CMD_RGS_ARCA7_OFFSET_FLAG Fld(1, 7) //[7:7] + #define MISC_PHY_RGS_CMD_RGS_ARCA8_OFFSET_FLAG Fld(1, 8) //[8:8] + #define MISC_PHY_RGS_CMD_RGS_ARCA9_OFFSET_FLAG Fld(1, 9) //[9:9] + #define MISC_PHY_RGS_CMD_RGS_ARCKE0_OFFSET_FLAG Fld(1, 10) //[10:10] + #define MISC_PHY_RGS_CMD_RGS_ARCKE1_OFFSET_FLAG Fld(1, 11) //[11:11] + #define MISC_PHY_RGS_CMD_RGS_ARCKE2_OFFSET_FLAG Fld(1, 12) //[12:12] + #define MISC_PHY_RGS_CMD_RGS_ARCS0_OFFSET_FLAG Fld(1, 13) //[13:13] + #define MISC_PHY_RGS_CMD_RGS_ARCS1_OFFSET_FLAG Fld(1, 14) //[14:14] + #define MISC_PHY_RGS_CMD_RGS_ARCS2_OFFSET_FLAG Fld(1, 15) //[15:15] + #define MISC_PHY_RGS_CMD_RGS_RX_ARCLK_RDY_EYE Fld(1, 16) //[16:16] + #define MISC_PHY_RGS_CMD_RGS_RIMPCALOUT Fld(1, 24) //[24:24] + +#define DDRPHY_REG_MISC_PHY_RGS_STBEN_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0198) + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ0_STBEN_B0 Fld(9, 0) //[8:0] + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0 Fld(1, 16) //[16:16] + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0 Fld(1, 17) //[17:17] + #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_PD_EN_B0 Fld(1, 18) //[18:18] + #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_MON_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_PHY_RGS_STBEN_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x019C) + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ0_STBEN_B1 Fld(9, 0) //[8:0] + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1 Fld(1, 16) //[16:16] + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1 Fld(1, 17) //[17:17] + #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_PD_EN_B1 Fld(1, 18) //[18:18] + #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_MON_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_PHY_RGS_STBEN_CMD (DDRPHY_NAO_BASE_ADDRESS + 0x01A0) + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA0_STBEN Fld(9, 0) //[8:0] + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD Fld(1, 16) //[16:16] + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG Fld(1, 17) //[17:17] + #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_PD_EN_CA Fld(1, 18) //[18:18] + #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_MON_CA Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S0 (DDRPHY_NAO_BASE_ADDRESS + 0x01A4) + #define MISC_PHY_PICG_MON_S0_PICG_MON_S0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S1 (DDRPHY_NAO_BASE_ADDRESS + 0x01A8) + #define MISC_PHY_PICG_MON_S1_PICG_MON_S1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S2 (DDRPHY_NAO_BASE_ADDRESS + 0x01AC) + #define MISC_PHY_PICG_MON_S2_PICG_MON_S2 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S3 (DDRPHY_NAO_BASE_ADDRESS + 0x01B0) + #define MISC_PHY_PICG_MON_S3_PICG_MON_S3 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S4 (DDRPHY_NAO_BASE_ADDRESS + 0x01B4) + #define MISC_PHY_PICG_MON_S4_PICG_MON_S4 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S5 (DDRPHY_NAO_BASE_ADDRESS + 0x01B8) + #define MISC_PHY_PICG_MON_S5_PICG_MON_S5 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S6 (DDRPHY_NAO_BASE_ADDRESS + 0x01BC) + #define MISC_PHY_PICG_MON_S6_PICG_MON_S6 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S7 (DDRPHY_NAO_BASE_ADDRESS + 0x01C0) + #define MISC_PHY_PICG_MON_S7_PICG_MON_S7 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S8 (DDRPHY_NAO_BASE_ADDRESS + 0x01C4) + #define MISC_PHY_PICG_MON_S8_PICG_MON_S8 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_MBIST_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x01C8) + #define MISC_MBIST_STATUS_MISC_MBIST_PRE_RP_FAIL Fld(1, 0) //[0:0] + #define MISC_MBIST_STATUS_MISC_MBIST_PRE_RP_OK Fld(1, 1) //[1:1] + #define MISC_MBIST_STATUS_MISC_MBIST_PRE_FUSE Fld(7, 2) //[8:2] + +#define DDRPHY_REG_MISC_MBIST_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x01CC) + #define MISC_MBIST_STATUS2_MISC_MBIST_FAIL Fld(1, 0) //[0:0] + #define MISC_MBIST_STATUS2_MISC_MBIST_DONE Fld(1, 1) //[1:1] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x01D0) + #define MISC_IMPCAL_STATUS1_DRVNDQS_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS1_DRVPDQS_SAVE_1 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS1_ODTNDQS_SAVE_1 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x01D4) + #define MISC_IMPCAL_STATUS2_DRVNDQS_SAVE_2 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS2_DRVPDQS_SAVE_2 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS2_ODTNDQS_SAVE_2 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x01D8) + #define MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x01DC) + #define MISC_IMPCAL_STATUS4_DRVNDQ_SAVE_2 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS4_DRVPDQ_SAVE_2 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS4_ODTNDQ_SAVE_2 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x01E0) + #define MISC_IMPCAL_STATUS5_DRVNWCK_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS5_DRVPWCK_SAVE_1 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS5_DRVNWCK_SAVE_2 Fld(5, 16) //[20:16] + #define MISC_IMPCAL_STATUS5_DRVPWCK_SAVE_2 Fld(5, 24) //[28:24] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS6 (DDRPHY_NAO_BASE_ADDRESS + 0x01E4) + #define MISC_IMPCAL_STATUS6_DRVNCS_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS6_DRVPCS_SAVE_1 Fld(5, 8) //[12:8] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS7 (DDRPHY_NAO_BASE_ADDRESS + 0x01E8) + #define MISC_IMPCAL_STATUS7_DRVNCMD_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS7_DRVPCMD_SAVE_1 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS7_ODTNCMD_SAVE_1 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS8 (DDRPHY_NAO_BASE_ADDRESS + 0x01EC) + #define MISC_IMPCAL_STATUS8_DRVNCMD_SAVE_2 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS8_DRVPCMD_SAVE_2 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS8_ODTNCMD_SAVE_2 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS9 (DDRPHY_NAO_BASE_ADDRESS + 0x01F4) + #define MISC_IMPCAL_STATUS9_IMPCAL_N_ERROR Fld(1, 0) //[0:0] + #define MISC_IMPCAL_STATUS9_IMPCAL_P_ERROR Fld(1, 1) //[1:1] + #define MISC_IMPCAL_STATUS9_DRVNDQC_SAVE_1 Fld(5, 10) //[14:10] + #define MISC_IMPCAL_STATUS9_DRVPDQC_SAVE_1 Fld(5, 15) //[19:15] + #define MISC_IMPCAL_STATUS9_DRVNDQC_SAVE_2 Fld(5, 20) //[24:20] + #define MISC_IMPCAL_STATUS9_DRVPDQC_SAVE_2 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_MISC_STA_TOGLB0 (DDRPHY_NAO_BASE_ADDRESS + 0x01F8) + #define MISC_STA_TOGLB0_STA_TOGLB_DONE Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_TOGLB1 (DDRPHY_NAO_BASE_ADDRESS + 0x01FC) + #define MISC_STA_TOGLB1_STA_TOGLB_FAIL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB_DBG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0214) + #define MISC_STA_EXTLB_DBG0_STA_EXTLB_DVS_LEAD_0TO1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB_DBG1 (DDRPHY_NAO_BASE_ADDRESS + 0x0218) + #define MISC_STA_EXTLB_DBG1_STA_EXTLB_DVS_LEAD_1TO0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB_DBG2 (DDRPHY_NAO_BASE_ADDRESS + 0x021C) + #define MISC_STA_EXTLB_DBG2_STA_EXTLB_DVS_LAG_0TO1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB_DBG3 (DDRPHY_NAO_BASE_ADDRESS + 0x0220) + #define MISC_STA_EXTLB_DBG3_STA_EXTLB_DVS_LAG_1TO0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_TOGGLE_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0224) + #define MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0228) + #define MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT0 (DDRPHY_NAO_BASE_ADDRESS + 0x022C) + #define MISC_DUTY_DQ_ERR_CNT0_DQ_ERR_CNT0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0230) + #define MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT1 (DDRPHY_NAO_BASE_ADDRESS + 0x0234) + #define MISC_DUTY_DQ_ERR_CNT1_DQ_ERR_CNT1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0238) + #define MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT2 (DDRPHY_NAO_BASE_ADDRESS + 0x023C) + #define MISC_DUTY_DQ_ERR_CNT2_DQ_ERR_CNT2 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0240) + #define MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT3 (DDRPHY_NAO_BASE_ADDRESS + 0x0244) + #define MISC_DUTY_DQ_ERR_CNT3_DQ_ERR_CNT3 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_JMETER_ST0 (DDRPHY_NAO_BASE_ADDRESS + 0x0248) + #define MISC_JMETER_ST0_JMTR_DONE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_JMETER_ST1 (DDRPHY_NAO_BASE_ADDRESS + 0x024C) + #define MISC_JMETER_ST1_ZEROS_CNT Fld(16, 0) //[15:0] + #define MISC_JMETER_ST1_ONES_CNT Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0250) + #define MISC_EMI_LPBK0_RDATA_DQ0_B0 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK0_RDATA_DQ1_B0 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0254) + #define MISC_EMI_LPBK1_RDATA_DQ2_B0 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK1_RDATA_DQ3_B0 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK2 (DDRPHY_NAO_BASE_ADDRESS + 0x0258) + #define MISC_EMI_LPBK2_RDATA_DQ4_B0 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK2_RDATA_DQ5_B0 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK3 (DDRPHY_NAO_BASE_ADDRESS + 0x025C) + #define MISC_EMI_LPBK3_RDATA_DQ6_B0 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK3_RDATA_DQ7_B0 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK4 (DDRPHY_NAO_BASE_ADDRESS + 0x0260) + #define MISC_EMI_LPBK4_RDATA_DQ0_B1 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK4_RDATA_DQ1_B1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK5 (DDRPHY_NAO_BASE_ADDRESS + 0x0264) + #define MISC_EMI_LPBK5_RDATA_DQ2_B1 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK5_RDATA_DQ3_B1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK6 (DDRPHY_NAO_BASE_ADDRESS + 0x0268) + #define MISC_EMI_LPBK6_RDATA_DQ4_B1 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK6_RDATA_DQ5_B1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK7 (DDRPHY_NAO_BASE_ADDRESS + 0x026C) + #define MISC_EMI_LPBK7_RDATA_DQ6_B1 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK7_RDATA_DQ7_B1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_FT_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0270) + #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1 Fld(8, 0) //[7:0] + #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B1 Fld(8, 8) //[15:8] + #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B0 Fld(8, 16) //[23:16] + #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_FT_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0274) + #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B1 Fld(8, 0) //[7:0] + #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B1 Fld(8, 8) //[15:8] + #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B0 Fld(8, 16) //[23:16] + #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_FT_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0278) + #define MISC_FT_STATUS2_AD_RRESETB_O Fld(1, 0) //[0:0] + +#define DDRPHY_REG_MISC_FT_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x027C) + #define MISC_FT_STATUS3_AD_RX_ARCA0_DVS_R_LAG Fld(1, 0) //[0:0] + #define MISC_FT_STATUS3_AD_RX_ARCA1_DVS_R_LAG Fld(1, 1) //[1:1] + #define MISC_FT_STATUS3_AD_RX_ARCA2_DVS_R_LAG Fld(1, 2) //[2:2] + #define MISC_FT_STATUS3_AD_RX_ARCA3_DVS_R_LAG Fld(1, 3) //[3:3] + #define MISC_FT_STATUS3_AD_RX_ARCA4_DVS_R_LAG Fld(1, 4) //[4:4] + #define MISC_FT_STATUS3_AD_RX_ARCA5_DVS_R_LAG Fld(1, 5) //[5:5] + #define MISC_FT_STATUS3_AD_RX_ARCKE0_DVS_R_LAG Fld(1, 6) //[6:6] + #define MISC_FT_STATUS3_AD_RX_ARCKE1_DVS_R_LAG Fld(1, 7) //[7:7] + #define MISC_FT_STATUS3_AD_RX_ARCS0_DVS_R_LAG Fld(1, 8) //[8:8] + #define MISC_FT_STATUS3_AD_RX_ARCS1_DVS_R_LAG Fld(1, 9) //[9:9] + #define MISC_FT_STATUS3_AD_RX_ARCA0_DVS_R_LEAD Fld(1, 16) //[16:16] + #define MISC_FT_STATUS3_AD_RX_ARCA1_DVS_R_LEAD Fld(1, 17) //[17:17] + #define MISC_FT_STATUS3_AD_RX_ARCA2_DVS_R_LEAD Fld(1, 18) //[18:18] + #define MISC_FT_STATUS3_AD_RX_ARCA3_DVS_R_LEAD Fld(1, 19) //[19:19] + #define MISC_FT_STATUS3_AD_RX_ARCA4_DVS_R_LEAD Fld(1, 20) //[20:20] + #define MISC_FT_STATUS3_AD_RX_ARCA5_DVS_R_LEAD Fld(1, 21) //[21:21] + #define MISC_FT_STATUS3_AD_RX_ARCKE0_DVS_R_LEAD Fld(1, 22) //[22:22] + #define MISC_FT_STATUS3_AD_RX_ARCKE1_DVS_R_LEAD Fld(1, 23) //[23:23] + #define MISC_FT_STATUS3_AD_RX_ARCS0_DVS_R_LEAD Fld(1, 24) //[24:24] + #define MISC_FT_STATUS3_AD_RX_ARCS1_DVS_R_LEAD Fld(1, 25) //[25:25] + +#define DDRPHY_REG_MISC_FT_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0280) + #define MISC_FT_STATUS4_AD_RX_ARCA0_DVS_F_LAG Fld(1, 0) //[0:0] + #define MISC_FT_STATUS4_AD_RX_ARCA1_DVS_F_LAG Fld(1, 1) //[1:1] + #define MISC_FT_STATUS4_AD_RX_ARCA2_DVS_F_LAG Fld(1, 2) //[2:2] + #define MISC_FT_STATUS4_AD_RX_ARCA3_DVS_F_LAG Fld(1, 3) //[3:3] + #define MISC_FT_STATUS4_AD_RX_ARCA4_DVS_F_LAG Fld(1, 4) //[4:4] + #define MISC_FT_STATUS4_AD_RX_ARCA5_DVS_F_LAG Fld(1, 5) //[5:5] + #define MISC_FT_STATUS4_AD_RX_ARCKE0_DVS_F_LAG Fld(1, 6) //[6:6] + #define MISC_FT_STATUS4_AD_RX_ARCKE1_DVS_F_LAG Fld(1, 7) //[7:7] + #define MISC_FT_STATUS4_AD_RX_ARCS0_DVS_F_LAG Fld(1, 8) //[8:8] + #define MISC_FT_STATUS4_AD_RX_ARCS1_DVS_F_LAG Fld(1, 9) //[9:9] + #define MISC_FT_STATUS4_AD_RX_ARCA0_DVS_F_LEAD Fld(1, 16) //[16:16] + #define MISC_FT_STATUS4_AD_RX_ARCA1_DVS_F_LEAD Fld(1, 17) //[17:17] + #define MISC_FT_STATUS4_AD_RX_ARCA2_DVS_F_LEAD Fld(1, 18) //[18:18] + #define MISC_FT_STATUS4_AD_RX_ARCA3_DVS_F_LEAD Fld(1, 19) //[19:19] + #define MISC_FT_STATUS4_AD_RX_ARCA4_DVS_F_LEAD Fld(1, 20) //[20:20] + #define MISC_FT_STATUS4_AD_RX_ARCA5_DVS_F_LEAD Fld(1, 21) //[21:21] + #define MISC_FT_STATUS4_AD_RX_ARCKE0_DVS_F_LEAD Fld(1, 22) //[22:22] + #define MISC_FT_STATUS4_AD_RX_ARCKE1_DVS_F_LEAD Fld(1, 23) //[23:23] + #define MISC_FT_STATUS4_AD_RX_ARCS0_DVS_F_LEAD Fld(1, 24) //[24:24] + #define MISC_FT_STATUS4_AD_RX_ARCS1_DVS_F_LEAD Fld(1, 25) //[25:25] + +#define DDRPHY_REG_MISC_STA_TOGLB2 (DDRPHY_NAO_BASE_ADDRESS + 0x0284) + #define MISC_STA_TOGLB2_STA_TOGLB_PUHI_TIMEOUT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_TOGLB3 (DDRPHY_NAO_BASE_ADDRESS + 0x0288) + #define MISC_STA_TOGLB3_STA_TOGLB_PULO_TIMEOUT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB3 (DDRPHY_NAO_BASE_ADDRESS + 0x028C) + #define MISC_STA_EXTLB3_STA_EXTLB_RISING_FAIL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB4 (DDRPHY_NAO_BASE_ADDRESS + 0x0290) + #define MISC_STA_EXTLB4_STA_EXTLB_FALLING_FAIL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB5 (DDRPHY_NAO_BASE_ADDRESS + 0x0294) + #define MISC_STA_EXTLB5_STA_EXTLB_DBG_INFO2 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DEBUG_APHY_RX_CTL (DDRPHY_NAO_BASE_ADDRESS + 0x0400) + #define DEBUG_APHY_RX_CTL_DEBUG_STATUS_APHY_RX_CTL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_GATING_ERR_INFOR (DDRPHY_NAO_BASE_ADDRESS + 0x0410) + #define GATING_ERR_INFOR_STB_GATING_ERR Fld(1, 0) //[0:0] + #define GATING_ERR_INFOR_STBUPD_STOP Fld(1, 1) //[1:1] + #define GATING_ERR_INFOR_R_OTHER_SHU_GP_GATING_ERR Fld(2, 4) //[5:4] + #define GATING_ERR_INFOR_R_MPDIV_SHU_GP_GATING_ERR Fld(3, 8) //[10:8] + #define GATING_ERR_INFOR_GATING_ERR_INF_STATUS Fld(4, 16) //[19:16] + #define GATING_ERR_INFOR_GATING_ERR_PRE_SHU_ST Fld(4, 20) //[23:20] + #define GATING_ERR_INFOR_GATING_ERR_CUR_SHU_ST Fld(4, 24) //[27:24] + +#define DDRPHY_REG_DEBUG_DQSIEN_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0414) + #define DEBUG_DQSIEN_B0_DQSIEN_PICG_HEAD_ERR_FLAG_B0_RK0 Fld(1, 0) //[0:0] + #define DEBUG_DQSIEN_B0_STB_CNT_SHU_ST_ERR_FLAG_B0_RK0 Fld(1, 1) //[1:1] + #define DEBUG_DQSIEN_B0_DQSIEN_PICG_HEAD_ERR_FLAG_B0_RK1 Fld(1, 16) //[16:16] + #define DEBUG_DQSIEN_B0_STB_CNT_SHU_ST_ERR_FLAG_B0_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DEBUG_DQSIEN_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x0418) + #define DEBUG_DQSIEN_B1_DQSIEN_PICG_HEAD_ERR_FLAG_B1_RK0 Fld(1, 0) //[0:0] + #define DEBUG_DQSIEN_B1_STB_CNT_SHU_ST_ERR_FLAG_B1_RK0 Fld(1, 1) //[1:1] + #define DEBUG_DQSIEN_B1_DQSIEN_PICG_HEAD_ERR_FLAG_B1_RK1 Fld(1, 16) //[16:16] + #define DEBUG_DQSIEN_B1_STB_CNT_SHU_ST_ERR_FLAG_B1_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DEBUG_DQSIEN_CA (DDRPHY_NAO_BASE_ADDRESS + 0x041C) + #define DEBUG_DQSIEN_CA_DQSIEN_PICG_HEAD_ERR_FLAG_CA_RK0 Fld(1, 0) //[0:0] + #define DEBUG_DQSIEN_CA_STB_CNT_SHU_ST_ERR_FLAG_CA_RK0 Fld(1, 1) //[1:1] + #define DEBUG_DQSIEN_CA_DQSIEN_PICG_HEAD_ERR_FLAG_CA_RK1 Fld(1, 16) //[16:16] + #define DEBUG_DQSIEN_CA_STB_CNT_SHU_ST_ERR_FLAG_CA_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0420) + #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0424) + #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_PI_DLY_RK0 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_CA_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0428) + #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_PI_DLY_RK0 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0430) + #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_PI_DLY_RK1 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0434) + #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_PI_DLY_RK1 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_CA_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0438) + #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_PI_DLY_RK1 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_DEBUG_RODT_CTL (DDRPHY_NAO_BASE_ADDRESS + 0x0440) + #define DEBUG_RODT_CTL_DEBUG_STATUS_RODTCTL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_CAL_DQSG_CNT_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0500) + #define CAL_DQSG_CNT_B0_DQS_B0_F_GATING_COUNTER Fld(8, 0) //[7:0] + #define CAL_DQSG_CNT_B0_DQS_B0_R_GATING_COUNTER Fld(8, 8) //[15:8] + +#define DDRPHY_REG_CAL_DQSG_CNT_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x0504) + #define CAL_DQSG_CNT_B1_DQS_B1_F_GATING_COUNTER Fld(8, 0) //[7:0] + #define CAL_DQSG_CNT_B1_DQS_B1_R_GATING_COUNTER Fld(8, 8) //[15:8] + +#define DDRPHY_REG_CAL_DQSG_CNT_CA (DDRPHY_NAO_BASE_ADDRESS + 0x0508) + #define CAL_DQSG_CNT_CA_DQS_CA_F_GATING_COUNTER Fld(8, 0) //[7:0] + #define CAL_DQSG_CNT_CA_DQS_CA_R_GATING_COUNTER Fld(8, 8) //[15:8] + +#define DDRPHY_REG_DVFS_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x050C) + #define DVFS_STATUS_CUT_PHY_ST_SHU Fld(8, 0) //[7:0] + #define DVFS_STATUS_PLL_SEL Fld(1, 8) //[8:8] + #define DVFS_STATUS_MPDIV_SHU_GP Fld(3, 12) //[14:12] + #define DVFS_STATUS_OTHER_SHU_GP Fld(2, 16) //[17:16] + #define DVFS_STATUS_PICG_SHUFFLE Fld(1, 20) //[20:20] + #define DVFS_STATUS_SHUFFLE_PHY_STATE_START Fld(1, 21) //[21:21] + #define DVFS_STATUS_SHUFFLE_PHY_STATE_DONE Fld(1, 22) //[22:22] + #define DVFS_STATUS_SHUFFLE_PERIOD Fld(1, 23) //[23:23] + +#define DDRPHY_REG_RX_AUTOK_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0510) + #define RX_AUTOK_STATUS0_RO_RX_CAL_FAIL Fld(1, 0) //[0:0] + #define RX_AUTOK_STATUS0_RO_RX_CAL_PASS Fld(1, 1) //[1:1] + #define RX_AUTOK_STATUS0_RO_RX_CAL_DONE Fld(1, 2) //[2:2] + #define RX_AUTOK_STATUS0_RO_RX_CAL_OUT_WIN1_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS0_RO_RX_CAL_OUT_WIN1_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0514) + #define RX_AUTOK_STATUS1_RO_RX_CAL_OUT_WIN2_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS1_RO_RX_CAL_OUT_WIN2_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0518) + #define RX_AUTOK_STATUS2_RO_RX_CAL_OUT_WIN3_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS2_RO_RX_CAL_OUT_WIN3_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x051C) + #define RX_AUTOK_STATUS3_RO_RX_CAL_OUT_WIN4_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS3_RO_RX_CAL_OUT_WIN4_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0520) + #define RX_AUTOK_STATUS4_RO_RX_CAL_OUT_WIN5_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS4_RO_RX_CAL_OUT_WIN5_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x0524) + #define RX_AUTOK_STATUS5_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ0 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS5_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ0 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS6 (DDRPHY_NAO_BASE_ADDRESS + 0x0528) + #define RX_AUTOK_STATUS6_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ1 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS6_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ1 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS7 (DDRPHY_NAO_BASE_ADDRESS + 0x052C) + #define RX_AUTOK_STATUS7_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ2 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS7_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ2 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS8 (DDRPHY_NAO_BASE_ADDRESS + 0x0530) + #define RX_AUTOK_STATUS8_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ3 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS8_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ3 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS9 (DDRPHY_NAO_BASE_ADDRESS + 0x0534) + #define RX_AUTOK_STATUS9_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ4 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS9_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ4 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS10 (DDRPHY_NAO_BASE_ADDRESS + 0x0538) + #define RX_AUTOK_STATUS10_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ5 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS10_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ5 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS11 (DDRPHY_NAO_BASE_ADDRESS + 0x053C) + #define RX_AUTOK_STATUS11_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ6 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS11_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ6 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS12 (DDRPHY_NAO_BASE_ADDRESS + 0x0540) + #define RX_AUTOK_STATUS12_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ7 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS12_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ7 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS13 (DDRPHY_NAO_BASE_ADDRESS + 0x0544) + #define RX_AUTOK_STATUS13_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ8 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS13_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ8 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS14 (DDRPHY_NAO_BASE_ADDRESS + 0x0548) + #define RX_AUTOK_STATUS14_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ9 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS14_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ9 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS15 (DDRPHY_NAO_BASE_ADDRESS + 0x054C) + #define RX_AUTOK_STATUS15_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ10 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS15_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ10 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS16 (DDRPHY_NAO_BASE_ADDRESS + 0x0550) + #define RX_AUTOK_STATUS16_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ11 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS16_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ11 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS17 (DDRPHY_NAO_BASE_ADDRESS + 0x0554) + #define RX_AUTOK_STATUS17_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ12 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS17_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ12 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS18 (DDRPHY_NAO_BASE_ADDRESS + 0x0558) + #define RX_AUTOK_STATUS18_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ13 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS18_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ13 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS19 (DDRPHY_NAO_BASE_ADDRESS + 0x055C) + #define RX_AUTOK_STATUS19_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ14 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS19_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ14 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS20 (DDRPHY_NAO_BASE_ADDRESS + 0x0560) + #define RX_AUTOK_STATUS20_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ15 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS20_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ15 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0600) + #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_DONE_B0_RK0 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_ERR_B0_RK0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0604) + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK0 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK0 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK0 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0608) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x060C) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0610) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0614) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0618) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x061C) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0620) + #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B0_RK1_STATUS0_AUTOK_DONE_B0_RK1 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_B0_RK1_STATUS0_AUTOK_ERR_B0_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0624) + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK1 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK1 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK1 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0628) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x062C) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0630) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0634) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0638) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x063C) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0640) + #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B1_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B1_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B1_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B1_RK0_STATUS0_AUTOK_DONE_B1_RK0 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_B1_RK0_STATUS0_AUTOK_ERR_B1_RK0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0644) + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B1_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B1_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B1_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B1_RK0 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B1_RK0 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B1_RK0 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0648) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x064C) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0650) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0654) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0658) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x065C) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0660) + #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C__PI_B1_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C__UI_B1_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_B1_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B1_RK1_STATUS0_AUTOK_DONE_B1_RK1 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_B1_RK1_STATUS0_AUTOK_ERR_B1_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0664) + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R__PI_B1_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R__UI_B1_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_B1_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L__PI_B1_RK1 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L__UI_B1_RK1 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_B1_RK1 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0668) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x066C) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0670) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0674) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0678) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x067C) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0680) + #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C__PI_CA_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C__UI_CA_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_CA_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_CA_RK0_STATUS0_AUTOK_DONE_CA_RK0 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_CA_RK0_STATUS0_AUTOK_ERR_CA_RK0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0684) + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R__PI_CA_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R__UI_CA_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_CA_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L__PI_CA_RK0 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L__UI_CA_RK0 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_CA_RK0 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0688) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x068C) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0690) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0694) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0698) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x069C) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0700) + #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C__PI_CA_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C__UI_CA_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_CA_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_CA_RK1_STATUS0_AUTOK_DONE_CA_RK1 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_CA_RK1_STATUS0_AUTOK_ERR_CA_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0704) + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R__PI_CA_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R__UI_CA_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_CA_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L__PI_CA_RK1 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L__UI_CA_RK1 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_CA_RK1 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0708) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x070C) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0710) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0714) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0718) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x071C) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CTRL_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x0720) + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DONE_RK0 Fld(1, 0) //[0:0] + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DONE_RK1 Fld(1, 1) //[1:1] + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DLE_TIMEOUT_ERROR Fld(1, 2) //[2:2] + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_FSM_ST Fld(3, 4) //[6:4] + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_FSM_CUR_EDGE Fld(1, 8) //[8:8] + +#define DDRPHY_REG_AD_DLINE_MON (DDRPHY_NAO_BASE_ADDRESS + 0x0724) + #define AD_DLINE_MON_AD_RPLLGP_DLINE_MON Fld(24, 0) //[23:0] + +#define DDRPHY_REG_DLINE_MON_TRACK_DBG (DDRPHY_NAO_BASE_ADDRESS + 0x0728) + #define DLINE_MON_TRACK_DBG_DLINE_MON_TRACK_DBG Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTYCAL_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x072C) + #define MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B0 Fld(1, 0) //[0:0] + #define MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1 Fld(1, 1) //[1:1] + #define MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0 Fld(1, 2) //[2:2] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE0 (DDRPHY_NAO_BASE_ADDRESS + 0x0730) + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_WCK0_DRVP_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_WCK0_DRVP_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE1 (DDRPHY_NAO_BASE_ADDRESS + 0x0734) + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_WCK0_DRVN_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_WCK0_DRVN_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE2 (DDRPHY_NAO_BASE_ADDRESS + 0x0738) + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_WCK1_DRVP_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_WCK1_DRVP_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE3 (DDRPHY_NAO_BASE_ADDRESS + 0x073C) + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_WCK1_DRVN_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_WCK1_DRVN_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE4 (DDRPHY_NAO_BASE_ADDRESS + 0x0740) + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CS_DRVP_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CS_DRVP_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE5 (DDRPHY_NAO_BASE_ADDRESS + 0x0744) + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CS_DRVN_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CS_DRVN_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE6 (DDRPHY_NAO_BASE_ADDRESS + 0x0748) + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_WCK0_DRVP_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_WCK0_DRVP_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE7 (DDRPHY_NAO_BASE_ADDRESS + 0x074C) + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_WCK0_DRVN_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_WCK0_DRVN_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE8 (DDRPHY_NAO_BASE_ADDRESS + 0x0750) + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_WCK1_DRVP_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_WCK1_DRVP_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE9 (DDRPHY_NAO_BASE_ADDRESS + 0x0754) + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_WCK1_DRVN_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_WCK1_DRVN_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE10 (DDRPHY_NAO_BASE_ADDRESS + 0x0758) + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CS_DRVP_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CS_DRVP_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE11 (DDRPHY_NAO_BASE_ADDRESS + 0x075C) + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CS_DRVN_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CS_DRVN_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DMA_SRAM_MBIST (DDRPHY_NAO_BASE_ADDRESS + 0x0800) + #define MISC_DMA_SRAM_MBIST_DRAMC_MBIST_MBIST_PRE_FUSE Fld(8, 0) //[7:0] + +#define DDRPHY_REG_MISC_APHY_OBS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0820) + #define MISC_APHY_OBS0_AD_RX_ARDQ1_RCNT_B0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS0_AD_RX_ARDQ2_RCNT_B0 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS0_AD_RX_ARDQ3_RCNT_B0 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0824) + #define MISC_APHY_OBS1_AD_RX_ARDQ5_RCNT_B0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS1_AD_RX_ARDQ6_RCNT_B0 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS1_AD_RX_ARDQ7_RCNT_B0 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0828) + #define MISC_APHY_OBS2_AD_RX_ARDQ1_RCNT_B1 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS2_AD_RX_ARDQ2_RCNT_B1 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS2_AD_RX_ARDQ3_RCNT_B1 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS3 (DDRPHY_NAO_BASE_ADDRESS + 0x082C) + #define MISC_APHY_OBS3_AD_RX_ARDQ5_RCNT_B1 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS3_AD_RX_ARDQ6_RCNT_B1 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS3_AD_RX_ARDQ7_RCNT_B1 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0830) + #define MISC_APHY_OBS4_AD_RX_ARDQM_RCNT_B0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS4_AD_RX_ARDQM_RCNT_B1 Fld(9, 9) //[17:9] + +#define DDRPHY_REG_MISC_APHY_OBS5 (DDRPHY_NAO_BASE_ADDRESS + 0x0834) + #define MISC_APHY_OBS5_AD_RX_ARCA1_RCNT_C0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS5_AD_RX_ARCA2_RCNT_C0 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS5_AD_RX_ARCA3_RCNT_C0 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS6 (DDRPHY_NAO_BASE_ADDRESS + 0x0838) + #define MISC_APHY_OBS6_AD_RX_ARCA5_RCNT_C0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS6_AD_RX_ARCS0_RCNT_C0 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS6_AD_RX_ARCS1_RCNT_C0 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS7 (DDRPHY_NAO_BASE_ADDRESS + 0x083C) + #define MISC_APHY_OBS7_AD_RX_ARCKE0_RCNT_C0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS7_AD_RX_ARCKE1_RCNT_C0 Fld(9, 9) //[17:9] + +#define DDRPHY_REG_MISC_APHY_OBS8 (DDRPHY_NAO_BASE_ADDRESS + 0x0840) + #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_B0 Fld(2, 0) //[1:0] + #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_B1 Fld(2, 2) //[3:2] + #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_C0 Fld(2, 4) //[5:4] + #define MISC_APHY_OBS8_RGS_RPHYPLL_DET_RSTB Fld(1, 6) //[6:6] + #define MISC_APHY_OBS8_RGS_RCLRPLL_DET_RSTB Fld(1, 7) //[7:7] + +#endif // __DDRPHY_NAO_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h new file mode 100644 index 0000000000..7fc3b2f0a8 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h @@ -0,0 +1,1624 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_AO_REGS_H__ +#define __DRAMC_AO_REGS_H__ + +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000 +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x10240000 + +#define DRAMC_AO_BASE_ADDRESS Channel_A_DRAMC_AO_BASE_VIRTUAL + +#define DRAMC_REG_DDRCOMMON0 (DRAMC_AO_BASE_ADDRESS + 0x0000) + #define DDRCOMMON0_DISSTOP26M Fld(1, 0) //[0:0] + #define DDRCOMMON0_RANK_ASYM Fld(1, 1) //[1:1] + #define DDRCOMMON0_DM16BITFULL Fld(1, 2) //[2:2] + #define DDRCOMMON0_TRCDEARLY Fld(1, 3) //[3:3] + #define DDRCOMMON0_BK8EN Fld(1, 8) //[8:8] + #define DDRCOMMON0_BG4EN Fld(1, 11) //[11:11] + #define DDRCOMMON0_GDDR3EN Fld(1, 16) //[16:16] + #define DDRCOMMON0_LPDDR2EN Fld(1, 17) //[17:17] + #define DDRCOMMON0_LPDDR3EN Fld(1, 18) //[18:18] + #define DDRCOMMON0_LPDDR4EN Fld(1, 19) //[19:19] + #define DDRCOMMON0_LPDDR5EN Fld(1, 20) //[20:20] + #define DDRCOMMON0_DDR2EN Fld(1, 22) //[22:22] + #define DDRCOMMON0_DDR3EN Fld(1, 23) //[23:23] + #define DDRCOMMON0_DDR4EN Fld(1, 24) //[24:24] + #define DDRCOMMON0_DRAMC_SW_RST Fld(1, 31) //[31:31] + +#define DRAMC_REG_SA_RESERVE (DRAMC_AO_BASE_ADDRESS + 0x000C) + #define SA_RESERVE_SINGLE_RANK Fld(1, 0) //[0:0] + #define SA_RESERVE_DFS_FSP_RTMRW Fld(2, 1) //[2:1] + #define SA_RESERVE_SUPPORT_4266 Fld(1, 3) //[3:3] + #define SA_RESERVE_SA_RESERVE Fld(20, 4) //[23:4] + #define SA_RESERVE_MODE_RK1 Fld(4, 24) //[27:24] + #define SA_RESERVE_MODE_RK0 Fld(4, 28) //[31:28] + +#define DRAMC_REG_NONSHU_RSV (DRAMC_AO_BASE_ADDRESS + 0x00FC) + #define NONSHU_RSV_NONSHU_RSV Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST2_A0 (DRAMC_AO_BASE_ADDRESS + 0x0100) + #define TEST2_A0_TEST2_PAT1 Fld(8, 0) //[7:0] + #define TEST2_A0_TEST2_PAT0 Fld(8, 8) //[15:8] + #define TEST2_A0_LOOP_NV_END Fld(1, 16) //[16:16] + #define TEST2_A0_ERR_BREAK_EN Fld(1, 17) //[17:17] + #define TEST2_A0_TA2_LOOP_EN Fld(1, 18) //[18:18] + #define TEST2_A0_TA2_CG_FR Fld(1, 19) //[19:19] + #define TEST2_A0_LOOP_CNT_INDEX Fld(4, 20) //[23:20] + #define TEST2_A0_WDT_BY_DRAMC_DIS Fld(1, 24) //[24:24] + +#define DRAMC_REG_TEST2_A2 (DRAMC_AO_BASE_ADDRESS + 0x0104) + #define TEST2_A2_TEST2_OFF Fld(28, 4) //[31:4] + +#define DRAMC_REG_TEST2_A3 (DRAMC_AO_BASE_ADDRESS + 0x0108) + #define TEST2_A3_TESTCNT Fld(4, 0) //[3:0] + #define TEST2_A3_TESTWRHIGH Fld(1, 4) //[4:4] + #define TEST2_A3_ADRDECEN_TARKMODE Fld(1, 5) //[5:5] + #define TEST2_A3_PSTWR2 Fld(1, 6) //[6:6] + #define TEST2_A3_TESTAUDPAT Fld(1, 7) //[7:7] + #define TEST2_A3_TESTCLKRUN Fld(1, 8) //[8:8] + #define TEST2_A3_ERRFLAG_BYTE_SEL Fld(2, 9) //[10:9] + #define TEST2_A3_PAT_SHIFT_SW_EN Fld(1, 11) //[11:11] + #define TEST2_A3_PAT_SHIFT_OFFSET Fld(3, 12) //[14:12] + #define TEST2_A3_TEST2_PAT_SHIFT Fld(1, 15) //[15:15] + #define TEST2_A3_TEST_AID_EN Fld(1, 16) //[16:16] + #define TEST2_A3_HFIDPAT Fld(1, 17) //[17:17] + #define TEST2_A3_AUTO_GEN_PAT Fld(1, 18) //[18:18] + #define TEST2_A3_LBSELFCMP Fld(1, 19) //[19:19] + #define TEST2_A3_DMPAT32 Fld(1, 24) //[24:24] + #define TEST2_A3_TESTADR_SHIFT Fld(1, 25) //[25:25] + #define TEST2_A3_TAHPRI_B Fld(1, 26) //[26:26] + #define TEST2_A3_TESTLP Fld(1, 27) //[27:27] + #define TEST2_A3_TEST2WREN2_HW_EN Fld(1, 28) //[28:28] + #define TEST2_A3_TEST1 Fld(1, 29) //[29:29] + #define TEST2_A3_TEST2R Fld(1, 30) //[30:30] + #define TEST2_A3_TEST2W Fld(1, 31) //[31:31] + +#define DRAMC_REG_TEST2_A4 (DRAMC_AO_BASE_ADDRESS + 0x010C) + #define TEST2_A4_TESTAUDINC Fld(5, 0) //[4:0] + #define TEST2_A4_TEST2DISSCRAM Fld(1, 5) //[5:5] + #define TEST2_A4_TESTSSOPAT Fld(1, 6) //[6:6] + #define TEST2_A4_TESTSSOXTALKPAT Fld(1, 7) //[7:7] + #define TEST2_A4_TESTAUDINIT Fld(5, 8) //[12:8] + #define TEST2_A4_TEST2_EN1ARB_DIS Fld(1, 13) //[13:13] + #define TEST2_A4_TESTAUDBITINV Fld(1, 14) //[14:14] + #define TEST2_A4_TESTAUDMODE Fld(1, 15) //[15:15] + #define TEST2_A4_TESTXTALKPAT Fld(1, 16) //[16:16] + #define TEST2_A4_TEST_REQ_LEN1 Fld(1, 17) //[17:17] + #define TEST2_A4_TEST2EN1_OPT2 Fld(1, 18) //[18:18] + #define TEST2_A4_TEST2EN1_OPT1_DIS Fld(1, 19) //[19:19] + #define TEST2_A4_TEST2_DQMTGL Fld(1, 21) //[21:21] + #define TEST2_A4_TESTAGENTRK Fld(2, 24) //[25:24] + #define TEST2_A4_TESTDMITGLPAT Fld(1, 26) //[26:26] + #define TEST2_A4_TEST1TO4LEN1_DIS Fld(1, 27) //[27:27] + #define TEST2_A4_TESTAGENTRKSEL Fld(3, 28) //[30:28] + #define TEST2_A4_TESTAGENT_DMYRD_OPT Fld(1, 31) //[31:31] + +#define DRAMC_REG_DUMMY_RD (DRAMC_AO_BASE_ADDRESS + 0x0110) + #define DUMMY_RD_SREF_DMYRD_MASK Fld(1, 0) //[0:0] + #define DUMMY_RD_DMYRDOFOEN Fld(1, 1) //[1:1] + #define DUMMY_RD_DUMMY_RD_SW Fld(1, 4) //[4:4] + #define DUMMY_RD_DMYWR_LPRI_EN Fld(1, 5) //[5:5] + #define DUMMY_RD_DMY_WR_DBG Fld(1, 6) //[6:6] + #define DUMMY_RD_DMY_RD_DBG Fld(1, 7) //[7:7] + #define DUMMY_RD_DRS_CNTX Fld(7, 8) //[14:8] + #define DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS Fld(1, 15) //[15:15] + #define DUMMY_RD_RANK_NUM Fld(2, 16) //[17:16] + #define DUMMY_RD_DUMMY_RD_EN Fld(1, 20) //[20:20] + #define DUMMY_RD_SREF_DMYRD_EN Fld(1, 21) //[21:21] + #define DUMMY_RD_DQSG_DMYRD_EN Fld(1, 22) //[22:22] + #define DUMMY_RD_DQSG_DMYWR_EN Fld(1, 23) //[23:23] + #define DUMMY_RD_DUMMY_RD_PA_OPT Fld(1, 24) //[24:24] + #define DUMMY_RD_DMY_RD_RX_TRACK Fld(1, 25) //[25:25] + #define DUMMY_RD_DMYRD_HPRI_DIS Fld(1, 26) //[26:26] + #define DUMMY_RD_DMYRD_REORDER_DIS Fld(1, 27) //[27:27] + #define DUMMY_RD_RETRY_SP_RK_DIS Fld(1, 28) //[28:28] + +#define DRAMC_REG_DUMMY_RD_INTV (DRAMC_AO_BASE_ADDRESS + 0x0114) + #define DUMMY_RD_INTV_DUMMY_RD_CNT0 Fld(1, 0) //[0:0] + #define DUMMY_RD_INTV_DUMMY_RD_CNT1 Fld(1, 1) //[1:1] + #define DUMMY_RD_INTV_DUMMY_RD_CNT2 Fld(1, 2) //[2:2] + #define DUMMY_RD_INTV_DUMMY_RD_CNT3 Fld(1, 3) //[3:3] + #define DUMMY_RD_INTV_DUMMY_RD_CNT4 Fld(1, 4) //[4:4] + #define DUMMY_RD_INTV_DUMMY_RD_CNT5 Fld(1, 5) //[5:5] + #define DUMMY_RD_INTV_DUMMY_RD_CNT6 Fld(1, 6) //[6:6] + #define DUMMY_RD_INTV_DUMMY_RD_CNT7 Fld(1, 7) //[7:7] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT0 Fld(1, 16) //[16:16] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT1 Fld(1, 17) //[17:17] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT2 Fld(1, 18) //[18:18] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT3 Fld(1, 19) //[19:19] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT4 Fld(1, 20) //[20:20] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT5 Fld(1, 21) //[21:21] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT6 Fld(1, 22) //[22:22] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT7 Fld(1, 23) //[23:23] + +#define DRAMC_REG_BUS_MON1 (DRAMC_AO_BASE_ADDRESS + 0x0118) + #define BUS_MON1_WRBYTE_CNT_OPT Fld(1, 0) //[0:0] + +#define DRAMC_REG_DRAMC_DBG_SEL1 (DRAMC_AO_BASE_ADDRESS + 0x011C) + #define DRAMC_DBG_SEL1_DEBUG_SEL_0 Fld(16, 0) //[15:0] + #define DRAMC_DBG_SEL1_DEBUG_SEL_1 Fld(16, 16) //[31:16] + +#define DRAMC_REG_DRAMC_DBG_SEL2 (DRAMC_AO_BASE_ADDRESS + 0x0120) + #define DRAMC_DBG_SEL2_DEBUG_SEL_2 Fld(16, 0) //[15:0] + #define DRAMC_DBG_SEL2_DEBUG_SEL_3 Fld(16, 16) //[31:16] + +#define DRAMC_REG_SWCMD_EN (DRAMC_AO_BASE_ADDRESS + 0x0124) + #define SWCMD_EN_MPRWEN Fld(1, 0) //[0:0] + #define SWCMD_EN_STESTEN Fld(1, 1) //[1:1] + #define SWCMD_EN_MPCMANEN Fld(1, 2) //[2:2] + #define SWCMD_EN_PREAEN Fld(1, 3) //[3:3] + #define SWCMD_EN_ACTEN Fld(1, 4) //[4:4] + #define SWCMD_EN_RDDQCEN Fld(1, 5) //[5:5] + #define SWCMD_EN_WRFIFOEN Fld(1, 6) //[6:6] + #define SWCMD_EN_RDFIFOEN Fld(1, 7) //[7:7] + #define SWCMD_EN_DQSOSCDISEN Fld(1, 8) //[8:8] + #define SWCMD_EN_DQSOSCENEN Fld(1, 9) //[9:9] + #define SWCMD_EN_ZQLATEN Fld(1, 10) //[10:10] + #define SWCMD_EN_MRWEN Fld(1, 11) //[11:11] + #define SWCMD_EN_MRREN Fld(1, 12) //[12:12] + #define SWCMD_EN_AREFEN Fld(1, 13) //[13:13] + #define SWCMD_EN_ZQCEN Fld(1, 14) //[14:14] + #define SWCMD_EN_SPREA_EN Fld(1, 15) //[15:15] + #define SWCMD_EN_ZQCEN_SWTRIG Fld(1, 16) //[16:16] + #define SWCMD_EN_ZQLATEN_SWTRIG Fld(1, 17) //[17:17] + #define SWCMD_EN_WCK2DQI_START_SWTRIG Fld(1, 18) //[18:18] + #define SWCMD_EN_WCK2DQO_START_SWTRIG Fld(1, 19) //[19:19] + #define SWCMD_EN_ZQ_SW Fld(1, 20) //[20:20] + #define SWCMD_EN_WCK2DQ_SW Fld(1, 21) //[21:21] + #define SWCMD_EN_SWCMDEN_RESERVED87 Fld(2, 22) //[23:22] + #define SWCMD_EN_RTMRWEN Fld(1, 24) //[24:24] + #define SWCMD_EN_RTSWCMDEN Fld(1, 25) //[25:25] + #define SWCMD_EN_RTSWCMD_SEL Fld(6, 26) //[31:26] + +#define DRAMC_REG_SWCMD_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0128) + #define SWCMD_CTRL0_MRSOP Fld(8, 0) //[7:0] + #define SWCMD_CTRL0_MRSMA Fld(13, 8) //[20:8] + #define SWCMD_CTRL0_MRSBA Fld(3, 21) //[23:21] + #define SWCMD_CTRL0_MRSRK Fld(2, 24) //[25:24] + #define SWCMD_CTRL0_MRRRK Fld(2, 26) //[27:26] + #define SWCMD_CTRL0_MRSBG Fld(2, 28) //[29:28] + #define SWCMD_CTRL0_SWTRIG_ZQ_RK Fld(1, 30) //[30:30] + +#define DRAMC_REG_SWCMD_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x012C) + #define SWCMD_CTRL1_RDDQC_LP_INTV Fld(2, 0) //[1:0] + #define SWCMD_CTRL1_RDDQC_LP_ENB Fld(1, 2) //[2:2] + #define SWCMD_CTRL1_ACTEN_BK Fld(3, 3) //[5:3] + #define SWCMD_CTRL1_ACTEN_ROW_R17_R16 Fld(2, 22) //[22:23] //Lewis add for ppr + #define SWCMD_CTRL1_ACTEN_ROW Fld(18, 6) //[23:6] + #define SWCMD_CTRL1_WRFIFO_MODE2 Fld(1, 31) //[31:31] + +#define DRAMC_REG_SWCMD_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0130) + #define SWCMD_CTRL2_RTSWCMD_AGE Fld(10, 0) //[9:0] + #define SWCMD_CTRL2_RTSWCMD_RK Fld(2, 10) //[11:10] + #define SWCMD_CTRL2_RTSWCMD_MA Fld(8, 12) //[19:12] + #define SWCMD_CTRL2_RTSWCMD_OP Fld(8, 20) //[27:20] + #define SWCMD_CTRL2_RTSWCMD_ALLTYPE_OPT Fld(1, 28) //[28:28] + +#define DRAMC_REG_RDDQCGOLDEN1 (DRAMC_AO_BASE_ADDRESS + 0x0134) + #define RDDQCGOLDEN1_LP5_MR20_6_GOLDEN Fld(1, 0) //[0:0] + #define RDDQCGOLDEN1_LP5_MR20_7_GOLDEN Fld(1, 1) //[1:1] + +#define DRAMC_REG_RDDQCGOLDEN (DRAMC_AO_BASE_ADDRESS + 0x0138) + #define RDDQCGOLDEN_MR20_GOLDEN Fld(8, 0) //[7:0] + #define RDDQCGOLDEN_MR15_GOLDEN Fld(8, 8) //[15:8] + #define RDDQCGOLDEN_MR40_GOLDEN Fld(8, 16) //[23:16] + #define RDDQCGOLDEN_MR32_GOLDEN Fld(8, 24) //[31:24] + +#define DRAMC_REG_RTMRW_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x013C) + #define RTMRW_CTRL0_RTMRW0_RK Fld(2, 0) //[1:0] + #define RTMRW_CTRL0_RTMRW1_RK Fld(2, 2) //[3:2] + #define RTMRW_CTRL0_RTMRW2_RK Fld(2, 4) //[5:4] + #define RTMRW_CTRL0_RTMRW3_RK Fld(2, 6) //[7:6] + #define RTMRW_CTRL0_RTMRW4_RK Fld(2, 8) //[9:8] + #define RTMRW_CTRL0_RTMRW5_RK Fld(2, 10) //[11:10] + #define RTMRW_CTRL0_RTMRW_LEN Fld(3, 12) //[14:12] + #define RTMRW_CTRL0_RTMRW_AGE Fld(10, 15) //[24:15] + #define RTMRW_CTRL0_RTMRW_LAT Fld(7, 25) //[31:25] + +#define DRAMC_REG_RTMRW_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0140) + #define RTMRW_CTRL1_RTMRW0_MA Fld(8, 0) //[7:0] + #define RTMRW_CTRL1_RTMRW1_MA Fld(8, 8) //[15:8] + #define RTMRW_CTRL1_RTMRW2_MA Fld(8, 16) //[23:16] + #define RTMRW_CTRL1_RTMRW3_MA Fld(8, 24) //[31:24] + +#define DRAMC_REG_RTMRW_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0144) + #define RTMRW_CTRL2_RTMRW0_OP Fld(8, 0) //[7:0] + #define RTMRW_CTRL2_RTMRW1_OP Fld(8, 8) //[15:8] + #define RTMRW_CTRL2_RTMRW2_OP Fld(8, 16) //[23:16] + #define RTMRW_CTRL2_RTMRW3_OP Fld(8, 24) //[31:24] + +#define DRAMC_REG_RTMRW_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0148) + #define RTMRW_CTRL3_RTMRW4_MA Fld(8, 0) //[7:0] + #define RTMRW_CTRL3_RTMRW5_MA Fld(8, 8) //[15:8] + #define RTMRW_CTRL3_RTMRW4_OP Fld(8, 16) //[23:16] + #define RTMRW_CTRL3_RTMRW5_OP Fld(8, 24) //[31:24] + +#define DRAMC_REG_CBT_WLEV_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x014C) + #define CBT_WLEV_CTRL0_CBT_CAPATEN Fld(1, 0) //[0:0] + #define CBT_WLEV_CTRL0_TCMDEN Fld(1, 1) //[1:1] + #define CBT_WLEV_CTRL0_BYTEMODECBTEN Fld(1, 2) //[2:2] + #define CBT_WLEV_CTRL0_WRITE_LEVEL_EN Fld(1, 3) //[3:3] + #define CBT_WLEV_CTRL0_DQSOEAOEN Fld(1, 4) //[4:4] + #define CBT_WLEV_CTRL0_CBTMASKDQSOE Fld(1, 5) //[5:5] + #define CBT_WLEV_CTRL0_WLEV_DQSPATEN Fld(1, 6) //[6:6] + #define CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG Fld(1, 7) //[7:7] + #define CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL Fld(4, 8) //[11:8] + #define CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT Fld(8, 12) //[19:12] + #define CBT_WLEV_CTRL0_WLEV_MCK_NUM Fld(2, 20) //[21:20] + #define CBT_WLEV_CTRL0_WLEV_WCK_HR Fld(1, 22) //[22:22] + #define CBT_WLEV_CTRL0_CBT_WLEV_WCKAO Fld(1, 23) //[23:23] + #define CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5 Fld(1, 24) //[24:24] + #define CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 Fld(1, 25) //[25:25] + #define CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN Fld(4, 26) //[29:26] + #define CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE Fld(1, 30) //[30:30] + +#define DRAMC_REG_CBT_WLEV_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0150) + #define CBT_WLEV_CTRL1_CATRAINCSEXT Fld(1, 0) //[0:0] + #define CBT_WLEV_CTRL1_CATRAINMRS Fld(1, 1) //[1:1] + #define CBT_WLEV_CTRL1_CATRAINEN Fld(1, 2) //[2:2] + #define CBT_WLEV_CTRL1_CATRAINLAT Fld(4, 11) //[14:11] + #define CBT_WLEV_CTRL1_CATRAIN_INTV Fld(8, 15) //[22:15] + #define CBT_WLEV_CTRL1_TCMDO1LAT Fld(8, 23) //[30:23] + +#define DRAMC_REG_CBT_WLEV_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0154) + #define CBT_WLEV_CTRL2_CATRAINCA Fld(16, 0) //[15:0] + #define CBT_WLEV_CTRL2_CATRAINCA_Y Fld(16, 16) //[31:16] + +#define DRAMC_REG_CBT_WLEV_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0158) + #define CBT_WLEV_CTRL3_CATRAIN_PAT_STOP0 Fld(4, 0) //[3:0] + #define CBT_WLEV_CTRL3_CATRAIN_PAT_STOP1 Fld(3, 4) //[6:4] + #define CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL0 Fld(4, 7) //[10:7] + #define CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL1 Fld(3, 11) //[13:11] + #define CBT_WLEV_CTRL3_DQSBX_G Fld(4, 14) //[17:14] + #define CBT_WLEV_CTRL3_DQSBY_G Fld(4, 18) //[21:18] + #define CBT_WLEV_CTRL3_DQSBX1_G Fld(4, 22) //[25:22] + #define CBT_WLEV_CTRL3_DQSBY1_G Fld(4, 26) //[29:26] + +#define DRAMC_REG_CBT_WLEV_CTRL4 (DRAMC_AO_BASE_ADDRESS + 0x015C) + #define CBT_WLEV_CTRL4_CBT_TXDQ_B0 Fld(8, 0) //[7:0] + #define CBT_WLEV_CTRL4_CBT_TXDQ_B1 Fld(8, 8) //[15:8] + +#define DRAMC_REG_CBT_WLEV_ATK_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0160) + #define CBT_WLEV_ATK_CTRL0_ARPICS_SW Fld(1, 0) //[0:0] + #define CBT_WLEV_ATK_CTRL0_ARPICA_SW Fld(1, 1) //[1:1] + #define CBT_WLEV_ATK_CTRL0_ARPIDQS_SW Fld(1, 2) //[2:2] + #define CBT_WLEV_ATK_CTRL0_CSTRAIN_ATKEN Fld(1, 3) //[3:3] + #define CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN Fld(1, 4) //[4:4] + #define CBT_WLEV_ATK_CTRL0_WLEV_ATKEN Fld(1, 5) //[5:5] + #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INTV Fld(5, 6) //[10:6] + #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_LENPI Fld(6, 11) //[16:11] + #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_RESPI Fld(2, 17) //[18:17] + #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INITPI Fld(6, 19) //[24:19] + #define CBT_WLEV_ATK_CTRL0_CBT_ATK_CABITDBG Fld(3, 25) //[27:25] + +#define DRAMC_REG_CBT_WLEV_ATK_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0164) + #define CBT_WLEV_ATK_CTRL1_UICS_SW Fld(2, 0) //[1:0] + #define CBT_WLEV_ATK_CTRL1_UICA_SW Fld(7, 2) //[8:2] + #define CBT_WLEV_ATK_CTRL1_UIDQS_SW Fld(4, 9) //[12:9] + #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B1_RK0_SW Fld(1, 13) //[13:13] + #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B0_RK0_SW Fld(1, 14) //[14:14] + #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B1_RK1_SW Fld(1, 15) //[15:15] + #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B0_RK1_SW Fld(1, 16) //[16:16] + #define CBT_WLEV_ATK_CTRL1_CBT_ATK_CA1UI64PI Fld(1, 17) //[17:17] + +#define DRAMC_REG_SREF_DPD_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0168) + #define SREF_DPD_CTRL_LPSM_BYPASS_B Fld(1, 7) //[7:7] + #define SREF_DPD_CTRL_DPDWOSC Fld(1, 8) //[8:8] + #define SREF_DPD_CTRL_CLR_EN Fld(1, 9) //[9:9] + #define SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN Fld(1, 10) //[10:10] + #define SREF_DPD_CTRL_SREF_PRD_OPT Fld(1, 11) //[11:11] + #define SREF_DPD_CTRL_SREF_CG_OPT Fld(1, 12) //[12:12] + #define SREF_DPD_CTRL_SRFPD_DIS Fld(1, 13) //[13:13] + #define SREF_DPD_CTRL_SREF3_OPTION Fld(1, 14) //[14:14] + #define SREF_DPD_CTRL_SREF2_OPTION Fld(1, 15) //[15:15] + #define SREF_DPD_CTRL_SREFDLY Fld(4, 16) //[19:16] + #define SREF_DPD_CTRL_DSM_HW_EN Fld(1, 20) //[20:20] + #define SREF_DPD_CTRL_DSM_TRIGGER Fld(1, 21) //[21:21] + #define SREF_DPD_CTRL_SREF_HW_EN Fld(1, 22) //[22:22] + #define SREF_DPD_CTRL_SELFREF Fld(1, 23) //[23:23] + #define SREF_DPD_CTRL_DPDWAKEDCMCKE Fld(1, 25) //[25:25] + #define SREF_DPD_CTRL_CMDCKAR Fld(1, 26) //[26:26] + #define SREF_DPD_CTRL_GTDMW_SYNC_MASK Fld(1, 28) //[28:28] + #define SREF_DPD_CTRL_GT_SYNC_MASK Fld(1, 29) //[29:29] + #define SREF_DPD_CTRL_DAT_SYNC_MASK Fld(1, 30) //[30:30] + #define SREF_DPD_CTRL_PHY_SYNC_MASK Fld(1, 31) //[31:31] + +#define DRAMC_REG_CFC_CTRL (DRAMC_AO_BASE_ADDRESS + 0x016C) + #define CFC_CTRL_CFC_CTRL_RESERVED Fld(1, 0) //[0:0] + +#define DRAMC_REG_DLLFRZ_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0170) + #define DLLFRZ_CTRL_INPUTRXTRACK_BLOCK Fld(1, 0) //[0:0] + #define DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT Fld(1, 1) //[1:1] + #define DLLFRZ_CTRL_DLLFRZ_BLOCKLONG Fld(1, 2) //[2:2] + #define DLLFRZ_CTRL_DLLFRZIDLE4XUPD Fld(1, 3) //[3:3] + #define DLLFRZ_CTRL_FASTDQSG2X Fld(1, 4) //[4:4] + #define DLLFRZ_CTRL_FASTDQSGUPD Fld(1, 5) //[5:5] + #define DLLFRZ_CTRL_MANUDLLFRZ Fld(1, 6) //[6:6] + #define DLLFRZ_CTRL_DLLFRZ Fld(1, 7) //[7:7] + #define DLLFRZ_CTRL_UPDBYWR Fld(1, 8) //[8:8] + +#define DRAMC_REG_MPC_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0174) + #define MPC_CTRL_MPC_BLOCKALE_OPT Fld(1, 0) //[0:0] + #define MPC_CTRL_MPC_BLOCKALE_OPT1 Fld(1, 1) //[1:1] + #define MPC_CTRL_MPC_BLOCKALE_OPT2 Fld(1, 2) //[2:2] + #define MPC_CTRL_ZQ_BLOCKALE_OPT Fld(1, 3) //[3:3] + #define MPC_CTRL_RW2ZQLAT_OPT Fld(1, 4) //[4:4] + #define MPC_CTRL_REFR_BLOCKEN Fld(1, 5) //[5:5] + #define MPC_CTRL_RTMRW_HPRI_EN Fld(1, 6) //[6:6] + #define MPC_CTRL_RTSWCMD_HPRI_EN Fld(1, 7) //[7:7] + +#define DRAMC_REG_HW_MRR_FUN (DRAMC_AO_BASE_ADDRESS + 0x0178) + #define HW_MRR_FUN_TMRR_ENA Fld(1, 0) //[0:0] + #define HW_MRR_FUN_TRCDMRR_EN Fld(1, 1) //[1:1] + #define HW_MRR_FUN_TRPMRR_EN Fld(1, 2) //[2:2] + #define HW_MRR_FUN_MANTMRR_EN Fld(1, 3) //[3:3] + #define HW_MRR_FUN_TR2MRR_ENA Fld(1, 4) //[4:4] + #define HW_MRR_FUN_R2MRRHPRICTL Fld(1, 5) //[5:5] + #define HW_MRR_FUN_BUFEN_RFC_OPT Fld(1, 8) //[8:8] + #define HW_MRR_FUN_MRR_REQNOPUSH_DIS Fld(1, 9) //[9:9] + #define HW_MRR_FUN_MRR_BLOCK_NOR_DIS Fld(1, 10) //[10:10] + #define HW_MRR_FUN_MRR_HW_HIPRI Fld(1, 11) //[11:11] + #define HW_MRR_FUN_MRR_SPCMD_WAKE_DIS Fld(1, 12) //[12:12] + #define HW_MRR_FUN_TMRR_OE_OPT_DIS Fld(1, 13) //[13:13] + #define HW_MRR_FUN_MRR_SBR_OPT_DIS Fld(1, 14) //[14:14] + #define HW_MRR_FUN_MRR_INT_TIE0_DIS Fld(1, 15) //[15:15] + #define HW_MRR_FUN_MRR_PUSH2POP_ENA Fld(1, 16) //[16:16] + #define HW_MRR_FUN_MRR_PUSH2POP_CLR Fld(1, 17) //[17:17] + #define HW_MRR_FUN_MRR_PUSH2POP_ST_CLR Fld(1, 18) //[18:18] + #define HW_MRR_FUN_MRR_MADIS Fld(1, 19) //[19:19] + #define HW_MRR_FUN_MRR_PUSH2POP_SEL Fld(3, 20) //[22:20] + #define HW_MRR_FUN_MRR_SBR3_BKVA_DIS Fld(1, 23) //[23:23] + #define HW_MRR_FUN_MRR_DDRCLKCOMB_DIS Fld(1, 24) //[24:24] + #define HW_MRR_FUN_TRPRCD_DIS_OPT1 Fld(1, 25) //[25:25] + #define HW_MRR_FUN_TRPRCD_OPT2 Fld(1, 26) //[26:26] + #define HW_MRR_FUN_MRR_SBR2_QHIT_DIS Fld(1, 27) //[27:27] + #define HW_MRR_FUN_MRR_INPUT_BANK Fld(3, 28) //[30:28] + #define HW_MRR_FUN_MRR_TZQCS_DIS Fld(1, 31) //[31:31] + +#define DRAMC_REG_SCHEDULER_COM (DRAMC_AO_BASE_ADDRESS + 0x017C) + #define SCHEDULER_COM_RWOFOEN Fld(1, 0) //[0:0] + #define SCHEDULER_COM_RWHPRICTL Fld(1, 4) //[4:4] + #define SCHEDULER_COM_RWSPLIT Fld(1, 5) //[5:5] + #define SCHEDULER_COM_MWHPRIEN Fld(1, 6) //[6:6] + #define SCHEDULER_COM_SPEC_MODE Fld(1, 7) //[7:7] + #define SCHEDULER_COM_DISRDPHASE1 Fld(1, 8) //[8:8] + #define SCHEDULER_COM_PBR2PBR_OPT Fld(1, 9) //[9:9] + +#define DRAMC_REG_ACTIMING_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0190) + #define ACTIMING_CTRL_SEQCLKRUN3 Fld(1, 0) //[0:0] + #define ACTIMING_CTRL_SEQCLKRUN2 Fld(1, 1) //[1:1] + #define ACTIMING_CTRL_SEQCLKRUN Fld(1, 2) //[2:2] + #define ACTIMING_CTRL_TMRR2WDIS Fld(1, 4) //[4:4] + #define ACTIMING_CTRL_MRRSWUPD Fld(1, 5) //[5:5] + #define ACTIMING_CTRL_REFNA_OPT Fld(1, 6) //[6:6] + #define ACTIMING_CTRL_REFBW_FREN Fld(1, 8) //[8:8] + #define ACTIMING_CTRL_CLKWITRFC Fld(1, 9) //[9:9] + #define ACTIMING_CTRL_CHKFORPRE Fld(1, 10) //[10:10] + #define ACTIMING_CTRL_BC4OTF_OPT Fld(1, 11) //[11:11] + #define ACTIMING_CTRL_TMRRICHKDIS Fld(1, 21) //[21:21] + #define ACTIMING_CTRL_TMRRIBYRK_DIS Fld(1, 22) //[22:22] + #define ACTIMING_CTRL_MRRIOPT Fld(1, 23) //[23:23] + #define ACTIMING_CTRL_FASTW2R Fld(1, 24) //[24:24] + #define ACTIMING_CTRL_APBL2 Fld(1, 25) //[25:25] + #define ACTIMING_CTRL_LPDDR2_NO_INT Fld(1, 27) //[27:27] + +#define DRAMC_REG_ZQ_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01A0) + #define ZQ_SET0_ZQCSOP Fld(8, 0) //[7:0] + #define ZQ_SET0_ZQCSAD Fld(8, 8) //[15:8] + #define ZQ_SET0_ZQCS_MASK_SEL Fld(3, 16) //[18:16] + #define ZQ_SET0_ZQCS_MASK_SEL_CGAR Fld(1, 19) //[19:19] + #define ZQ_SET0_ZQMASK_CGAR Fld(1, 20) //[20:20] + #define ZQ_SET0_ZQCSMASK_OPT Fld(1, 21) //[21:21] + #define ZQ_SET0_ZQ_SRF_OPT Fld(1, 22) //[22:22] + #define ZQ_SET0_DM3RANK Fld(1, 23) //[23:23] + #define ZQ_SET0_ZQCSMASK Fld(1, 29) //[29:29] + #define ZQ_SET0_ZQCSDUAL Fld(1, 30) //[30:30] + #define ZQ_SET0_ZQCALL Fld(1, 31) //[31:31] + +#define DRAMC_REG_ZQ_SET1 (DRAMC_AO_BASE_ADDRESS + 0x01A4) + #define ZQ_SET1_ZQCS_NONMASK_CLR Fld(1, 20) //[20:20] + #define ZQ_SET1_ZQCS_MASK_FIX Fld(1, 21) //[21:21] + #define ZQ_SET1_ZQCS_MASK_VALUE Fld(1, 22) //[22:22] + #define ZQ_SET1_ZQCALDISB Fld(1, 30) //[30:30] + #define ZQ_SET1_ZQCSDISB Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_TRACKING_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01B0) + #define TX_TRACKING_SET0_TX_TRACKING_OPT Fld(1, 15) //[15:15] + #define TX_TRACKING_SET0_SW_UP_TX_NOW_CASE Fld(1, 16) //[16:16] + #define TX_TRACKING_SET0_TXUIPI_CAL_CGAR Fld(1, 17) //[17:17] + #define TX_TRACKING_SET0_SHU_PRELOAD_TX_START Fld(1, 18) //[18:18] + #define TX_TRACKING_SET0_SHU_PRELOAD_TX_HW Fld(1, 19) //[19:19] + #define TX_TRACKING_SET0_APHY_CG_OPT1 Fld(1, 20) //[20:20] + #define TX_TRACKING_SET0_HMRRSEL_CGAR Fld(1, 21) //[21:21] + #define TX_TRACKING_SET0_RDDQSOSC_CGAR Fld(1, 22) //[22:22] + #define TX_TRACKING_SET0_DQSOSC_THRD_OPT Fld(1, 23) //[23:23] + #define TX_TRACKING_SET0_TX_PRECAL_RELOAD_OPT Fld(1, 24) //[24:24] + #define TX_TRACKING_SET0_DQSOSC_C2R_OPT Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_RETRY_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01C0) + #define TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK Fld(1, 0) //[0:0] + #define TX_RETRY_SET0_XSR_TX_RETRY_OPT Fld(1, 1) //[1:1] + #define TX_RETRY_SET0_XSR_TX_RETRY_EN Fld(1, 2) //[2:2] + #define TX_RETRY_SET0_XSR_TX_RETRY_SPM_MODE Fld(1, 3) //[3:3] + #define TX_RETRY_SET0_XSR_TX_RETRY_SW_EN Fld(1, 4) //[4:4] + #define TX_RETRY_SET0_TX_RETRY_UPDPI_CG_OPT Fld(1, 5) //[5:5] + #define TX_RETRY_SET0_TX_RETRY_SHU_RESP_OPT Fld(1, 6) //[6:6] + +#define DRAMC_REG_MPC_OPTION (DRAMC_AO_BASE_ADDRESS + 0x01C8) + #define MPC_OPTION_MPCOP Fld(7, 8) //[14:8] + #define MPC_OPTION_MPCMAN_CAS2EN Fld(1, 16) //[16:16] + #define MPC_OPTION_MPCRKEN Fld(1, 17) //[17:17] + +#define DRAMC_REG_MRR_BIT_MUX1 (DRAMC_AO_BASE_ADDRESS + 0x01D0) + #define MRR_BIT_MUX1_MRR_BIT0_SEL Fld(5, 0) //[4:0] + #define MRR_BIT_MUX1_MRR_BIT1_SEL Fld(5, 8) //[12:8] + #define MRR_BIT_MUX1_MRR_BIT2_SEL Fld(5, 16) //[20:16] + #define MRR_BIT_MUX1_MRR_BIT3_SEL Fld(5, 24) //[28:24] + +#define DRAMC_REG_MRR_BIT_MUX2 (DRAMC_AO_BASE_ADDRESS + 0x01D4) + #define MRR_BIT_MUX2_MRR_BIT4_SEL Fld(5, 0) //[4:0] + #define MRR_BIT_MUX2_MRR_BIT5_SEL Fld(5, 8) //[12:8] + #define MRR_BIT_MUX2_MRR_BIT6_SEL Fld(5, 16) //[20:16] + #define MRR_BIT_MUX2_MRR_BIT7_SEL Fld(5, 24) //[28:24] + +#define DRAMC_REG_MRR_BIT_MUX3 (DRAMC_AO_BASE_ADDRESS + 0x01D8) + #define MRR_BIT_MUX3_MRR_BIT8_SEL Fld(5, 0) //[4:0] + #define MRR_BIT_MUX3_MRR_BIT9_SEL Fld(5, 8) //[12:8] + #define MRR_BIT_MUX3_MRR_BIT10_SEL Fld(5, 16) //[20:16] + #define MRR_BIT_MUX3_MRR_BIT11_SEL Fld(5, 24) //[28:24] + +#define DRAMC_REG_MRR_BIT_MUX4 (DRAMC_AO_BASE_ADDRESS + 0x01DC) + #define MRR_BIT_MUX4_MRR_BIT12_SEL Fld(5, 0) //[4:0] + #define MRR_BIT_MUX4_MRR_BIT13_SEL Fld(5, 8) //[12:8] + #define MRR_BIT_MUX4_MRR_BIT14_SEL Fld(5, 16) //[20:16] + #define MRR_BIT_MUX4_MRR_BIT15_SEL Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHUCTRL (DRAMC_AO_BASE_ADDRESS + 0x01F8) + #define SHUCTRL_R_DVFS_FSM_CLR Fld(1, 0) //[0:0] + #define SHUCTRL_DMSHU_DRAMC Fld(1, 4) //[4:4] + +#define DRAMC_REG_DRAMC_PD_CTRL (DRAMC_AO_BASE_ADDRESS + 0x01FC) + #define DRAMC_PD_CTRL_DCMEN Fld(1, 0) //[0:0] + #define DRAMC_PD_CTRL_DCMEN2 Fld(1, 1) //[1:1] + #define DRAMC_PD_CTRL_DCMENNOTRFC Fld(1, 2) //[2:2] + #define DRAMC_PD_CTRL_PHYGLUECLKRUN Fld(1, 3) //[3:3] + #define DRAMC_PD_CTRL_PHYCLK_REFWKEN Fld(1, 4) //[4:4] + #define DRAMC_PD_CTRL_COMBPHY_CLKENSAME Fld(1, 5) //[5:5] + #define DRAMC_PD_CTRL_MIOCKCTRLOFF Fld(1, 6) //[6:6] + #define DRAMC_PD_CTRL_DRAMC_IDLE_DCM_FIXON Fld(1, 7) //[7:7] + #define DRAMC_PD_CTRL_PG_DCM_OPT Fld(1, 9) //[9:9] + #define DRAMC_PD_CTRL_COMB_DCM Fld(1, 10) //[10:10] + #define DRAMC_PD_CTRL_APHYCKCG_FIXOFF Fld(1, 12) //[12:12] + #define DRAMC_PD_CTRL_TCKFIXON Fld(1, 13) //[13:13] + #define DRAMC_PD_CTRL_PHYCLKDYNGEN Fld(1, 30) //[30:30] + #define DRAMC_PD_CTRL_COMBCLKCTRL Fld(1, 31) //[31:31] + +#define DRAMC_REG_DCM_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0200) + #define DCM_CTRL0_BCLKAR Fld(1, 2) //[2:2] + #define DCM_CTRL0_DBG_CKE1FIXON Fld(1, 4) //[4:4] + #define DCM_CTRL0_DBG_CKE1FIXOFF Fld(1, 5) //[5:5] + #define DCM_CTRL0_DBG_CKEFIXON Fld(1, 6) //[6:6] + #define DCM_CTRL0_DBG_CKEFIXOFF Fld(1, 7) //[7:7] + #define DCM_CTRL0_DISDMOEDIS Fld(1, 8) //[8:8] + #define DCM_CTRL0_IDLE_CNT_OPT Fld(1, 16) //[16:16] + #define DCM_CTRL0_IDLEDCM_CNT_OPT Fld(1, 17) //[17:17] + #define DCM_CTRL0_IDLE_COND_OPT Fld(1, 18) //[18:18] + +#define DRAMC_REG_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0x0204) + #define CKECTRL_CKE2RANK_OPT3 Fld(1, 1) //[1:1] + #define CKECTRL_CKE2FIXON Fld(1, 2) //[2:2] + #define CKECTRL_CKE2FIXOFF Fld(1, 3) //[3:3] + #define CKECTRL_CKE1FIXON Fld(1, 4) //[4:4] + #define CKECTRL_CKE1FIXOFF Fld(1, 5) //[5:5] + #define CKECTRL_CKEFIXON Fld(1, 6) //[6:6] + #define CKECTRL_CKEFIXOFF Fld(1, 7) //[7:7] + #define CKECTRL_CKE2RANK_OPT5 Fld(1, 8) //[8:8] + #define CKECTRL_CKE2RANK_OPT6 Fld(1, 9) //[9:9] + #define CKECTRL_CKE2RANK_OPT7 Fld(1, 10) //[10:10] + #define CKECTRL_CKE2RANK_OPT8 Fld(1, 11) //[11:11] + #define CKECTRL_CKEEXTEND Fld(1, 12) //[12:12] + #define CKECTRL_CKETIMER_SEL Fld(1, 13) //[13:13] + #define CKECTRL_FASTWAKE_SEL Fld(1, 14) //[14:14] + #define CKECTRL_CKEWAKE_SEL Fld(1, 15) //[15:15] + #define CKECTRL_CKEWAKE_SEL2 Fld(1, 16) //[16:16] + #define CKECTRL_CKE2RANK_OPT9 Fld(1, 17) //[17:17] + #define CKECTRL_CKE2RANK_OPT10 Fld(1, 18) //[18:18] + #define CKECTRL_CKE2RANK_OPT11 Fld(1, 19) //[19:19] + #define CKECTRL_CKE2RANK_OPT12 Fld(1, 20) //[20:20] + #define CKECTRL_CKE2RANK_OPT13 Fld(1, 21) //[21:21] + #define CKECTRL_CKEPBDIS Fld(1, 22) //[22:22] + #define CKECTRL_CKELCKFIX Fld(1, 23) //[23:23] + #define CKECTRL_CKE2RANK_OPT2 Fld(1, 24) //[24:24] + #define CKECTRL_CKE2RANK_OPT Fld(1, 25) //[25:25] + #define CKECTRL_RUNTIMEMRRCKEFIX Fld(1, 27) //[27:27] + #define CKECTRL_RUNTIMEMRRMIODIS Fld(1, 28) //[28:28] + #define CKECTRL_CKEON Fld(1, 31) //[31:31] + +#define DRAMC_REG_DVFS_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0208) + #define DVFS_CTRL0_R_DRAMC_CHA Fld(1, 0) //[0:0] + #define DVFS_CTRL0_SHU_PHYRST_SEL Fld(1, 1) //[1:1] + #define DVFS_CTRL0_R_DVFS_SREF_OPT Fld(1, 5) //[5:5] + #define DVFS_CTRL0_HWSET_WLRL Fld(1, 8) //[8:8] + #define DVFS_CTRL0_MR13_SHU_EN Fld(1, 9) //[9:9] + #define DVFS_CTRL0_VRCG_EN Fld(1, 10) //[10:10] + #define DVFS_CTRL0_SHU_CLK_MASK Fld(1, 12) //[12:12] + #define DVFS_CTRL0_DVFS_RXFIFOST_SKIP Fld(1, 13) //[13:13] + #define DVFS_CTRL0_DVFS_MR2_SKIP Fld(1, 14) //[14:14] + #define DVFS_CTRL0_DVFS_NOQUEFLUSH_EN Fld(1, 15) //[15:15] + #define DVFS_CTRL0_DVFS_CKE_OPT Fld(1, 16) //[16:16] + #define DVFS_CTRL0_R_SHUFFLE_BLOCK_OPT Fld(2, 17) //[18:17] + #define DVFS_CTRL0_DVFS_CG_OPT Fld(1, 19) //[19:19] + #define DVFS_CTRL0_SCARB_PRI_OPT Fld(1, 20) //[20:20] + #define DVFS_CTRL0_R_DMDVFSMRW_EN Fld(1, 21) //[21:21] + #define DVFS_CTRL0_MRWWOPRA Fld(1, 22) //[22:22] + #define DVFS_CTRL0_SHU2RKOPT Fld(1, 23) //[23:23] + #define DVFS_CTRL0_R_DMSHU_RDATRST_MASK Fld(1, 25) //[25:25] + #define DVFS_CTRL0_DVFS_SYNC_MASK Fld(1, 27) //[27:27] + +#define DRAMC_REG_SHUCTRL1 (DRAMC_AO_BASE_ADDRESS + 0x020C) + #define SHUCTRL1_FC_PRDCNT Fld(8, 0) //[7:0] + #define SHUCTRL1_CKFSPE_PRDCNT Fld(8, 8) //[15:8] + #define SHUCTRL1_CKFSPX_PRDCNT Fld(8, 16) //[23:16] + #define SHUCTRL1_VRCGEN_PRDCNT Fld(8, 24) //[31:24] + +#define DRAMC_REG_DVFS_TIMING_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0210) + #define DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT Fld(8, 0) //[7:0] + #define DVFS_TIMING_CTRL1_DMSHU_CNT Fld(6, 16) //[21:16] + +#define DRAMC_REG_SHUCTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0214) + #define SHUCTRL3_VRCGDIS_MRSMA Fld(13, 0) //[12:0] + #define SHUCTRL3_VRCGDISOP Fld(8, 16) //[23:16] + +#define DRAMC_REG_DVFS_TIMING_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0218) + #define DVFS_TIMING_CTRL3_PREA_INTV Fld(5, 0) //[4:0] + #define DVFS_TIMING_CTRL3_MRW_INTV Fld(5, 8) //[12:8] + #define DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP Fld(1, 16) //[16:16] + #define DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP Fld(1, 17) //[17:17] + #define DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP Fld(1, 18) //[18:18] + #define DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE Fld(1, 19) //[19:19] + #define DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE Fld(1, 20) //[20:20] + #define DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE Fld(1, 21) //[21:21] + #define DVFS_TIMING_CTRL3_RTMRW_MRW3_PRDCNT Fld(8, 24) //[31:24] + +#define DRAMC_REG_CMD_DEC_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x021C) + #define CMD_DEC_CTRL0_GDDR3RST Fld(1, 0) //[0:0] + #define CMD_DEC_CTRL0_SELPH_CMD_CG_DIS Fld(1, 4) //[4:4] + #define CMD_DEC_CTRL0_RA15TOCS1 Fld(1, 27) //[27:27] + #define CMD_DEC_CTRL0_RKMODE Fld(3, 8) //[10:8] + #define CMD_DEC_CTRL0_RKSWAP Fld(1, 11) //[11:11] + #define CMD_DEC_CTRL0_CS1FIXOFF Fld(1, 12) //[12:12] + #define CMD_DEC_CTRL0_PHYPIPE1EN Fld(1, 15) //[15:15] + #define CMD_DEC_CTRL0_PHYPIPE2EN Fld(1, 16) //[16:16] + #define CMD_DEC_CTRL0_PHYPIPE3EN Fld(1, 17) //[17:17] + #define CMD_DEC_CTRL0_DQCMD Fld(1, 19) //[19:19] + +#define DRAMC_REG_HMR4 (DRAMC_AO_BASE_ADDRESS + 0x0220) + #define HMR4_DRS_MR4_OPT_B Fld(1, 0) //[0:0] + #define HMR4_HMR4_TOG_OPT Fld(1, 1) //[1:1] + #define HMR4_SPDR_MR4_OPT Fld(1, 2) //[2:2] + #define HMR4_SRFMR4_CNTKEEP_B Fld(1, 3) //[3:3] + #define HMR4_MRRREFUPD_B Fld(1, 4) //[4:4] + #define HMR4_HMR4_BYTEMODE_EN Fld(1, 5) //[5:5] + #define HMR4_MR4INT_LIMITEN Fld(1, 6) //[6:6] + #define HMR4_REFR_PERIOD_OPT Fld(1, 7) //[7:7] + #define HMR4_REFRDIS Fld(1, 8) //[8:8] + #define HMR4_REFRCNT_OPT Fld(1, 9) //[9:9] + +#define DRAMC_REG_BYPASS_FSPOP (DRAMC_AO_BASE_ADDRESS + 0x0224) + #define BYPASS_FSPOP_BPFSP_SET_SHU0 Fld(1, 0) //[0:0] + #define BYPASS_FSPOP_BPFSP_SET_SHU1 Fld(1, 1) //[1:1] + #define BYPASS_FSPOP_BPFSP_SET_SHU2 Fld(1, 2) //[2:2] + #define BYPASS_FSPOP_BPFSP_SET_SHU3 Fld(1, 3) //[3:3] + #define BYPASS_FSPOP_BPFSP_SET_SHU4 Fld(1, 4) //[4:4] + #define BYPASS_FSPOP_BPFSP_SET_SHU5 Fld(1, 5) //[5:5] + #define BYPASS_FSPOP_BPFSP_SET_SHU6 Fld(1, 6) //[6:6] + #define BYPASS_FSPOP_BPFSP_SET_SHU7 Fld(1, 7) //[7:7] + #define BYPASS_FSPOP_BPFSP_SET_SHU8 Fld(1, 8) //[8:8] + #define BYPASS_FSPOP_BPFSP_SET_SHU9 Fld(1, 9) //[9:9] + #define BYPASS_FSPOP_BPFSP_OPT Fld(1, 16) //[16:16] + +#define DRAMC_REG_RKCFG (DRAMC_AO_BASE_ADDRESS + 0x0228) + #define RKCFG_MRS2RK Fld(1, 10) //[10:10] + #define RKCFG_CKE2RANK Fld(1, 12) //[12:12] + +#define DRAMC_REG_SLP4_TESTMODE (DRAMC_AO_BASE_ADDRESS + 0x022C) + #define SLP4_TESTMODE_CA0_TEST Fld(4, 0) //[3:0] + #define SLP4_TESTMODE_CA1_TEST Fld(4, 4) //[7:4] + #define SLP4_TESTMODE_CA2_TEST Fld(4, 8) //[11:8] + #define SLP4_TESTMODE_CA3_TEST Fld(4, 12) //[15:12] + #define SLP4_TESTMODE_CA4_TEST Fld(4, 16) //[19:16] + #define SLP4_TESTMODE_CA5_TEST Fld(4, 20) //[23:20] + +#define DRAMC_REG_DQ_MUX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0230) + #define DQ_MUX_SET0_SRF_ENTER_MASK_OPT Fld(1, 30) //[30:30] + #define DQ_MUX_SET0_DQ4BMUX Fld(1, 31) //[31:31] + +#define DRAMC_REG_DBIWR_PROTECT (DRAMC_AO_BASE_ADDRESS + 0x0234) + #define DBIWR_PROTECT_DBIWR_IMP_EN Fld(1, 0) //[0:0] + #define DBIWR_PROTECT_DBIWR_PINMUX_EN Fld(1, 1) //[1:1] + #define DBIWR_PROTECT_DBIWR_OPT_B0 Fld(8, 16) //[23:16] + #define DBIWR_PROTECT_DBIWR_OPT_B1 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0238) + #define TX_SET0_TXRANK Fld(2, 0) //[1:0] + #define TX_SET0_TXRANKFIX Fld(1, 2) //[2:2] + #define TX_SET0_DDRPHY_COMB_CG_SEL Fld(1, 3) //[3:3] + #define TX_SET0_TX_DQM_DEFAULT Fld(1, 4) //[4:4] + #define TX_SET0_DQBUS_X32 Fld(1, 5) //[5:5] + #define TX_SET0_OE_DOWNGRADE Fld(1, 6) //[6:6] + #define TX_SET0_DQ16COM1 Fld(1, 21) //[21:21] + #define TX_SET0_WPRE2T Fld(1, 22) //[22:22] + #define TX_SET0_DRSCLR_EN Fld(1, 24) //[24:24] + #define TX_SET0_DRSCLR_RK0_EN Fld(1, 25) //[25:25] + #define TX_SET0_ARPI_CAL_E2OPT Fld(1, 26) //[26:26] + #define TX_SET0_TX_DLY_CAL_E2OPT Fld(1, 27) //[27:27] + #define TX_SET0_DQS_OE_OP1_DIS Fld(1, 28) //[28:28] + #define TX_SET0_DQS_OE_OP2_EN Fld(1, 29) //[29:29] + #define TX_SET0_RK_SCINPUT_OPT Fld(1, 30) //[30:30] + #define TX_SET0_DRAMOEN Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x023C) + #define TX_CG_SET0_SELPH_4LCG_DIS Fld(1, 0) //[0:0] + #define TX_CG_SET0_SELPH_CG_DIS Fld(1, 1) //[1:1] + #define TX_CG_SET0_DWCLKRUN Fld(1, 2) //[2:2] + #define TX_CG_SET0_WDATA_CG_DIS Fld(1, 3) //[3:3] + #define TX_CG_SET0_TX_ATK_CLKRUN Fld(1, 4) //[4:4] + #define TX_CG_SET0_PSEL_OPT3 Fld(1, 22) //[22:22] + #define TX_CG_SET0_PSEL_OPT2 Fld(1, 23) //[23:23] + #define TX_CG_SET0_PSEL_OPT1 Fld(1, 24) //[24:24] + #define TX_CG_SET0_PSEL_CNT Fld(6, 25) //[30:25] + #define TX_CG_SET0_PSELAR Fld(1, 31) //[31:31] + +#define DRAMC_REG_RX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0240) + #define RX_SET0_RDATRST Fld(1, 0) //[0:0] + #define RX_SET0_PRE_DLE_VLD_OPT Fld(1, 1) //[1:1] + #define RX_SET0_DATLAT_PDLE_TH Fld(3, 2) //[4:2] + #define RX_SET0_RANKRDY_OPT Fld(1, 5) //[5:5] + #define RX_SET0_SMRR_UPD_OLD Fld(1, 6) //[6:6] + #define RX_SET0_EBG_DLE_SKIP_SPEC_RID Fld(1, 29) //[29:29] + #define RX_SET0_DM32BIT_RDSEL_OPT Fld(1, 30) //[30:30] + #define RX_SET0_DM4TO1MODE Fld(1, 31) //[31:31] + +#define DRAMC_REG_RX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0244) + #define RX_CG_SET0_RDPERIODON Fld(1, 29) //[29:29] + #define RX_CG_SET0_RDATCKAR Fld(1, 30) //[30:30] + #define RX_CG_SET0_RDYCKAR Fld(1, 31) //[31:31] + +#define DRAMC_REG_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0x0248) + #define DQSOSCR_DQSOSC_INTEN Fld(1, 0) //[0:0] + #define DQSOSCR_DQSOSC2RK Fld(1, 1) //[1:1] + #define DQSOSCR_TXUPD_BLOCK_SEL Fld(2, 2) //[3:2] + #define DQSOSCR_TXUPD_BLOCK_OPT Fld(1, 4) //[4:4] + #define DQSOSCR_TXUPDMODE Fld(1, 5) //[5:5] + #define DQSOSCR_MANUTXUPD Fld(1, 6) //[6:6] + #define DQSOSCR_ARUIDQ_SW Fld(1, 7) //[7:7] + #define DQSOSCR_DQS2DQ_UPD_BLOCK_CNT Fld(5, 8) //[12:8] + #define DQSOSCR_TDQS2DQ_UPD_BLOCKING Fld(1, 13) //[13:13] + #define DQSOSCR_DQS2DQ_UPD_MON_OPT Fld(1, 14) //[14:14] + #define DQSOSCR_DQS2DQ_UPD_MON_CNT_SEL Fld(2, 15) //[16:15] + #define DQSOSCR_TXUPD_IDLE_SEL Fld(2, 17) //[18:17] + #define DQSOSCR_TXUPD_ABREF_SEL Fld(2, 19) //[20:19] + #define DQSOSCR_TXUPD_IDLE_OPT Fld(1, 21) //[21:21] + #define DQSOSCR_DQS2DQ_SHU_HW_CAL_DIS Fld(1, 22) //[22:22] + #define DQSOSCR_SREF_TXUI_RELOAD_OPT Fld(1, 23) //[23:23] + #define DQSOSCR_DQSOSCRDIS Fld(1, 24) //[24:24] + #define DQSOSCR_DQS2DQ_WARN_OPT Fld(1, 25) //[25:25] + #define DQSOSCR_R_DMDQS2DQ_FILT_OPT Fld(1, 26) //[26:26] + #define DQSOSCR_SREF_TXPI_RELOAD_OPT Fld(1, 27) //[27:27] + #define DQSOSCR_EMPTY_WRITE_OPT Fld(1, 28) //[28:28] + #define DQSOSCR_TXUPD_ABREF_OPT Fld(1, 29) //[29:29] + #define DQSOSCR_DQSOSCLOPAD Fld(1, 30) //[30:30] + #define DQSOSCR_DQSOSC_CALEN Fld(1, 31) //[31:31] + +#define DRAMC_REG_DRAMCTRL (DRAMC_AO_BASE_ADDRESS + 0x024C) + #define DRAMCTRL_CTOREQ_HPRI_OPT Fld(1, 0) //[0:0] + #define DRAMCTRL_MATAB_LP5_MODE Fld(1, 1) //[1:1] + #define DRAMCTRL_ADRDECEN Fld(1, 2) //[2:2] + #define DRAMCTRL_ADRBIT3DEC Fld(1, 3) //[3:3] + #define DRAMCTRL_ADRDEN_1TO4_OPT Fld(1, 5) //[5:5] + #define DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN Fld(1, 8) //[8:8] + #define DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN Fld(1, 9) //[9:9] + #define DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN Fld(1, 10) //[10:10] + #define DRAMCTRL_AG0MWR Fld(1, 12) //[12:12] + #define DRAMCTRL_DYNMWREN Fld(1, 13) //[13:13] + #define DRAMCTRL_ALEBLOCK Fld(1, 14) //[14:14] + #define DRAMCTRL_PREALL_OPTION Fld(1, 19) //[19:19] + #define DRAMCTRL_REQQUE_DEPTH_UPD Fld(1, 25) //[25:25] + #define DRAMCTRL_REQQUE_THD_EN Fld(1, 26) //[26:26] + #define DRAMCTRL_REQQUE_MAXCNT_CHG Fld(1, 27) //[27:27] + #define DRAMCTRL_PREA_RK Fld(2, 28) //[29:28] + #define DRAMCTRL_SHORTQ_OPT Fld(1, 31) //[31:31] + +#define DRAMC_REG_MISCTL0 (DRAMC_AO_BASE_ADDRESS + 0x0250) + #define MISCTL0_REFP_ARBMASK_PBR2PBR_ENA Fld(1, 0) //[0:0] + #define MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS Fld(1, 1) //[1:1] + #define MISCTL0_WDLE_DVFS_NO_FLUSH_OPT_DIS Fld(1, 4) //[4:4] + #define MISCTL0_GROUP_A_REV Fld(4, 8) //[11:8] + #define MISCTL0_PG_WAKEUP_OPT Fld(2, 14) //[15:14] + #define MISCTL0_PAGDIS Fld(1, 17) //[17:17] + #define MISCTL0_REFA_ARB_EN2 Fld(1, 19) //[19:19] + #define MISCTL0_REFA_ARB_EN_OPTION Fld(1, 21) //[21:21] + #define MISCTL0_REORDER_MASK_E1T Fld(1, 22) //[22:22] + #define MISCTL0_PBC_ARB_E1T Fld(1, 23) //[23:23] + #define MISCTL0_PBC_ARB_EN Fld(1, 24) //[24:24] + #define MISCTL0_REFA_ARB_EN Fld(1, 25) //[25:25] + #define MISCTL0_REFP_ARB_EN Fld(1, 26) //[26:26] + #define MISCTL0_EMIPREEN Fld(1, 27) //[27:27] + #define MISCTL0_REFP_ARB_EN2 Fld(1, 31) //[31:31] + +#define DRAMC_REG_PERFCTL0 (DRAMC_AO_BASE_ADDRESS + 0x0254) + #define PERFCTL0_EBG_EN Fld(1, 0) //[0:0] + #define PERFCTL0_AIDCHKEN Fld(1, 3) //[3:3] + #define PERFCTL0_RWHPRIEN Fld(1, 8) //[8:8] + #define PERFCTL0_RWLLATEN Fld(1, 9) //[9:9] + #define PERFCTL0_RWAGEEN Fld(1, 10) //[10:10] + #define PERFCTL0_EMILLATEN Fld(1, 11) //[11:11] + #define PERFCTL0_WFLUSHEN Fld(1, 14) //[14:14] + #define PERFCTL0_REORDER_MODE Fld(1, 18) //[18:18] + #define PERFCTL0_REORDEREN Fld(1, 19) //[19:19] + #define PERFCTL0_SBR_MASK_OPT Fld(1, 20) //[20:20] + #define PERFCTL0_SBR_MASK_OPT2 Fld(1, 21) //[21:21] + #define PERFCTL0_MAFIXHIGH Fld(1, 22) //[22:22] + #define PERFCTL0_RECORDER_MASK_OPT Fld(1, 24) //[24:24] + #define PERFCTL0_MDMCU_MASK_EN Fld(1, 25) //[25:25] + +#define DRAMC_REG_ARBCTL (DRAMC_AO_BASE_ADDRESS + 0x0258) + #define ARBCTL_MAXPENDCNT Fld(8, 0) //[7:0] + #define ARBCTL_RDATACNTDIS Fld(1, 8) //[8:8] + #define ARBCTL_WDATACNTDIS Fld(1, 9) //[9:9] + +#define DRAMC_REG_DATASCR (DRAMC_AO_BASE_ADDRESS + 0x025C) + #define DATASCR_WDATKEY0 Fld(1, 0) //[0:0] + #define DATASCR_WDATKEY1 Fld(1, 1) //[1:1] + #define DATASCR_WDATKEY2 Fld(1, 2) //[2:2] + #define DATASCR_WDATKEY3 Fld(1, 3) //[3:3] + #define DATASCR_WDATKEY4 Fld(1, 4) //[4:4] + #define DATASCR_WDATKEY5 Fld(1, 5) //[5:5] + #define DATASCR_WDATKEY6 Fld(1, 6) //[6:6] + #define DATASCR_WDATKEY7 Fld(1, 7) //[7:7] + #define DATASCR_WDATITLV Fld(1, 8) //[8:8] + +#define DRAMC_REG_CLKAR (DRAMC_AO_BASE_ADDRESS + 0x0260) + #define CLKAR_REQQUE_PACG_DIS Fld(15, 0) //[14:0] + #define CLKAR_SRF_CLKRUN Fld(1, 17) //[17:17] + #define CLKAR_IDLE_OPT Fld(1, 18) //[18:18] + #define CLKAR_RKSIZE Fld(3, 20) //[22:20] + #define CLKAR_DCMREF_OPT Fld(1, 24) //[24:24] + #define CLKAR_REQQUECLKRUN Fld(1, 27) //[27:27] + +#define DRAMC_REG_REFCTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0264) + #define REFCTRL0_PBREF_BK_REFA_NUM Fld(3, 0) //[2:0] + #define REFCTRL0_PBREF_BK_REFA_ENA Fld(1, 3) //[3:3] + #define REFCTRL0_RFRINTCTL Fld(1, 5) //[5:5] + #define REFCTRL0_RFRINTEN Fld(1, 6) //[6:6] + #define REFCTRL0_REFOVERCNT_RST Fld(1, 7) //[7:7] + #define REFCTRL0_DMPGVLD_IG Fld(1, 8) //[8:8] + #define REFCTRL0_KEEP_PBREF_OPT Fld(1, 9) //[9:9] + #define REFCTRL0_KEEP_PBREF Fld(1, 10) //[10:10] + #define REFCTRL0_DISBYREFNUM Fld(3, 12) //[14:12] + #define REFCTRL0_PBREF_DISBYREFNUM Fld(1, 16) //[16:16] + #define REFCTRL0_PBREF_DISBYRATE Fld(1, 17) //[17:17] + #define REFCTRL0_SREF3_OPTION1 Fld(1, 19) //[19:19] + #define REFCTRL0_ADVREF_CNT Fld(4, 20) //[23:20] + #define REFCTRL0_REF_PREGATE_CNT Fld(4, 24) //[27:24] + #define REFCTRL0_REFDIS Fld(1, 29) //[29:29] + +#define DRAMC_REG_REFCTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0268) + #define REFCTRL1_PB2AB_OPT Fld(1, 0) //[0:0] + #define REFCTRL1_PB2AB_OPT1 Fld(1, 1) //[1:1] + #define REFCTRL1_PBREF_DISBYMODREF Fld(1, 2) //[2:2] + #define REFCTRL1_REFPENDINGINT_OPT1 Fld(1, 3) //[3:3] + #define REFCTRL1_PRE8REF Fld(1, 4) //[4:4] + #define REFCTRL1_REF_QUE_AUTOSAVE_EN Fld(1, 5) //[5:5] + #define REFCTRL1_REFPEND_OPT1 Fld(1, 6) //[6:6] + #define REFCTRL1_REFPEND_OPT2 Fld(1, 7) //[7:7] + #define REFCTRL1_REFPB2AB_IGZQCS Fld(1, 8) //[8:8] + #define REFCTRL1_REFRATE_MON_CLR Fld(1, 11) //[11:11] + #define REFCTRL1_REF_OVERHEAD_PBR2PB_ENA Fld(1, 13) //[13:13] + #define REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA Fld(1, 14) //[14:14] + #define REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA Fld(1, 15) //[15:15] + #define REFCTRL1_REFRATE_MANUAL Fld(5, 16) //[20:16] + #define REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA Fld(1, 24) //[24:24] + #define REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA Fld(1, 25) //[25:25] + #define REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA Fld(1, 26) //[26:26] + #define REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA Fld(1, 27) //[27:27] + #define REFCTRL1_REFRATE_MANUAL_RATE_TRIG Fld(1, 31) //[31:31] + +#define DRAMC_REG_REF_BOUNCE1 (DRAMC_AO_BASE_ADDRESS + 0x026C) + #define REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT Fld(8, 0) //[7:0] + #define REF_BOUNCE1_REFRATE_DEBOUNCE_TH Fld(5, 8) //[12:8] + #define REF_BOUNCE1_REFRATE_DEBOUNCE_OPT Fld(1, 13) //[13:13] + #define REF_BOUNCE1_REFRATE_DEBOUNCE_DIS Fld(16, 16) //[31:16] + +#define DRAMC_REG_REF_BOUNCE2 (DRAMC_AO_BASE_ADDRESS + 0x0270) + #define REF_BOUNCE2_PRE_MR4INT_TH Fld(5, 0) //[4:0] + +#define DRAMC_REG_REFPEND1 (DRAMC_AO_BASE_ADDRESS + 0x0278) + #define REFPEND1_MPENDREFCNT_TH0 Fld(4, 0) //[3:0] + #define REFPEND1_MPENDREFCNT_TH1 Fld(4, 4) //[7:4] + #define REFPEND1_MPENDREFCNT_TH2 Fld(4, 8) //[11:8] + #define REFPEND1_MPENDREFCNT_TH3 Fld(4, 12) //[15:12] + #define REFPEND1_MPENDREFCNT_TH4 Fld(4, 16) //[19:16] + #define REFPEND1_MPENDREFCNT_TH5 Fld(4, 20) //[23:20] + #define REFPEND1_MPENDREFCNT_TH6 Fld(4, 24) //[27:24] + #define REFPEND1_MPENDREFCNT_TH7 Fld(4, 28) //[31:28] + +#define DRAMC_REG_REFPEND2 (DRAMC_AO_BASE_ADDRESS + 0x027C) + #define REFPEND2_MPENDREFCNT_TH8 Fld(4, 0) //[3:0] + #define REFPEND2_MPENDREFCNT_TH9 Fld(4, 4) //[7:4] + #define REFPEND2_MPENDREFCNT_TH10 Fld(4, 8) //[11:8] + #define REFPEND2_MPENDREFCNT_TH11 Fld(4, 12) //[15:12] + #define REFPEND2_MPENDREFCNT_TH12 Fld(4, 16) //[19:16] + #define REFPEND2_MPENDREFCNT_TH13 Fld(4, 20) //[23:20] + #define REFPEND2_MPENDREFCNT_TH14 Fld(4, 24) //[27:24] + #define REFPEND2_MPENDREFCNT_TH15 Fld(4, 28) //[31:28] + +#define DRAMC_REG_REFQUE_CNT (DRAMC_AO_BASE_ADDRESS + 0x0280) + #define REFQUE_CNT_REFRESH_QUEUE_CNT_FROM_AO Fld(4, 0) //[3:0] + +#define DRAMC_REG_SCSMCTRL (DRAMC_AO_BASE_ADDRESS + 0x0284) + #define SCSMCTRL_SC_PG_UPD_OPT Fld(1, 0) //[0:0] + #define SCSMCTRL_SC_PG_MAN_DIS Fld(1, 1) //[1:1] + #define SCSMCTRL_SC_PG_OPT2_DIS Fld(1, 8) //[8:8] + #define SCSMCTRL_SC_PG_STCMD_AREF_DIS Fld(1, 9) //[9:9] + #define SCSMCTRL_SC_PG_MPRW_DIS Fld(1, 10) //[10:10] + #define SCSMCTRL_SCPRE Fld(1, 19) //[19:19] + +#define DRAMC_REG_SCSMCTRL_CG (DRAMC_AO_BASE_ADDRESS + 0x0288) + #define SCSMCTRL_CG_SCARB_SM_CGAR Fld(1, 30) //[30:30] + #define SCSMCTRL_CG_SCSM_CGAR Fld(1, 31) //[31:31] + +#define DRAMC_REG_REFCTRL2 (DRAMC_AO_BASE_ADDRESS + 0x028C) + #define REFCTRL2_MR4INT_TH Fld(5, 0) //[4:0] + #define REFCTRL2_PB2AB_THD Fld(3, 8) //[10:8] + #define REFCTRL2_REF_OVERHEAD_RATE Fld(16, 16) //[31:16] + +#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0 (DRAMC_AO_BASE_ADDRESS + 0x0290) + #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_8 Fld(5, 0) //[4:0] + #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_9 Fld(5, 8) //[12:8] + #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_10 Fld(5, 16) //[20:16] + #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_11 Fld(5, 24) //[28:24] + #define TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE1 (DRAMC_AO_BASE_ADDRESS + 0x0294) + #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_4 Fld(5, 0) //[4:0] + #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_5 Fld(5, 8) //[12:8] + #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_6 Fld(5, 16) //[20:16] + #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_7 Fld(5, 24) //[28:24] + +#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE2 (DRAMC_AO_BASE_ADDRESS + 0x0298) + #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_0 Fld(5, 0) //[4:0] + #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_1 Fld(5, 8) //[12:8] + #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_2 Fld(5, 16) //[20:16] + #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_3 Fld(5, 24) //[28:24] + +#define DRAMC_REG_WDT_RST (DRAMC_AO_BASE_ADDRESS + 0x029C) + #define WDT_RST_WDT_DBG_RST Fld(1, 0) //[0:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B01 (DRAMC_AO_BASE_ADDRESS + 0x02A0) + #define SEDA_LOOP_BAK_ERR_PAT_B01_SEDA_LOOP_BAK_ERR_PAT0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B23 (DRAMC_AO_BASE_ADDRESS + 0x02A4) + #define SEDA_LOOP_BAK_ERR_PAT_B23_SEDA_LOOP_BAK_ERR_PAT1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B45 (DRAMC_AO_BASE_ADDRESS + 0x02A8) + #define SEDA_LOOP_BAK_ERR_PAT_B45_SEDA_LOOP_BAK_ERR_PAT2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B67 (DRAMC_AO_BASE_ADDRESS + 0x02AC) + #define SEDA_LOOP_BAK_ERR_PAT_B67_SEDA_LOOP_BAK_ERR_PAT3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_SET (DRAMC_AO_BASE_ADDRESS + 0x02B0) + #define SEDA_LOOP_BAK_SET_WPRE0T Fld(1, 0) //[0:0] + #define SEDA_LOOP_BAK_SET_DRAMC_LOOP_BAK_EN Fld(1, 1) //[1:1] + #define SEDA_LOOP_BAK_SET_DRAMC_LOOP_BAK_CMP_EN Fld(1, 2) //[2:2] + #define SEDA_LOOP_BAK_SET_LOOP_BAK_WDAT_SEL Fld(3, 4) //[6:4] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL0 (DRAMC_AO_BASE_ADDRESS + 0x02C0) + #define DBG_CMDDEC_CMDSEL0_RANK0_10GBEN Fld(1, 0) //[0:0] + #define DBG_CMDDEC_CMDSEL0_RANK1_10GBEN Fld(1, 1) //[1:1] + #define DBG_CMDDEC_CMDSEL0_DBG_CMDDEC_CMDSEL Fld(1, 4) //[4:4] + #define DBG_CMDDEC_CMDSEL0_DBG_CMDDEC_CMDTYPE Fld(16, 16) //[31:16] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL1 (DRAMC_AO_BASE_ADDRESS + 0x02C4) + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_OP Fld(8, 0) //[7:0] + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_MA Fld(8, 8) //[15:8] + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_C Fld(12, 16) //[27:16] + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_RK Fld(2, 28) //[29:28] + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_SINGLE Fld(1, 30) //[30:30] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL2 (DRAMC_AO_BASE_ADDRESS + 0x02C8) + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_R Fld(17, 0) //[16:0] + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_BA Fld(3, 17) //[19:17] + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_BL Fld(1, 20) //[20:20] + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_AP Fld(1, 21) //[21:21] + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_AB Fld(1, 22) //[22:22] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL3 (DRAMC_AO_BASE_ADDRESS + 0x02CC) + #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA0 Fld(8, 0) //[7:0] + #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA1 Fld(8, 8) //[15:8] + #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA2 Fld(8, 16) //[23:16] + #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA3 Fld(8, 24) //[31:24] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL4 (DRAMC_AO_BASE_ADDRESS + 0x02D0) + #define DBG_CMDDEC_CMDSEL4_DBG_CMDDEC_CMDSEL_CA4 Fld(8, 0) //[7:0] + #define DBG_CMDDEC_CMDSEL4_DBG_CMDDEC_CMDSEL_CA5 Fld(8, 8) //[15:8] + +#define DRAMC_REG_RTSWCMD_CNT (DRAMC_AO_BASE_ADDRESS + 0x02D4) + #define RTSWCMD_CNT_RTSWCMD_CNT Fld(32, 0) //[31:0] + +#define DRAMC_REG_REFCTRL3 (DRAMC_AO_BASE_ADDRESS + 0x02D8) + #define REFCTRL3_REF_DERATING_EN Fld(16, 0) //[15:0] + +#define DRAMC_REG_DRAMC_IRQ_EN (DRAMC_AO_BASE_ADDRESS + 0x02E0) + #define DRAMC_IRQ_EN_MR4INT_EN Fld(1, 0) //[0:0] + #define DRAMC_IRQ_EN_REFPENDINGINT_EN Fld(1, 1) //[1:1] + #define DRAMC_IRQ_EN_PRE_MR4INT_EN Fld(1, 2) //[2:2] + #define DRAMC_IRQ_EN_RTMRWINT_EN Fld(1, 3) //[3:3] + #define DRAMC_IRQ_EN_INT_SREF_REQ_NO_ACK_EN Fld(1, 6) //[6:6] + #define DRAMC_IRQ_EN_INT_SREF_REQ_SHORT_EN Fld(1, 7) //[7:7] + #define DRAMC_IRQ_EN_INT_SREF_REQ_DTRIG_EN Fld(1, 8) //[8:8] + #define DRAMC_IRQ_EN_RTSWCMDINT_EN Fld(1, 12) //[12:12] + #define DRAMC_IRQ_EN_TX_TRACKING_INT1_EN Fld(1, 16) //[16:16] + #define DRAMC_IRQ_EN_TX_TRACKING_INT2_EN Fld(1, 17) //[17:17] + #define DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV Fld(14, 18) //[31:18] + +#define DRAMC_REG_DRAMC_IRQ_CLEAR (DRAMC_AO_BASE_ADDRESS + 0x02E4) + #define DRAMC_IRQ_CLEAR_MR4INT_CLR Fld(1, 0) //[0:0] + #define DRAMC_IRQ_CLEAR_REFPENDINGINT_CLR Fld(1, 1) //[1:1] + #define DRAMC_IRQ_CLEAR_PRE_MR4INT_CLR Fld(1, 2) //[2:2] + #define DRAMC_IRQ_CLEAR_RTMRWINT_CLR Fld(1, 3) //[3:3] + #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_NO_ACK_CLR Fld(1, 6) //[6:6] + #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_SHORT_CLR Fld(1, 7) //[7:7] + #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_DTRIG_CLR Fld(1, 8) //[8:8] + #define DRAMC_IRQ_CLEAR_RTSWCMDINT_CLR Fld(1, 12) //[12:12] + #define DRAMC_IRQ_CLEAR_DRAMC_IRQ_CLEAR_RSV Fld(19, 13) //[31:13] + +#define DRAMC_REG_IRQ_RSV1 (DRAMC_AO_BASE_ADDRESS + 0x02E8) + #define IRQ_RSV1_IRQ_RSV1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_IRQ_RSV2 (DRAMC_AO_BASE_ADDRESS + 0x02EC) + #define IRQ_RSV2_IRQ_RSV2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_REFCNT_FR_CLK1 (DRAMC_AO_BASE_ADDRESS + 0x02F0) + #define REFCNT_FR_CLK1_REFCNT_FR_CLK_1X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK1_REFCNT_FR_CLK_2X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK2 (DRAMC_AO_BASE_ADDRESS + 0x02F4) + #define REFCNT_FR_CLK2_REFCNT_FR_CLK_4X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK2_REFCNT_FR_CLK_8X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK3 (DRAMC_AO_BASE_ADDRESS + 0x02F8) + #define REFCNT_FR_CLK3_REFCNT_FR_CLK_0P25X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK3_REFCNT_FR_CLK_0P5X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK4 (DRAMC_AO_BASE_ADDRESS + 0x02FC) + #define REFCNT_FR_CLK4_REFCNT_FR_CLK_1P3X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK4_REFCNT_FR_CLK_1P7X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK5 (DRAMC_AO_BASE_ADDRESS + 0x0300) + #define REFCNT_FR_CLK5_REFCNT_FR_CLK_2P5X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK5_REFCNT_FR_CLK_3P3X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK6 (DRAMC_AO_BASE_ADDRESS + 0x0304) + #define REFCNT_FR_CLK6_REFCNT_FR_CLK_6X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK6_REFCNT_FR_CLK_0P7X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK7 (DRAMC_AO_BASE_ADDRESS + 0x0308) + #define REFCNT_FR_CLK7_REFCNT_FR_CLK_0P125X Fld(11, 0) //[10:0] + +#define DRAMC_REG_DCM_SUB_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0310) + #define DCM_SUB_CTRL_SUBCLK_CTRL_ZQ_CAL Fld(1, 0) //[0:0] + #define DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING Fld(1, 1) //[1:1] + #define DCM_SUB_CTRL_SUBCLK_CTRL_TEST2 Fld(1, 2) //[2:2] + #define DCM_SUB_CTRL_SUBCLK_CTRL_SWCMD Fld(1, 3) //[3:3] + #define DCM_SUB_CTRL_SUBCLK_CTRL_SREF Fld(1, 4) //[4:4] + #define DCM_SUB_CTRL_SUBCLK_CTRL_SHUFFLE_SM Fld(1, 5) //[5:5] + #define DCM_SUB_CTRL_SUBCLK_CTRL_REF Fld(1, 6) //[6:6] + #define DCM_SUB_CTRL_SUBCLK_CTRL_PD_NEW Fld(1, 7) //[7:7] + #define DCM_SUB_CTRL_SUBCLK_CTRL_HMR4 Fld(1, 8) //[8:8] + #define DCM_SUB_CTRL_SUBCLK_CTRL_DUMMY_READ Fld(1, 9) //[9:9] + #define DCM_SUB_CTRL_SUBCLK_CTRL_DPD Fld(1, 10) //[10:10] + #define DCM_SUB_CTRL_SUBCLK_CTRL_CBT_WLEV Fld(1, 11) //[11:11] + #define DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK Fld(1, 12) //[12:12] + +#define DRAMC_REG_CBT_WLEV_CTRL5 (DRAMC_AO_BASE_ADDRESS + 0x0320) + #define CBT_WLEV_CTRL5_NEW_CBT_CAPATEN Fld(1, 0) //[0:0] + #define CBT_WLEV_CTRL5_NEW_CBT_CAGOLDEN_SEL Fld(3, 1) //[3:1] + #define CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV Fld(8, 4) //[11:4] + #define CBT_WLEV_CTRL5_NEW_CBT_INVERT_NUM Fld(1, 12) //[12:12] + #define CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM Fld(3, 13) //[15:13] + #define CBT_WLEV_CTRL5_NEW_CBT_CA_NUM Fld(4, 16) //[19:16] + #define CBT_WLEV_CTRL5_NEW_CBT_PAT_RKSEL Fld(2, 20) //[21:20] + #define CBT_WLEV_CTRL5_CBT_NEW_MODE Fld(1, 22) //[22:22] + +#define DRAMC_REG_DRAM_CLK_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0330) + #define DRAM_CLK_CTRL_CLK_EN Fld(1, 0) //[0:0] + +#define DRAMC_REG_RK_TEST2_A1 (DRAMC_AO_BASE_ADDRESS + 0x0500) + #define RK_TEST2_A1_TEST2_BASE Fld(29, 3) //[31:3] + +#define DRAMC_REG_RK_DUMMY_RD_WDATA0 (DRAMC_AO_BASE_ADDRESS + 0x0504) + #define RK_DUMMY_RD_WDATA0_DMY_RD_WDATA0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK_DUMMY_RD_WDATA1 (DRAMC_AO_BASE_ADDRESS + 0x0508) + #define RK_DUMMY_RD_WDATA1_DMY_RD_WDATA1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK_DUMMY_RD_WDATA2 (DRAMC_AO_BASE_ADDRESS + 0x050C) + #define RK_DUMMY_RD_WDATA2_DMY_RD_WDATA2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK_DUMMY_RD_WDATA3 (DRAMC_AO_BASE_ADDRESS + 0x0510) + #define RK_DUMMY_RD_WDATA3_DMY_RD_WDATA3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK_DUMMY_RD_ADR (DRAMC_AO_BASE_ADDRESS + 0x0514) + #define RK_DUMMY_RD_ADR_DMY_RD_COL_ADR Fld(11, 17) //[27:17] + #define RK_DUMMY_RD_ADR_DMY_RD_LEN Fld(4, 28) //[31:28] + +#define DRAMC_REG_RK_DUMMY_RD_ADR2 (DRAMC_AO_BASE_ADDRESS + 0x0554) + #define RK_DUMMY_RD_ADR2_DMY_RD_BK Fld(4, 0) //[3:0] + #define RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR Fld(18, 4) //[21:4] + +#define DRAMC_REG_RK_SREF_DPD_TCK_RK_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0568) + #define RK_SREF_DPD_TCK_RK_CTRL_DPD_EN Fld(1, 29) //[29:29] + #define RK_SREF_DPD_TCK_RK_CTRL_DPDX_EN Fld(1, 30) //[30:30] + #define RK_SREF_DPD_TCK_RK_CTRL_SRF_EN Fld(1, 31) //[31:31] + +#define DRAMC_REG_RK_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x0590) + #define RK_DQSOSC_RK0_BYTE_MODE Fld(1, 29) //[29:29] + #define RK_DQSOSC_DQSOSCR_RK0EN Fld(1, 30) //[30:30] + #define RK_DQSOSC_DQSOSC_RK0INTCLR Fld(1, 31) //[31:31] + +#define DRAMC_REG_WDT_DBG_SIGNAL (DRAMC_AO_BASE_ADDRESS + 0x0D00) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK0_FROM_AO Fld(1, 0) //[0:0] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK1_FROM_AO Fld(1, 1) //[1:1] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK0_FROM_AO Fld(1, 2) //[2:2] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK1_FROM_AO Fld(1, 3) //[3:3] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK0_FROM_AO Fld(1, 4) //[4:4] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK1_FROM_AO Fld(1, 5) //[5:5] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK0_FROM_AO Fld(1, 8) //[8:8] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK1_FROM_AO Fld(1, 9) //[9:9] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK0_FROM_AO Fld(1, 10) //[10:10] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK1_FROM_AO Fld(1, 11) //[11:11] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK0_FROM_AO Fld(1, 12) //[12:12] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK1_FROM_AO Fld(1, 13) //[13:13] + #define WDT_DBG_SIGNAL_LATCH_DRAMC_GATING_ERROR_FROM_AO Fld(1, 14) //[14:14] + +#define DRAMC_REG_SELFREF_HWSAVE_FLAG (DRAMC_AO_BASE_ADDRESS + 0x0D08) + #define SELFREF_HWSAVE_FLAG_SELFREF_HWSAVE_FLAG_FROM_AO Fld(1, 0) //[0:0] + +#define DRAMC_REG_DRAMC_IRQ_STATUS1 (DRAMC_AO_BASE_ADDRESS + 0x0F00) + #define DRAMC_IRQ_STATUS1_DRAMC_IRQ_STATUS1_X0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_IRQ_STATUS2 (DRAMC_AO_BASE_ADDRESS + 0x0F04) + #define DRAMC_IRQ_STATUS2_DRAMC_IRQ_STATUS2_X0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_IRQ_INFO1 (DRAMC_AO_BASE_ADDRESS + 0x0F10) + #define DRAMC_IRQ_INFO1_REFRESH_RATE_FOR_INT_X0 Fld(5, 0) //[4:0] + #define DRAMC_IRQ_INFO1_REFRESH_QUEUE_CNT_FOR_INT_X0 Fld(4, 8) //[11:8] + #define DRAMC_IRQ_INFO1_REFRESH_RATE_CHG_QUEUE_CNT_FOR_INT_X0 Fld(4, 12) //[15:12] + +#define DRAMC_REG_DRAMC_IRQ_INFO1A (DRAMC_AO_BASE_ADDRESS + 0x0F14) + #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_FOR_INT_X0 Fld(5, 0) //[4:0] + #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_FOR_INT_X0 Fld(5, 8) //[12:8] + #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_B1_FOR_INT_X0 Fld(5, 16) //[20:16] + #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_B1_FOR_INT_X0 Fld(5, 24) //[28:24] + +#define DRAMC_REG_DRAMC_IRQ_INFO2 (DRAMC_AO_BASE_ADDRESS + 0x0F20) + #define DRAMC_IRQ_INFO2_RK0_MR18_INT1_X0 Fld(16, 0) //[15:0] + #define DRAMC_IRQ_INFO2_RK0_MR19_INT1_X0 Fld(16, 16) //[31:16] + +#define DRAMC_REG_DRAMC_IRQ_INFO3 (DRAMC_AO_BASE_ADDRESS + 0x0F24) + #define DRAMC_IRQ_INFO3_RK1_MR18_INT1_X0 Fld(16, 0) //[15:0] + #define DRAMC_IRQ_INFO3_RK1_MR19_INT1_X0 Fld(16, 16) //[31:16] + +#define DRAMC_REG_DRAMC_IRQ_INFO4 (DRAMC_AO_BASE_ADDRESS + 0x0F28) + #define DRAMC_IRQ_INFO4_RK0_MR18_INT2_X0 Fld(16, 0) //[15:0] + #define DRAMC_IRQ_INFO4_RK0_MR19_INT2_X0 Fld(16, 16) //[31:16] + +#define DRAMC_REG_DRAMC_IRQ_INFO5 (DRAMC_AO_BASE_ADDRESS + 0x0F2C) + #define DRAMC_IRQ_INFO5_RK1_MR18_INT2_X0 Fld(16, 0) //[15:0] + #define DRAMC_IRQ_INFO5_RK1_MR19_INT2_X0 Fld(16, 16) //[31:16] + +#define DRAMC_REG_SHURK_SELPH_DQ0 (DRAMC_AO_BASE_ADDRESS + 0x1200) + #define SHURK_SELPH_DQ0_TXDLY_DQ0 Fld(3, 0) //[2:0] + #define SHURK_SELPH_DQ0_TXDLY_DQ1 Fld(3, 4) //[6:4] + #define SHURK_SELPH_DQ0_TXDLY_DQ2 Fld(3, 8) //[10:8] + #define SHURK_SELPH_DQ0_TXDLY_DQ3 Fld(3, 12) //[14:12] + #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ0 Fld(3, 16) //[18:16] + #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ1 Fld(3, 20) //[22:20] + #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ2 Fld(3, 24) //[26:24] + #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ3 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHURK_SELPH_DQ1 (DRAMC_AO_BASE_ADDRESS + 0x1204) + #define SHURK_SELPH_DQ1_TXDLY_DQM0 Fld(3, 0) //[2:0] + #define SHURK_SELPH_DQ1_TXDLY_DQM1 Fld(3, 4) //[6:4] + #define SHURK_SELPH_DQ1_TXDLY_DQM2 Fld(3, 8) //[10:8] + #define SHURK_SELPH_DQ1_TXDLY_DQM3 Fld(3, 12) //[14:12] + #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM0 Fld(3, 16) //[18:16] + #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM1 Fld(3, 20) //[22:20] + #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM2 Fld(3, 24) //[26:24] + #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM3 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHURK_SELPH_DQ2 (DRAMC_AO_BASE_ADDRESS + 0x1208) + #define SHURK_SELPH_DQ2_DLY_DQ0 Fld(4, 0) //[3:0] + #define SHURK_SELPH_DQ2_DLY_DQ1 Fld(4, 4) //[7:4] + #define SHURK_SELPH_DQ2_DLY_DQ2 Fld(4, 8) //[11:8] + #define SHURK_SELPH_DQ2_DLY_DQ3 Fld(4, 12) //[15:12] + #define SHURK_SELPH_DQ2_DLY_OEN_DQ0 Fld(4, 16) //[19:16] + #define SHURK_SELPH_DQ2_DLY_OEN_DQ1 Fld(4, 20) //[23:20] + #define SHURK_SELPH_DQ2_DLY_OEN_DQ2 Fld(4, 24) //[27:24] + #define SHURK_SELPH_DQ2_DLY_OEN_DQ3 Fld(4, 28) //[31:28] + +#define DRAMC_REG_SHURK_SELPH_DQ3 (DRAMC_AO_BASE_ADDRESS + 0x120C) + #define SHURK_SELPH_DQ3_DLY_DQM0 Fld(4, 0) //[3:0] + #define SHURK_SELPH_DQ3_DLY_DQM1 Fld(4, 4) //[7:4] + #define SHURK_SELPH_DQ3_DLY_DQM2 Fld(4, 8) //[11:8] + #define SHURK_SELPH_DQ3_DLY_DQM3 Fld(4, 12) //[15:12] + #define SHURK_SELPH_DQ3_DLY_OEN_DQM0 Fld(4, 16) //[19:16] + #define SHURK_SELPH_DQ3_DLY_OEN_DQM1 Fld(4, 20) //[23:20] + #define SHURK_SELPH_DQ3_DLY_OEN_DQM2 Fld(4, 24) //[27:24] + #define SHURK_SELPH_DQ3_DLY_OEN_DQM3 Fld(4, 28) //[31:28] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL1 (DRAMC_AO_BASE_ADDRESS + 0x1210) + #define SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 Fld(11, 0) //[10:0] + #define SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 Fld(11, 16) //[26:16] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL2 (DRAMC_AO_BASE_ADDRESS + 0x1214) + #define SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 Fld(11, 0) //[10:0] + #define SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 Fld(11, 16) //[26:16] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL3 (DRAMC_AO_BASE_ADDRESS + 0x1218) + #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 Fld(6, 0) //[5:0] + #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 Fld(6, 6) //[11:6] + #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 Fld(5, 12) //[16:12] + #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 Fld(5, 17) //[21:17] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL4 (DRAMC_AO_BASE_ADDRESS + 0x121C) + #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 Fld(6, 0) //[5:0] + #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 Fld(6, 6) //[11:6] + #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 Fld(5, 12) //[16:12] + #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 Fld(5, 17) //[21:17] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL5 (DRAMC_AO_BASE_ADDRESS + 0x1220) + #define SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 Fld(11, 0) //[10:0] + #define SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 Fld(11, 16) //[26:16] + +#define DRAMC_REG_SHURK_PI (DRAMC_AO_BASE_ADDRESS + 0x1224) + #define SHURK_PI_RK0_ARPI_DQ_B1 Fld(6, 0) //[5:0] + #define SHURK_PI_RK0_ARPI_DQ_B0 Fld(6, 8) //[13:8] + #define SHURK_PI_RK0_ARPI_DQM_B1 Fld(6, 16) //[21:16] + #define SHURK_PI_RK0_ARPI_DQM_B0 Fld(6, 24) //[29:24] + +#define DRAMC_REG_SHURK_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x1228) + #define SHURK_DQSOSC_DQSOSC_BASE_RK0 Fld(16, 0) //[15:0] + #define SHURK_DQSOSC_DQSOSC_BASE_RK0_B1 Fld(16, 16) //[31:16] + +#define DRAMC_REG_SHURK_DQSOSC_THRD (DRAMC_AO_BASE_ADDRESS + 0x122C) + #define SHURK_DQSOSC_THRD_DQSOSCTHRD_INC Fld(12, 0) //[11:0] + #define SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC Fld(12, 16) //[27:16] + +#define DRAMC_REG_SHURK_APHY_TX_PICG_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1230) + #define SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 Fld(3, 0) //[2:0] + #define SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 Fld(3, 4) //[6:4] + +#define DRAMC_REG_SHURK_WCK_WR_MCK (DRAMC_AO_BASE_ADDRESS + 0x1240) + #define SHURK_WCK_WR_MCK_WCK_WR_B0_MCK Fld(4, 0) //[3:0] + #define SHURK_WCK_WR_MCK_WCK_WR_B1_MCK Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_RD_MCK (DRAMC_AO_BASE_ADDRESS + 0x1244) + #define SHURK_WCK_RD_MCK_WCK_RD_B0_MCK Fld(4, 0) //[3:0] + #define SHURK_WCK_RD_MCK_WCK_RD_B1_MCK Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_FS_MCK (DRAMC_AO_BASE_ADDRESS + 0x1248) + #define SHURK_WCK_FS_MCK_WCK_FS_B0_MCK Fld(4, 0) //[3:0] + #define SHURK_WCK_FS_MCK_WCK_FS_B1_MCK Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_WR_UI (DRAMC_AO_BASE_ADDRESS + 0x124C) + #define SHURK_WCK_WR_UI_WCK_WR_B0_UI Fld(4, 0) //[3:0] + #define SHURK_WCK_WR_UI_WCK_WR_B1_UI Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_RD_UI (DRAMC_AO_BASE_ADDRESS + 0x1250) + #define SHURK_WCK_RD_UI_WCK_RD_B0_UI Fld(4, 0) //[3:0] + #define SHURK_WCK_RD_UI_WCK_RD_B1_UI Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_FS_UI (DRAMC_AO_BASE_ADDRESS + 0x1254) + #define SHURK_WCK_FS_UI_WCK_FS_B0_UI Fld(4, 0) //[3:0] + #define SHURK_WCK_FS_UI_WCK_FS_B1_UI Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_CKE_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1260) + #define SHURK_CKE_CTRL_CKE_DBE_CNT Fld(4, 0) //[3:0] + +#define DRAMC_REG_SHU_MATYPE (DRAMC_AO_BASE_ADDRESS + 0x1600) + #define SHU_MATYPE_MATYPE Fld(2, 0) //[1:0] + #define SHU_MATYPE_NORMPOP_LEN Fld(3, 4) //[6:4] + +#define DRAMC_REG_SHU_COMMON0 (DRAMC_AO_BASE_ADDRESS + 0x1604) + #define SHU_COMMON0_FREQDIV4 Fld(1, 0) //[0:0] + #define SHU_COMMON0_FDIV2 Fld(1, 1) //[1:1] + #define SHU_COMMON0_FREQDIV8 Fld(1, 2) //[2:2] + #define SHU_COMMON0_DM64BITEN Fld(1, 4) //[4:4] + #define SHU_COMMON0_DLE256EN Fld(1, 5) //[5:5] + #define SHU_COMMON0_LP5BGEN Fld(1, 6) //[6:6] + #define SHU_COMMON0_LP5WCKON Fld(1, 7) //[7:7] + #define SHU_COMMON0_CL2 Fld(1, 8) //[8:8] + #define SHU_COMMON0_BL2 Fld(1, 9) //[9:9] + #define SHU_COMMON0_BL4 Fld(1, 10) //[10:10] + #define SHU_COMMON0_LP5BGOTF Fld(1, 11) //[11:11] + #define SHU_COMMON0_BC4OTF Fld(1, 12) //[12:12] + #define SHU_COMMON0_LP5HEFF_MODE Fld(1, 13) //[13:13] + #define SHU_COMMON0_LP5WRAPEN Fld(1, 14) //[14:14] + #define SHU_COMMON0_SHU_COMMON0_RSV Fld(17, 15) //[31:15] + +#define DRAMC_REG_SHU_SREF_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1608) + #define SHU_SREF_CTRL_CKEHCMD Fld(2, 4) //[5:4] + #define SHU_SREF_CTRL_SREF_CK_DLY Fld(2, 28) //[29:28] + +#define DRAMC_REG_SHU_SCHEDULER (DRAMC_AO_BASE_ADDRESS + 0x160C) + #define SHU_SCHEDULER_DUALSCHEN Fld(1, 2) //[2:2] + +#define DRAMC_REG_SHU_DCM_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x1610) + #define SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT Fld(1, 7) //[7:7] + #define SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT Fld(3, 8) //[10:8] + #define SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL Fld(4, 12) //[15:12] + #define SHU_DCM_CTRL0_APHYPI_CKCGL_CNT Fld(4, 16) //[19:16] + #define SHU_DCM_CTRL0_APHYPI_CKCGH_CNT Fld(4, 20) //[23:20] + #define SHU_DCM_CTRL0_FASTWAKE2 Fld(1, 29) //[29:29] + #define SHU_DCM_CTRL0_FASTWAKE Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_HMR4_DVFS_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x1614) + #define SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT Fld(8, 8) //[15:8] + #define SHU_HMR4_DVFS_CTRL0_REFRCNT Fld(12, 16) //[27:16] + +#define DRAMC_REG_SHU_SELPH_CA1 (DRAMC_AO_BASE_ADDRESS + 0x1618) + #define SHU_SELPH_CA1_TXDLY_CS Fld(3, 0) //[2:0] + #define SHU_SELPH_CA1_TXDLY_CKE Fld(3, 4) //[6:4] + #define SHU_SELPH_CA1_TXDLY_ODT Fld(3, 8) //[10:8] + #define SHU_SELPH_CA1_TXDLY_RESET Fld(3, 12) //[14:12] + #define SHU_SELPH_CA1_TXDLY_WE Fld(3, 16) //[18:16] + #define SHU_SELPH_CA1_TXDLY_CAS Fld(3, 20) //[22:20] + #define SHU_SELPH_CA1_TXDLY_RAS Fld(3, 24) //[26:24] + #define SHU_SELPH_CA1_TXDLY_CS1 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA2 (DRAMC_AO_BASE_ADDRESS + 0x161C) + #define SHU_SELPH_CA2_TXDLY_BA0 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA2_TXDLY_BA1 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA2_TXDLY_BA2 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA2_TXDLY_CMD Fld(5, 16) //[20:16] + #define SHU_SELPH_CA2_TXDLY_CKE1 Fld(3, 24) //[26:24] + +#define DRAMC_REG_SHU_SELPH_CA3 (DRAMC_AO_BASE_ADDRESS + 0x1620) + #define SHU_SELPH_CA3_TXDLY_RA0 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA3_TXDLY_RA1 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA3_TXDLY_RA2 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA3_TXDLY_RA3 Fld(3, 12) //[14:12] + #define SHU_SELPH_CA3_TXDLY_RA4 Fld(3, 16) //[18:16] + #define SHU_SELPH_CA3_TXDLY_RA5 Fld(3, 20) //[22:20] + #define SHU_SELPH_CA3_TXDLY_RA6 Fld(3, 24) //[26:24] + #define SHU_SELPH_CA3_TXDLY_RA7 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA4 (DRAMC_AO_BASE_ADDRESS + 0x1624) + #define SHU_SELPH_CA4_TXDLY_RA8 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA4_TXDLY_RA9 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA4_TXDLY_RA10 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA4_TXDLY_RA11 Fld(3, 12) //[14:12] + #define SHU_SELPH_CA4_TXDLY_RA12 Fld(3, 16) //[18:16] + #define SHU_SELPH_CA4_TXDLY_RA13 Fld(3, 20) //[22:20] + #define SHU_SELPH_CA4_TXDLY_RA14 Fld(3, 24) //[26:24] + #define SHU_SELPH_CA4_TXDLY_RA15 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA5 (DRAMC_AO_BASE_ADDRESS + 0x1628) + #define SHU_SELPH_CA5_DLY_CS Fld(3, 0) //[2:0] + #define SHU_SELPH_CA5_DLY_CKE Fld(3, 4) //[6:4] + #define SHU_SELPH_CA5_DLY_ODT Fld(3, 8) //[10:8] + #define SHU_SELPH_CA5_DLY_RESET Fld(3, 12) //[14:12] + #define SHU_SELPH_CA5_DLY_WE Fld(3, 16) //[18:16] + #define SHU_SELPH_CA5_DLY_CAS Fld(3, 20) //[22:20] + #define SHU_SELPH_CA5_DLY_RAS Fld(3, 24) //[26:24] + #define SHU_SELPH_CA5_DLY_CS1 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA6 (DRAMC_AO_BASE_ADDRESS + 0x162C) + #define SHU_SELPH_CA6_DLY_BA0 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA6_DLY_BA1 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA6_DLY_BA2 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA6_DLY_CKE1 Fld(3, 24) //[26:24] + +#define DRAMC_REG_SHU_SELPH_CA7 (DRAMC_AO_BASE_ADDRESS + 0x1630) + #define SHU_SELPH_CA7_DLY_RA0 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA7_DLY_RA1 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA7_DLY_RA2 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA7_DLY_RA3 Fld(3, 12) //[14:12] + #define SHU_SELPH_CA7_DLY_RA4 Fld(3, 16) //[18:16] + #define SHU_SELPH_CA7_DLY_RA5 Fld(3, 20) //[22:20] + #define SHU_SELPH_CA7_DLY_RA6 Fld(3, 24) //[26:24] + #define SHU_SELPH_CA7_DLY_RA7 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA8 (DRAMC_AO_BASE_ADDRESS + 0x1634) + #define SHU_SELPH_CA8_DLY_RA8 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA8_DLY_RA9 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA8_DLY_RA10 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA8_DLY_RA11 Fld(3, 12) //[14:12] + #define SHU_SELPH_CA8_DLY_RA12 Fld(3, 16) //[18:16] + #define SHU_SELPH_CA8_DLY_RA13 Fld(3, 20) //[22:20] + #define SHU_SELPH_CA8_DLY_RA14 Fld(3, 24) //[26:24] + #define SHU_SELPH_CA8_DLY_RA15 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_HWSET_MR2 (DRAMC_AO_BASE_ADDRESS + 0x1638) + #define SHU_HWSET_MR2_HWSET_MR2_MRSMA Fld(13, 0) //[12:0] + #define SHU_HWSET_MR2_HWSET_MR2_OP Fld(8, 16) //[23:16] + +#define DRAMC_REG_SHU_HWSET_MR13 (DRAMC_AO_BASE_ADDRESS + 0x163C) + #define SHU_HWSET_MR13_HWSET_MR13_MRSMA Fld(13, 0) //[12:0] + #define SHU_HWSET_MR13_HWSET_MR13_OP Fld(8, 16) //[23:16] + +#define DRAMC_REG_SHU_HWSET_VRCG (DRAMC_AO_BASE_ADDRESS + 0x1640) + #define SHU_HWSET_VRCG_HWSET_VRCG_MRSMA Fld(13, 0) //[12:0] + #define SHU_HWSET_VRCG_HWSET_VRCG_OP Fld(8, 16) //[23:16] + #define SHU_HWSET_VRCG_VRCGDIS_PRDCNT Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHU_ACTIM0 (DRAMC_AO_BASE_ADDRESS + 0x1644) + #define SHU_ACTIM0_TWTR Fld(6, 0) //[5:0] + #define SHU_ACTIM0_TWR Fld(8, 8) //[15:8] + #define SHU_ACTIM0_TRRD Fld(3, 16) //[18:16] + #define SHU_ACTIM0_TRCD Fld(4, 24) //[27:24] + #define SHU_ACTIM0_CKELCKCNT Fld(4, 28) //[31:28] + +#define DRAMC_REG_SHU_ACTIM1 (DRAMC_AO_BASE_ADDRESS + 0x1648) + #define SHU_ACTIM1_TRPAB Fld(4, 0) //[3:0] + #define SHU_ACTIM1_TMRWCKEL Fld(4, 4) //[7:4] + #define SHU_ACTIM1_TRP Fld(4, 8) //[11:8] + #define SHU_ACTIM1_TRAS Fld(6, 16) //[21:16] + #define SHU_ACTIM1_TRC Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHU_ACTIM2 (DRAMC_AO_BASE_ADDRESS + 0x164C) + #define SHU_ACTIM2_TXP Fld(4, 0) //[3:0] + #define SHU_ACTIM2_TMRRI Fld(5, 4) //[8:4] + #define SHU_ACTIM2_TRTP Fld(3, 12) //[14:12] + #define SHU_ACTIM2_TR2W Fld(6, 16) //[21:16] + #define SHU_ACTIM2_TFAW Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHU_ACTIM3 (DRAMC_AO_BASE_ADDRESS + 0x1650) + #define SHU_ACTIM3_TRFCPB Fld(8, 0) //[7:0] + #define SHU_ACTIM3_MANTMRR Fld(4, 8) //[11:8] + #define SHU_ACTIM3_TR2MRR Fld(4, 12) //[15:12] + #define SHU_ACTIM3_TRFC Fld(8, 16) //[23:16] + #define SHU_ACTIM3_TWTR_L Fld(6, 24) //[29:24] + +#define DRAMC_REG_SHU_ACTIM4 (DRAMC_AO_BASE_ADDRESS + 0x1654) + #define SHU_ACTIM4_TXREFCNT Fld(10, 0) //[9:0] + #define SHU_ACTIM4_TMRR2MRW Fld(6, 10) //[15:10] + #define SHU_ACTIM4_TMRR2W Fld(6, 16) //[21:16] + #define SHU_ACTIM4_TZQCS Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHU_ACTIM5 (DRAMC_AO_BASE_ADDRESS + 0x1658) + #define SHU_ACTIM5_TR2PD Fld(7, 0) //[6:0] + #define SHU_ACTIM5_TWTPD Fld(7, 8) //[14:8] + #define SHU_ACTIM5_TPBR2PBR Fld(8, 16) //[23:16] + #define SHU_ACTIM5_TPBR2ACT Fld(2, 28) //[29:28] + +#define DRAMC_REG_SHU_ACTIM6 (DRAMC_AO_BASE_ADDRESS + 0x165C) + #define SHU_ACTIM6_TZQLAT2 Fld(5, 0) //[4:0] + #define SHU_ACTIM6_TMRD Fld(4, 8) //[11:8] + #define SHU_ACTIM6_TMRW Fld(4, 12) //[15:12] + #define SHU_ACTIM6_TW2MRW Fld(6, 20) //[25:20] + #define SHU_ACTIM6_TR2MRW Fld(6, 26) //[31:26] + +#define DRAMC_REG_SHU_ACTIM_XRT (DRAMC_AO_BASE_ADDRESS + 0x1660) + #define SHU_ACTIM_XRT_XRTR2R Fld(5, 0) //[4:0] + #define SHU_ACTIM_XRT_XRTR2W Fld(6, 8) //[13:8] + #define SHU_ACTIM_XRT_XRTW2R Fld(4, 16) //[19:16] + #define SHU_ACTIM_XRT_XRTW2W Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHU_AC_TIME_05T (DRAMC_AO_BASE_ADDRESS + 0x1664) + #define SHU_AC_TIME_05T_TRC_05T Fld(1, 0) //[0:0] + #define SHU_AC_TIME_05T_TRFCPB_05T Fld(1, 1) //[1:1] + #define SHU_AC_TIME_05T_TRFC_05T Fld(1, 2) //[2:2] + #define SHU_AC_TIME_05T_TPBR2PBR_05T Fld(1, 3) //[3:3] + #define SHU_AC_TIME_05T_TXP_05T Fld(1, 4) //[4:4] + #define SHU_AC_TIME_05T_TRTP_05T Fld(1, 5) //[5:5] + #define SHU_AC_TIME_05T_TRCD_05T Fld(1, 6) //[6:6] + #define SHU_AC_TIME_05T_TRP_05T Fld(1, 7) //[7:7] + #define SHU_AC_TIME_05T_TRPAB_05T Fld(1, 8) //[8:8] + #define SHU_AC_TIME_05T_TRAS_05T Fld(1, 9) //[9:9] + #define SHU_AC_TIME_05T_TWR_M05T Fld(1, 10) //[10:10] + #define SHU_AC_TIME_05T_TRRD_05T Fld(1, 12) //[12:12] + #define SHU_AC_TIME_05T_TFAW_05T Fld(1, 13) //[13:13] + #define SHU_AC_TIME_05T_TCKEPRD_05T Fld(1, 14) //[14:14] + #define SHU_AC_TIME_05T_TR2PD_05T Fld(1, 15) //[15:15] + #define SHU_AC_TIME_05T_TWTPD_M05T Fld(1, 16) //[16:16] + #define SHU_AC_TIME_05T_TMRRI_05T Fld(1, 17) //[17:17] + #define SHU_AC_TIME_05T_TMRWCKEL_05T Fld(1, 18) //[18:18] + #define SHU_AC_TIME_05T_BGTRRD_05T Fld(1, 19) //[19:19] + #define SHU_AC_TIME_05T_BGTCCD_05T Fld(1, 20) //[20:20] + #define SHU_AC_TIME_05T_BGTWTR_M05T Fld(1, 21) //[21:21] + #define SHU_AC_TIME_05T_TR2W_05T Fld(1, 22) //[22:22] + #define SHU_AC_TIME_05T_TWTR_M05T Fld(1, 23) //[23:23] + #define SHU_AC_TIME_05T_XRTR2W_05T Fld(1, 24) //[24:24] + #define SHU_AC_TIME_05T_TMRD_05T Fld(1, 25) //[25:25] + #define SHU_AC_TIME_05T_TMRW_05T Fld(1, 26) //[26:26] + #define SHU_AC_TIME_05T_TMRR2MRW_05T Fld(1, 27) //[27:27] + #define SHU_AC_TIME_05T_TW2MRW_05T Fld(1, 28) //[28:28] + #define SHU_AC_TIME_05T_TR2MRW_05T Fld(1, 29) //[29:29] + #define SHU_AC_TIME_05T_TPBR2ACT_05T Fld(1, 30) //[30:30] + #define SHU_AC_TIME_05T_XRTW2R_M05T Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_AC_DERATING0 (DRAMC_AO_BASE_ADDRESS + 0x1668) + #define SHU_AC_DERATING0_ACDERATEEN Fld(1, 0) //[0:0] + #define SHU_AC_DERATING0_TRRD_DERATE Fld(3, 16) //[18:16] + #define SHU_AC_DERATING0_TRCD_DERATE Fld(4, 24) //[27:24] + +#define DRAMC_REG_SHU_AC_DERATING1 (DRAMC_AO_BASE_ADDRESS + 0x166C) + #define SHU_AC_DERATING1_TRPAB_DERATE Fld(4, 0) //[3:0] + #define SHU_AC_DERATING1_TRP_DERATE Fld(4, 8) //[11:8] + #define SHU_AC_DERATING1_TRAS_DERATE Fld(6, 16) //[21:16] + #define SHU_AC_DERATING1_TRC_DERATE Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHU_AC_DERATING_05T (DRAMC_AO_BASE_ADDRESS + 0x1670) + #define SHU_AC_DERATING_05T_TRC_05T_DERATE Fld(1, 0) //[0:0] + #define SHU_AC_DERATING_05T_TRCD_05T_DERATE Fld(1, 6) //[6:6] + #define SHU_AC_DERATING_05T_TRP_05T_DERATE Fld(1, 7) //[7:7] + #define SHU_AC_DERATING_05T_TRPAB_05T_DERATE Fld(1, 8) //[8:8] + #define SHU_AC_DERATING_05T_TRAS_05T_DERATE Fld(1, 9) //[9:9] + #define SHU_AC_DERATING_05T_TRRD_05T_DERATE Fld(1, 12) //[12:12] + +#define DRAMC_REG_SHU_ACTIMING_CONF (DRAMC_AO_BASE_ADDRESS + 0x1674) + #define SHU_ACTIMING_CONF_SCINTV Fld(6, 0) //[5:0] + #define SHU_ACTIMING_CONF_TRFCPBIG Fld(1, 8) //[8:8] + #define SHU_ACTIMING_CONF_REFBW_FR Fld(10, 16) //[25:16] + #define SHU_ACTIMING_CONF_TREFBWIG Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0x1678) + #define SHU_CKECTRL_TPDE_05T Fld(1, 0) //[0:0] + #define SHU_CKECTRL_TPDX_05T Fld(1, 1) //[1:1] + #define SHU_CKECTRL_TPDE Fld(3, 12) //[14:12] + #define SHU_CKECTRL_TPDX Fld(3, 16) //[18:16] + #define SHU_CKECTRL_TCKEPRD Fld(3, 20) //[22:20] + #define SHU_CKECTRL_TCKESRX Fld(2, 24) //[25:24] + +#define DRAMC_REG_SHU_SELPH_DQS0 (DRAMC_AO_BASE_ADDRESS + 0x167C) + #define SHU_SELPH_DQS0_TXDLY_DQS0 Fld(3, 0) //[2:0] + #define SHU_SELPH_DQS0_TXDLY_DQS1 Fld(3, 4) //[6:4] + #define SHU_SELPH_DQS0_TXDLY_DQS2 Fld(3, 8) //[10:8] + #define SHU_SELPH_DQS0_TXDLY_DQS3 Fld(3, 12) //[14:12] + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS0 Fld(3, 16) //[18:16] + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS1 Fld(3, 20) //[22:20] + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS2 Fld(3, 24) //[26:24] + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS3 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_DQS1 (DRAMC_AO_BASE_ADDRESS + 0x1680) + #define SHU_SELPH_DQS1_DLY_DQS0 Fld(4, 0) //[3:0] + #define SHU_SELPH_DQS1_DLY_DQS1 Fld(4, 4) //[7:4] + #define SHU_SELPH_DQS1_DLY_DQS2 Fld(4, 8) //[11:8] + #define SHU_SELPH_DQS1_DLY_DQS3 Fld(4, 12) //[15:12] + #define SHU_SELPH_DQS1_DLY_OEN_DQS0 Fld(4, 16) //[19:16] + #define SHU_SELPH_DQS1_DLY_OEN_DQS1 Fld(4, 20) //[23:20] + #define SHU_SELPH_DQS1_DLY_OEN_DQS2 Fld(4, 24) //[27:24] + #define SHU_SELPH_DQS1_DLY_OEN_DQS3 Fld(4, 28) //[31:28] + +#define DRAMC_REG_SHU_WODT (DRAMC_AO_BASE_ADDRESS + 0x1684) + #define SHU_WODT_DISWODT Fld(3, 0) //[2:0] + #define SHU_WODT_WODTFIX Fld(1, 3) //[3:3] + #define SHU_WODT_WODTFIXOFF Fld(1, 4) //[4:4] + #define SHU_WODT_DISWODTE Fld(1, 5) //[5:5] + #define SHU_WODT_DISWODTE2 Fld(1, 6) //[6:6] + #define SHU_WODT_WODTPDEN Fld(1, 7) //[7:7] + #define SHU_WODT_WOEN Fld(1, 8) //[8:8] + #define SHU_WODT_DQS2DQ_WARN_PITHRD Fld(6, 9) //[14:9] + #define SHU_WODT_TWODT Fld(7, 16) //[22:16] + +#define DRAMC_REG_SHU_TX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x1688) + #define SHU_TX_SET0_DQOE_CNT Fld(4, 0) //[3:0] + #define SHU_TX_SET0_DQOE_OPT Fld(1, 4) //[4:4] + #define SHU_TX_SET0_WR_NEW_OPT Fld(1, 5) //[5:5] + #define SHU_TX_SET0_TXUPD_SEL Fld(2, 6) //[7:6] + #define SHU_TX_SET0_TXUPD_W2R_SEL Fld(3, 8) //[10:8] + #define SHU_TX_SET0_WECC_EN Fld(1, 11) //[11:11] + #define SHU_TX_SET0_DBIWR Fld(1, 12) //[12:12] + #define SHU_TX_SET0_WDATRGO Fld(1, 13) //[13:13] + #define SHU_TX_SET0_TXUPD_W2R_OPT Fld(1, 14) //[14:14] + #define SHU_TX_SET0_WPST1P5T Fld(1, 15) //[15:15] + #define SHU_TX_SET0_TXOEN_AUTOSET_OFFSET Fld(4, 16) //[19:16] + #define SHU_TX_SET0_TWCKPST Fld(2, 20) //[21:20] + #define SHU_TX_SET0_OE_EXT2UI Fld(3, 22) //[24:22] + #define SHU_TX_SET0_DQS2DQ_FILT_PITHRD Fld(6, 25) //[30:25] + #define SHU_TX_SET0_TXOEN_AUTOSET_EN Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_RX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x168C) + #define SHU_RX_CG_SET0_DLE_LAST_EXTEND3 Fld(1, 0) //[0:0] + #define SHU_RX_CG_SET0_READ_START_EXTEND3 Fld(1, 1) //[1:1] + #define SHU_RX_CG_SET0_DLE_LAST_EXTEND2 Fld(1, 2) //[2:2] + #define SHU_RX_CG_SET0_READ_START_EXTEND2 Fld(1, 3) //[3:3] + #define SHU_RX_CG_SET0_DLE_LAST_EXTEND1 Fld(1, 4) //[4:4] + #define SHU_RX_CG_SET0_READ_START_EXTEND1 Fld(1, 5) //[5:5] + +#define DRAMC_REG_SHU_DQSOSC_SET0 (DRAMC_AO_BASE_ADDRESS + 0x1690) + #define SHU_DQSOSC_SET0_DQSOSCENDIS Fld(1, 0) //[0:0] + #define SHU_DQSOSC_SET0_DQSOSC_PRDCNT Fld(10, 4) //[13:4] + #define SHU_DQSOSC_SET0_DQSOSCENCNT Fld(16, 16) //[31:16] + +#define DRAMC_REG_SHU_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0x1694) + #define SHU_DQSOSCR_DQSOSCRCNT Fld(8, 0) //[7:0] + #define SHU_DQSOSCR_DQSOSC_ADV_SEL Fld(2, 8) //[9:8] + #define SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL Fld(2, 10) //[11:10] + #define SHU_DQSOSCR_TX_SW_FORCE_UPD_SEL Fld(3, 12) //[14:12] + #define SHU_DQSOSCR_DQSOSC_DELTA Fld(16, 16) //[31:16] + +#define DRAMC_REG_SHU_TX_RANKCTL (DRAMC_AO_BASE_ADDRESS + 0x1698) + #define SHU_TX_RANKCTL_TXRANKINCTL_TXDLY Fld(4, 0) //[3:0] + #define SHU_TX_RANKCTL_TXRANKINCTL Fld(4, 4) //[7:4] + #define SHU_TX_RANKCTL_TXRANKINCTL_ROOT Fld(4, 8) //[11:8] + +#define DRAMC_REG_SHU_ZQ_SET0 (DRAMC_AO_BASE_ADDRESS + 0x169C) + #define SHU_ZQ_SET0_ZQCSCNT Fld(16, 0) //[15:0] + #define SHU_ZQ_SET0_TZQLAT Fld(5, 27) //[31:27] + +#define DRAMC_REG_SHU_CONF0 (DRAMC_AO_BASE_ADDRESS + 0x16A0) + #define SHU_CONF0_DMPGTIM Fld(7, 0) //[6:0] + #define SHU_CONF0_ADVPREEN Fld(1, 7) //[7:7] + #define SHU_CONF0_PBREFEN Fld(1, 8) //[8:8] + #define SHU_CONF0_REFTHD Fld(4, 12) //[15:12] + #define SHU_CONF0_REQQUE_DEPTH Fld(4, 16) //[19:16] + #define SHU_CONF0_ADVREFEN Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_MISC (DRAMC_AO_BASE_ADDRESS + 0x16A4) + #define SHU_MISC_REQQUE_MAXCNT Fld(4, 0) //[3:0] + #define SHU_MISC_DCMDLYREF Fld(3, 16) //[18:16] + #define SHU_MISC_DAREFEN Fld(1, 30) //[30:30] + +#define DRAMC_REG_SHU_NEW_XRW2W_CTRL (DRAMC_AO_BASE_ADDRESS + 0x16A8) + #define SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0 Fld(3, 16) //[18:16] + #define SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1 Fld(3, 24) //[26:24] + #define SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_APHY_TX_PICG_CTRL (DRAMC_AO_BASE_ADDRESS + 0x16AC) + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT Fld(4, 0) //[3:0] + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 Fld(3, 4) //[6:4] + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 Fld(3, 8) //[10:8] + #define SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT Fld(4, 12) //[15:12] + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_FREQ_RATIO_SET0 (DRAMC_AO_BASE_ADDRESS + 0x16B0) + #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3 Fld(8, 0) //[7:0] + #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2 Fld(8, 8) //[15:8] + #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1 Fld(8, 16) //[23:16] + #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0 Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHU_FREQ_RATIO_SET1 (DRAMC_AO_BASE_ADDRESS + 0x16B4) + #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7 Fld(8, 0) //[7:0] + #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6 Fld(8, 8) //[15:8] + #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5 Fld(8, 16) //[23:16] + #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4 Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHU_FREQ_RATIO_SET2 (DRAMC_AO_BASE_ADDRESS + 0x16B8) + #define SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9 Fld(8, 16) //[23:16] + #define SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8 Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHUREG_RSV (DRAMC_AO_BASE_ADDRESS + 0x16BC) + #define SHUREG_RSV_SHUREG_RSV Fld(32, 0) //[31:0] + +#define DRAMC_REG_SHU_WCKCTRL (DRAMC_AO_BASE_ADDRESS + 0x16C0) + #define SHU_WCKCTRL_WCKRDOFF Fld(6, 0) //[5:0] + #define SHU_WCKCTRL_WCKRDOFF_05T Fld(1, 7) //[7:7] + #define SHU_WCKCTRL_WCKWROFF Fld(6, 8) //[13:8] + #define SHU_WCKCTRL_WCKWROFF_05T Fld(1, 15) //[15:15] + #define SHU_WCKCTRL_WCKDUAL Fld(1, 16) //[16:16] + +#define DRAMC_REG_SHU_WCKCTRL_1 (DRAMC_AO_BASE_ADDRESS + 0x16C4) + #define SHU_WCKCTRL_1_WCKSYNC_PRE_MODE Fld(1, 0) //[0:0] + +#define DRAMC_REG_SHU_RX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x16D0) + #define SHU_RX_SET0_RECC_EN Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_REF0 (DRAMC_AO_BASE_ADDRESS + 0x16D4) + #define SHU_REF0_MPENDREF_CNT Fld(3, 0) //[2:0] + +#define DRAMC_REG_SHU_LP5_CMD (DRAMC_AO_BASE_ADDRESS + 0x16E0) + #define SHU_LP5_CMD_LP5_CMD1TO2EN Fld(1, 0) //[0:0] + #define SHU_LP5_CMD_TCSH Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHU_LP5_SACT (DRAMC_AO_BASE_ADDRESS + 0x16E4) + #define SHU_LP5_SACT_LP5_SEPARATE_ACT Fld(1, 0) //[0:0] + +#define DRAMC_REG_SHU_ACTIM7 (DRAMC_AO_BASE_ADDRESS + 0x16E8) + #define SHU_ACTIM7_TCSH_CSCAL Fld(4, 0) //[3:0] + #define SHU_ACTIM7_TCACSH Fld(4, 4) //[7:4] + +#endif // __DRAMC_AO_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h new file mode 100644 index 0000000000..f3a1342ab3 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h @@ -0,0 +1,1081 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_NAO_REGS_H__ +#define __DRAMC_NAO_REGS_H__ + +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10234000 +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x10244000 + +#define DRAMC_NAO_BASE_ADDRESS Channel_A_DRAMC_NAO_BASE_VIRTUAL + +#define DRAMC_REG_TESTMODE (DRAMC_NAO_BASE_ADDRESS + 0x0000) + #define TESTMODE_TESTM_PAT0 Fld(8, 24) //[31:24] + +#define DRAMC_REG_RDQC_CMP (DRAMC_NAO_BASE_ADDRESS + 0x0014) + #define RDQC_CMP_RDDQC_CMP0_ERR Fld(16, 0) //[15:0] + #define RDQC_CMP_RDDQC_CMP1_ERR Fld(16, 16) //[31:16] + +#define DRAMC_REG_RDQC_DQM_CMP (DRAMC_NAO_BASE_ADDRESS + 0x0018) + #define RDQC_DQM_CMP_RDDQC_DQM_CMP0_ERR Fld(2, 0) //[1:0] + #define RDQC_DQM_CMP_RDDQC_DQM_CMP1_ERR Fld(2, 2) //[3:2] + +#define DRAMC_REG_DMMONITOR (DRAMC_NAO_BASE_ADDRESS + 0x0024) + #define DMMONITOR_MONPAUSE_SW Fld(1, 2) //[2:2] + #define DMMONITOR_BUSMONEN_SW Fld(1, 3) //[3:3] + #define DMMONITOR_WDQ_MON_OPT Fld(1, 4) //[4:4] + #define DMMONITOR_REQQUE_MON_SREF_DIS Fld(1, 8) //[8:8] + #define DMMONITOR_REQQUE_MON_SREF_REOR Fld(1, 9) //[9:9] + #define DMMONITOR_REQQUE_MON_SREF_LLAT Fld(1, 10) //[10:10] + #define DMMONITOR_REQQUE_MON_SREF_HPRI Fld(1, 11) //[11:11] + #define DMMONITOR_REQQUE_MON_SREF_RW Fld(1, 12) //[12:12] + #define DMMONITOR_EBG_PGHIT_COUNTER_CLR Fld(1, 16) //[16:16] + +#define DRAMC_REG_INITK_PAT0 (DRAMC_NAO_BASE_ADDRESS + 0x0030) + #define INITK_PAT0_INITK_PAT0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_INITK_PAT1 (DRAMC_NAO_BASE_ADDRESS + 0x0034) + #define INITK_PAT1_INITK_PAT1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_INITK_PAT2 (DRAMC_NAO_BASE_ADDRESS + 0x0038) + #define INITK_PAT2_INITK_PAT2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_INITK_PAT3 (DRAMC_NAO_BASE_ADDRESS + 0x003C) + #define INITK_PAT3_INITK_PAT3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_INITK_PAT4 (DRAMC_NAO_BASE_ADDRESS + 0x0040) + #define INITK_PAT4_INITK_PAT4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SPCMDRESP3 (DRAMC_NAO_BASE_ADDRESS + 0x0050) + #define SPCMDRESP3_RTSWCMD_RESPONSE Fld(1, 0) //[0:0] + #define SPCMDRESP3_ZQC_SWTRIG_RESPONSE Fld(1, 1) //[1:1] + #define SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE Fld(1, 2) //[2:2] + #define SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE Fld(1, 3) //[3:3] + #define SPCMDRESP3_WCK2DQO_START_SWTRIG_RESPONSE Fld(1, 4) //[4:4] + #define SPCMDRESP3_DVFS_RTMRW_RESPONSE Fld(1, 5) //[5:5] + +#define DRAMC_REG_CBT_WLEV_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x0054) + #define CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT Fld(1, 0) //[0:0] + #define CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B0 Fld(7, 1) //[7:1] + #define CBT_WLEV_STATUS2_CBT_PAT_RDAT_B0 Fld(7, 8) //[14:8] + #define CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B1 Fld(7, 15) //[21:15] + #define CBT_WLEV_STATUS2_CBT_PAT_RDAT_B1 Fld(7, 22) //[28:22] + +#define DRAMC_REG_MISC_STATUSA (DRAMC_NAO_BASE_ADDRESS + 0x0080) + #define MISC_STATUSA_WAIT_DLE Fld(1, 0) //[0:0] + #define MISC_STATUSA_WRITE_DATA_BUFFER_EMPTY Fld(1, 1) //[1:1] + #define MISC_STATUSA_REQQ_EMPTY Fld(1, 2) //[2:2] + #define MISC_STATUSA_PG_VLD Fld(1, 3) //[3:3] + #define MISC_STATUSA_REQQUE_DEPTH Fld(4, 4) //[7:4] + #define MISC_STATUSA_REFRESH_RATE Fld(5, 8) //[12:8] + #define MISC_STATUSA_CKEO_PRE Fld(1, 13) //[13:13] + #define MISC_STATUSA_CKE1O_PRE Fld(1, 14) //[14:14] + #define MISC_STATUSA_SREF_STATE Fld(1, 16) //[16:16] + #define MISC_STATUSA_SELFREF_SM Fld(3, 17) //[19:17] + #define MISC_STATUSA_REFRESH_OVER_CNT Fld(4, 20) //[23:20] + #define MISC_STATUSA_REFRESH_QUEUE_CNT Fld(4, 24) //[27:24] + #define MISC_STATUSA_REQDEPTH_UPD_DONE Fld(1, 28) //[28:28] + #define MISC_STATUSA_DRAMC_IDLE_STATUS Fld(1, 30) //[30:30] + #define MISC_STATUSA_DRAMC_IDLE_DCM Fld(1, 31) //[31:31] + +#define DRAMC_REG_SPECIAL_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0084) + #define SPECIAL_STATUS_SPECIAL_COMMAND_ENABLE Fld(1, 0) //[0:0] + #define SPECIAL_STATUS_H_ZQLAT_REQ Fld(1, 1) //[1:1] + #define SPECIAL_STATUS_H_ZQLCAL_REQ Fld(1, 2) //[2:2] + #define SPECIAL_STATUS_TX_RETRY_PERIOD Fld(1, 3) //[3:3] + #define SPECIAL_STATUS_H_DQSOSCEN_REQ Fld(1, 4) //[4:4] + #define SPECIAL_STATUS_DQSOSCEN_PERIOD Fld(1, 5) //[5:5] + #define SPECIAL_STATUS_H_ZQCS_REQ Fld(1, 6) //[6:6] + #define SPECIAL_STATUS_H_REFR_REQ Fld(1, 7) //[7:7] + #define SPECIAL_STATUS_HW_ZQLAT_REQ Fld(1, 9) //[9:9] + #define SPECIAL_STATUS_HW_ZQCAL_REQ Fld(1, 10) //[10:10] + #define SPECIAL_STATUS_SPECIAL_STATUS Fld(1, 11) //[11:11] + #define SPECIAL_STATUS_SCSM Fld(5, 12) //[16:12] + #define SPECIAL_STATUS_XSR_TX_RETRY_SM Fld(3, 17) //[19:17] + #define SPECIAL_STATUS_SCARB_SM Fld(5, 20) //[24:20] + #define SPECIAL_STATUS_TX_RETRY_PERIOD_WO_RX_RETRY Fld(1, 25) //[25:25] + #define SPECIAL_STATUS_DSM_REQ_2Q Fld(1, 26) //[26:26] + #define SPECIAL_STATUS_DSM_REQ Fld(1, 27) //[27:27] + #define SPECIAL_STATUS_SC_DRAMC_QUEUE_ACK Fld(1, 28) //[28:28] + #define SPECIAL_STATUS_SREF_REQ_2Q Fld(1, 30) //[30:30] + #define SPECIAL_STATUS_SREF_REQ Fld(1, 31) //[31:31] + +#define DRAMC_REG_SPCMDRESP (DRAMC_NAO_BASE_ADDRESS + 0x0088) + #define SPCMDRESP_MRW_RESPONSE Fld(1, 0) //[0:0] + #define SPCMDRESP_MRR_RESPONSE Fld(1, 1) //[1:1] + #define SPCMDRESP_PREA_RESPONSE Fld(1, 2) //[2:2] + #define SPCMDRESP_AREF_RESPONSE Fld(1, 3) //[3:3] + #define SPCMDRESP_ZQC_RESPONSE Fld(1, 4) //[4:4] + #define SPCMDRESP_TCMD_RESPONSE Fld(1, 5) //[5:5] + #define SPCMDRESP_ZQLAT_RESPONSE Fld(1, 6) //[6:6] + #define SPCMDRESP_RDDQC_RESPONSE Fld(1, 7) //[7:7] + #define SPCMDRESP_STEST_RESPONSE Fld(1, 8) //[8:8] + #define SPCMDRESP_MPCMAN_RESPONSE Fld(1, 9) //[9:9] + #define SPCMDRESP_DQSOSCEN_RESPONSE Fld(1, 10) //[10:10] + #define SPCMDRESP_DQSOSCDIS_RESPONSE Fld(1, 11) //[11:11] + #define SPCMDRESP_ACT_RESPONSE Fld(1, 12) //[12:12] + #define SPCMDRESP_MPRW_RESPONSE Fld(1, 13) //[13:13] + #define SPCMDRESP_TX_RETRY_DONE_RESPONSE Fld(1, 15) //[15:15] + #define SPCMDRESP_DVFS_RESPONSE Fld(1, 16) //[16:16] + #define SPCMDRESP_HW_ZQLAT_POP Fld(1, 17) //[17:17] + #define SPCMDRESP_HW_ZQCAL_POP Fld(1, 18) //[18:18] + #define SPCMDRESP_RTMRW_RESPONSE Fld(1, 19) //[19:19] + #define SPCMDRESP_RTMRW_REQ_CNT Fld(3, 20) //[22:20] + #define SPCMDRESP_RTMRW_ACK_CNT Fld(3, 23) //[25:23] + #define SPCMDRESP_RTMRW_POP_CNT Fld(3, 26) //[28:26] + #define SPCMDRESP_RDFIFO_RESPONSE Fld(1, 30) //[30:30] + #define SPCMDRESP_WRFIFO_RESPONSE Fld(1, 31) //[31:31] + +#define DRAMC_REG_MRR_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x008C) + #define MRR_STATUS_MRR_REG Fld(16, 0) //[15:0] + #define MRR_STATUS_MRR_SW_REG Fld(16, 16) //[31:16] + +#define DRAMC_REG_MRR_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x0090) + #define MRR_STATUS2_MR4_REG Fld(16, 0) //[15:0] + #define MRR_STATUS2_SHUFFLE_MRW_VRCG_NORMAL_OK Fld(1, 16) //[16:16] + #define MRR_STATUS2_TFC_OK Fld(1, 17) //[17:17] + #define MRR_STATUS2_TCKFSPX_OK Fld(1, 18) //[18:18] + #define MRR_STATUS2_TVRCG_EN_OK Fld(1, 19) //[19:19] + #define MRR_STATUS2_TCKFSPE_OK Fld(1, 20) //[20:20] + #define MRR_STATUS2_TVRCG_DIS_OK Fld(1, 21) //[21:21] + #define MRR_STATUS2_PHY_SHUFFLE_PERIOD_GO_ZERO_OK Fld(1, 22) //[22:22] + #define MRR_STATUS2_DVFS_STATE Fld(8, 24) //[31:24] + +#define DRAMC_REG_MRRDATA0 (DRAMC_NAO_BASE_ADDRESS + 0x0094) + #define MRRDATA0_MRR_DATA0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_MRRDATA1 (DRAMC_NAO_BASE_ADDRESS + 0x0098) + #define MRRDATA1_MRR_DATA1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_MRRDATA2 (DRAMC_NAO_BASE_ADDRESS + 0x009C) + #define MRRDATA2_MRR_DATA2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_MRRDATA3 (DRAMC_NAO_BASE_ADDRESS + 0x00A0) + #define MRRDATA3_MRR_DATA3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_REF_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x00A4) + #define REF_STATUS_REFRATE_INT_TRIGGER1 Fld(1, 0) //[0:0] + #define REF_STATUS_REFRATE_INT_TRIGGER2 Fld(1, 1) //[1:1] + #define REF_STATUS_PRE_REFRATE_INT_TRIGGER1 Fld(1, 2) //[2:2] + #define REF_STATUS_REFPENDING_INT_TRIGGER_1 Fld(1, 3) //[3:3] + #define REF_STATUS_REFPENDING_INT_TRIGGER_2 Fld(1, 4) //[4:4] + +#define DRAMC_REG_WCK_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x00B0) + #define WCK_STATUS_WCKEN_RK0_SM Fld(2, 0) //[1:0] + #define WCK_STATUS_WCKEN_RK1_SM Fld(2, 2) //[3:2] + +#define DRAMC_REG_TCMDO1LAT (DRAMC_NAO_BASE_ADDRESS + 0x00C0) + #define TCMDO1LAT_MANUTXUPD_B0_DONE Fld(1, 6) //[6:6] + #define TCMDO1LAT_MANUTXUPD_B1_DONE Fld(1, 7) //[7:7] + +#define DRAMC_REG_CBT_WLEV_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x00C4) + #define CBT_WLEV_STATUS1_CATRAIN_CMP_CPT Fld(1, 0) //[0:0] + #define CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B0 Fld(7, 1) //[7:1] + #define CBT_WLEV_STATUS1_CATRAIN_RDAT_B0 Fld(7, 8) //[14:8] + #define CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B1 Fld(7, 15) //[21:15] + #define CBT_WLEV_STATUS1_CATRAIN_RDAT_B1 Fld(7, 22) //[28:22] + +#define DRAMC_REG_CBT_WLEV_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x00C8) + #define CBT_WLEV_STATUS_WLEV_CMP_CPT Fld(1, 0) //[0:0] + #define CBT_WLEV_STATUS_WLEV_CMP_ERR Fld(2, 1) //[2:1] + #define CBT_WLEV_STATUS_TCMD_CMP_ERR_B0 Fld(1, 3) //[3:3] + #define CBT_WLEV_STATUS_TCMD_CMP_ERR_B1 Fld(1, 4) //[4:4] + #define CBT_WLEV_STATUS_TCMD_O1_LATCH_DATA_B0 Fld(7, 5) //[11:5] + #define CBT_WLEV_STATUS_TCMD_O1_LATCH_DATA_B1 Fld(7, 12) //[18:12] + #define CBT_WLEV_STATUS_CBT_WLEV_ATK_CNT Fld(6, 19) //[24:19] + #define CBT_WLEV_STATUS_CBT_WLEV_ATK_RESPONSE Fld(1, 25) //[25:25] + +#define DRAMC_REG_SPCMDRESP2 (DRAMC_NAO_BASE_ADDRESS + 0x00CC) + #define SPCMDRESP2_RTMRW_ABNORMAL_STOP Fld(1, 0) //[0:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT0 (DRAMC_NAO_BASE_ADDRESS + 0x00D0) + #define CBT_WLEV_ATK_RESULT0_CBT_WLEV_ATK_CMP_ERR0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT1 (DRAMC_NAO_BASE_ADDRESS + 0x00D4) + #define CBT_WLEV_ATK_RESULT1_CBT_WLEV_ATK_CMP_ERR1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT2 (DRAMC_NAO_BASE_ADDRESS + 0x00D8) + #define CBT_WLEV_ATK_RESULT2_CBT_WLEV_ATK_CMP_ERR2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT3 (DRAMC_NAO_BASE_ADDRESS + 0x00DC) + #define CBT_WLEV_ATK_RESULT3_CBT_WLEV_ATK_CMP_ERR3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT4 (DRAMC_NAO_BASE_ADDRESS + 0x00E0) + #define CBT_WLEV_ATK_RESULT4_CBT_WLEV_ATK_CMP_ERR4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT5 (DRAMC_NAO_BASE_ADDRESS + 0x00E4) + #define CBT_WLEV_ATK_RESULT5_CBT_WLEV_ATK_CMP_ERR5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT6 (DRAMC_NAO_BASE_ADDRESS + 0x00E8) + #define CBT_WLEV_ATK_RESULT6_CBT_WLEV_ATK_CMP_ERR6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT7 (DRAMC_NAO_BASE_ADDRESS + 0x00EC) + #define CBT_WLEV_ATK_RESULT7_CBT_WLEV_ATK_CMP_ERR7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT8 (DRAMC_NAO_BASE_ADDRESS + 0x00F0) + #define CBT_WLEV_ATK_RESULT8_CBT_WLEV_ATK_CMP_ERR8 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT9 (DRAMC_NAO_BASE_ADDRESS + 0x00F4) + #define CBT_WLEV_ATK_RESULT9_CBT_WLEV_ATK_CMP_ERR9 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT10 (DRAMC_NAO_BASE_ADDRESS + 0x00F8) + #define CBT_WLEV_ATK_RESULT10_CBT_WLEV_ATK_CMP_ERR10 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT11 (DRAMC_NAO_BASE_ADDRESS + 0x00FC) + #define CBT_WLEV_ATK_RESULT11_CBT_WLEV_ATK_CMP_ERR11 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT12 (DRAMC_NAO_BASE_ADDRESS + 0x0100) + #define CBT_WLEV_ATK_RESULT12_CBT_WLEV_ATK_CMP_ERR12 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT13 (DRAMC_NAO_BASE_ADDRESS + 0x0104) + #define CBT_WLEV_ATK_RESULT13_CBT_WLEV_ATK_CMP_ERR13 Fld(32, 0) //[31:0] + +#define DRAMC_REG_HWMRR_PUSH2POP_CNT (DRAMC_NAO_BASE_ADDRESS + 0x010C) + #define HWMRR_PUSH2POP_CNT_HWMRR_PUSH2POP_CNT Fld(32, 0) //[31:0] + +#define DRAMC_REG_HWMRR_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0110) + #define HWMRR_STATUS_OV_P2P_CNT Fld(8, 0) //[7:0] + #define HWMRR_STATUS_MRR_CNT_UNDER_FULL Fld(1, 30) //[30:30] + #define HWMRR_STATUS_MRR_CNT_OVER_FULL Fld(1, 31) //[31:31] + +#define DRAMC_REG_HW_REFRATE_MON (DRAMC_NAO_BASE_ADDRESS + 0x0114) + #define HW_REFRATE_MON_REFRESH_RATE_MIN_MON Fld(5, 0) //[4:0] + #define HW_REFRATE_MON_REFRESH_RATE_MAX_MON Fld(5, 8) //[12:8] + +#define DRAMC_REG_HW_REFRATE_MON2 (DRAMC_NAO_BASE_ADDRESS + 0x0118) + #define HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK1_B1 Fld(5, 0) //[4:0] + #define HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK1_B1 Fld(5, 8) //[12:8] + #define HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK0_B1 Fld(5, 16) //[20:16] + #define HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK0_B1 Fld(5, 24) //[28:24] + +#define DRAMC_REG_HW_REFRATE_MON3 (DRAMC_NAO_BASE_ADDRESS + 0x011C) + #define HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK1_B0 Fld(5, 0) //[4:0] + #define HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK1_B0 Fld(5, 8) //[12:8] + #define HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK0_B0 Fld(5, 16) //[20:16] + #define HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK0_B0 Fld(5, 24) //[28:24] + +#define DRAMC_REG_TESTRPT (DRAMC_NAO_BASE_ADDRESS + 0x0120) + #define TESTRPT_DM_CMP_CPT_RK0 Fld(1, 0) //[0:0] + #define TESTRPT_DM_CMP_CPT_RK1 Fld(1, 1) //[1:1] + #define TESTRPT_DM_CMP_ERR_RK0 Fld(1, 4) //[4:4] + #define TESTRPT_DM_CMP_ERR_RK1 Fld(1, 5) //[5:5] + #define TESTRPT_DLE_CNT_OK_RK0 Fld(1, 8) //[8:8] + #define TESTRPT_DLE_CNT_OK_RK1 Fld(1, 9) //[9:9] + #define TESTRPT_LPBK_CMP_ERR Fld(1, 12) //[12:12] + #define TESTRPT_TESTSTAT Fld(3, 20) //[22:20] + +#define DRAMC_REG_CMP_ERR (DRAMC_NAO_BASE_ADDRESS + 0x0124) + #define CMP_ERR_CMP_ERR Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x0128) + #define TEST_ABIT_STATUS1_TEST_ABIT_ERR1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x012C) + #define TEST_ABIT_STATUS2_TEST_ABIT_ERR2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS3 (DRAMC_NAO_BASE_ADDRESS + 0x0130) + #define TEST_ABIT_STATUS3_TEST_ABIT_ERR3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS4 (DRAMC_NAO_BASE_ADDRESS + 0x0134) + #define TEST_ABIT_STATUS4_TEST_ABIT_ERR4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS5 (DRAMC_NAO_BASE_ADDRESS + 0x0138) + #define TEST_ABIT_STATUS5_TEST_ABIT_ERR5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS6 (DRAMC_NAO_BASE_ADDRESS + 0x013C) + #define TEST_ABIT_STATUS6_TEST_ABIT_ERR6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS7 (DRAMC_NAO_BASE_ADDRESS + 0x0140) + #define TEST_ABIT_STATUS7_TEST_ABIT_ERR7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS8 (DRAMC_NAO_BASE_ADDRESS + 0x0144) + #define TEST_ABIT_STATUS8_TEST_ABIT_ERR8 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_RF_ERROR_FLAG0 (DRAMC_NAO_BASE_ADDRESS + 0x0148) + #define TEST_RF_ERROR_FLAG0_TEST_RF_ERROR_FLAG0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_RF_ERROR_FLAG1 (DRAMC_NAO_BASE_ADDRESS + 0x014C) + #define TEST_RF_ERROR_FLAG1_TEST_RF_ERROR_FLAG1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x0150) + #define TEST_RF_ERROR_CNT1_DQ0F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT1_DQ0R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x0154) + #define TEST_RF_ERROR_CNT2_DQ1F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT2_DQ1R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT3 (DRAMC_NAO_BASE_ADDRESS + 0x0158) + #define TEST_RF_ERROR_CNT3_DQ2F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT3_DQ2R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT4 (DRAMC_NAO_BASE_ADDRESS + 0x015C) + #define TEST_RF_ERROR_CNT4_DQ3F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT4_DQ3R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT5 (DRAMC_NAO_BASE_ADDRESS + 0x0160) + #define TEST_RF_ERROR_CNT5_DQ4F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT5_DQ4R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT6 (DRAMC_NAO_BASE_ADDRESS + 0x0164) + #define TEST_RF_ERROR_CNT6_DQ5F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT6_DQ5R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT7 (DRAMC_NAO_BASE_ADDRESS + 0x0168) + #define TEST_RF_ERROR_CNT7_DQ6F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT7_DQ6R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT8 (DRAMC_NAO_BASE_ADDRESS + 0x016C) + #define TEST_RF_ERROR_CNT8_DQ7F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT8_DQ7R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_LOOP_CNT (DRAMC_NAO_BASE_ADDRESS + 0x0170) + #define TEST_LOOP_CNT_LOOP_CNT Fld(16, 0) //[15:0] + +#define DRAMC_REG_SREF_DLY_CNT (DRAMC_NAO_BASE_ADDRESS + 0x0180) + #define SREF_DLY_CNT_SREF_DLY_CNT Fld(16, 0) //[15:0] + #define SREF_DLY_CNT_SREF_DLY_CNT_ECO Fld(16, 16) //[31:16] + +#define DRAMC_REG_TX_ATK_SET0 (DRAMC_NAO_BASE_ADDRESS + 0x0200) + #define TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT Fld(6, 0) //[5:0] + #define TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT Fld(6, 8) //[13:8] + #define TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT Fld(6, 16) //[21:16] + #define TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT Fld(6, 24) //[29:24] + +#define DRAMC_REG_TX_ATK_SET1 (DRAMC_NAO_BASE_ADDRESS + 0x0204) + #define TX_ATK_SET1_TX_ATK_DQ_PI_EN Fld(1, 0) //[0:0] + #define TX_ATK_SET1_TX_ATK_DQM_PI_EN Fld(1, 1) //[1:1] + #define TX_ATK_SET1_TX_ATK_PI_LEN Fld(2, 2) //[3:2] + #define TX_ATK_SET1_TX_ATK_EARLY_BREAK Fld(1, 4) //[4:4] + #define TX_ATK_SET1_TX_ATK_PASS_PI_THRD Fld(6, 8) //[13:8] + #define TX_ATK_SET1_TX_ATK_DBG_EN Fld(1, 15) //[15:15] + #define TX_ATK_SET1_TX_ATK_DBG_BIT_SEL Fld(4, 16) //[19:16] + #define TX_ATK_SET1_TX_ATK_CLR Fld(1, 30) //[30:30] + #define TX_ATK_SET1_TX_ATK_TRIG Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_ATK_RESULT0 (DRAMC_NAO_BASE_ADDRESS + 0x0210) + #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT0 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT1 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT2 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT3 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT1 (DRAMC_NAO_BASE_ADDRESS + 0x0214) + #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT4 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT5 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT6 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT7 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT2 (DRAMC_NAO_BASE_ADDRESS + 0x0218) + #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT8 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT9 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT10 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT11 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT3 (DRAMC_NAO_BASE_ADDRESS + 0x021C) + #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT12 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT13 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT14 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT4 (DRAMC_NAO_BASE_ADDRESS + 0x0220) + #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT0 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT1 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT2 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT3 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT5 (DRAMC_NAO_BASE_ADDRESS + 0x0224) + #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT4 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT5 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT6 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT7 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT6 (DRAMC_NAO_BASE_ADDRESS + 0x0228) + #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT8 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT9 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT10 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT11 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT7 (DRAMC_NAO_BASE_ADDRESS + 0x022C) + #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT12 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT13 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT14 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT8 (DRAMC_NAO_BASE_ADDRESS + 0x0230) + #define TX_ATK_RESULT8_TX_ATK_FIND_PW Fld(1, 24) //[24:24] + #define TX_ATK_RESULT8_TX_ATK_DONE Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x0240) + #define TX_ATK_DBG_BIT_STATUS1_TX_ATK_DBG_BIT_STATUS1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x0244) + #define TX_ATK_DBG_BIT_STATUS2_TX_ATK_DBG_BIT_STATUS2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS3 (DRAMC_NAO_BASE_ADDRESS + 0x0248) + #define TX_ATK_DBG_BIT_STATUS3_TX_ATK_DBG_BIT_STATUS3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS4 (DRAMC_NAO_BASE_ADDRESS + 0x024C) + #define TX_ATK_DBG_BIT_STATUS4_TX_ATK_DBG_BIT_STATUS4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_LP5_PDX_PDE_MON (DRAMC_NAO_BASE_ADDRESS + 0x02D8) + #define LP5_PDX_PDE_MON_PDX_CMD_REQ_RK0_COUNTER Fld(8, 0) //[7:0] + #define LP5_PDX_PDE_MON_PDX_CMD_REQ_RK1_COUNTER Fld(8, 8) //[15:8] + #define LP5_PDX_PDE_MON_PDE_CMD_REQ_RK0_COUNTER Fld(8, 16) //[23:16] + #define LP5_PDX_PDE_MON_PDE_CMD_REQ_RK1_COUNTER Fld(8, 24) //[31:24] + +#define DRAMC_REG_LP5_PDX_PDE_MAX_MON (DRAMC_NAO_BASE_ADDRESS + 0x02DC) + #define LP5_PDX_PDE_MAX_MON_WAIT_PDX_CMD_RK0_MAX_COUNTER Fld(8, 0) //[7:0] + #define LP5_PDX_PDE_MAX_MON_WAIT_PDX_CMD_RK1_MAX_COUNTER Fld(8, 8) //[15:8] + #define LP5_PDX_PDE_MAX_MON_WAIT_PDE_CMD_RK0_MAX_COUNTER Fld(8, 16) //[23:16] + #define LP5_PDX_PDE_MAX_MON_WAIT_PDE_CMD_RK1_MAX_COUNTER Fld(8, 24) //[31:24] + +#define DRAMC_REG_DRAM_CLK_EN_0_OLD_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02E0) + #define DRAM_CLK_EN_0_OLD_COUNTER_DRAM_CLK_EN_0_OLD_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_APHYPI_CG_CK_OLD_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02E4) + #define APHYPI_CG_CK_OLD_COUNTER_APHYPI_CG_CK_OLD_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_CKEO_PRE_OLD_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02E8) + #define CKEO_PRE_OLD_COUNTER_CKEO_PRE_OLD_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_CKE1O_PRE_OLD_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02EC) + #define CKE1O_PRE_OLD_COUNTER_CKE1O_PRE_OLD_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAM_CLK_EN_0_NEW_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02F0) + #define DRAM_CLK_EN_0_NEW_COUNTER_DRAM_CLK_EN_0_NEW_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_APHYPI_CG_CK_NEW_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02F4) + #define APHYPI_CG_CK_NEW_COUNTER_APHYPI_CG_CK_NEW_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_CKEO_PRE_NEW_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02F8) + #define CKEO_PRE_NEW_COUNTER_CKEO_PRE_NEW_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_CKE1O_PRE_NEW_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02FC) + #define CKE1O_PRE_NEW_COUNTER_CKE1O_PRE_NEW_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_REFRESH_POP_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0300) + #define REFRESH_POP_COUNTER_REFRESH_POP_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_FREERUN_26M_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0304) + #define FREERUN_26M_COUNTER_FREERUN_26M_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_IDLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0308) + #define DRAMC_IDLE_COUNTER_DRAMC_IDLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2R_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x030C) + #define R2R_PAGE_HIT_COUNTER_R2R_PAGE_HIT_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2R_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0310) + #define R2R_PAGE_MISS_COUNTER_R2R_PAGE_MISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2R_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0314) + #define R2R_INTERBANK_COUNTER_R2R_INTERBANK_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2W_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0318) + #define R2W_PAGE_HIT_COUNTER_R2W_PAGE_HIT_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2W_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x031C) + #define R2W_PAGE_MISS_COUNTER_R2W_PAGE_MISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2W_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0320) + #define R2W_INTERBANK_COUNTER_R2W_INTERBANK_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2R_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0324) + #define W2R_PAGE_HIT_COUNTER_W2R_PAGE_HIT_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2R_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0328) + #define W2R_PAGE_MISS_COUNTER_W2R_PAGE_MISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2R_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x032C) + #define W2R_INTERBANK_COUNTER_W2R_INTERBANK_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2W_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0330) + #define W2W_PAGE_HIT_COUNTER_W2W_PAGE_HIT_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2W_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0334) + #define W2W_PAGE_MISS_COUNTER_W2W_PAGE_MISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2W_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0338) + #define W2W_INTERBANK_COUNTER_W2W_INTERBANK_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x033C) + #define RK0_PRE_STANDBY_COUNTER_RK0_PRE_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0340) + #define RK0_PRE_POWERDOWN_COUNTER_RK0_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0344) + #define RK0_ACT_STANDBY_COUNTER_RK0_ACT_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0348) + #define RK0_ACT_POWERDOWN_COUNTER_RK0_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x034C) + #define RK1_PRE_STANDBY_COUNTER_RK1_PRE_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0350) + #define RK1_PRE_POWERDOWN_COUNTER_RK1_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0354) + #define RK1_ACT_STANDBY_COUNTER_RK1_ACT_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0358) + #define RK1_ACT_POWERDOWN_COUNTER_RK1_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK2_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x035C) + #define RK2_PRE_STANDBY_COUNTER_RK2_PRE_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK2_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0360) + #define RK2_PRE_POWERDOWN_COUNTER_RK2_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK2_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0364) + #define RK2_ACT_STANDBY_COUNTER_RK2_ACT_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK2_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0368) + #define RK2_ACT_POWERDOWN_COUNTER_RK2_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ0_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x036C) + #define DQ0_TOGGLE_COUNTER_DQ0_TOGGLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ1_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0370) + #define DQ1_TOGGLE_COUNTER_DQ1_TOGGLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ2_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0374) + #define DQ2_TOGGLE_COUNTER_DQ2_TOGGLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ3_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0378) + #define DQ3_TOGGLE_COUNTER_DQ3_TOGGLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ0_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x037C) + #define DQ0_TOGGLE_COUNTER_R_DQ0_TOGGLE_COUNTER_R Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ1_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x0380) + #define DQ1_TOGGLE_COUNTER_R_DQ1_TOGGLE_COUNTER_R Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ2_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x0384) + #define DQ2_TOGGLE_COUNTER_R_DQ2_TOGGLE_COUNTER_R Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ3_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x0388) + #define DQ3_TOGGLE_COUNTER_R_DQ3_TOGGLE_COUNTER_R Fld(32, 0) //[31:0] + +#define DRAMC_REG_READ_BYTES_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x038C) + #define READ_BYTES_COUNTER_READ_BYTES_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_WRITE_BYTES_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0390) + #define WRITE_BYTES_COUNTER_WRITE_BYTES_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0394) + #define MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER_SREF_REQTOACK_MAX_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_IDLE_DCM_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x03A0) + #define DRAMC_IDLE_DCM_COUNTER_DRAMC_IDLE_DCM_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DDRPHY_CLK_EN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x03A4) + #define DDRPHY_CLK_EN_COUNTER_DDRPHY_CLK_EN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DDRPHY_CLK_EN_COMB_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x03A8) + #define DDRPHY_CLK_EN_COMB_COUNTER_DDRPHY_CLK_EN_COMB_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_EBG_COUNTER_CNT0 (DRAMC_NAO_BASE_ADDRESS + 0x03B0) + #define EBG_COUNTER_CNT0_EBG_PGHIT_COUNTER Fld(16, 0) //[15:0] + +#define DRAMC_REG_EBG_COUNTER_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x03B4) + #define EBG_COUNTER_CNT1_EBG_PGMISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_EBG_COUNTER_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x03B8) + #define EBG_COUNTER_CNT2_EBG_PGOPEN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_LAT_COUNTER_CMD0 (DRAMC_NAO_BASE_ADDRESS + 0x03C0) + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD1 (DRAMC_NAO_BASE_ADDRESS + 0x03C4) + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD2 (DRAMC_NAO_BASE_ADDRESS + 0x03C8) + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD3 (DRAMC_NAO_BASE_ADDRESS + 0x03CC) + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD4 (DRAMC_NAO_BASE_ADDRESS + 0x03D0) + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD5 (DRAMC_NAO_BASE_ADDRESS + 0x03D4) + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD6 (DRAMC_NAO_BASE_ADDRESS + 0x03D8) + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD7 (DRAMC_NAO_BASE_ADDRESS + 0x03DC) + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_AVER (DRAMC_NAO_BASE_ADDRESS + 0x03E0) + #define LAT_COUNTER_AVER_LAT_CMD_AVER_CNT Fld(32, 0) //[31:0] + +#define DRAMC_REG_LAT_COUNTER_NUM (DRAMC_NAO_BASE_ADDRESS + 0x03E4) + #define LAT_COUNTER_NUM_LAT_CMD_NUM Fld(16, 0) //[15:0] + +#define DRAMC_REG_LAT_COUNTER_BLOCK_ALE (DRAMC_NAO_BASE_ADDRESS + 0x03E8) + #define LAT_COUNTER_BLOCK_ALE_CTO_BLOCK_CNT_MAX Fld(16, 0) //[15:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_ADR (DRAMC_NAO_BASE_ADDRESS + 0x0504) + #define DRAMC_LOOP_BAK_ADR_TEST_WR_BK_ADR Fld(3, 0) //[2:0] + #define DRAMC_LOOP_BAK_ADR_TEST_WR_COL_ADR Fld(11, 3) //[13:3] + #define DRAMC_LOOP_BAK_ADR_TEST_WR_ROW_ADR Fld(18, 14) //[31:14] + +#define DRAMC_REG_DRAMC_LOOP_BAK_RK (DRAMC_NAO_BASE_ADDRESS + 0x0508) + #define DRAMC_LOOP_BAK_RK_TEST_WR_RK Fld(2, 0) //[1:0] + #define DRAMC_LOOP_BAK_RK_LOOP_BAK_ADR_CMP_FAIL Fld(1, 4) //[4:4] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT0 (DRAMC_NAO_BASE_ADDRESS + 0x0510) + #define DRAMC_LOOP_BAK_WDAT0_LOOP_BACK_WDAT0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT1 (DRAMC_NAO_BASE_ADDRESS + 0x0514) + #define DRAMC_LOOP_BAK_WDAT1_LOOP_BACK_WDAT1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT2 (DRAMC_NAO_BASE_ADDRESS + 0x0518) + #define DRAMC_LOOP_BAK_WDAT2_LOOP_BACK_WDAT2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT3 (DRAMC_NAO_BASE_ADDRESS + 0x051C) + #define DRAMC_LOOP_BAK_WDAT3_LOOP_BACK_WDAT3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT4 (DRAMC_NAO_BASE_ADDRESS + 0x0520) + #define DRAMC_LOOP_BAK_WDAT4_LOOP_BACK_WDAT4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT5 (DRAMC_NAO_BASE_ADDRESS + 0x0524) + #define DRAMC_LOOP_BAK_WDAT5_LOOP_BACK_WDAT5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT6 (DRAMC_NAO_BASE_ADDRESS + 0x0528) + #define DRAMC_LOOP_BAK_WDAT6_LOOP_BACK_WDAT6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT7 (DRAMC_NAO_BASE_ADDRESS + 0x052C) + #define DRAMC_LOOP_BAK_WDAT7_LOOP_BACK_WDAT7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DQSOSC_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0600) + #define RK0_DQSOSC_STATUS_MR18_REG Fld(16, 0) //[15:0] + #define RK0_DQSOSC_STATUS_MR19_REG Fld(16, 16) //[31:16] + +#define DRAMC_REG_RK0_DQSOSC_DELTA (DRAMC_NAO_BASE_ADDRESS + 0x0604) + #define RK0_DQSOSC_DELTA_ABS_RK0_DQSOSC_DELTA Fld(16, 0) //[15:0] + #define RK0_DQSOSC_DELTA_SIGN_RK0_DQSOSC_DELTA Fld(1, 16) //[16:16] + #define RK0_DQSOSC_DELTA_DQSOSCR_RESPONSE Fld(1, 17) //[17:17] + #define RK0_DQSOSC_DELTA_H_DQSOSCLSBR_REQ Fld(1, 18) //[18:18] + #define RK0_DQSOSC_DELTA_DQSOSC_INT_RK0 Fld(1, 19) //[19:19] + +#define DRAMC_REG_RK0_DQSOSC_DELTA2 (DRAMC_NAO_BASE_ADDRESS + 0x0608) + #define RK0_DQSOSC_DELTA2_ABS_RK0_DQSOSC_B1_DELTA Fld(16, 0) //[15:0] + #define RK0_DQSOSC_DELTA2_SIGN_RK0_DQSOSC_B1_DELTA Fld(1, 16) //[16:16] + +#define DRAMC_REG_RK0_CURRENT_TX_SETTING1 (DRAMC_NAO_BASE_ADDRESS + 0x0610) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ0_MOD Fld(3, 0) //[2:0] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ1_MOD Fld(3, 4) //[6:4] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ2_MOD Fld(3, 8) //[10:8] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ3_MOD Fld(3, 12) //[14:12] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM0_MOD Fld(3, 16) //[18:16] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM1_MOD Fld(3, 20) //[22:20] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM2_MOD Fld(3, 24) //[26:24] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK0_CURRENT_TX_SETTING2 (DRAMC_NAO_BASE_ADDRESS + 0x0614) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ0_MOD Fld(3, 0) //[2:0] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ1_MOD Fld(3, 4) //[6:4] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ2_MOD Fld(3, 8) //[10:8] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ3_MOD Fld(3, 12) //[14:12] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM0_MOD Fld(3, 16) //[18:16] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM1_MOD Fld(3, 20) //[22:20] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM2_MOD Fld(3, 24) //[26:24] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK0_CURRENT_TX_SETTING3 (DRAMC_NAO_BASE_ADDRESS + 0x0618) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ0_MOD Fld(3, 0) //[2:0] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ1_MOD Fld(3, 4) //[6:4] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ2_MOD Fld(3, 8) //[10:8] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ3_MOD Fld(3, 12) //[14:12] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM0_MOD Fld(3, 16) //[18:16] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM1_MOD Fld(3, 20) //[22:20] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM2_MOD Fld(3, 24) //[26:24] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK0_CURRENT_TX_SETTING4 (DRAMC_NAO_BASE_ADDRESS + 0x061C) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ0_MOD Fld(3, 0) //[2:0] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ1_MOD Fld(3, 4) //[6:4] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ2_MOD Fld(3, 8) //[10:8] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ3_MOD Fld(3, 12) //[14:12] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM0_MOD Fld(3, 16) //[18:16] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM1_MOD Fld(3, 20) //[22:20] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM2_MOD Fld(3, 24) //[26:24] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA0 (DRAMC_NAO_BASE_ADDRESS + 0x0620) + #define RK0_DUMMY_RD_DATA0_DUMMY_RD_RK0_DATA0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA1 (DRAMC_NAO_BASE_ADDRESS + 0x0624) + #define RK0_DUMMY_RD_DATA1_DUMMY_RD_RK0_DATA1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA2 (DRAMC_NAO_BASE_ADDRESS + 0x0628) + #define RK0_DUMMY_RD_DATA2_DUMMY_RD_RK0_DATA2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA3 (DRAMC_NAO_BASE_ADDRESS + 0x062C) + #define RK0_DUMMY_RD_DATA3_DUMMY_RD_RK0_DATA3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA4 (DRAMC_NAO_BASE_ADDRESS + 0x0630) + #define RK0_DUMMY_RD_DATA4_DUMMY_RD_RK0_DATA4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA5 (DRAMC_NAO_BASE_ADDRESS + 0x0634) + #define RK0_DUMMY_RD_DATA5_DUMMY_RD_RK0_DATA5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA6 (DRAMC_NAO_BASE_ADDRESS + 0x0638) + #define RK0_DUMMY_RD_DATA6_DUMMY_RD_RK0_DATA6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA7 (DRAMC_NAO_BASE_ADDRESS + 0x063C) + #define RK0_DUMMY_RD_DATA7_DUMMY_RD_RK0_DATA7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_PI_DQ_CAL (DRAMC_NAO_BASE_ADDRESS + 0x0660) + #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B0_CAL Fld(6, 0) //[5:0] + #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B1_CAL Fld(6, 8) //[13:8] + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0 Fld(6, 16) //[21:16] + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_OVERFLOW Fld(1, 22) //[22:22] + #define RK0_PI_DQ_CAL_RK0_B0_PI_CHANGE_DBG Fld(1, 23) //[23:23] + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1 Fld(6, 24) //[29:24] + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1_OVERFLOW Fld(1, 30) //[30:30] + #define RK0_PI_DQ_CAL_RK0_B1_PI_CHANGE_DBG Fld(1, 31) //[31:31] + +#define DRAMC_REG_RK0_PI_DQM_CAL (DRAMC_NAO_BASE_ADDRESS + 0x0668) + #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B0_CAL Fld(6, 0) //[5:0] + #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B1_CAL Fld(6, 8) //[13:8] + +#define DRAMC_REG_RK1_DQSOSC_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0700) + #define RK1_DQSOSC_STATUS_MR18_RK1_REG Fld(16, 0) //[15:0] + #define RK1_DQSOSC_STATUS_MR19_RK1_REG Fld(16, 16) //[31:16] + +#define DRAMC_REG_RK1_DQSOSC_DELTA (DRAMC_NAO_BASE_ADDRESS + 0x0704) + #define RK1_DQSOSC_DELTA_ABS_RK1_DQSOSC_DELTA Fld(16, 0) //[15:0] + #define RK1_DQSOSC_DELTA_SIGN_RK1_DQSOSC_DELTA Fld(1, 16) //[16:16] + #define RK1_DQSOSC_DELTA_DQSOSCR_RK1_RESPONSE Fld(1, 17) //[17:17] + #define RK1_DQSOSC_DELTA_H_DQSOSCLSBR_RK1_REQ Fld(1, 18) //[18:18] + #define RK1_DQSOSC_DELTA_DQSOSC_INT_RK1 Fld(1, 19) //[19:19] + +#define DRAMC_REG_RK1_DQSOSC_DELTA2 (DRAMC_NAO_BASE_ADDRESS + 0x0708) + #define RK1_DQSOSC_DELTA2_ABS_RK1_DQSOSC_B1_DELTA Fld(16, 0) //[15:0] + #define RK1_DQSOSC_DELTA2_SIGN_RK1_DQSOSC_B1_DELTA Fld(1, 16) //[16:16] + +#define DRAMC_REG_RK1_CURRENT_TX_SETTING1 (DRAMC_NAO_BASE_ADDRESS + 0x0710) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ0_MOD Fld(3, 0) //[2:0] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ1_MOD Fld(3, 4) //[6:4] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ2_MOD Fld(3, 8) //[10:8] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ3_MOD Fld(3, 12) //[14:12] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM0_MOD Fld(3, 16) //[18:16] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM1_MOD Fld(3, 20) //[22:20] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM2_MOD Fld(3, 24) //[26:24] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK1_CURRENT_TX_SETTING2 (DRAMC_NAO_BASE_ADDRESS + 0x0714) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ0_MOD Fld(3, 0) //[2:0] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ1_MOD Fld(3, 4) //[6:4] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ2_MOD Fld(3, 8) //[10:8] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ3_MOD Fld(3, 12) //[14:12] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM0_MOD Fld(3, 16) //[18:16] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM1_MOD Fld(3, 20) //[22:20] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM2_MOD Fld(3, 24) //[26:24] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK1_CURRENT_TX_SETTING3 (DRAMC_NAO_BASE_ADDRESS + 0x0718) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ0_MOD Fld(3, 0) //[2:0] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ1_MOD Fld(3, 4) //[6:4] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ2_MOD Fld(3, 8) //[10:8] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ3_MOD Fld(3, 12) //[14:12] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM0_MOD Fld(3, 16) //[18:16] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM1_MOD Fld(3, 20) //[22:20] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM2_MOD Fld(3, 24) //[26:24] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK1_CURRENT_TX_SETTING4 (DRAMC_NAO_BASE_ADDRESS + 0x071C) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ0_MOD Fld(3, 0) //[2:0] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ1_MOD Fld(3, 4) //[6:4] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ2_MOD Fld(3, 8) //[10:8] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ3_MOD Fld(3, 12) //[14:12] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM0_MOD Fld(3, 16) //[18:16] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM1_MOD Fld(3, 20) //[22:20] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM2_MOD Fld(3, 24) //[26:24] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA0 (DRAMC_NAO_BASE_ADDRESS + 0x0720) + #define RK1_DUMMY_RD_DATA0_DUMMY_RD_RK1_DATA0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA1 (DRAMC_NAO_BASE_ADDRESS + 0x0724) + #define RK1_DUMMY_RD_DATA1_DUMMY_RD_RK1_DATA1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA2 (DRAMC_NAO_BASE_ADDRESS + 0x0728) + #define RK1_DUMMY_RD_DATA2_DUMMY_RD_RK1_DATA2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA3 (DRAMC_NAO_BASE_ADDRESS + 0x072C) + #define RK1_DUMMY_RD_DATA3_DUMMY_RD_RK1_DATA3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA4 (DRAMC_NAO_BASE_ADDRESS + 0x0730) + #define RK1_DUMMY_RD_DATA4_DUMMY_RD_RK1_DATA4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA5 (DRAMC_NAO_BASE_ADDRESS + 0x0734) + #define RK1_DUMMY_RD_DATA5_DUMMY_RD_RK1_DATA5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA6 (DRAMC_NAO_BASE_ADDRESS + 0x0738) + #define RK1_DUMMY_RD_DATA6_DUMMY_RD_RK1_DATA6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA7 (DRAMC_NAO_BASE_ADDRESS + 0x073C) + #define RK1_DUMMY_RD_DATA7_DUMMY_RD_RK1_DATA7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_PI_DQ_CAL (DRAMC_NAO_BASE_ADDRESS + 0x0760) + #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B0_CAL Fld(6, 0) //[5:0] + #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B1_CAL Fld(6, 8) //[13:8] + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1 Fld(6, 16) //[21:16] + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_OVERFLOW Fld(1, 22) //[22:22] + #define RK1_PI_DQ_CAL_RK1_B0_PI_CHANGE_DBG Fld(1, 23) //[23:23] + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1 Fld(6, 24) //[29:24] + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1_OVERFLOW Fld(1, 30) //[30:30] + #define RK1_PI_DQ_CAL_RK1_B1_PI_CHANGE_DBG Fld(1, 31) //[31:31] + +#define DRAMC_REG_RK1_PI_DQM_CAL (DRAMC_NAO_BASE_ADDRESS + 0x0768) + #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B0_CAL Fld(6, 0) //[5:0] + #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B1_CAL Fld(6, 8) //[13:8] + +#define DRAMC_REG_MR_BACKUP_00_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0900) + #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR4 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0904) + #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR9 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR10 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR11 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR12 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0908) + #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR13 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR14 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR15 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR16 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x090C) + #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_04_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0910) + #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR21 Fld(8, 0) //[7:0] + #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR22 Fld(8, 8) //[15:8] + #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR23 Fld(8, 16) //[23:16] + #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR24 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_05_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0914) + #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR25 Fld(8, 0) //[7:0] + #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR26 Fld(8, 8) //[15:8] + #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR27 Fld(8, 16) //[23:16] + #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR28 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_06_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0918) + #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR30 Fld(8, 0) //[7:0] + #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR31 Fld(8, 8) //[15:8] + #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR32 Fld(8, 16) //[23:16] + #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR33 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_07_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x091C) + #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR34 Fld(8, 0) //[7:0] + #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR37 Fld(8, 8) //[15:8] + #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR39 Fld(8, 16) //[23:16] + #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR40 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_08_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0920) + #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR41 Fld(8, 0) //[7:0] + #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR42 Fld(8, 8) //[15:8] + #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR46 Fld(8, 16) //[23:16] + #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR48 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_09_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0924) + #define MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR63 Fld(8, 0) //[7:0] + #define MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR51 Fld(8, 8) //[15:8] + +#define DRAMC_REG_MR_BACKUP_00_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0930) + #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR10 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0934) + #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR11 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR12 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR14 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0938) + #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x093C) + #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR22 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR24 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR30 Fld(8, 16) //[23:16] + #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR41 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_04_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0940) + #define MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR21 Fld(8, 0) //[7:0] + #define MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR51 Fld(8, 8) //[15:8] + +#define DRAMC_REG_MR_BACKUP_00_RK0_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0960) + #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR10 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK0_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0964) + #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR11 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR12 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR14 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK0_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0968) + #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK0_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x096C) + #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR24 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR30 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR41 Fld(8, 16) //[23:16] + +#define DRAMC_REG_MR_BACKUP_00_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B00) + #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR4 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B04) + #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR9 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR10 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR11 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR12 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B08) + #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR13 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR14 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR15 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR16 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B0C) + #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_04_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B10) + #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR21 Fld(8, 0) //[7:0] + #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR22 Fld(8, 8) //[15:8] + #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR23 Fld(8, 16) //[23:16] + #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR24 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_05_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B14) + #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR25 Fld(8, 0) //[7:0] + #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR26 Fld(8, 8) //[15:8] + #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR27 Fld(8, 16) //[23:16] + #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR28 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_06_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B18) + #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR30 Fld(8, 0) //[7:0] + #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR31 Fld(8, 8) //[15:8] + #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR32 Fld(8, 16) //[23:16] + #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR33 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_07_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B1C) + #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR34 Fld(8, 0) //[7:0] + #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR37 Fld(8, 8) //[15:8] + #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR39 Fld(8, 16) //[23:16] + #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR40 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_08_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B20) + #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR41 Fld(8, 0) //[7:0] + #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR42 Fld(8, 8) //[15:8] + #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR46 Fld(8, 16) //[23:16] + #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR48 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_09_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B24) + #define MR_BACKUP_09_RK1_FSP0_MRWBK_RK1_FSP0_MR63 Fld(8, 0) //[7:0] + #define MR_BACKUP_09_RK1_FSP0_MRWBK_RK1_FSP0_MR51 Fld(8, 8) //[15:8] + +#define DRAMC_REG_MR_BACKUP_00_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B30) + #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR10 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B34) + #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR11 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR12 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR14 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B38) + #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B3C) + #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR22 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR24 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR30 Fld(8, 16) //[23:16] + #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR41 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_04_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B40) + #define MR_BACKUP_04_RK1_FSP1_MRWBK_RK1_FSP1_MR21 Fld(8, 0) //[7:0] + #define MR_BACKUP_04_RK1_FSP1_MRWBK_RK1_FSP1_MR51 Fld(8, 8) //[15:8] + +#define DRAMC_REG_MR_BACKUP_00_RK1_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0B60) + #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR10 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK1_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0B64) + #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR11 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR12 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR14 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK1_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0B68) + #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK1_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0B6C) + #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR24 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR30 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR41 Fld(8, 16) //[23:16] + +#endif // __DRAMC_NAO_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/addressmap.h b/src/vendorcode/mediatek/mt8192/include/addressmap.h new file mode 100644 index 0000000000..85402d0010 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/addressmap.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef ADDRESSMAP_H +#define ADDRESSMAP_H + +#include <soc/addressmap.h> + +enum { + PWRAP_BASE = IO_PHYS + 0x00026000, +}; + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/custom_emi.h b/src/vendorcode/mediatek/mt8192/include/custom_emi.h new file mode 100644 index 0000000000..c8cf32598c --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/custom_emi.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __CUSTOM_EMI__ +#define __CUSTOM_EMI__ + +#define __ETT__ 0 + +#include "dramc_pi_api.h" +#include "emi.h" + +#define MT29VZZZBD9DQKPR + +#ifdef MT29VZZZBD9DQKPR +EMI_SETTINGS default_emi_setting = +//MT29VZZZBD9DQKPR +{ + 0x1, /* sub_version */ + 0x0206, /* TYPE */ + 9, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x13,0x01,0x4E,0x53,0x30,0x4A,0x39,0x4D,0x39,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3530154, /* EMI_CONA_VAL */ + 0x66660033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0xC0000000,0xC0000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x466005D, /* CHN0_EMI_CONA_VAL */ + 0x466005D, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x000000FF, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ +}; +#endif + +EMI_SETTINGS emi_settings[] = +{ + //H9HKNNNFBMMVAR - 4GB (2+2) + { + 0x1, /* sub_version */ + 0x0006, /* TYPE */ + 0, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0xF053F154, /* EMI_CONA_VAL */ + 0x44440003, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x80000000,0x80000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x444F051, /* CHN0_EMI_CONA_VAL */ + 0x444F051, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000006, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + } , + //MT29VZZZBD9DQKPR - 6GB (3+3) + { + 0x1, /* sub_version */ + 0x0206, /* TYPE */ + 9, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x13,0x01,0x4E,0x53,0x30,0x4A,0x39,0x4D,0x39,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3530154, /* EMI_CONA_VAL */ + 0x66660033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0xC0000000,0xC0000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x466005D, /* CHN0_EMI_CONA_VAL */ + 0x466005D, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x000000FF, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + } , + //H9HQ16AFAMMDAR / H9HCNNNFAMMLXR-NEE / K4UCE3Q4AA-MGCR - 8GB (4+4) Byte Mode + { + 0x1, /* sub_version */ + 0x0306, /* TYPE */ + 14, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x48,0x39,0x48,0x51,0x31,0x36,0x41,0x46,0x41,0x4D,0x4D,0x44,0x41,0x52,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3530154, /* EMI_CONA_VAL */ + 0x88880033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x100000000,0x100000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x488005D, /* CHN0_EMI_CONA_VAL */ + 0x488005D, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_BYTE, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000006, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + }, + //MT29VZZZAD8GQFSL-046 - 4GB -Normal mode (4+0) + { + 0x1, /* sub_version */ + 0x0006, /* TYPE */ + 0, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3500154, /* EMI_CONA_VAL */ + 0x88880033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x100000000,0,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x488005C, /* CHN0_EMI_CONA_VAL */ + 0x488005C, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000006, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + }, + //KM2V8001CM_B707 - 6GB -byte mode (2+4) + { + 0x1, /* sub_version */ + 0x0306, /* TYPE */ + 14, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x4b,0x4d,0x32,0x56,0x38,0x30,0x30,0x31,0x43,0x4d,0x2d,0x42,0x37,0x30,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x32533154, /* EMI_CONA_VAL */ + 0x84840023, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x80000000,0x100000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x4843059, /* CHN0_EMI_CONA_VAL */ + 0x4843059, /* CHN1_EMI_CONA_VAL */ + CBT_R0_NORMAL_R1_BYTE, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000001, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + } , + //MT53E2G32D4 - 8GB (4+4) Normal Mode + { + 0x1, /* sub_version */ + 0x0306, /* TYPE */ + 14, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x48,0x39,0x48,0x51,0x31,0x36,0x41,0x46,0x41,0x4D,0x4D,0x44,0x41,0x52,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3530154, /* EMI_CONA_VAL */ + 0x88880033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x100000000,0x100000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x488005D, /* CHN0_EMI_CONA_VAL */ + 0x488005D, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000006, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + }, +}; + +#define num_of_emi_records (sizeof(emi_settings) / sizeof(emi_settings[0])) + +#endif /* __CUSTOM_EMI__ */ + diff --git a/src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h b/src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h new file mode 100644 index 0000000000..a48629f914 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h @@ -0,0 +1,391 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_NAO_REG_H__ +#define __DDRPHY_NAO_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define MISC_STA_EXTLB0 0x00000000 + #define MISC_STA_EXTLB0_STA_EXTLB_DONE GENMASK(31, 0) +#define MISC_STA_EXTLB1 0x00000004 + #define MISC_STA_EXTLB1_STA_EXTLB_FAIL GENMASK(31, 0) +#define MISC_STA_EXTLB2 0x00000008 + #define MISC_STA_EXTLB2_STA_EXTLB_DBG_INFO GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO0 0x00000080 + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B0 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B0 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B1 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B1 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO1 0x00000084 + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B2 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B2 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B3 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B3 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO2 0x00000088 + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B4 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B4 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B5 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B5 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO3 0x0000008c + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B6 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B6 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B7 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B7 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO4 0x00000090 + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B0 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B1 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B2 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B3 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO5 0x00000094 + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B4 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B5 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B6 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B7 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO6 0x00000098 + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LAG_CNT_OUT_DQM0 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LEAD_CNT_OUT_DQM0 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_LEAD_LAG_CNT_OUT_DQM0 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO7 0x0000009c + #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B0_SW_UP_DONE BIT(0) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B1_SW_UP_DONE BIT(4) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B0_SW_UP_DONE BIT(8) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B1_SW_UP_DONE BIT(12) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B0_SW_UP_DONE BIT(16) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B1_SW_UP_DONE BIT(20) +#define MISC_DQ_RXDLY_TRRO8 0x000000a0 + #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B0 GENMASK(8, 0) + #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B1 GENMASK(24, 16) +#define MISC_DQ_RXDLY_TRRO9 0x000000a4 + #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B2 GENMASK(8, 0) + #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B3 GENMASK(24, 16) +#define MISC_DQ_RXDLY_TRRO10 0x000000a8 + #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B4 GENMASK(8, 0) + #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B5 GENMASK(24, 16) +#define MISC_DQ_RXDLY_TRRO11 0x000000ac + #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B6 GENMASK(8, 0) + #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B7 GENMASK(24, 16) +#define MISC_DQ_RXDLY_TRRO12 0x000000b0 + #define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_TH_CNT_OUT_DQM0 GENMASK(8, 0) +#define MISC_DQ_RXDLY_TRRO13 0x000000b4 + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B0_R_DLY GENMASK(5, 0) + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS0_R_DLY GENMASK(14, 8) + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B1_R_DLY GENMASK(21, 16) + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS1_R_DLY GENMASK(30, 24) +#define MISC_DQ_RXDLY_TRRO14 0x000000b8 + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B0_R_DLY GENMASK(5, 0) + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS0_R_DLY GENMASK(14, 8) + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B1_R_DLY GENMASK(21, 16) + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS1_R_DLY GENMASK(30, 24) +#define MISC_DQ_RXDLY_TRRO15 0x000000bc + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B0_R_DLY GENMASK(5, 0) + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS0_R_DLY GENMASK(14, 8) + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B1_R_DLY GENMASK(21, 16) + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS1_R_DLY GENMASK(30, 24) +#define MISC_DQ_RXDLY_TRRO16 0x000000c0 + #define MISC_DQ_RXDLY_TRRO16_DVS_RXDLY_STS_ERR_CNT_ALL GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO17 0x000000c4 + #define MISC_DQ_RXDLY_TRRO17_DVS_RXDLY_STS_ERR_CNT_ALL_47_32 GENMASK(15, 0) + #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B0 BIT(16) + #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B1 BIT(24) +#define MISC_DQ_RXDLY_TRRO18 0x000000c8 + #define MISC_DQ_RXDLY_TRRO18_RXDLY_DBG_MON_VALID BIT(0) + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK0_FAIL_LAT BIT(1) + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK1_FAIL_LAT BIT(2) + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK2_FAIL_LAT BIT(3) + #define MISC_DQ_RXDLY_TRRO18_DFS_SHU_GP_FAIL_LAT GENMASK(5, 4) +#define MISC_DQ_RXDLY_TRRO19 0x000000cc + #define MISC_DQ_RXDLY_TRRO19_RESERVED_0X00C GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO20 0x000000d0 + #define MISC_DQ_RXDLY_TRRO20_RESERVED_0X0D0 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO21 0x000000d4 + #define MISC_DQ_RXDLY_TRRO21_RESERVED_0X0D4 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO22 0x000000d8 + #define MISC_DQ_RXDLY_TRRO22_RESERVED_0X0D8 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO23 0x000000dc + #define MISC_DQ_RXDLY_TRRO23_RESERVED_0X0DC GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO24 0x000000e0 + #define MISC_DQ_RXDLY_TRRO24_RESERVED_0X0E0 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO25 0x000000e4 + #define MISC_DQ_RXDLY_TRRO25_RESERVED_0X0E4 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO26 0x000000e8 + #define MISC_DQ_RXDLY_TRRO26_RESERVED_0X0E8 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO27 0x000000ec + #define MISC_DQ_RXDLY_TRRO27_RESERVED_0X0EC GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO28 0x000000f0 + #define MISC_DQ_RXDLY_TRRO28_RESERVED_0X0F0 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO29 0x000000f4 + #define MISC_DQ_RXDLY_TRRO29_RESERVED_0X0F4 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO30 0x000000f8 + #define MISC_DQ_RXDLY_TRRO30_RESERVED_0X0F8 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO31 0x000000fc + #define MISC_DQ_RXDLY_TRRO31_RESERVED_0X0FC GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO0 0x00000100 + #define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LAG_CNT_OUT_CA0 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA0 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LAG_CNT_OUT_CA1 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA1 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO1 0x00000104 + #define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LAG_CNT_OUT_CA2 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA2 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LAG_CNT_OUT_CA3 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA3 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO2 0x00000108 + #define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LAG_CNT_OUT_CA4 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA4 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LAG_CNT_OUT_CA5 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA5 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO3 0x0000010c + #define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE0 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE0 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE1 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE1 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO4 0x00000110 + #define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE2 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE2 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LAG_CNT_OUT_CS0 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS0 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO5 0x00000114 + #define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LAG_CNT_OUT_CS1 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS1 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LAG_CNT_OUT_CS2 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS2 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO6 0x00000118 + #define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA0 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA1 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA2 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA3 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO7 0x0000011c + #define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA4 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA5 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE0 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE1 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO8 0x00000120 + #define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE2 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS0 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS1 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS2 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO9 0x00000124 + #define MISC_CA_RXDLY_TRRO9_DVS_RK0_CA_SW_UP_DONE BIT(0) + #define MISC_CA_RXDLY_TRRO9_DVS_RK1_CA_SW_UP_DONE BIT(8) + #define MISC_CA_RXDLY_TRRO9_DVS_RK2_CA_SW_UP_DONE BIT(16) +#define MISC_CA_RXDLY_TRRO10 0x00000128 + #define MISC_CA_RXDLY_TRRO10_DVS_RKX_CA_TH_CNT_OUT_CA0 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO10_DVS_RKX_CA_TH_CNT_OUT_CA1 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO11 0x0000012c + #define MISC_CA_RXDLY_TRRO11_DVS_RKX_CA_TH_CNT_OUT_CA2 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO11_DVS_RKX_CA_TH_CNT_OUT_CA3 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO12 0x00000130 + #define MISC_CA_RXDLY_TRRO12_DVS_RKX_CA_TH_CNT_OUT_CA4 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO12_DVS_RKX_CA_TH_CNT_OUT_CA5 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO13 0x00000134 + #define MISC_CA_RXDLY_TRRO13_DVS_RKX_CA_TH_CNT_OUT_CKE0 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO13_DVS_RKX_CA_TH_CNT_OUT_CKE1 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO14 0x00000138 + #define MISC_CA_RXDLY_TRRO14_DVS_RKX_CA_TH_CNT_OUT_CKE2 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO14_DVS_RKX_CA_TH_CNT_OUT_CS0 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO15 0x0000013c + #define MISC_CA_RXDLY_TRRO15_DVS_RKX_CA_TH_CNT_OUT_CS1 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO15_DVS_RKX_CA_TH_CNT_OUT_CS2 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO16 0x00000140 + #define MISC_CA_RXDLY_TRRO16_DA_RK0_CAX_CA_R_DLY GENMASK(5, 0) + #define MISC_CA_RXDLY_TRRO16_DA_RK0_CLK_R_DLY GENMASK(15, 8) +#define MISC_CA_RXDLY_TRRO17 0x00000144 + #define MISC_CA_RXDLY_TRRO17_DA_RK1_CAX_CA_R_DLY GENMASK(5, 0) + #define MISC_CA_RXDLY_TRRO17_DA_RK1_CLK_R_DLY GENMASK(15, 8) +#define MISC_CA_RXDLY_TRRO18 0x00000148 + #define MISC_CA_RXDLY_TRRO18_DA_RK2_CAX_CA_R_DLY GENMASK(5, 0) + #define MISC_CA_RXDLY_TRRO18_DA_RK2_CLK_R_DLY GENMASK(15, 8) +#define MISC_CA_RXDLY_TRRO19 0x0000014c + #define MISC_CA_RXDLY_TRRO19_DVS_RXDLY_STS_ERR_CNT_ALL_CA GENMASK(23, 0) + #define MISC_CA_RXDLY_TRRO19_PBYTE_LEADLAG_STUCK_CA BIT(24) +#define MISC_CA_RXDLY_TRRO20 0x00000150 + #define MISC_CA_RXDLY_TRRO20_RESERVED_0X150 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO21 0x00000154 + #define MISC_CA_RXDLY_TRRO21_RESERVED_0X154 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO22 0x00000158 + #define MISC_CA_RXDLY_TRRO22_RESERVED_0X158 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO23 0x0000015c + #define MISC_CA_RXDLY_TRRO23_RESERVED_0X15C GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO24 0x00000160 + #define MISC_CA_RXDLY_TRRO24_RESERVED_0X160 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO25 0x00000164 + #define MISC_CA_RXDLY_TRRO25_RESERVED_0X164 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO26 0x00000168 + #define MISC_CA_RXDLY_TRRO26_RESERVED_0X168 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO27 0x0000016c + #define MISC_CA_RXDLY_TRRO27_RESERVED_0X16C GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO28 0x00000170 + #define MISC_CA_RXDLY_TRRO28_RESERVED_0X170 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO29 0x00000174 + #define MISC_CA_RXDLY_TRRO29_RESERVED_0X174 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO30 0x00000178 + #define MISC_CA_RXDLY_TRRO30_RESERVED_0X178 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO31 0x0000017c + #define MISC_CA_RXDLY_TRRO31_RESERVED_0X17C GENMASK(31, 0) +#define MISC_DQO1 0x00000180 + #define MISC_DQO1_DQO1_RO GENMASK(31, 0) +#define MISC_CAO1 0x00000184 + #define MISC_CAO1_RA0_O1 BIT(0) + #define MISC_CAO1_RA1_O1 BIT(1) + #define MISC_CAO1_RA2_O1 BIT(2) + #define MISC_CAO1_RA3_O1 BIT(3) + #define MISC_CAO1_RA4_O1 BIT(4) + #define MISC_CAO1_RA5_O1 BIT(5) + #define MISC_CAO1_RA6_O1 BIT(6) + #define MISC_CAO1_RA7_O1 BIT(7) + #define MISC_CAO1_RA8_O1 BIT(8) + #define MISC_CAO1_RA9_O1 BIT(9) + #define MISC_CAO1_CKEO1_RO BIT(10) + #define MISC_CAO1_CKE1O1_RO BIT(11) + #define MISC_CAO1_CKE2O1_RO BIT(12) + #define MISC_CAO1_CSO1_RO BIT(13) + #define MISC_CAO1_CS1O1_RO BIT(14) + #define MISC_CAO1_CS2O1_RO BIT(15) + #define MISC_CAO1_RESETO1_RO BIT(16) + #define MISC_CAO1_DQM0O1_RO BIT(24) + #define MISC_CAO1_DQM1O1_RO BIT(25) + #define MISC_CAO1_DQM2O1_RO BIT(26) + #define MISC_CAO1_DQM3O1_RO BIT(27) +#define MISC_AD_RX_DQ_O1 0x00000188 + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0 GENMASK(7, 0) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0_BIT2 BIT(2)//[2:2] //francis added + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0 BIT(8) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1 GENMASK(23, 16) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1 BIT(24) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1_BIT2 BIT(18)//[18:18] //francis added +#define MISC_AD_RX_CMD_O1 0x0000018c + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA0_O1 BIT(0) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA1_O1 BIT(1) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA2_O1 BIT(2) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA3_O1 BIT(3) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA4_O1 BIT(4) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA5_O1 BIT(5) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA6_O1 BIT(6) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA7_O1 BIT(7) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA8_O1 BIT(8) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA9_O1 BIT(9) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1 BIT(10) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1 BIT(11) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE2_O1 BIT(12) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1 BIT(13) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1 BIT(14) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS2_O1 BIT(15) +#define MISC_PHY_RGS_DQ 0x00000190 + #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B0 GENMASK(7, 0) + #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B0 BIT(8) + #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B0 BIT(9) + #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B1 GENMASK(23, 16) + #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B1 BIT(24) + #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B1 BIT(25) + #define MISC_PHY_RGS_DQ_DA_RPHYPLLGP_CK_SEL BIT(31) +#define MISC_PHY_RGS_CMD 0x00000194 + #define MISC_PHY_RGS_CMD_RGS_ARCA0_OFFSET_FLAG BIT(0) + #define MISC_PHY_RGS_CMD_RGS_ARCA1_OFFSET_FLAG BIT(1) + #define MISC_PHY_RGS_CMD_RGS_ARCA2_OFFSET_FLAG BIT(2) + #define MISC_PHY_RGS_CMD_RGS_ARCA3_OFFSET_FLAG BIT(3) + #define MISC_PHY_RGS_CMD_RGS_ARCA4_OFFSET_FLAG BIT(4) + #define MISC_PHY_RGS_CMD_RGS_ARCA5_OFFSET_FLAG BIT(5) + #define MISC_PHY_RGS_CMD_RGS_ARCA6_OFFSET_FLAG BIT(6) + #define MISC_PHY_RGS_CMD_RGS_ARCA7_OFFSET_FLAG BIT(7) + #define MISC_PHY_RGS_CMD_RGS_ARCA8_OFFSET_FLAG BIT(8) + #define MISC_PHY_RGS_CMD_RGS_ARCA9_OFFSET_FLAG BIT(9) + #define MISC_PHY_RGS_CMD_RGS_ARCKE0_OFFSET_FLAG BIT(10) + #define MISC_PHY_RGS_CMD_RGS_ARCKE1_OFFSET_FLAG BIT(11) + #define MISC_PHY_RGS_CMD_RGS_ARCKE2_OFFSET_FLAG BIT(12) + #define MISC_PHY_RGS_CMD_RGS_ARCS0_OFFSET_FLAG BIT(13) + #define MISC_PHY_RGS_CMD_RGS_ARCS1_OFFSET_FLAG BIT(14) + #define MISC_PHY_RGS_CMD_RGS_ARCS2_OFFSET_FLAG BIT(15) + #define MISC_PHY_RGS_CMD_RGS_RX_ARCLK_RDY_EYE BIT(16) + #define MISC_PHY_RGS_CMD_RGS_RIMPCALOUT BIT(24) +#define MISC_PHY_RGS_STBEN_B0 0x00000198 + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ0_STBEN_B0 GENMASK(7, 0) + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ4_STBEN_B0 GENMASK(15, 8) + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0 BIT(16) + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0 BIT(17) + #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_PD_EN_B0 BIT(18) + #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_MON_B0 GENMASK(31, 24) +#define MISC_PHY_RGS_STBEN_B1 0x0000019c + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ0_STBEN_B1 GENMASK(7, 0) + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ4_STBEN_B1 GENMASK(15, 8) + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1 BIT(16) + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1 BIT(17) + #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_PD_EN_B1 BIT(18) + #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_MON_B1 GENMASK(31, 24) +#define MISC_PHY_RGS_STBEN_CMD 0x000001a0 + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA0_STBEN GENMASK(7, 0) + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA4_STBEN GENMASK(15, 8) + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD BIT(16) + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG BIT(17) + #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_PD_EN_CA BIT(18) + #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_MON_CA GENMASK(31, 24) +#define MISC_STA_TOGLB0 0x000001a4 + #define MISC_STA_TOGLB0_STA_TOGLB_DONE GENMASK(31, 0) +#define MISC_STA_TOGLB1 0x000001a8 + #define MISC_STA_TOGLB1_STA_TOGLB_FAIL GENMASK(31, 0) +#define MISC_STA_TOGLB2 0x000001ac + #define MISC_STA_TOGLB2_STA_TOGLB_PUHI_TIMEOUT GENMASK(31, 0) +#define MISC_STA_TOGLB3 0x000001b0 + #define MISC_STA_TOGLB3_STA_TOGLB_PULO_TIMEOUT GENMASK(31, 0) +#define MISC_FT_STATUS_0 0x000001b4 + #define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LAG_B1 GENMASK(7, 0) + #define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LEAD_B1 GENMASK(15, 8) + #define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LAG_B0 GENMASK(23, 16) + #define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LEAD_B0 GENMASK(31, 24) +#define MISC_FT_STATUS_1 0x000001b8 + #define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LAG_B1 GENMASK(7, 0) + #define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LEAD_B1 GENMASK(15, 8) + #define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LAG_B0 GENMASK(23, 16) + #define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LEAD_B0 GENMASK(31, 24) +#define MISC_FT_STATUS_2 0x000001bc + #define MISC_FT_STATUS_2_AD_RRESETB_O BIT(0) +#define MISC_FT_STATUS_3 0x000001c0 + #define MISC_FT_STATUS_3_AD_RX_ARCA0_DVS_R_LAG BIT(0) + #define MISC_FT_STATUS_3_AD_RX_ARCA1_DVS_R_LAG BIT(1) + #define MISC_FT_STATUS_3_AD_RX_ARCA2_DVS_R_LAG BIT(2) + #define MISC_FT_STATUS_3_AD_RX_ARCA3_DVS_R_LAG BIT(3) + #define MISC_FT_STATUS_3_AD_RX_ARCA4_DVS_R_LAG BIT(4) + #define MISC_FT_STATUS_3_AD_RX_ARCA5_DVS_R_LAG BIT(5) + #define MISC_FT_STATUS_3_AD_RX_ARCKE0_DVS_R_LAG BIT(6) + #define MISC_FT_STATUS_3_AD_RX_ARCKE1_DVS_R_LAG BIT(7) + #define MISC_FT_STATUS_3_AD_RX_ARCS0_DVS_R_LAG BIT(8) + #define MISC_FT_STATUS_3_AD_RX_ARCS1_DVS_R_LAG BIT(9) + #define MISC_FT_STATUS_3_AD_RX_ARCA0_DVS_R_LEAD BIT(16) + #define MISC_FT_STATUS_3_AD_RX_ARCA1_DVS_R_LEAD BIT(17) + #define MISC_FT_STATUS_3_AD_RX_ARCA2_DVS_R_LEAD BIT(18) + #define MISC_FT_STATUS_3_AD_RX_ARCA3_DVS_R_LEAD BIT(19) + #define MISC_FT_STATUS_3_AD_RX_ARCA4_DVS_R_LEAD BIT(20) + #define MISC_FT_STATUS_3_AD_RX_ARCA5_DVS_R_LEAD BIT(21) + #define MISC_FT_STATUS_3_AD_RX_ARCKE0_DVS_R_LEAD BIT(22) + #define MISC_FT_STATUS_3_AD_RX_ARCKE1_DVS_R_LEAD BIT(23) + #define MISC_FT_STATUS_3_AD_RX_ARCS0_DVS_R_LEAD BIT(24) + #define MISC_FT_STATUS_3_AD_RX_ARCS1_DVS_R_LEAD BIT(25) +#define MISC_FT_STATUS_4 0x000001c4 + #define MISC_FT_STATUS_4_AD_RX_ARCA0_DVS_F_LAG BIT(0) + #define MISC_FT_STATUS_4_AD_RX_ARCA1_DVS_F_LAG BIT(1) + #define MISC_FT_STATUS_4_AD_RX_ARCA2_DVS_F_LAG BIT(2) + #define MISC_FT_STATUS_4_AD_RX_ARCA3_DVS_F_LAG BIT(3) + #define MISC_FT_STATUS_4_AD_RX_ARCA4_DVS_F_LAG BIT(4) + #define MISC_FT_STATUS_4_AD_RX_ARCA5_DVS_F_LAG BIT(5) + #define MISC_FT_STATUS_4_AD_RX_ARCKE0_DVS_F_LAG BIT(6) + #define MISC_FT_STATUS_4_AD_RX_ARCKE1_DVS_F_LAG BIT(7) + #define MISC_FT_STATUS_4_AD_RX_ARCS0_DVS_F_LAG BIT(8) + #define MISC_FT_STATUS_4_AD_RX_ARCS1_DVS_F_LAG BIT(9) + #define MISC_FT_STATUS_4_AD_RX_ARCA0_DVS_F_LEAD BIT(16) + #define MISC_FT_STATUS_4_AD_RX_ARCA1_DVS_F_LEAD BIT(17) + #define MISC_FT_STATUS_4_AD_RX_ARCA2_DVS_F_LEAD BIT(18) + #define MISC_FT_STATUS_4_AD_RX_ARCA3_DVS_F_LEAD BIT(19) + #define MISC_FT_STATUS_4_AD_RX_ARCA4_DVS_F_LEAD BIT(20) + #define MISC_FT_STATUS_4_AD_RX_ARCA5_DVS_F_LEAD BIT(21) + #define MISC_FT_STATUS_4_AD_RX_ARCKE0_DVS_F_LEAD BIT(22) + #define MISC_FT_STATUS_4_AD_RX_ARCKE1_DVS_F_LEAD BIT(23) + #define MISC_FT_STATUS_4_AD_RX_ARCS0_DVS_F_LEAD BIT(24) + #define MISC_FT_STATUS_4_AD_RX_ARCS1_DVS_F_LEAD BIT(25) +#define MISC_STA_EXTLB_DBG0 0x000001c8 + #define MISC_STA_EXTLB_DBG0_STA_EXTLB_DVS_LEAD_0TO1 GENMASK(31, 0) +#define MISC_STA_EXTLB_DBG1 0x000001cc + #define MISC_STA_EXTLB_DBG1_STA_EXTLB_DVS_LEAD_1TO0 GENMASK(31, 0) +#define MISC_STA_EXTLB_DBG2 0x000001d0 + #define MISC_STA_EXTLB_DBG2_STA_EXTLB_DVS_LAG_0TO1 GENMASK(31, 0) +#define MISC_STA_EXTLB_DBG3 0x000001d4 + #define MISC_STA_EXTLB_DBG3_STA_EXTLB_DVS_LAG_1TO0 GENMASK(31, 0) + +#endif /*__DDRPHY_NAO_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h b/src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h new file mode 100644 index 0000000000..4546910893 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_PLL_REG_H__ +#define __DDRPHY_PLL_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define PLL1 0x00000000 + #define PLL1_RG_RPHYPLL_SDM_SSC_EN BIT(2) + #define PLL1_RG_RPHYPLL_EN BIT(31) +#define PLL2 0x00000004 + #define PLL2_RG_RCLRPLL_SDM_SSC_EN BIT(2) + #define PLL2_RG_RCLRPLL_EN BIT(31) +#define PLL3 0x00000008 + #define PLL3_RG_RPHYPLL_TSTOP_EN BIT(0) + #define PLL3_RG_RPHYPLL_TSTOD_EN BIT(1) + #define PLL3_RG_RPHYPLL_TSTFM_EN BIT(2) + #define PLL3_RG_RPHYPLL_TSTCK_EN BIT(3) + #define PLL3_RG_RPHYPLL_TST_EN BIT(4) + #define PLL3_RG_RPHYPLL_TSTLVROD_EN BIT(5) + #define PLL3_RG_RPHYPLL_TST_SEL GENMASK(11, 8) +#define PLL4 0x0000000c + #define PLL4_RG_RPHYPLL_RESETB BIT(16) + #define PLL4_RG_RPHYPLL_ATPG_EN BIT(17) + #define PLL4_RG_RPHYPLL_MCK8X_SEL BIT(18) + #define PLL4_PLL4_RFU BIT(19) + #define PLL4_RG_RPHYPLL_SER_MODE BIT(20) + #define PLL4_RG_RPHYPLL_AD_MCK8X_EN BIT(21) + #define PLL4_RG_RPHYPLL_ADA_MCK8X_EN BIT(22) + #define PLL4_RESERVED_0X0C BIT(24) +#define PLL5 0x00000010 + #define PLL5_RESERVED_0X010 GENMASK(31, 0) +#define PLL6 0x00000014 + #define PLL6_RESERVED_0X014 GENMASK(31, 0) +#define PLL7 0x00000018 + #define PLL7_RESERVED_0X018 GENMASK(31, 0) +#define PLL8 0x0000001c + #define PLL8_RESERVED_0X01C GENMASK(31, 0) +#define PLL9 0x00000020 + #define PLL9_RESERVED_0X020 GENMASK(31, 0) +#define PLL10 0x00000024 + #define PLL10_RESERVED_0X024 GENMASK(31, 0) +#define PLL11 0x00000028 + #define PLL11_RESERVED_0X028 GENMASK(31, 0) +#define PLL12 0x0000002c + #define PLL12_RESERVED_0X02C GENMASK(31, 0) +#define PLL13 0x00000030 + #define PLL13_RESERVED_0X030 GENMASK(31, 0) +#define PLL14 0x00000034 + #define PLL14_RESERVED_0X034 GENMASK(31, 0) +#define PLL15 0x00000038 + #define PLL15_RESERVED_0X038 GENMASK(31, 0) +#define PLL16 0x0000003c + #define PLL16_RESERVED_0X03C GENMASK(31, 0) +#define SHU1_PLL0 0x00000d80 + #define SHU1_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0) + #define SHU1_PLL0_RG_RPHYPLL_LOAD_EN BIT(19) +#define SHU1_PLL1 0x00000d84 + #define SHU1_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0) + #define SHU1_PLL1_SHU1_PLL1_RFU GENMASK(3, 1) + #define SHU1_PLL1_R_SHU_AUTO_PLL_MUX BIT(4) + #define SHU1_PLL1_RESERVED_0XD84 GENMASK(31, 5) +#define SHU1_PLL2 0x00000d88 + #define SHU1_PLL2_RG_RCLRPLL_LOAD_EN BIT(19) +#define SHU1_PLL3 0x00000d8c + #define SHU1_PLL3_RESERVED_0XD8C GENMASK(31, 0) +#define SHU1_PLL4 0x00000d90 + #define SHU1_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0) + #define SHU1_PLL4_RG_RPHYPLL_FS GENMASK(19, 18) + #define SHU1_PLL4_RG_RPHYPLL_BW GENMASK(22, 20) + #define SHU1_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24) + #define SHU1_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26) + #define SHU1_PLL4_RG_RPHYPLL_BLP BIT(29) + #define SHU1_PLL4_RG_RPHYPLL_BR BIT(30) + #define SHU1_PLL4_RG_RPHYPLL_BP BIT(31) +#define SHU1_PLL5 0x00000d94 + #define SHU1_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0) + #define SHU1_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1) + #define SHU1_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16) +#define SHU1_PLL6 0x00000d98 + #define SHU1_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0) + #define SHU1_PLL6_RG_RCLRPLL_FS GENMASK(19, 18) + #define SHU1_PLL6_RG_RCLRPLL_BW GENMASK(22, 20) + #define SHU1_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24) + #define SHU1_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26) + #define SHU1_PLL6_RG_RCLRPLL_BLP BIT(29) + #define SHU1_PLL6_RG_RCLRPLL_BR BIT(30) + #define SHU1_PLL6_RG_RCLRPLL_BP BIT(31) +#define SHU1_PLL7 0x00000d9c + #define SHU1_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0) + #define SHU1_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1) + #define SHU1_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16) +#define SHU1_PLL8 0x00000da0 + #define SHU1_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0) + #define SHU1_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18) +#define SHU1_PLL9 0x00000da4 + #define SHU1_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8) + #define SHU1_PLL9_RG_RPHYPLL_LVROD_EN BIT(12) + #define SHU1_PLL9_RG_RPHYPLL_MONREF_EN BIT(13) + #define SHU1_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14) + #define SHU1_PLL9_RG_RPHYPLL_MONCK_EN BIT(16) +#define SHU1_PLL10 0x00000da8 + #define SHU1_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0) + #define SHU1_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18) +#define SHU1_PLL11 0x00000dac + #define SHU1_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8) + #define SHU1_PLL11_RG_RCLRPLL_LVROD_EN BIT(12) + #define SHU1_PLL11_RG_RCLRPLL_MONREF_EN BIT(13) + #define SHU1_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14) + #define SHU1_PLL11_RG_RCLRPLL_MONCK_EN BIT(16) +#define SHU1_PLL12 0x00000db0 + #define SHU1_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0) + #define SHU1_PLL12_RG_RCLRPLL_BYPASS BIT(6) + #define SHU1_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7) + #define SHU1_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8) + #define SHU1_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15) + #define SHU1_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16) + #define SHU1_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22) +#define SHU1_PLL13 0x00000db4 + #define SHU1_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0) + #define SHU1_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8) + #define SHU1_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16) + #define SHU1_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24) +#define SHU1_PLL14 0x00000db8 + #define SHU1_PLL14_RG_RPHYPLL_SDM_HREN BIT(0) + #define SHU1_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU1_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU1_PLL15 0x00000dbc + #define SHU1_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU1_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU1_PLL20 0x00000dd0 + #define SHU1_PLL20_RG_RCLRPLL_SDM_HREN BIT(0) + #define SHU1_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU1_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU1_PLL21 0x00000dd4 + #define SHU1_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU1_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU2_PLL0 0x00001280 + #define SHU2_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0) + #define SHU2_PLL0_RG_RPHYPLL_LOAD_EN BIT(19) +#define SHU2_PLL1 0x00001284 + #define SHU2_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0) + #define SHU2_PLL1_SHU2_PLL1_RFU GENMASK(3, 1) + #define SHU2_PLL1_R_SHU_AUTO_PLL_MUX BIT(4) + #define SHU2_PLL1_RESERVED_0X1284 GENMASK(31, 5) +#define SHU2_PLL2 0x00001288 + #define SHU2_PLL2_RG_RCLRPLL_LOAD_EN BIT(19) +#define SHU2_PLL3 0x0000128c + #define SHU2_PLL3_RESERVED_0X128C GENMASK(31, 0) +#define SHU2_PLL4 0x00001290 + #define SHU2_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0) + #define SHU2_PLL4_RG_RPHYPLL_FS GENMASK(19, 18) + #define SHU2_PLL4_RG_RPHYPLL_BW GENMASK(22, 20) + #define SHU2_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24) + #define SHU2_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26) + #define SHU2_PLL4_RG_RPHYPLL_BLP BIT(29) + #define SHU2_PLL4_RG_RPHYPLL_BR BIT(30) + #define SHU2_PLL4_RG_RPHYPLL_BP BIT(31) +#define SHU2_PLL5 0x00001294 + #define SHU2_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0) + #define SHU2_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1) + #define SHU2_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16) +#define SHU2_PLL6 0x00001298 + #define SHU2_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0) + #define SHU2_PLL6_RG_RCLRPLL_FS GENMASK(19, 18) + #define SHU2_PLL6_RG_RCLRPLL_BW GENMASK(22, 20) + #define SHU2_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24) + #define SHU2_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26) + #define SHU2_PLL6_RG_RCLRPLL_BLP BIT(29) + #define SHU2_PLL6_RG_RCLRPLL_BR BIT(30) + #define SHU2_PLL6_RG_RCLRPLL_BP BIT(31) +#define SHU2_PLL7 0x0000129c + #define SHU2_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0) + #define SHU2_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1) + #define SHU2_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16) +#define SHU2_PLL8 0x000012a0 + #define SHU2_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0) + #define SHU2_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18) +#define SHU2_PLL9 0x000012a4 + #define SHU2_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8) + #define SHU2_PLL9_RG_RPHYPLL_LVROD_EN BIT(12) + #define SHU2_PLL9_RG_RPHYPLL_MONREF_EN BIT(13) + #define SHU2_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14) + #define SHU2_PLL9_RG_RPHYPLL_MONCK_EN BIT(16) +#define SHU2_PLL10 0x000012a8 + #define SHU2_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0) + #define SHU2_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18) +#define SHU2_PLL11 0x000012ac + #define SHU2_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8) + #define SHU2_PLL11_RG_RCLRPLL_LVROD_EN BIT(12) + #define SHU2_PLL11_RG_RCLRPLL_MONREF_EN BIT(13) + #define SHU2_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14) + #define SHU2_PLL11_RG_RCLRPLL_MONCK_EN BIT(16) +#define SHU2_PLL12 0x000012b0 + #define SHU2_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0) + #define SHU2_PLL12_RG_RCLRPLL_BYPASS BIT(6) + #define SHU2_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7) + #define SHU2_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8) + #define SHU2_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15) + #define SHU2_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16) + #define SHU2_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22) +#define SHU2_PLL13 0x000012b4 + #define SHU2_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0) + #define SHU2_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8) + #define SHU2_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16) + #define SHU2_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24) +#define SHU2_PLL14 0x000012b8 + #define SHU2_PLL14_RG_RPHYPLL_SDM_HREN BIT(0) + #define SHU2_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU2_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU2_PLL15 0x000012bc + #define SHU2_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU2_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU2_PLL20 0x000012d0 + #define SHU2_PLL20_RG_RCLRPLL_SDM_HREN BIT(0) + #define SHU2_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU2_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU2_PLL21 0x000012d4 + #define SHU2_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU2_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU3_PLL0 0x00001780 + #define SHU3_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0) + #define SHU3_PLL0_RG_RPHYPLL_LOAD_EN BIT(19) +#define SHU3_PLL1 0x00001784 + #define SHU3_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0) + #define SHU3_PLL1_SHU3_PLL1_RFU GENMASK(3, 1) + #define SHU3_PLL1_R_SHU_AUTO_PLL_MUX BIT(4) + #define SHU3_PLL1_RESERVED_0X1784 GENMASK(31, 5) +#define SHU3_PLL2 0x00001788 + #define SHU3_PLL2_RG_RCLRPLL_LOAD_EN BIT(19) +#define SHU3_PLL3 0x0000178c + #define SHU3_PLL3_RESERVED_0X178C GENMASK(31, 0) +#define SHU3_PLL4 0x00001790 + #define SHU3_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0) + #define SHU3_PLL4_RG_RPHYPLL_FS GENMASK(19, 18) + #define SHU3_PLL4_RG_RPHYPLL_BW GENMASK(22, 20) + #define SHU3_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24) + #define SHU3_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26) + #define SHU3_PLL4_RG_RPHYPLL_BLP BIT(29) + #define SHU3_PLL4_RG_RPHYPLL_BR BIT(30) + #define SHU3_PLL4_RG_RPHYPLL_BP BIT(31) +#define SHU3_PLL5 0x00001794 + #define SHU3_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0) + #define SHU3_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1) + #define SHU3_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16) +#define SHU3_PLL6 0x00001798 + #define SHU3_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0) + #define SHU3_PLL6_RG_RCLRPLL_FS GENMASK(19, 18) + #define SHU3_PLL6_RG_RCLRPLL_BW GENMASK(22, 20) + #define SHU3_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24) + #define SHU3_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26) + #define SHU3_PLL6_RG_RCLRPLL_BLP BIT(29) + #define SHU3_PLL6_RG_RCLRPLL_BR BIT(30) + #define SHU3_PLL6_RG_RCLRPLL_BP BIT(31) +#define SHU3_PLL7 0x0000179c + #define SHU3_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0) + #define SHU3_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1) + #define SHU3_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16) +#define SHU3_PLL8 0x000017a0 + #define SHU3_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0) + #define SHU3_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18) +#define SHU3_PLL9 0x000017a4 + #define SHU3_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8) + #define SHU3_PLL9_RG_RPHYPLL_LVROD_EN BIT(12) + #define SHU3_PLL9_RG_RPHYPLL_MONREF_EN BIT(13) + #define SHU3_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14) + #define SHU3_PLL9_RG_RPHYPLL_MONCK_EN BIT(16) +#define SHU3_PLL10 0x000017a8 + #define SHU3_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0) + #define SHU3_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18) +#define SHU3_PLL11 0x000017ac + #define SHU3_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8) + #define SHU3_PLL11_RG_RCLRPLL_LVROD_EN BIT(12) + #define SHU3_PLL11_RG_RCLRPLL_MONREF_EN BIT(13) + #define SHU3_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14) + #define SHU3_PLL11_RG_RCLRPLL_MONCK_EN BIT(16) +#define SHU3_PLL12 0x000017b0 + #define SHU3_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0) + #define SHU3_PLL12_RG_RCLRPLL_BYPASS BIT(6) + #define SHU3_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7) + #define SHU3_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8) + #define SHU3_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15) + #define SHU3_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16) + #define SHU3_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22) +#define SHU3_PLL13 0x000017b4 + #define SHU3_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0) + #define SHU3_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8) + #define SHU3_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16) + #define SHU3_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24) +#define SHU3_PLL14 0x000017b8 + #define SHU3_PLL14_RG_RPHYPLL_SDM_HREN BIT(0) + #define SHU3_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU3_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU3_PLL15 0x000017bc + #define SHU3_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU3_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU3_PLL20 0x000017d0 + #define SHU3_PLL20_RG_RCLRPLL_SDM_HREN BIT(0) + #define SHU3_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU3_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU3_PLL21 0x000017d4 + #define SHU3_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU3_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU4_PLL0 0x00001c80 + #define SHU4_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0) + #define SHU4_PLL0_RG_RPHYPLL_LOAD_EN BIT(19) +#define SHU4_PLL1 0x00001c84 + #define SHU4_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0) + #define SHU4_PLL1_SHU4_PLL1_RFU GENMASK(3, 1) + #define SHU4_PLL1_R_SHU_AUTO_PLL_MUX BIT(4) + #define SHU4_PLL1_RESERVED_0X1C84 GENMASK(31, 5) +#define SHU4_PLL2 0x00001c88 + #define SHU4_PLL2_RG_RCLRPLL_LOAD_EN BIT(19) +#define SHU4_PLL3 0x00001c8c + #define SHU4_PLL3_RESERVED_0X1C8C GENMASK(31, 0) +#define SHU4_PLL4 0x00001c90 + #define SHU4_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0) + #define SHU4_PLL4_RG_RPHYPLL_FS GENMASK(19, 18) + #define SHU4_PLL4_RG_RPHYPLL_BW GENMASK(22, 20) + #define SHU4_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24) + #define SHU4_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26) + #define SHU4_PLL4_RG_RPHYPLL_BLP BIT(29) + #define SHU4_PLL4_RG_RPHYPLL_BR BIT(30) + #define SHU4_PLL4_RG_RPHYPLL_BP BIT(31) +#define SHU4_PLL5 0x00001c94 + #define SHU4_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0) + #define SHU4_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1) + #define SHU4_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16) +#define SHU4_PLL6 0x00001c98 + #define SHU4_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0) + #define SHU4_PLL6_RG_RCLRPLL_FS GENMASK(19, 18) + #define SHU4_PLL6_RG_RCLRPLL_BW GENMASK(22, 20) + #define SHU4_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24) + #define SHU4_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26) + #define SHU4_PLL6_RG_RCLRPLL_BLP BIT(29) + #define SHU4_PLL6_RG_RCLRPLL_BR BIT(30) + #define SHU4_PLL6_RG_RCLRPLL_BP BIT(31) +#define SHU4_PLL7 0x00001c9c + #define SHU4_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0) + #define SHU4_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1) + #define SHU4_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16) +#define SHU4_PLL8 0x00001ca0 + #define SHU4_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0) + #define SHU4_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18) +#define SHU4_PLL9 0x00001ca4 + #define SHU4_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8) + #define SHU4_PLL9_RG_RPHYPLL_LVROD_EN BIT(12) + #define SHU4_PLL9_RG_RPHYPLL_MONREF_EN BIT(13) + #define SHU4_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14) + #define SHU4_PLL9_RG_RPHYPLL_MONCK_EN BIT(16) +#define SHU4_PLL10 0x00001ca8 + #define SHU4_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0) + #define SHU4_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18) +#define SHU4_PLL11 0x00001cac + #define SHU4_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8) + #define SHU4_PLL11_RG_RCLRPLL_LVROD_EN BIT(12) + #define SHU4_PLL11_RG_RCLRPLL_MONREF_EN BIT(13) + #define SHU4_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14) + #define SHU4_PLL11_RG_RCLRPLL_MONCK_EN BIT(16) +#define SHU4_PLL12 0x00001cb0 + #define SHU4_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0) + #define SHU4_PLL12_RG_RCLRPLL_BYPASS BIT(6) + #define SHU4_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7) + #define SHU4_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8) + #define SHU4_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15) + #define SHU4_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16) + #define SHU4_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22) +#define SHU4_PLL13 0x00001cb4 + #define SHU4_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0) + #define SHU4_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8) + #define SHU4_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16) + #define SHU4_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24) +#define SHU4_PLL14 0x00001cb8 + #define SHU4_PLL14_RG_RPHYPLL_SDM_HREN BIT(0) + #define SHU4_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU4_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU4_PLL15 0x00001cbc + #define SHU4_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU4_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU4_PLL20 0x00001cd0 + #define SHU4_PLL20_RG_RCLRPLL_SDM_HREN BIT(0) + #define SHU4_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU4_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU4_PLL21 0x00001cd4 + #define SHU4_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU4_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16) + +#endif /*__DDRPHY_PLL_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h b/src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h new file mode 100644 index 0000000000..10cda8c9e4 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h @@ -0,0 +1,4604 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_WO_PLL_REG_H__ +#define __DDRPHY_WO_PLL_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define B0_DLL_ARPI0 0x00000080 + #define B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0 BIT(1) + #define B0_DLL_ARPI0_RG_ARPI_RESETB_B0 BIT(3) + #define B0_DLL_ARPI0_RG_ARPI_LS_EN_B0 BIT(4) + #define B0_DLL_ARPI0_RG_ARPI_LS_SEL_B0 BIT(5) + #define B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0 BIT(6) +#define B0_DLL_ARPI1 0x00000084 + #define B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0 BIT(11) + #define B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0 BIT(13) + #define B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0 BIT(14) + #define B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0 BIT(15) + #define B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0 BIT(17) + #define B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0 BIT(19) + #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT BIT(20) + #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0 BIT(21) + #define B0_DLL_ARPI1_RG_ARPI_SET_UPDN_B0 GENMASK(30, 28) +#define B0_DLL_ARPI2 0x00000088 + #define B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0 BIT(0) + #define B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 BIT(10) + #define B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0 BIT(11) + #define B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0 BIT(13) + #define B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0 BIT(14) + #define B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0 BIT(15) + #define B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 BIT(17) + #define B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0 BIT(19) + #define B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0 BIT(27) + #define B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0 BIT(31) +#define B0_DLL_ARPI3 0x0000008c + #define B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0 BIT(11) + #define B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0 BIT(13) + #define B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0 BIT(14) + #define B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0 BIT(15) + #define B0_DLL_ARPI3_RG_ARPI_FB_EN_B0 BIT(17) + #define B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0 BIT(19) +#define B0_DLL_ARPI4 0x00000090 + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B0 BIT(11) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B0 BIT(13) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B0 BIT(14) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B0 BIT(15) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_FB_B0 BIT(17) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B0 BIT(19) +#define B0_DLL_ARPI5 0x00000094 + #define B0_DLL_ARPI5_RG_ARDLL_DIV_MCTL_B0 GENMASK(3, 2) + #define B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0 GENMASK(7, 4) + #define B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0 BIT(8) + #define B0_DLL_ARPI5_B0_DLL_ARPI5_RFU GENMASK(23, 12) + #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0 BIT(25) + #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0 BIT(26) + #define B0_DLL_ARPI5_B0_DLL_ARPI5_RFU1 BIT(31) +#define B0_DQ0 0x00000098 + #define B0_DQ0_RG_RX_ARDQ0_OFFC_B0 GENMASK(3, 0) + #define B0_DQ0_RG_RX_ARDQ1_OFFC_B0 GENMASK(7, 4) + #define B0_DQ0_RG_RX_ARDQ2_OFFC_B0 GENMASK(11, 8) + #define B0_DQ0_RG_RX_ARDQ3_OFFC_B0 GENMASK(15, 12) + #define B0_DQ0_RG_RX_ARDQ4_OFFC_B0 GENMASK(19, 16) + #define B0_DQ0_RG_RX_ARDQ5_OFFC_B0 GENMASK(23, 20) + #define B0_DQ0_RG_RX_ARDQ6_OFFC_B0 GENMASK(27, 24) + #define B0_DQ0_RG_RX_ARDQ7_OFFC_B0 GENMASK(31, 28) +#define B0_DQ1 0x0000009c + #define B0_DQ1_RG_RX_ARDQM0_OFFC_B0 GENMASK(3, 0) +#define B0_DQ2 0x000000a0 + #define B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0 BIT(16) + #define B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0 BIT(17) + #define B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0 BIT(18) + #define B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0 BIT(19) + #define B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0 BIT(20) + #define B0_DQ2_RG_TX_ARDQ_OE_DIS_B0 BIT(21) +#define B0_DQ3 0x000000a4 + #define B0_DQ3_RG_ARDQ_ATPG_EN_B0 BIT(0) + #define B0_DQ3_RG_RX_ARDQ_SMT_EN_B0 BIT(1) + #define B0_DQ3_RG_TX_ARDQ_EN_B0 BIT(2) + #define B0_DQ3_RG_ARDQ_RESETB_B0 BIT(3) + #define B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0 BIT(5) + #define B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B0 BIT(6) + #define B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0 BIT(7) + #define B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0 BIT(10) + #define B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0 BIT(11) + #define B0_DQ3_RG_RX_ARDQS0_SWAP_EN_B0 BIT(15) +#define B0_DQ4 0x000000a8 + #define B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0 GENMASK(6, 0) + #define B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0 GENMASK(14, 8) + #define B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0 GENMASK(21, 16) + #define B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0 GENMASK(29, 24) +#define B0_DQ5 0x000000ac + #define B0_DQ5_B0_DQ5_RFU GENMASK(7, 0) + #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0 GENMASK(13, 8) + #define B0_DQ5_RG_RX_ARDQ_VREF_EN_B0 BIT(16) + #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0 BIT(17) + #define B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0 GENMASK(23, 20) + #define B0_DQ5_RG_RX_ARDQ_EYE_EN_B0 BIT(24) + #define B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0 BIT(25) + #define B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0 BIT(31) +#define B0_DQ6 0x000000b0 + #define B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0 GENMASK(1, 0) + #define B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0 BIT(2) + #define B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0 BIT(3) + #define B0_DQ6_RG_TX_ARDQ_SER_MODE_B0 BIT(4) + #define B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0 BIT(5) + #define B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0 BIT(6) + #define B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0 BIT(7) + #define B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0 BIT(8) + #define B0_DQ6_RG_RX_ARDQ_O1_SEL_B0 BIT(9) + #define B0_DQ6_RG_RX_ARDQ_JM_SEL_B0 BIT(11) + #define B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0 BIT(12) + #define B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0 GENMASK(15, 14) + #define B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0 BIT(16) + #define B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0 BIT(17) + #define B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0 BIT(18) + #define B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0 BIT(19) + #define B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0 BIT(24) + #define B0_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B0 BIT(28) + #define B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0 BIT(31) +#define B0_DQ7 0x000000b4 + #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0 BIT(0) + #define B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0 BIT(1) + #define B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0 BIT(2) + #define B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0 BIT(3) + #define B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0 BIT(4) + #define B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0 BIT(5) + #define B0_DQ7_RG_TX_ARDQ_PULL_DN_B0 BIT(6) + #define B0_DQ7_RG_TX_ARDQ_PULL_UP_B0 BIT(7) + #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y BIT(16) +#define B0_DQ8 0x000000b8 + #define B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0 BIT(0) + #define B0_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B0 BIT(1) + #define B0_DQ8_RG_TX_ARDQ_CAP_DET_B0 BIT(2) + #define B0_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B0 GENMASK(4, 3) + #define B0_DQ8_RG_ARPI_TX_CG_DQ_EN_B0 BIT(5) + #define B0_DQ8_RG_ARPI_TX_CG_DQM_EN_B0 BIT(6) + #define B0_DQ8_RG_ARPI_TX_CG_DQS_EN_B0 BIT(7) + #define B0_DQ8_RG_RX_ARDQS_BURST_E1_EN_B0 BIT(8) + #define B0_DQ8_RG_RX_ARDQS_BURST_E2_EN_B0 BIT(9) + #define B0_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B0 BIT(10) + #define B0_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B0 BIT(12) + #define B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0 BIT(13) + #define B0_DQ8_RG_ARDLL_RESETB_B0 BIT(15) +#define B0_DQ9 0x000000bc + #define B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0 BIT(0) + #define B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0 BIT(4) + #define B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 BIT(5) + #define B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0 BIT(7) + #define B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 GENMASK(15, 8) + #define B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 GENMASK(18, 16) + #define B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 GENMASK(22, 20) + #define B0_DQ9_R_DMRXDVS_VALID_LAT_B0 GENMASK(26, 24) + #define B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0 GENMASK(30, 28) +#define RFU_0X0C0 0x000000c0 + #define RFU_0X0C0_RESERVED_0X0C0 GENMASK(31, 0) +#define RFU_0X0C4 0x000000c4 + #define RFU_0X0C4_RESERVED_0X0C4 GENMASK(31, 0) +#define RFU_0X0C8 0x000000c8 + #define RFU_0X0C8_RESERVED_0X0C8 GENMASK(31, 0) +#define RFU_0X0CC 0x000000cc + #define RFU_0X0CC_RESERVED_0X0CC GENMASK(31, 0) +#define B0_TX_MCK 0x000000d0 + #define B0_TX_MCK_R_DM_TX_MCK_FRUN_B0 GENMASK(9, 0) +#define RFU_0X0D4 0x000000d4 + #define RFU_0X0D4_RESERVED_0X0D4 GENMASK(31, 0) +#define RFU_0X0D8 0x000000d8 + #define RFU_0X0D8_RESERVED_0X0D8 GENMASK(31, 0) +#define RFU_0X0DC 0x000000dc + #define RFU_0X0DC_RESERVED_0X0DC GENMASK(31, 0) +#define B1_DLL_ARPI0 0x00000100 + #define B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1 BIT(1) + #define B1_DLL_ARPI0_RG_ARPI_RESETB_B1 BIT(3) + #define B1_DLL_ARPI0_RG_ARPI_LS_EN_B1 BIT(4) + #define B1_DLL_ARPI0_RG_ARPI_LS_SEL_B1 BIT(5) + #define B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1 BIT(6) +#define B1_DLL_ARPI1 0x00000104 + #define B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1 BIT(11) + #define B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1 BIT(13) + #define B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1 BIT(14) + #define B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1 BIT(15) + #define B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1 BIT(17) + #define B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1 BIT(19) + #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT BIT(20) + #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1 BIT(21) + #define B1_DLL_ARPI1_RG_ARPI_SET_UPDN_B1 GENMASK(30, 28) +#define B1_DLL_ARPI2 0x00000108 + #define B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1 BIT(0) + #define B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 BIT(10) + #define B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1 BIT(11) + #define B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1 BIT(13) + #define B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1 BIT(14) + #define B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1 BIT(15) + #define B1_DLL_ARPI2_RG_ARPI_CG_FB_B1 BIT(17) + #define B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1 BIT(19) + #define B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1 BIT(27) + #define B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1 BIT(31) +#define B1_DLL_ARPI3 0x0000010c + #define B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1 BIT(11) + #define B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1 BIT(13) + #define B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1 BIT(14) + #define B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1 BIT(15) + #define B1_DLL_ARPI3_RG_ARPI_FB_EN_B1 BIT(17) + #define B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 BIT(19) +#define B1_DLL_ARPI4 0x00000110 + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B1 BIT(11) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B1 BIT(13) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B1 BIT(14) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B1 BIT(15) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_FB_B1 BIT(17) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B1 BIT(19) +#define B1_DLL_ARPI5 0x00000114 + #define B1_DLL_ARPI5_RG_ARDLL_DIV_MCTL_B1 GENMASK(3, 2) + #define B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1 GENMASK(7, 4) + #define B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1 BIT(8) + #define B1_DLL_ARPI5_B1_DLL_ARPI5_RFU GENMASK(23, 12) + #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1 BIT(25) + #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1 BIT(26) + #define B1_DLL_ARPI5_B1_DLL_ARPI5_RFU1 BIT(31) +#define B1_DQ0 0x00000118 + #define B1_DQ0_RG_RX_ARDQ0_OFFC_B1 GENMASK(3, 0) + #define B1_DQ0_RG_RX_ARDQ1_OFFC_B1 GENMASK(7, 4) + #define B1_DQ0_RG_RX_ARDQ2_OFFC_B1 GENMASK(11, 8) + #define B1_DQ0_RG_RX_ARDQ3_OFFC_B1 GENMASK(15, 12) + #define B1_DQ0_RG_RX_ARDQ4_OFFC_B1 GENMASK(19, 16) + #define B1_DQ0_RG_RX_ARDQ5_OFFC_B1 GENMASK(23, 20) + #define B1_DQ0_RG_RX_ARDQ6_OFFC_B1 GENMASK(27, 24) + #define B1_DQ0_RG_RX_ARDQ7_OFFC_B1 GENMASK(31, 28) +#define B1_DQ1 0x0000011c + #define B1_DQ1_RG_RX_ARDQM0_OFFC_B1 GENMASK(3, 0) +#define B1_DQ2 0x00000120 + #define B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1 BIT(16) + #define B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1 BIT(17) + #define B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1 BIT(18) + #define B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1 BIT(19) + #define B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1 BIT(20) + #define B1_DQ2_RG_TX_ARDQ_OE_DIS_B1 BIT(21) +#define B1_DQ3 0x00000124 + #define B1_DQ3_RG_ARDQ_ATPG_EN_B1 BIT(0) + #define B1_DQ3_RG_RX_ARDQ_SMT_EN_B1 BIT(1) + #define B1_DQ3_RG_TX_ARDQ_EN_B1 BIT(2) + #define B1_DQ3_RG_ARDQ_RESETB_B1 BIT(3) + #define B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1 BIT(5) + #define B1_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B1 BIT(6) + #define B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1 BIT(7) + #define B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1 BIT(10) + #define B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1 BIT(11) + #define B1_DQ3_RG_RX_ARDQS0_SWAP_EN_B1 BIT(15) +#define B1_DQ4 0x00000128 + #define B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1 GENMASK(6, 0) + #define B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1 GENMASK(14, 8) + #define B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1 GENMASK(21, 16) + #define B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1 GENMASK(29, 24) +#define B1_DQ5 0x0000012c + #define B1_DQ5_B1_DQ5_RFU GENMASK(7, 0) + #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1 GENMASK(13, 8) + #define B1_DQ5_RG_RX_ARDQ_VREF_EN_B1 BIT(16) + #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1 BIT(17) + #define B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1 GENMASK(23, 20) + #define B1_DQ5_RG_RX_ARDQ_EYE_EN_B1 BIT(24) + #define B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1 BIT(25) + #define B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1 BIT(31) +#define B1_DQ6 0x00000130 + #define B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1 GENMASK(1, 0) + #define B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1 BIT(2) + #define B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1 BIT(3) + #define B1_DQ6_RG_TX_ARDQ_SER_MODE_B1 BIT(4) + #define B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1 BIT(5) + #define B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1 BIT(6) + #define B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1 BIT(7) + #define B1_DQ6_RG_RX_ARDQ_LPBK_EN_B1 BIT(8) + #define B1_DQ6_RG_RX_ARDQ_O1_SEL_B1 BIT(9) + #define B1_DQ6_RG_RX_ARDQ_JM_SEL_B1 BIT(11) + #define B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1 BIT(12) + #define B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1 GENMASK(15, 14) + #define B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1 BIT(16) + #define B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1 BIT(17) + #define B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1 BIT(18) + #define B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1 BIT(19) + #define B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1 BIT(24) + #define B1_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B1 BIT(28) + #define B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1 BIT(31) +#define B1_DQ7 0x00000134 + #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1 BIT(0) + #define B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1 BIT(1) + #define B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1 BIT(2) + #define B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1 BIT(3) + #define B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1 BIT(4) + #define B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 BIT(5) + #define B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 BIT(6) + #define B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 BIT(7) + #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y BIT(16) +#define B1_DQ8 0x00000138 + #define B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1 BIT(0) + #define B1_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B1 BIT(1) + #define B1_DQ8_RG_TX_ARDQ_CAP_DET_B1 BIT(2) + #define B1_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B1 GENMASK(4, 3) + #define B1_DQ8_RG_ARPI_TX_CG_DQ_EN_B1 BIT(5) + #define B1_DQ8_RG_ARPI_TX_CG_DQM_EN_B1 BIT(6) + #define B1_DQ8_RG_ARPI_TX_CG_DQS_EN_B1 BIT(7) + #define B1_DQ8_RG_RX_ARDQS_BURST_E1_EN_B1 BIT(8) + #define B1_DQ8_RG_RX_ARDQS_BURST_E2_EN_B1 BIT(9) + #define B1_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B1 BIT(10) + #define B1_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B1 BIT(12) + #define B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1 BIT(13) + #define B1_DQ8_RG_ARDLL_RESETB_B1 BIT(15) +#define B1_DQ9 0x0000013c + #define B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1 BIT(0) + #define B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1 BIT(4) + #define B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 BIT(5) + #define B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 BIT(7) + #define B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 GENMASK(15, 8) + #define B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 GENMASK(18, 16) + #define B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 GENMASK(22, 20) + #define B1_DQ9_R_DMRXDVS_VALID_LAT_B1 GENMASK(26, 24) + #define B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1 GENMASK(30, 28) +#define RFU_0X140 0x00000140 + #define RFU_0X140_RESERVED_0X140 GENMASK(31, 0) +#define RFU_0X144 0x00000144 + #define RFU_0X144_RESERVED_0X144 GENMASK(31, 0) +#define RFU_0X148 0x00000148 + #define RFU_0X148_RESERVED_0X148 GENMASK(31, 0) +#define RFU_0X14C 0x0000014c + #define RFU_0X14C_RESERVED_0X14C GENMASK(31, 0) +#define B1_TX_MCK 0x00000150 + #define B1_TX_MCK_R_DM_TX_MCK_FRUN_B1 GENMASK(9, 0) +#define RFU_0X154 0x00000154 + #define RFU_0X154_RESERVED_0X154 GENMASK(31, 0) +#define RFU_0X158 0x00000158 + #define RFU_0X158_RESERVED_0X158 GENMASK(31, 0) +#define RFU_0X15C 0x0000015c + #define RFU_0X15C_RESERVED_0X15C GENMASK(31, 0) +#define CA_DLL_ARPI0 0x00000180 + #define CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA BIT(1) + #define CA_DLL_ARPI0_RG_ARPI_RESETB_CA BIT(3) + #define CA_DLL_ARPI0_RG_ARPI_LS_EN_CA BIT(4) + #define CA_DLL_ARPI0_RG_ARPI_LS_SEL_CA BIT(5) + #define CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA BIT(6) +#define CA_DLL_ARPI1 0x00000184 + #define CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN BIT(11) + #define CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN BIT(13) + #define CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN BIT(15) + #define CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN BIT(16) + #define CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA BIT(17) + #define CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA BIT(19) + #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT BIT(20) + #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA BIT(21) + #define CA_DLL_ARPI1_RG_ARPI_SET_UPDN_CA GENMASK(30, 28) +#define CA_DLL_ARPI2 0x00000188 + #define CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA BIT(0) + #define CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA BIT(10) + #define CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN BIT(11) + #define CA_DLL_ARPI2_RG_ARPI_CG_CMD BIT(13) + #define CA_DLL_ARPI2_RG_ARPI_CG_CLK BIT(15) + #define CA_DLL_ARPI2_RG_ARPI_CG_CS BIT(16) + #define CA_DLL_ARPI2_RG_ARPI_CG_FB_CA BIT(17) + #define CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA BIT(19) + #define CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA BIT(27) + #define CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA BIT(31) +#define CA_DLL_ARPI3 0x0000018c + #define CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN BIT(11) + #define CA_DLL_ARPI3_RG_ARPI_CMD_EN BIT(13) + #define CA_DLL_ARPI3_RG_ARPI_CLK_EN BIT(15) + #define CA_DLL_ARPI3_RG_ARPI_CS_EN BIT(16) + #define CA_DLL_ARPI3_RG_ARPI_FB_EN_CA BIT(17) + #define CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA BIT(19) +#define CA_DLL_ARPI4 0x00000190 + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLKIEN BIT(11) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CMD BIT(13) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLK BIT(15) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CS BIT(16) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_FB_CA BIT(17) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_CA BIT(19) +#define CA_DLL_ARPI5 0x00000194 + #define CA_DLL_ARPI5_RG_ARDLL_DIV_MCTL_CA GENMASK(3, 2) + #define CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA GENMASK(7, 4) + #define CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA BIT(8) + #define CA_DLL_ARPI5_CA_DLL_ARPI5_RFU GENMASK(23, 12) + #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA BIT(25) + #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA BIT(26) +#define CA_CMD0 0x00000198 + #define CA_CMD0_RG_RX_ARCA0_OFFC GENMASK(3, 0) + #define CA_CMD0_RG_RX_ARCA1_OFFC GENMASK(7, 4) + #define CA_CMD0_RG_RX_ARCA2_OFFC GENMASK(11, 8) + #define CA_CMD0_RG_RX_ARCA3_OFFC GENMASK(15, 12) + #define CA_CMD0_RG_RX_ARCA4_OFFC GENMASK(19, 16) + #define CA_CMD0_RG_RX_ARCA5_OFFC GENMASK(23, 20) +#define CA_CMD1 0x0000019c + #define CA_CMD1_RG_RX_ARCS0_OFFC GENMASK(3, 0) + #define CA_CMD1_RG_RX_ARCS1_OFFC GENMASK(7, 4) + #define CA_CMD1_RG_RX_ARCS2_OFFC GENMASK(11, 8) + #define CA_CMD1_RG_RX_ARCKE0_OFFC GENMASK(15, 12) + #define CA_CMD1_RG_RX_ARCKE1_OFFC GENMASK(19, 16) + #define CA_CMD1_RG_RX_ARCKE2_OFFC GENMASK(23, 20) +#define CA_CMD2 0x000001a0 + #define CA_CMD2_RG_TX_ARCLK_ODTEN_DIS BIT(16) + #define CA_CMD2_RG_TX_ARCLK_OE_DIS BIT(17) + #define CA_CMD2_RG_TX_ARCMD_ODTEN_DIS BIT(20) + #define CA_CMD2_RG_TX_ARCMD_OE_DIS BIT(21) +#define CA_CMD3 0x000001a4 + #define CA_CMD3_RG_ARCMD_ATPG_EN BIT(0) + #define CA_CMD3_RG_RX_ARCMD_SMT_EN BIT(1) + #define CA_CMD3_RG_TX_ARCMD_EN BIT(2) + #define CA_CMD3_RG_ARCMD_RESETB BIT(3) + #define CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN BIT(5) + #define CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN BIT(7) + #define CA_CMD3_RG_RX_ARCMD_STBENCMP_EN BIT(10) + #define CA_CMD3_RG_RX_ARCMD_OFFC_EN BIT(11) + #define CA_CMD3_RG_RX_ARCLK_SWAP_EN BIT(15) +#define CA_CMD4 0x000001a8 + #define CA_CMD4_RG_RX_ARCLK_EYE_R_DLY GENMASK(6, 0) + #define CA_CMD4_RG_RX_ARCLK_EYE_F_DLY GENMASK(14, 8) + #define CA_CMD4_RG_RX_ARCMD_EYE_R_DLY GENMASK(21, 16) + #define CA_CMD4_RG_RX_ARCMD_EYE_F_DLY GENMASK(29, 24) +#define CA_CMD5 0x000001ac + #define CA_CMD5_CA_CMD5_RFU GENMASK(7, 0) + #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL GENMASK(13, 8) + #define CA_CMD5_RG_RX_ARCMD_VREF_EN BIT(16) + #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN BIT(17) + #define CA_CMD5_RG_RX_ARCMD_EYE_SEL GENMASK(23, 20) + #define CA_CMD5_RG_RX_ARCMD_EYE_EN BIT(24) + #define CA_CMD5_RG_RX_ARCMD_EYE_STBEN_RESETB BIT(25) + #define CA_CMD5_RG_RX_ARCLK_DVS_EN BIT(31) +#define CA_CMD6 0x000001b0 + #define CA_CMD6_RG_RX_ARCMD_BIAS_PS GENMASK(1, 0) + #define CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS BIT(2) + #define CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS BIT(3) + #define CA_CMD6_RG_TX_ARCMD_SER_MODE BIT(4) + #define CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN BIT(5) + #define CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN BIT(6) + #define CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN BIT(7) + #define CA_CMD6_RG_RX_ARCMD_LPBK_EN BIT(8) + #define CA_CMD6_RG_RX_ARCMD_O1_SEL BIT(9) + #define CA_CMD6_RG_RX_ARCMD_JM_SEL BIT(11) + #define CA_CMD6_RG_RX_ARCMD_BIAS_EN BIT(12) + #define CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL GENMASK(15, 14) + #define CA_CMD6_RG_RX_ARCMD_DDR4_SEL BIT(16) + #define CA_CMD6_RG_TX_ARCMD_DDR4_SEL BIT(17) + #define CA_CMD6_RG_RX_ARCMD_DDR3_SEL BIT(18) + #define CA_CMD6_RG_TX_ARCMD_DDR3_SEL BIT(19) + #define CA_CMD6_RG_RX_ARCMD_EYE_DLY_DQS_BYPASS BIT(24) + #define CA_CMD6_RG_RX_ARCMD_EYE_OE_GATE_EN BIT(28) + #define CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL BIT(31) +#define CA_CMD7 0x000001b4 + #define CA_CMD7_RG_TX_ARCLKB_PULL_DN BIT(0) + #define CA_CMD7_RG_TX_ARCLKB_PULL_UP BIT(1) + #define CA_CMD7_RG_TX_ARCLK_PULL_DN BIT(2) + #define CA_CMD7_RG_TX_ARCLK_PULL_UP BIT(3) + #define CA_CMD7_RG_TX_ARCS_PULL_DN BIT(4) + #define CA_CMD7_RG_TX_ARCS_PULL_UP BIT(5) + #define CA_CMD7_RG_TX_ARCMD_PULL_DN BIT(6) + #define CA_CMD7_RG_TX_ARCMD_PULL_UP BIT(7) + #define CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y BIT(16) +#define CA_CMD8 0x000001b8 + #define CA_CMD8_RG_RRESETB_DRVP GENMASK(4, 0) + #define CA_CMD8_RG_RRESETB_DRVN GENMASK(12, 8) + #define CA_CMD8_RG_RX_RRESETB_SMT_EN BIT(16) + #define CA_CMD8_RG_TX_RRESETB_SCAN_IN_EN BIT(17) + #define CA_CMD8_RG_TX_RRESETB_DDR4_SEL BIT(18) + #define CA_CMD8_RG_TX_RRESETB_DDR3_SEL BIT(19) + #define CA_CMD8_RG_TX_RRESETB_PULL_DN BIT(20) + #define CA_CMD8_RG_TX_RRESETB_PULL_UP BIT(21) +#define CA_CMD9 0x000001bc + #define CA_CMD9_RG_TX_ARCMD_EN_LP4P BIT(0) + #define CA_CMD9_RG_TX_ARCMD_EN_CAP_LP4P BIT(1) + #define CA_CMD9_RG_TX_ARCMD_CAP_DET BIT(2) + #define CA_CMD9_RG_TX_ARCMD_CKE_MCK4X_SEL GENMASK(4, 3) + #define CA_CMD9_RG_ARPI_TX_CG_CS_EN BIT(5) + #define CA_CMD9_RG_ARPI_TX_CG_CA_EN BIT(6) + #define CA_CMD9_RG_ARPI_TX_CG_CLK_EN BIT(7) + #define CA_CMD9_RG_RX_ARCLK_DQSIEN_BURST_E1_EN BIT(8) + #define CA_CMD9_RG_RX_ARCLK_DQSIEN_BURST_E2_EN BIT(9) + #define CA_CMD9_RG_RX_ARCLK_DQSSTB_CG_EN BIT(10) + #define CA_CMD9_RG_RX_ARCLK_GATE_EN_MODE BIT(12) + #define CA_CMD9_RG_RX_ARCLK_SER_RST_MODE BIT(13) + #define CA_CMD9_RG_ARDLL_RESETB_CA BIT(15) + #define CA_CMD9_RG_TX_ARCMD_LP3_CKE_SEL BIT(16) + #define CA_CMD9_RG_TX_ARCMD_LP4_CKE_SEL BIT(17) + #define CA_CMD9_RG_TX_ARCMD_LP4X_CKE_SEL BIT(18) + #define CA_CMD9_RG_TX_ARCMD_LSH_DQM_CG_EN BIT(20) + #define CA_CMD9_RG_TX_ARCMD_LSH_DQS_CG_EN BIT(21) + #define CA_CMD9_RG_TX_ARCMD_LSH_DQ_CG_EN BIT(22) + #define CA_CMD9_RG_TX_ARCMD_OE_SUS_EN BIT(24) + #define CA_CMD9_RG_TX_ARCMD_ODTEN_OE_SUS_EN BIT(25) +#define CA_CMD10 0x000001c0 + #define CA_CMD10_RG_RX_ARCMD_STBEN_RESETB BIT(0) + #define CA_CMD10_RG_RX_ARCLK_STBEN_RESETB BIT(4) + #define CA_CMD10_RG_RX_ARCLK_DQSIENMODE BIT(5) + #define CA_CMD10_R_DMRXFIFO_STBENCMP_EN_CA BIT(7) + #define CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA GENMASK(15, 8) + #define CA_CMD10_R_DMDQSIEN_VALID_LAT_CA GENMASK(18, 16) + #define CA_CMD10_R_DMDQSIEN_RDSEL_LAT_CA GENMASK(22, 20) + #define CA_CMD10_R_DMRXDVS_VALID_LAT_CA GENMASK(26, 24) + #define CA_CMD10_R_DMRXDVS_RDSEL_LAT_CA GENMASK(30, 28) +#define RFU_0X1C4 0x000001c4 + #define RFU_0X1C4_RESERVED_0X1C4 GENMASK(31, 0) +#define RFU_0X1C8 0x000001c8 + #define RFU_0X1C8_RESERVED_0X1C8 GENMASK(31, 0) +#define RFU_0X1CC 0x000001cc + #define RFU_0X1CC_RESERVED_0X1CC GENMASK(31, 0) +#define CA_TX_MCK 0x000001d0 + #define CA_TX_MCK_R_DM_TX_MCK_FRUN_CA GENMASK(12, 0) + #define CA_TX_MCK_R_DMRESETB_DRVP_FRPHY GENMASK(25, 21) + #define CA_TX_MCK_R_DMRESETB_DRVN_FRPHY GENMASK(30, 26) + #define CA_TX_MCK_R_DMRESET_FRPHY_OPT BIT(31) +#define RFU_0X1D4 0x000001d4 + #define RFU_0X1D4_RESERVED_0X1D4 GENMASK(31, 0) +#define RFU_0X1D8 0x000001d8 + #define RFU_0X1D8_RESERVED_0X1D8 GENMASK(31, 0) +#define RFU_0X1DC 0x000001dc + #define RFU_0X1DC_RESERVED_0X1DC GENMASK(31, 0) +#define MISC_EXTLB0 0x00000200 + #define MISC_EXTLB0_R_EXTLB_LFSR_INI_0 GENMASK(15, 0) + #define MISC_EXTLB0_R_EXTLB_LFSR_INI_1 GENMASK(31, 16) +#define MISC_EXTLB1 0x00000204 + #define MISC_EXTLB1_R_EXTLB_LFSR_INI_2 GENMASK(15, 0) + #define MISC_EXTLB1_R_EXTLB_LFSR_INI_3 GENMASK(31, 16) +#define MISC_EXTLB2 0x00000208 + #define MISC_EXTLB2_R_EXTLB_LFSR_INI_4 GENMASK(15, 0) + #define MISC_EXTLB2_R_EXTLB_LFSR_INI_5 GENMASK(31, 16) +#define MISC_EXTLB3 0x0000020c + #define MISC_EXTLB3_R_EXTLB_LFSR_INI_6 GENMASK(15, 0) + #define MISC_EXTLB3_R_EXTLB_LFSR_INI_7 GENMASK(31, 16) +#define MISC_EXTLB4 0x00000210 + #define MISC_EXTLB4_R_EXTLB_LFSR_INI_8 GENMASK(15, 0) + #define MISC_EXTLB4_R_EXTLB_LFSR_INI_9 GENMASK(31, 16) +#define MISC_EXTLB5 0x00000214 + #define MISC_EXTLB5_R_EXTLB_LFSR_INI_10 GENMASK(15, 0) + #define MISC_EXTLB5_R_EXTLB_LFSR_INI_11 GENMASK(31, 16) +#define MISC_EXTLB6 0x00000218 + #define MISC_EXTLB6_R_EXTLB_LFSR_INI_12 GENMASK(15, 0) + #define MISC_EXTLB6_R_EXTLB_LFSR_INI_13 GENMASK(31, 16) +#define MISC_EXTLB7 0x0000021c + #define MISC_EXTLB7_R_EXTLB_LFSR_INI_14 GENMASK(15, 0) + #define MISC_EXTLB7_R_EXTLB_LFSR_INI_15 GENMASK(31, 16) +#define MISC_EXTLB8 0x00000220 + #define MISC_EXTLB8_R_EXTLB_LFSR_INI_16 GENMASK(15, 0) + #define MISC_EXTLB8_R_EXTLB_LFSR_INI_17 GENMASK(31, 16) +#define MISC_EXTLB9 0x00000224 + #define MISC_EXTLB9_R_EXTLB_LFSR_INI_18 GENMASK(15, 0) + #define MISC_EXTLB9_R_EXTLB_LFSR_INI_19 GENMASK(31, 16) +#define MISC_EXTLB10 0x00000228 + #define MISC_EXTLB10_R_EXTLB_LFSR_INI_20 GENMASK(15, 0) + #define MISC_EXTLB10_R_EXTLB_LFSR_INI_21 GENMASK(31, 16) +#define MISC_EXTLB11 0x0000022c + #define MISC_EXTLB11_R_EXTLB_LFSR_INI_22 GENMASK(15, 0) + #define MISC_EXTLB11_R_EXTLB_LFSR_INI_23 GENMASK(31, 16) +#define MISC_EXTLB12 0x00000230 + #define MISC_EXTLB12_R_EXTLB_LFSR_INI_24 GENMASK(15, 0) + #define MISC_EXTLB12_R_EXTLB_LFSR_INI_25 GENMASK(31, 16) +#define MISC_EXTLB13 0x00000234 + #define MISC_EXTLB13_R_EXTLB_LFSR_INI_26 GENMASK(15, 0) + #define MISC_EXTLB13_R_EXTLB_LFSR_INI_27 GENMASK(31, 16) +#define MISC_EXTLB14 0x00000238 + #define MISC_EXTLB14_R_EXTLB_LFSR_INI_28 GENMASK(15, 0) + #define MISC_EXTLB14_R_EXTLB_LFSR_INI_29 GENMASK(31, 16) +#define MISC_EXTLB15 0x0000023c + #define MISC_EXTLB15_R_EXTLB_LFSR_INI_30 GENMASK(15, 0) + #define MISC_EXTLB15_MISC_EXTLB15_RFU GENMASK(31, 16) +#define MISC_EXTLB16 0x00000240 + #define MISC_EXTLB16_R_EXTLB_LFSR_TAP GENMASK(15, 0) + #define MISC_EXTLB16_R_EXTLB_OE_DQB0_ON BIT(16) + #define MISC_EXTLB16_R_EXTLB_OE_DQM0_ON BIT(17) + #define MISC_EXTLB16_R_EXTLB_OE_DQS0_ON BIT(18) + #define MISC_EXTLB16_R_EXTLB_OE_DQB1_ON BIT(19) + #define MISC_EXTLB16_R_EXTLB_OE_DQM1_ON BIT(20) + #define MISC_EXTLB16_R_EXTLB_OE_DQS1_ON BIT(21) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQB0_ON BIT(22) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQM0_ON BIT(23) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQS0_ON BIT(24) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQB1_ON BIT(25) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQM1_ON BIT(26) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQS1_ON BIT(27) +#define MISC_EXTLB17 0x00000244 + #define MISC_EXTLB17_R_EXTLB BIT(0) + #define MISC_EXTLB17_R_EXTLB_RX_SWRST BIT(1) + #define MISC_EXTLB17_R_EXTLB_TX_EN BIT(2) + #define MISC_EXTLB17_R_EXTLB_TX_EN_OTHERCH_SEL BIT(3) + #define MISC_EXTLB17_R_INTLB_ARCLK_MUXSEL BIT(4) + #define MISC_EXTLB17_R_INTLB_DRDF_CA_MUXSEL BIT(5) + #define MISC_EXTLB17_R_EXTLB_TX_PRE_ON BIT(7) + #define MISC_EXTLB17_R_EXTLB_RX_LENGTH_M1 GENMASK(31, 8) +#define MISC_EXTLB18 0x00000248 + #define MISC_EXTLB18_R_TX_EN_SRC_SEL BIT(0) + #define MISC_EXTLB18_R_OTH_TX_EN_SRC_SEL BIT(1) + #define MISC_EXTLB18_R_LPBK_DQ_MODE_FOR_CA BIT(3) + #define MISC_EXTLB18_R_LPBK_DQ_TX_MODE BIT(4) + #define MISC_EXTLB18_R_LPBK_CA_TX_MODE BIT(5) + #define MISC_EXTLB18_R_LPBK_DQ_RX_MODE BIT(8) + #define MISC_EXTLB18_R_LPBK_CA_RX_MODE BIT(9) + #define MISC_EXTLB18_R_TX_TRIG_SRC_SEL GENMASK(19, 16) + #define MISC_EXTLB18_R_OTH_TX_TRIG_SRC_SEL GENMASK(23, 20) +#define MISC_EXTLB19 0x0000024c + #define MISC_EXTLB19_R_EXTLB_LFSR_ENABLE BIT(0) + #define MISC_EXTLB19_R_EXTLB_SSO_ENABLE BIT(1) + #define MISC_EXTLB19_R_EXTLB_XTALK_ENABLE BIT(2) + #define MISC_EXTLB19_R_EXTLB_LEADLAG_DBG_ENABLE BIT(3) + #define MISC_EXTLB19_R_EXTLB_DBG_SEL GENMASK(20, 16) + #define MISC_EXTLB19_R_LPBK_DC_TOG_MODE BIT(23) + #define MISC_EXTLB19_R_LPBK_DC_TOG_TIMER GENMASK(31, 24) +#define MISC_EXTLB20 0x00000250 + #define MISC_EXTLB20_R_XTALK_TX_00_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB20_R_XTALK_TX_01_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB20_R_XTALK_TX_02_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB20_R_XTALK_TX_03_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB20_R_XTALK_TX_04_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB20_R_XTALK_TX_05_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB20_R_XTALK_TX_06_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB20_R_XTALK_TX_07_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB21 0x00000254 + #define MISC_EXTLB21_R_XTALK_TX_08_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB21_R_XTALK_TX_09_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB21_R_XTALK_TX_10_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB21_R_XTALK_TX_11_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB21_R_XTALK_TX_12_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB21_R_XTALK_TX_13_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB21_R_XTALK_TX_14_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB21_R_XTALK_TX_15_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB22 0x00000258 + #define MISC_EXTLB22_R_XTALK_TX_16_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB22_R_XTALK_TX_17_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB22_R_XTALK_TX_18_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB22_R_XTALK_TX_19_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB22_R_XTALK_TX_20_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB22_R_XTALK_TX_21_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB22_R_XTALK_TX_22_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB22_R_XTALK_TX_23_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB23 0x0000025c + #define MISC_EXTLB23_R_XTALK_TX_24_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB23_R_XTALK_TX_25_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB23_R_XTALK_TX_26_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB23_R_XTALK_TX_27_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB23_R_XTALK_TX_28_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB23_R_XTALK_TX_29_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB23_R_XTALK_TX_30_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB23_R_XTALK_TX_31_TOG_CYCLE GENMASK(31, 28) +#define DVFS_EMI_CLK 0x00000260 + #define DVFS_EMI_CLK_RG_DLL_SHUFFLE BIT(24) + #define DVFS_EMI_CLK_RG_52M_104M_SEL BIT(29) + #define DVFS_EMI_CLK_RG_GATING_EMI_NEW GENMASK(31, 30) +#define MISC_VREF_CTRL 0x00000264 + #define MISC_VREF_CTRL_VREF_CTRL_RFU GENMASK(30, 16) + #define MISC_VREF_CTRL_RG_RVREF_VREF_EN BIT(31) +#define MISC_IMP_CTRL0 0x00000268 + #define MISC_IMP_CTRL0_RG_IMP_OCD_PUCMP_EN BIT(3) + #define MISC_IMP_CTRL0_RG_IMP_EN BIT(4) + #define MISC_IMP_CTRL0_RG_RIMP_DDR4_SEL BIT(5) + #define MISC_IMP_CTRL0_RG_RIMP_DDR3_SEL BIT(6) +#define MISC_IMP_CTRL1 0x0000026c + #define MISC_IMP_CTRL1_RG_RIMP_BIAS_EN BIT(4) + #define MISC_IMP_CTRL1_RG_RIMP_ODT_EN BIT(5) + #define MISC_IMP_CTRL1_RG_RIMP_PRE_EN BIT(6) + #define MISC_IMP_CTRL1_RG_RIMP_VREF_EN BIT(7) + #define MISC_IMP_CTRL1_RG_RIMP_DRV05 BIT(16) + #define MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT BIT(31) +#define MISC_SHU_OPT 0x00000270 + #define MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN BIT(0) + #define MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN GENMASK(3, 2) + #define MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN BIT(8) + #define MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN GENMASK(11, 10) + #define MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN BIT(16) + #define MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN GENMASK(19, 18) +#define MISC_SPM_CTRL0 0x00000274 + #define MISC_SPM_CTRL0_PHY_SPM_CTL0 GENMASK(31, 0) +#define MISC_SPM_CTRL1 0x00000278 + #define MISC_SPM_CTRL1_RG_ARDMSUS_10 BIT(0) + #define MISC_SPM_CTRL1_RG_ARDMSUS_10_B0 BIT(1) + #define MISC_SPM_CTRL1_RG_ARDMSUS_10_B1 BIT(2) + #define MISC_SPM_CTRL1_RG_ARDMSUS_10_CA BIT(3) + #define MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL BIT(16) + #define MISC_SPM_CTRL1_RG_DR_SHU_LEVEL GENMASK(18, 17) + #define MISC_SPM_CTRL1_RG_PHYPLL_SHU_EN BIT(19) + #define MISC_SPM_CTRL1_RG_PHYPLL2_SHU_EN BIT(20) + #define MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW BIT(21) + #define MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW BIT(22) + #define MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE BIT(23) + #define MISC_SPM_CTRL1_RG_DR_SHU_EN BIT(24) + #define MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH0_EN BIT(25) + #define MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH1_EN BIT(26) +#define MISC_SPM_CTRL2 0x0000027c + #define MISC_SPM_CTRL2_PHY_SPM_CTL2 GENMASK(31, 0) +#define MISC_SPM_CTRL3 0x00000280 + #define MISC_SPM_CTRL3_PHY_SPM_CTL3 GENMASK(31, 0) +#define MISC_CG_CTRL0 0x00000284 + #define MISC_CG_CTRL0_W_CHG_MEM BIT(0) + #define MISC_CG_CTRL0_CLK_MEM_SEL GENMASK(5, 4) + #define MISC_CG_CTRL0_CLK_MEM_INV BIT(6) + #define MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE BIT(8) + #define MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE BIT(9) + #define MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE BIT(10) + #define MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE BIT(11) + #define MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE BIT(12) + #define MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE BIT(13) + #define MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE BIT(14) + #define MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE BIT(15) + #define MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE BIT(16) + #define MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE BIT(17) + #define MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN BIT(18) + #define MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE BIT(19) + #define MISC_CG_CTRL0_RG_CG_DRAMC_CHB_CK_OFF BIT(20) + #define MISC_CG_CTRL0_RG_DBG_OUT_SEL BIT(21) + #define MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF BIT(22) + #define MISC_CG_CTRL0_RG_DA_RREF_CK_SEL BIT(28) + #define MISC_CG_CTRL0_RG_FREERUN_MCK_CG BIT(29) + #define MISC_CG_CTRL0_RG_FREERUN_MCK_CHB_SEL BIT(30) + #define MISC_CG_CTRL0_CLK_MEM_DFS_CFG GENMASK(31, 0) //cc add +#define MISC_CG_CTRL1 0x00000288 + #define MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL GENMASK(31, 0) +#define MISC_CG_CTRL2 0x0000028c + #define MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG BIT(0) + #define MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL GENMASK(5, 1) + #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON BIT(6) + #define MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN BIT(7) + #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN BIT(8) + #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT GENMASK(15, 9) + #define MISC_CG_CTRL2_RG_MEM_DCM_FSEL GENMASK(20, 16) + #define MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL GENMASK(25, 21) + #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF BIT(26) + #define MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE BIT(28) + #define MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE BIT(29) + #define MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE BIT(31) + #define MISC_CG_CTRL2_RG_MEM_DCM_CTL GENMASK(31, 0) +#define MISC_CG_CTRL3 0x00000290 + #define MISC_CG_CTRL3_R_LBK_CG_CTRL GENMASK(31, 0) +#define MISC_CG_CTRL4 0x00000294 + #define MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL GENMASK(31, 0) +#define MISC_CG_CTRL5 0x00000298 + #define MISC_CG_CTRL5_RESERVE GENMASK(15, 0) + #define MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN BIT(16) + #define MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN BIT(17) + #define MISC_CG_CTRL5_R_CA_DLY_DCM_EN BIT(18) + #define MISC_CG_CTRL5_R_DQ1_PI_DCM_EN BIT(20) + #define MISC_CG_CTRL5_R_DQ0_PI_DCM_EN BIT(21) + #define MISC_CG_CTRL5_R_CA_PI_DCM_EN BIT(22) +#define MISC_CTRL0 0x0000029c + #define MISC_CTRL0_R_DMDQSIEN_SYNCOPT GENMASK(3, 0) + #define MISC_CTRL0_R_DMDQSIEN_OUTSEL GENMASK(7, 4) + #define MISC_CTRL0_R_DMSTBEN_SYNCOPT BIT(8) + #define MISC_CTRL0_R_DMSTBEN_OUTSEL BIT(9) + #define MISC_CTRL0_IMPCAL_CHAB_EN BIT(10) + #define MISC_CTRL0_R_DMVALID_DLY_OPT BIT(11) + #define MISC_CTRL0_R_DMVALID_NARROW_IG BIT(12) + #define MISC_CTRL0_R_DMVALID_DLY GENMASK(15, 13) + #define MISC_CTRL0_R_DMDQSIEN_DEPTH_HALF BIT(16) + #define MISC_CTRL0_R_DMRDSEL_DIV2_OPT BIT(17) + #define MISC_CTRL0_IMPCAL_LP_ECO_OPT BIT(18) + #define MISC_CTRL0_IMPCAL_CDC_ECO_OPT BIT(19) + #define MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT BIT(20) + #define MISC_CTRL0_IMPCAL_CTL_CK_SEL BIT(21) + #define MISC_CTRL0_R_DMDQSIEN_FIFO_EN BIT(24) + #define MISC_CTRL0_R_DMSTBENCMP_FIFO_EN BIT(25) + #define MISC_CTRL0_R_DMSTBENCMP_RK_FIFO_EN BIT(26) + #define MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF BIT(27) + #define MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL BIT(28) + #define MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL BIT(29) + #define MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL BIT(30) + #define MISC_CTRL0_R_STBENCMP_DIV4CK_EN BIT(31) +#define MISC_CTRL1 0x000002a0 + #define MISC_CTRL1_R_DMPHYRST BIT(1) + #define MISC_CTRL1_R_DM_TX_ARCLK_OE BIT(2) + #define MISC_CTRL1_R_DM_TX_ARCMD_OE BIT(3) + #define MISC_CTRL1_R_DMMCTLPLL_CKSEL GENMASK(5, 4) + #define MISC_CTRL1_R_DMMUXCA BIT(6) + #define MISC_CTRL1_R_DMARPIDQ_SW BIT(7) + #define MISC_CTRL1_R_DMPINMUX GENMASK(9, 8) + #define MISC_CTRL1_R_DMARPICA_SW_UPDX BIT(10) + #define MISC_CTRL1_CK_BFE_DCM_EN BIT(11) + #define MISC_CTRL1_R_DMRRESETB_I_OPT BIT(12) + #define MISC_CTRL1_R_DMDA_RRESETB_I BIT(13) + #define MISC_CTRL1_R_DMMUXCA_SEC BIT(14) + #define MISC_CTRL1_R_DQ2DM_SWAP BIT(15) + #define MISC_CTRL1_R_DMDRAMCLKEN0 GENMASK(19, 16) + #define MISC_CTRL1_R_DMDRAMCLKEN1 GENMASK(23, 20) + #define MISC_CTRL1_R_DMDQSIENCG_EN BIT(24) + #define MISC_CTRL1_R_DMSTBENCMP_RK_OPT BIT(25) + #define MISC_CTRL1_R_WL_DOWNSP BIT(26) + #define MISC_CTRL1_R_DMODTDISOE_A BIT(27) + #define MISC_CTRL1_R_DMODTDISOE_B BIT(28) + #define MISC_CTRL1_R_DMODTDISOE_C BIT(29) + #define MISC_CTRL1_R_DMDA_RRESETB_E BIT(31) +#define MISC_CTRL2 0x000002a4 + #define MISC_CTRL2_PLL_SHU_GP GENMASK(1, 0) +#define MISC_CTRL3 0x000002a8 + #define MISC_CTRL3_ARPI_CG_CMD_OPT GENMASK(1, 0) + #define MISC_CTRL3_ARPI_CG_CLK_OPT GENMASK(3, 2) + #define MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT BIT(4) + #define MISC_CTRL3_ARPI_CG_MCK_CA_OPT BIT(5) + #define MISC_CTRL3_ARPI_CG_MCTL_CA_OPT BIT(6) + #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_CA_SEL GENMASK(9, 8) + #define MISC_CTRL3_DRAM_CLK_NEW_CA_EN_SEL GENMASK(15, 12) + #define MISC_CTRL3_ARPI_CG_DQ_OPT GENMASK(17, 16) + #define MISC_CTRL3_ARPI_CG_DQS_OPT GENMASK(19, 18) + #define MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT BIT(20) + #define MISC_CTRL3_ARPI_CG_MCK_DQ_OPT BIT(21) + #define MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT BIT(22) + #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_DQ_SEL GENMASK(25, 24) + #define MISC_CTRL3_R_DDRPHY_COMB_CG_IG BIT(26) + #define MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG BIT(27) + #define MISC_CTRL3_DRAM_CLK_NEW_DQ_EN_SEL GENMASK(31, 28) +#define MISC_CTRL4 0x000002ac + #define MISC_CTRL4_RG_PW_CON_CHA_0 GENMASK(31, 0) +#define MISC_CTRL5 0x000002b0 + #define MISC_CTRL5_RG_PW_CON_CHA_1 GENMASK(31, 0) +#define MISC_EXTLB_RX0 0x000002b4 + #define MISC_EXTLB_RX0_R_EXTLB_LFSR_RX_INI_0 GENMASK(15, 0) + #define MISC_EXTLB_RX0_R_EXTLB_LFSR_RX_INI_1 GENMASK(31, 16) +#define MISC_EXTLB_RX1 0x000002b8 + #define MISC_EXTLB_RX1_R_EXTLB_LFSR_RX_INI_2 GENMASK(15, 0) + #define MISC_EXTLB_RX1_R_EXTLB_LFSR_RX_INI_3 GENMASK(31, 16) +#define MISC_EXTLB_RX2 0x000002bc + #define MISC_EXTLB_RX2_R_EXTLB_LFSR_RX_INI_4 GENMASK(15, 0) + #define MISC_EXTLB_RX2_R_EXTLB_LFSR_RX_INI_5 GENMASK(31, 16) +#define MISC_EXTLB_RX3 0x000002c0 + #define MISC_EXTLB_RX3_R_EXTLB_LFSR_RX_INI_6 GENMASK(15, 0) + #define MISC_EXTLB_RX3_R_EXTLB_LFSR_RX_INI_7 GENMASK(31, 16) +#define MISC_EXTLB_RX4 0x000002c4 + #define MISC_EXTLB_RX4_R_EXTLB_LFSR_RX_INI_8 GENMASK(15, 0) + #define MISC_EXTLB_RX4_R_EXTLB_LFSR_RX_INI_9 GENMASK(31, 16) +#define MISC_EXTLB_RX5 0x000002c8 + #define MISC_EXTLB_RX5_R_EXTLB_LFSR_RX_INI_10 GENMASK(15, 0) + #define MISC_EXTLB_RX5_R_EXTLB_LFSR_RX_INI_11 GENMASK(31, 16) +#define MISC_EXTLB_RX6 0x000002cc + #define MISC_EXTLB_RX6_R_EXTLB_LFSR_RX_INI_12 GENMASK(15, 0) + #define MISC_EXTLB_RX6_R_EXTLB_LFSR_RX_INI_13 GENMASK(31, 16) +#define MISC_EXTLB_RX7 0x000002d0 + #define MISC_EXTLB_RX7_R_EXTLB_LFSR_RX_INI_14 GENMASK(15, 0) + #define MISC_EXTLB_RX7_R_EXTLB_LFSR_RX_INI_15 GENMASK(31, 16) +#define MISC_EXTLB_RX8 0x000002d4 + #define MISC_EXTLB_RX8_R_EXTLB_LFSR_RX_INI_16 GENMASK(15, 0) + #define MISC_EXTLB_RX8_R_EXTLB_LFSR_RX_INI_17 GENMASK(31, 16) +#define MISC_EXTLB_RX9 0x000002d8 + #define MISC_EXTLB_RX9_R_EXTLB_LFSR_RX_INI_18 GENMASK(15, 0) + #define MISC_EXTLB_RX9_R_EXTLB_LFSR_RX_INI_19 GENMASK(31, 16) +#define MISC_EXTLB_RX10 0x000002dc + #define MISC_EXTLB_RX10_R_EXTLB_LFSR_RX_INI_20 GENMASK(15, 0) + #define MISC_EXTLB_RX10_R_EXTLB_LFSR_RX_INI_21 GENMASK(31, 16) +#define MISC_EXTLB_RX11 0x000002e0 + #define MISC_EXTLB_RX11_R_EXTLB_LFSR_RX_INI_22 GENMASK(15, 0) + #define MISC_EXTLB_RX11_R_EXTLB_LFSR_RX_INI_23 GENMASK(31, 16) +#define MISC_EXTLB_RX12 0x000002e4 + #define MISC_EXTLB_RX12_R_EXTLB_LFSR_RX_INI_24 GENMASK(15, 0) + #define MISC_EXTLB_RX12_R_EXTLB_LFSR_RX_INI_25 GENMASK(31, 16) +#define MISC_EXTLB_RX13 0x000002e8 + #define MISC_EXTLB_RX13_R_EXTLB_LFSR_RX_INI_26 GENMASK(15, 0) + #define MISC_EXTLB_RX13_R_EXTLB_LFSR_RX_INI_27 GENMASK(31, 16) +#define MISC_EXTLB_RX14 0x000002ec + #define MISC_EXTLB_RX14_R_EXTLB_LFSR_RX_INI_28 GENMASK(15, 0) + #define MISC_EXTLB_RX14_R_EXTLB_LFSR_RX_INI_29 GENMASK(31, 16) +#define MISC_EXTLB_RX15 0x000002f0 + #define MISC_EXTLB_RX15_R_EXTLB_LFSR_RX_INI_30 GENMASK(15, 0) + #define MISC_EXTLB_RX15_MISC_EXTLB_RX15_RFU GENMASK(31, 16) +#define MISC_EXTLB_RX16 0x000002f4 + #define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_DQB0 GENMASK(6, 0) + #define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_DQB1 GENMASK(14, 8) + #define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_CA GENMASK(22, 16) +#define MISC_EXTLB_RX17 0x000002f8 + #define MISC_EXTLB_RX17_R_XTALK_RX_00_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB_RX17_R_XTALK_RX_01_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB_RX17_R_XTALK_RX_02_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB_RX17_R_XTALK_RX_03_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB_RX17_R_XTALK_RX_04_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB_RX17_R_XTALK_RX_05_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB_RX17_R_XTALK_RX_06_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB_RX17_R_XTALK_RX_07_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB_RX18 0x000002fc + #define MISC_EXTLB_RX18_R_XTALK_RX_08_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB_RX18_R_XTALK_RX_09_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB_RX18_R_XTALK_RX_10_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB_RX18_R_XTALK_RX_11_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB_RX18_R_XTALK_RX_12_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB_RX18_R_XTALK_RX_13_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB_RX18_R_XTALK_RX_14_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB_RX18_R_XTALK_RX_15_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB_RX19 0x00000300 + #define MISC_EXTLB_RX19_R_XTALK_RX_16_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB_RX19_R_XTALK_RX_17_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB_RX19_R_XTALK_RX_18_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB_RX19_R_XTALK_RX_19_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB_RX19_R_XTALK_RX_20_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB_RX19_R_XTALK_RX_21_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB_RX19_R_XTALK_RX_22_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB_RX19_R_XTALK_RX_23_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB_RX20 0x00000304 + #define MISC_EXTLB_RX20_R_XTALK_RX_24_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB_RX20_R_XTALK_RX_25_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB_RX20_R_XTALK_RX_26_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB_RX20_R_XTALK_RX_27_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB_RX20_R_XTALK_RX_28_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB_RX20_R_XTALK_RX_29_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB_RX20_R_XTALK_RX_30_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB_RX20_R_XTALK_RX_31_TOG_CYCLE GENMASK(31, 28) +#define CKMUX_SEL 0x00000308 + #define CKMUX_SEL_R_PHYCTRLMUX BIT(0) + #define CKMUX_SEL_R_PHYCTRLDCM BIT(1) + #define CKMUX_SEL_FB_CK_MUX GENMASK(17, 16) + #define CKMUX_SEL_FMEM_CK_MUX GENMASK(19, 18) +#define RFU_0X30C 0x0000030c + #define RFU_0X30C_RESERVED_0X30C GENMASK(31, 0) +#define RFU_0X310 0x00000310 + #define RFU_0X310_RESERVED_0X310 GENMASK(31, 0) +#define RFU_0X314 0x00000314 + #define RFU_0X314_RESERVED_0X314 GENMASK(31, 0) +#define RFU_0X318 0x00000318 + #define RFU_0X318_RESERVED_0X318 GENMASK(31, 0) +#define RFU_0X31C 0x0000031c + #define RFU_0X31C_RESERVED_0X31C GENMASK(31, 0) +#define RFU_0X320 0x00000320 + #define RFU_0X320_RESERVED_0X320 GENMASK(31, 0) +#define RFU_0X324 0x00000324 + #define RFU_0X324_RESERVED_0X324 GENMASK(31, 0) +#define RFU_0X328 0x00000328 + #define RFU_0X328_RESERVED_0X328 GENMASK(31, 0) +#define RFU_0X32C 0x0000032c + #define RFU_0X32C_RESERVED_0X32C GENMASK(31, 0) +#define RFU_0X330 0x00000330 + #define RFU_0X330_RESERVED_0X330 GENMASK(31, 0) +#define RFU_0X334 0x00000334 + #define RFU_0X334_RESERVED_0X334 GENMASK(31, 0) +#define RFU_0X338 0x00000338 + #define RFU_0X338_RESERVED_0X338 GENMASK(31, 0) +#define RFU_0X33C 0x0000033c + #define RFU_0X33C_RESERVED_0X33C GENMASK(31, 0) +#define MISC_STBERR_RK0_R 0x00000510 + #define MISC_STBERR_RK0_R_STBERR_RK0_R GENMASK(15, 0) + #define MISC_STBERR_RK0_R_STBENERR_ALL BIT(16) + #define MISC_STBERR_RK0_R_RX_ARDQ0_FIFO_STBEN_ERR_B0 BIT(24) + #define MISC_STBERR_RK0_R_RX_ARDQ4_FIFO_STBEN_ERR_B0 BIT(25) + #define MISC_STBERR_RK0_R_RX_ARDQ0_FIFO_STBEN_ERR_B1 BIT(26) + #define MISC_STBERR_RK0_R_RX_ARDQ4_FIFO_STBEN_ERR_B1 BIT(27) + #define MISC_STBERR_RK0_R_RX_ARCA0_FIFO_STBEN_ERR BIT(28) + #define MISC_STBERR_RK0_R_RX_ARCA4_FIFO_STBEN_ERR BIT(29) + #define MISC_STBERR_RK0_R_DA_RPHYPLLGP_CK_SEL BIT(31) +#define MISC_STBERR_RK0_F 0x00000514 + #define MISC_STBERR_RK0_F_STBERR_RK0_F GENMASK(15, 0) +#define MISC_STBERR_RK1_R 0x00000518 + #define MISC_STBERR_RK1_R_STBERR_RK1_R GENMASK(15, 0) +#define MISC_STBERR_RK1_F 0x0000051c + #define MISC_STBERR_RK1_F_STBERR_RK1_F GENMASK(15, 0) +#define MISC_STBERR_RK2_R 0x00000520 + #define MISC_STBERR_RK2_R_STBERR_RK2_R GENMASK(15, 0) +#define MISC_STBERR_RK2_F 0x00000524 + #define MISC_STBERR_RK2_F_STBERR_RK2_F GENMASK(15, 0) +#define MISC_RXDVS0 0x000005e0 + #define MISC_RXDVS0_R_RX_DLY_TRACK_RO_SEL GENMASK(2, 0) + #define MISC_RXDVS0_R_DA_DQX_R_DLY_RO_SEL GENMASK(11, 8) + #define MISC_RXDVS0_R_DA_CAX_R_DLY_RO_SEL GENMASK(15, 12) +#define MISC_RXDVS2 0x000005e8 + #define MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF BIT(0) + #define MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG BIT(8) + #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN BIT(16) + #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR BIT(17) + #define MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN BIT(18) +#define RFU_0X5EC 0x000005ec + #define RFU_0X5EC_RESERVED_0X5EC GENMASK(31, 0) +#define B0_RXDVS0 0x000005f0 + #define B0_RXDVS0_R_RX_RANKINSEL_B0 BIT(0) + #define B0_RXDVS0_B0_RXDVS0_RFU GENMASK(3, 1) + #define B0_RXDVS0_R_RX_RANKINCTL_B0 GENMASK(7, 4) + #define B0_RXDVS0_R_DVS_SW_UP_B0 BIT(8) + #define B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0 BIT(9) + #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B0 BIT(10) + #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B0 BIT(11) + #define B0_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B0 GENMASK(13, 12) + #define B0_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B0 GENMASK(18, 16) + #define B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0 BIT(19) + #define B0_RXDVS0_R_RX_DLY_RK_OPT_B0 GENMASK(21, 20) + #define B0_RXDVS0_R_HWRESTORE_ENA_B0 BIT(22) + #define B0_RXDVS0_R_HWSAVE_MODE_ENA_B0 BIT(24) + #define B0_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B0 BIT(26) + #define B0_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B0 BIT(27) + #define B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 BIT(28) + #define B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0 BIT(29) + #define B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0 BIT(30) + #define B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0 BIT(31) +#define B0_RXDVS1 0x000005f4 + #define B0_RXDVS1_B0_RXDVS1_RFU GENMASK(15, 0) + #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B0 BIT(16) + #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0 BIT(17) +#define RFU_0X5F8 0x000005f8 + #define RFU_0X5F8_RESERVED_0X5F8 GENMASK(31, 0) +#define RFU_0X5FC 0x000005fc + #define RFU_0X5FC_RESERVED_0X5FC GENMASK(31, 0) +#define R0_B0_RXDVS0 0x00000600 + #define R0_B0_RXDVS0_R_RK0_B0_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R0_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_CLR BIT(27) + #define R0_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_ENA BIT(31) +#define R0_B0_RXDVS1 0x00000604 + #define R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG GENMASK(15, 0) + #define R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD GENMASK(31, 16) +#define R0_B0_RXDVS2 0x00000608 + #define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0 GENMASK(17, 16) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0 GENMASK(19, 18) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0 BIT(23) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0 GENMASK(25, 24) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0 GENMASK(27, 26) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0 BIT(28) + #define R0_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0 BIT(29) + #define R0_B0_RXDVS2_R_RK0_DVS_MODE_B0 GENMASK(31, 30) +#define R0_B0_RXDVS7 0x0000061c + #define R0_B0_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B0 GENMASK(5, 0) + #define R0_B0_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B0_RFU GENMASK(7, 6) + #define R0_B0_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B0 GENMASK(13, 8) + #define R0_B0_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B0_RFU GENMASK(15, 14) + #define R0_B0_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B0 GENMASK(22, 16) + #define R0_B0_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B0_RFU BIT(23) + #define R0_B0_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B0 GENMASK(30, 24) + #define R0_B0_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B0_RFU BIT(31) +#define RFU_0X620 0x00000620 + #define RFU_0X620_RESERVED_0X620 GENMASK(31, 0) +#define RFU_0X624 0x00000624 + #define RFU_0X624_RESERVED_0X624 GENMASK(31, 0) +#define RFU_0X628 0x00000628 + #define RFU_0X628_RESERVED_0X628 GENMASK(31, 0) +#define RFU_0X62C 0x0000062c + #define RFU_0X62C_RESERVED_0X62C GENMASK(31, 0) +#define B1_RXDVS0 0x00000670 + #define B1_RXDVS0_R_RX_RANKINSEL_B1 BIT(0) + #define B1_RXDVS0_B1_RXDVS0_RFU GENMASK(3, 1) + #define B1_RXDVS0_R_RX_RANKINCTL_B1 GENMASK(7, 4) + #define B1_RXDVS0_R_DVS_SW_UP_B1 BIT(8) + #define B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1 BIT(9) + #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B1 BIT(10) + #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B1 BIT(11) + #define B1_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B1 GENMASK(13, 12) + #define B1_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B1 GENMASK(18, 16) + #define B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1 BIT(19) + #define B1_RXDVS0_R_RX_DLY_RK_OPT_B1 GENMASK(21, 20) + #define B1_RXDVS0_R_HWRESTORE_ENA_B1 BIT(22) + #define B1_RXDVS0_R_HWSAVE_MODE_ENA_B1 BIT(24) + #define B1_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B1 BIT(26) + #define B1_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B1 BIT(27) + #define B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 BIT(28) + #define B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1 BIT(29) + #define B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1 BIT(30) + #define B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1 BIT(31) +#define B1_RXDVS1 0x00000674 + #define B1_RXDVS1_B1_RXDVS1_RFU GENMASK(15, 0) + #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B1 BIT(16) + #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1 BIT(17) +#define RFU_0X678 0x00000678 + #define RFU_0X678_RESERVED_0X678 GENMASK(31, 0) +#define RFU_0X67C 0x0000067c + #define RFU_0X67C_RESERVED_0X67C GENMASK(31, 0) +#define R0_B1_RXDVS0 0x00000680 + #define R0_B1_RXDVS0_R_RK0_B1_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R0_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_CLR BIT(27) + #define R0_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_ENA BIT(31) +#define R0_B1_RXDVS1 0x00000684 + #define R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG GENMASK(15, 0) + #define R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD GENMASK(31, 16) +#define R0_B1_RXDVS2 0x00000688 + #define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1 GENMASK(17, 16) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1 GENMASK(19, 18) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1 BIT(23) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1 GENMASK(25, 24) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1 GENMASK(27, 26) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1 BIT(28) + #define R0_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1 BIT(29) + #define R0_B1_RXDVS2_R_RK0_DVS_MODE_B1 GENMASK(31, 30) +#define R0_B1_RXDVS7 0x0000069c + #define R0_B1_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B1 GENMASK(5, 0) + #define R0_B1_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B1_RFU GENMASK(7, 6) + #define R0_B1_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B1 GENMASK(13, 8) + #define R0_B1_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B1_RFU GENMASK(15, 14) + #define R0_B1_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B1 GENMASK(22, 16) + #define R0_B1_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B1_RFU BIT(23) + #define R0_B1_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B1 GENMASK(30, 24) + #define R0_B1_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B1_RFU BIT(31) +#define RFU_0X6A0 0x000006a0 + #define RFU_0X6A0_RESERVED_0X6A0 GENMASK(31, 0) +#define RFU_0X6A4 0x000006a4 + #define RFU_0X6A4_RESERVED_0X6A4 GENMASK(31, 0) +#define RFU_0X6A8 0x000006a8 + #define RFU_0X6A8_RESERVED_0X6A8 GENMASK(31, 0) +#define RFU_0X6AC 0x000006ac + #define RFU_0X6AC_RESERVED_0X6AC GENMASK(31, 0) +#define CA_RXDVS0 0x000006f0 + #define CA_RXDVS0_R_RX_RANKINSEL_CA BIT(0) + #define CA_RXDVS0_CA_RXDVS0_RFU GENMASK(3, 1) + #define CA_RXDVS0_R_RX_RANKINCTL_CA GENMASK(7, 4) + #define CA_RXDVS0_R_DVS_SW_UP_CA BIT(8) + #define CA_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_CA BIT(9) + #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_CA BIT(10) + #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_CA BIT(11) + #define CA_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_CA GENMASK(13, 12) + #define CA_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_CA GENMASK(18, 16) + #define CA_RXDVS0_R_DMRXDVS_CNTCMP_OPT_CA BIT(19) + #define CA_RXDVS0_R_RX_DLY_RK_OPT_CA GENMASK(21, 20) + #define CA_RXDVS0_R_HWRESTORE_ENA_CA BIT(22) + #define CA_RXDVS0_R_HWSAVE_MODE_ENA_CA BIT(24) + #define CA_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_CA BIT(26) + #define CA_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_CA BIT(27) + #define CA_RXDVS0_R_RX_DLY_TRACK_CG_EN_CA BIT(28) + #define CA_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_CA BIT(29) + #define CA_RXDVS0_R_RX_DLY_TRACK_CLR_CA BIT(30) + #define CA_RXDVS0_R_RX_DLY_TRACK_ENA_CA BIT(31) +#define CA_RXDVS1 0x000006f4 + #define CA_RXDVS1_CA_RXDVS1_RFU GENMASK(15, 0) + #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_CA BIT(16) + #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_CA BIT(17) +#define RFU_0X6F8 0x000006f8 + #define RFU_0X6F8_RESERVED_0X6F8 GENMASK(31, 0) +#define RFU_0X6FC 0x000006fc + #define RFU_0X6FC_RESERVED_0X6FC GENMASK(31, 0) +#define R0_CA_RXDVS0 0x00000700 + #define R0_CA_RXDVS0_R_RK0_CA_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R0_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_CLR BIT(27) + #define R0_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_ENA BIT(31) +#define R0_CA_RXDVS1 0x00000704 + #define R0_CA_RXDVS1_R_RK0_CA_DVS_TH_LAG GENMASK(15, 0) + #define R0_CA_RXDVS1_R_RK0_CA_DVS_TH_LEAD GENMASK(31, 16) +#define R0_CA_RXDVS2 0x00000708 + #define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_CA GENMASK(17, 16) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_CA GENMASK(19, 18) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_CA BIT(23) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_CA GENMASK(25, 24) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_CA GENMASK(27, 26) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_CA BIT(28) + #define R0_CA_RXDVS2_R_RK0_DVS_FDLY_MODE_CA BIT(29) + #define R0_CA_RXDVS2_R_RK0_DVS_MODE_CA GENMASK(31, 30) +#define R0_CA_RXDVS9 0x00000724 + #define R0_CA_RXDVS9_RG_RK0_ARCMD_MIN_DLY GENMASK(5, 0) + #define R0_CA_RXDVS9_RG_RK0_ARCMD_MIN_DLY_RFU GENMASK(7, 6) + #define R0_CA_RXDVS9_RG_RK0_ARCMD_MAX_DLY GENMASK(13, 8) + #define R0_CA_RXDVS9_RG_RK0_ARCMD_MAX_DLY_RFU GENMASK(15, 14) + #define R0_CA_RXDVS9_RG_RK0_ARCLK_MIN_DLY GENMASK(22, 16) + #define R0_CA_RXDVS9_RG_RK0_ARCLK_MIN_DLY_RFU BIT(23) + #define R0_CA_RXDVS9_RG_RK0_ARCLK_MAX_DLY GENMASK(30, 24) + #define R0_CA_RXDVS9_RG_RK0_ARCLK_MAX_DLY_RFU BIT(31) +#define RFU_0X728 0x00000728 + #define RFU_0X728_RESERVED_0X728 GENMASK(31, 0) +#define RFU_0X72C 0x0000072c + #define RFU_0X72C_RESERVED_0X72C GENMASK(31, 0) +#define R1_B0_RXDVS0 0x00000800 + #define R1_B0_RXDVS0_R_RK1_B0_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R1_B0_RXDVS0_R_RK1_B0_DVS_SW_CNT_CLR BIT(27) + #define R1_B0_RXDVS0_R_RK1_B0_DVS_SW_CNT_ENA BIT(31) +#define R1_B0_RXDVS1 0x00000804 + #define R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LAG GENMASK(15, 0) + #define R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LEAD GENMASK(31, 16) +#define R1_B0_RXDVS2 0x00000808 + #define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_B0 GENMASK(17, 16) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_B0 GENMASK(19, 18) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B0 BIT(23) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_B0 GENMASK(25, 24) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_B0 GENMASK(27, 26) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B0 BIT(28) + #define R1_B0_RXDVS2_R_RK1_DVS_FDLY_MODE_B0 BIT(29) + #define R1_B0_RXDVS2_R_RK1_DVS_MODE_B0 GENMASK(31, 30) +#define R1_B0_RXDVS7 0x0000081c + #define R1_B0_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B0 GENMASK(5, 0) + #define R1_B0_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B0_RFU GENMASK(7, 6) + #define R1_B0_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B0 GENMASK(13, 8) + #define R1_B0_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B0_RFU GENMASK(15, 14) + #define R1_B0_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B0 GENMASK(22, 16) + #define R1_B0_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B0_RFU BIT(23) + #define R1_B0_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B0 GENMASK(30, 24) + #define R1_B0_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B0_RFU BIT(31) +#define RFU_0X820 0x00000820 + #define RFU_0X820_RESERVED_0X820 GENMASK(31, 0) +#define RFU_0X824 0x00000824 + #define RFU_0X824_RESERVED_0X824 GENMASK(31, 0) +#define RFU_0X828 0x00000828 + #define RFU_0X828_RESERVED_0X828 GENMASK(31, 0) +#define RFU_0X82C 0x0000082c + #define RFU_0X82C_RESERVED_0X82C GENMASK(31, 0) +#define R1_B1_RXDVS0 0x00000880 + #define R1_B1_RXDVS0_R_RK1_B1_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R1_B1_RXDVS0_R_RK1_B1_DVS_SW_CNT_CLR BIT(27) + #define R1_B1_RXDVS0_R_RK1_B1_DVS_SW_CNT_ENA BIT(31) +#define R1_B1_RXDVS1 0x00000884 + #define R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LAG GENMASK(15, 0) + #define R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LEAD GENMASK(31, 16) +#define R1_B1_RXDVS2 0x00000888 + #define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_B1 GENMASK(17, 16) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_B1 GENMASK(19, 18) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B1 BIT(23) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_B1 GENMASK(25, 24) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_B1 GENMASK(27, 26) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B1 BIT(28) + #define R1_B1_RXDVS2_R_RK1_DVS_FDLY_MODE_B1 BIT(29) + #define R1_B1_RXDVS2_R_RK1_DVS_MODE_B1 GENMASK(31, 30) +#define R1_B1_RXDVS7 0x0000089c + #define R1_B1_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B1 GENMASK(5, 0) + #define R1_B1_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B1_RFU GENMASK(7, 6) + #define R1_B1_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B1 GENMASK(13, 8) + #define R1_B1_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B1_RFU GENMASK(15, 14) + #define R1_B1_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B1 GENMASK(22, 16) + #define R1_B1_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B1_RFU BIT(23) + #define R1_B1_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B1 GENMASK(30, 24) + #define R1_B1_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B1_RFU BIT(31) +#define RFU_0X8A0 0x000008a0 + #define RFU_0X8A0_RESERVED_0X8A0 GENMASK(31, 0) +#define RFU_0X8A4 0x000008a4 + #define RFU_0X8A4_RESERVED_0X8A4 GENMASK(31, 0) +#define RFU_0X8A8 0x000008a8 + #define RFU_0X8A8_RESERVED_0X8A8 GENMASK(31, 0) +#define RFU_0X8AC 0x000008ac + #define RFU_0X8AC_RESERVED_0X8AC GENMASK(31, 0) +#define R1_CA_RXDVS0 0x00000900 + #define R1_CA_RXDVS0_R_RK1_CA_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R1_CA_RXDVS0_R_RK1_CA_DVS_SW_CNT_CLR BIT(27) + #define R1_CA_RXDVS0_R_RK1_CA_DVS_SW_CNT_ENA BIT(31) +#define R1_CA_RXDVS1 0x00000904 + #define R1_CA_RXDVS1_R_RK1_CA_DVS_TH_LAG GENMASK(15, 0) + #define R1_CA_RXDVS1_R_RK1_CA_DVS_TH_LEAD GENMASK(31, 16) +#define R1_CA_RXDVS2 0x00000908 + #define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_CA GENMASK(17, 16) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_CA GENMASK(19, 18) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_CA BIT(23) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_CA GENMASK(25, 24) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_CA GENMASK(27, 26) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_CA BIT(28) + #define R1_CA_RXDVS2_R_RK1_DVS_FDLY_MODE_CA BIT(29) + #define R1_CA_RXDVS2_R_RK1_DVS_MODE_CA GENMASK(31, 30) +#define R1_CA_RXDVS9 0x00000924 + #define R1_CA_RXDVS9_RG_RK1_ARCMD_MIN_DLY GENMASK(5, 0) + #define R1_CA_RXDVS9_RG_RK1_ARCMD_MIN_DLY_RFU GENMASK(7, 6) + #define R1_CA_RXDVS9_RG_RK1_ARCMD_MAX_DLY GENMASK(13, 8) + #define R1_CA_RXDVS9_RG_RK1_ARCMD_MAX_DLY_RFU GENMASK(15, 14) + #define R1_CA_RXDVS9_RG_RK1_ARCLK_MIN_DLY GENMASK(22, 16) + #define R1_CA_RXDVS9_RG_RK1_ARCLK_MIN_DLY_RFU BIT(23) + #define R1_CA_RXDVS9_RG_RK1_ARCLK_MAX_DLY GENMASK(30, 24) + #define R1_CA_RXDVS9_RG_RK1_ARCLK_MAX_DLY_RFU BIT(31) +#define RFU_0X928 0x00000928 + #define RFU_0X928_RESERVED_0X928 GENMASK(31, 0) +#define RFU_0X92C 0x0000092c + #define RFU_0X92C_RESERVED_0X92C GENMASK(31, 0) +#define R2_B0_RXDVS0 0x00000a00 + #define R2_B0_RXDVS0_R_RK2_B0_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R2_B0_RXDVS0_R_RK2_B0_DVS_SW_CNT_CLR BIT(27) + #define R2_B0_RXDVS0_R_RK2_B0_DVS_SW_CNT_ENA BIT(31) +#define R2_B0_RXDVS1 0x00000a04 + #define R2_B0_RXDVS1_R_RK2_B0_DVS_TH_LAG GENMASK(15, 0) + #define R2_B0_RXDVS1_R_RK2_B0_DVS_TH_LEAD GENMASK(31, 16) +#define R2_B0_RXDVS2 0x00000a08 + #define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_B0 GENMASK(17, 16) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_B0 GENMASK(19, 18) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_B0 BIT(23) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_B0 GENMASK(25, 24) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_B0 GENMASK(27, 26) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_B0 BIT(28) + #define R2_B0_RXDVS2_R_RK2_DVS_FDLY_MODE_B0 BIT(29) + #define R2_B0_RXDVS2_R_RK2_DVS_MODE_B0 GENMASK(31, 30) +#define R2_B0_RXDVS7 0x00000a1c + #define R2_B0_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B0 GENMASK(5, 0) + #define R2_B0_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B0_RFU GENMASK(7, 6) + #define R2_B0_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B0 GENMASK(13, 8) + #define R2_B0_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B0_RFU GENMASK(15, 14) + #define R2_B0_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B0 GENMASK(22, 16) + #define R2_B0_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B0_RFU BIT(23) + #define R2_B0_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B0 GENMASK(30, 24) + #define R2_B0_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B0_RFU BIT(31) +#define RFU_0XA20 0x00000a20 + #define RFU_0XA20_RESERVED_0XA20 GENMASK(31, 0) +#define RFU_0XA24 0x00000a24 + #define RFU_0XA24_RESERVED_0XA24 GENMASK(31, 0) +#define RFU_0XA28 0x00000a28 + #define RFU_0XA28_RESERVED_0XA28 GENMASK(31, 0) +#define RFU_0XA2C 0x00000a2c + #define RFU_0XA2C_RESERVED_0XA2C GENMASK(31, 0) +#define R2_B1_RXDVS0 0x00000a80 + #define R2_B1_RXDVS0_R_RK2_B1_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R2_B1_RXDVS0_R_RK2_B1_DVS_SW_CNT_CLR BIT(27) + #define R2_B1_RXDVS0_R_RK2_B1_DVS_SW_CNT_ENA BIT(31) +#define R2_B1_RXDVS1 0x00000a84 + #define R2_B1_RXDVS1_R_RK2_B1_DVS_TH_LAG GENMASK(15, 0) + #define R2_B1_RXDVS1_R_RK2_B1_DVS_TH_LEAD GENMASK(31, 16) +#define R2_B1_RXDVS2 0x00000a88 + #define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_B1 GENMASK(17, 16) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_B1 GENMASK(19, 18) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_B1 BIT(23) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_B1 GENMASK(25, 24) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_B1 GENMASK(27, 26) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_B1 BIT(28) + #define R2_B1_RXDVS2_R_RK2_DVS_FDLY_MODE_B1 BIT(29) + #define R2_B1_RXDVS2_R_RK2_DVS_MODE_B1 GENMASK(31, 30) +#define R2_B1_RXDVS7 0x00000a9c + #define R2_B1_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B1 GENMASK(5, 0) + #define R2_B1_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B1_RFU GENMASK(7, 6) + #define R2_B1_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B1 GENMASK(13, 8) + #define R2_B1_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B1_RFU GENMASK(15, 14) + #define R2_B1_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B1 GENMASK(22, 16) + #define R2_B1_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B1_RFU BIT(23) + #define R2_B1_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B1 GENMASK(30, 24) + #define R2_B1_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B1_RFU BIT(31) +#define RFU_0XAA0 0x00000aa0 + #define RFU_0XAA0_RESERVED_0XAA0 GENMASK(31, 0) +#define RFU_0XAA4 0x00000aa4 + #define RFU_0XAA4_RESERVED_0XAA4 GENMASK(31, 0) +#define RFU_0XAA8 0x00000aa8 + #define RFU_0XAA8_RESERVED_0XAA8 GENMASK(31, 0) +#define RFU_0XAAC 0x00000aac + #define RFU_0XAAC_RESERVED_0XAAC GENMASK(31, 0) +#define R2_CA_RXDVS0 0x00000b00 + #define R2_CA_RXDVS0_R_RK2_CA_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R2_CA_RXDVS0_R_RK2_CA_DVS_SW_CNT_CLR BIT(27) + #define R2_CA_RXDVS0_R_RK2_CA_DVS_SW_CNT_ENA BIT(31) +#define R2_CA_RXDVS1 0x00000b04 + #define R2_CA_RXDVS1_R_RK2_CA_DVS_TH_LAG GENMASK(15, 0) + #define R2_CA_RXDVS1_R_RK2_CA_DVS_TH_LEAD GENMASK(31, 16) +#define R2_CA_RXDVS2 0x00000b08 + #define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_CA GENMASK(17, 16) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_CA GENMASK(19, 18) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_CA BIT(23) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_CA GENMASK(25, 24) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_CA GENMASK(27, 26) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_CA BIT(28) + #define R2_CA_RXDVS2_R_RK2_DVS_FDLY_MODE_CA BIT(29) + #define R2_CA_RXDVS2_R_RK2_DVS_MODE_CA GENMASK(31, 30) +#define R2_CA_RXDVS9 0x00000b24 + #define R2_CA_RXDVS9_RG_RK2_ARCMD_MIN_DLY GENMASK(5, 0) + #define R2_CA_RXDVS9_RG_RK2_ARCMD_MIN_DLY_RFU GENMASK(7, 6) + #define R2_CA_RXDVS9_RG_RK2_ARCMD_MAX_DLY GENMASK(13, 8) + #define R2_CA_RXDVS9_RG_RK2_ARCMD_MAX_DLY_RFU GENMASK(15, 14) + #define R2_CA_RXDVS9_RG_RK2_ARCLK_MIN_DLY GENMASK(22, 16) + #define R2_CA_RXDVS9_RG_RK2_ARCLK_MIN_DLY_RFU BIT(23) + #define R2_CA_RXDVS9_RG_RK2_ARCLK_MAX_DLY GENMASK(30, 24) + #define R2_CA_RXDVS9_RG_RK2_ARCLK_MAX_DLY_RFU BIT(31) +#define RFU_0XB28 0x00000b28 + #define RFU_0XB28_RESERVED_0XB28 GENMASK(31, 0) +#define RFU_0XB2C 0x00000b2c + #define RFU_0XB2C_RESERVED_0XB2C GENMASK(31, 0) +#define SHU1_B0_DQ0 0x00000c00 + #define SHU1_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 BIT(4) + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 GENMASK(10, 8) + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT2 BIT(10)//[10:10] //Francis added + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT1 BIT(9)//[9:9] //Francis added + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT0 BIT(8)//[8:8] //Francis added + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 GENMASK(14, 12) + #define SHU1_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 BIT(20) + #define SHU1_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 GENMASK(26, 24) + #define SHU1_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 GENMASK(30, 28) + #define SHU1_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 BIT(31) +#define SHU1_B0_DQ1 0x00000c04 + #define SHU1_B0_DQ1_RG_TX_ARDQ_DRVP_B0 GENMASK(4, 0) + #define SHU1_B0_DQ1_RG_TX_ARDQ_DRVN_B0 GENMASK(12, 8) + #define SHU1_B0_DQ1_RG_TX_ARDQ_ODTP_B0 GENMASK(20, 16) + #define SHU1_B0_DQ1_RG_TX_ARDQ_ODTN_B0 GENMASK(28, 24) +#define SHU1_B0_DQ2 0x00000c08 + #define SHU1_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 GENMASK(4, 0) + #define SHU1_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 GENMASK(12, 8) + #define SHU1_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 GENMASK(20, 16) + #define SHU1_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 GENMASK(28, 24) +#define SHU1_B0_DQ3 0x00000c0c + #define SHU1_B0_DQ3_RG_TX_ARDQS0_PU_B0 GENMASK(1, 0) + #define SHU1_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 GENMASK(3, 2) + #define SHU1_B0_DQ3_RG_TX_ARDQS0_PDB_B0 GENMASK(5, 4) + #define SHU1_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 GENMASK(7, 6) + #define SHU1_B0_DQ3_RG_TX_ARDQ_PU_B0 GENMASK(9, 8) + #define SHU1_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 GENMASK(11, 10) + #define SHU1_B0_DQ3_RG_TX_ARDQ_PDB_B0 GENMASK(13, 12) + #define SHU1_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 GENMASK(15, 14) +#define SHU1_B0_DQ4 0x00000c10 + #define SHU1_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 GENMASK(5, 0) + #define SHU1_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 GENMASK(13, 8) + #define SHU1_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 GENMASK(21, 16) +#define SHU1_B0_DQ5 0x00000c14 + #define SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 GENMASK(5, 0) + #define SHU1_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 BIT(6) + #define SHU1_B0_DQ5_RG_ARPI_FB_B0 GENMASK(13, 8) + #define SHU1_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 GENMASK(18, 16) + #define SHU1_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0 BIT(19) + #define SHU1_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 GENMASK(22, 20) + #define SHU1_B0_DQ5_RG_ARPI_MCTL_B0 GENMASK(29, 24) +#define SHU1_B0_DQ6 0x00000c18 + #define SHU1_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 GENMASK(5, 0) + #define SHU1_B0_DQ6_RG_ARPI_RESERVE_B0 GENMASK(21, 6) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 GENMASK(23, 22) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 GENMASK(25, 24) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_EN_B0 BIT(26) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 BIT(27) + #define SHU1_B0_DQ6_RG_ARPI_CAP_SEL_B0 GENMASK(29, 28) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0 BIT(31) +#define SHU1_B0_DQ7 0x00000c1c + #define SHU1_B0_DQ7_R_DMRANKRXDVS_B0 GENMASK(3, 0) + #define SHU1_B0_DQ7_MIDPI_ENABLE BIT(4) + #define SHU1_B0_DQ7_MIDPI_DIV4_ENABLE BIT(5) + #define SHU1_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 BIT(6) + #define SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0 BIT(7) + #define SHU1_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 GENMASK(11, 8) + #define SHU1_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 BIT(12) + #define SHU1_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 BIT(13) + #define SHU1_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 BIT(14) + #define SHU1_B0_DQ7_R_DMRODTEN_B0 BIT(15) + #define SHU1_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 BIT(16) + #define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 BIT(17) + #define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 BIT(18) + #define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 BIT(19) + #define SHU1_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 BIT(20) + #define SHU1_B0_DQ7_R_DMRXRANK_DQ_EN_B0 BIT(24) + #define SHU1_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 GENMASK(27, 25) + #define SHU1_B0_DQ7_R_DMRXRANK_DQS_EN_B0 BIT(28) + #define SHU1_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 GENMASK(31, 29) +#define SHU1_B0_DQ8 0x00000c20 + #define SHU1_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 GENMASK(14, 0) + #define SHU1_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 BIT(15) + #define SHU1_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 BIT(19) + #define SHU1_B0_DQ8_R_RMRODTEN_CG_IG_B0 BIT(20) + #define SHU1_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 BIT(21) + #define SHU1_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 BIT(22) + #define SHU1_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 BIT(23) + #define SHU1_B0_DQ8_R_DMRXDLY_CG_IG_B0 BIT(24) + #define SHU1_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0 BIT(25) + #define SHU1_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 BIT(26) + #define SHU1_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 BIT(27) + #define SHU1_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 BIT(28) + #define SHU1_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 BIT(29) + #define SHU1_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 BIT(30) + #define SHU1_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 BIT(31) +#define SHU1_B0_DQ9 0x00000c24 + #define SHU1_B0_DQ9_RESERVED_0XC24 GENMASK(31, 0) +#define SHU1_B0_DQ10 0x00000c28 + #define SHU1_B0_DQ10_RESERVED_0XC28 GENMASK(31, 0) +#define SHU1_B0_DQ11 0x00000c2c + #define SHU1_B0_DQ11_RESERVED_0XC2C GENMASK(31, 0) +#define SHU1_B0_DQ12 0x00000c30 + #define SHU1_B0_DQ12_RESERVED_0XC30 GENMASK(31, 0) +#define SHU1_B0_DLL0 0x00000c34 + #define SHU1_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU BIT(0) + #define SHU1_B0_DLL0_B0_DLL0_RFU BIT(3) + #define SHU1_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 BIT(4) + #define SHU1_B0_DLL0_RG_ARDLL_PHDIV_B0 BIT(9) + #define SHU1_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0 BIT(10) + #define SHU1_B0_DLL0_RG_ARDLL_P_GAIN_B0 GENMASK(15, 12) + #define SHU1_B0_DLL0_RG_ARDLL_IDLECNT_B0 GENMASK(19, 16) + #define SHU1_B0_DLL0_RG_ARDLL_GAIN_B0 GENMASK(23, 20) + #define SHU1_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0 BIT(30) + #define SHU1_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0 BIT(31) +#define SHU1_B0_DLL1 0x00000c38 + #define SHU1_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0 BIT(0) + #define SHU1_B0_DLL1_RG_ARDLL_PS_EN_B0 BIT(1) + #define SHU1_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 BIT(2) + #define SHU1_B0_DLL1_RG_ARDQ_REV_B0 GENMASK(31, 8) +#define SHU1_B1_DQ0 0x00000c80 + #define SHU1_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 BIT(4) + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 GENMASK(10, 8) + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT2 BIT(10)//[10:10] //Francis added + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT1 BIT(9)//[9:9] //Francis added + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT0 BIT(8)//[8:8] //Francis added + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 GENMASK(14, 12) + #define SHU1_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 BIT(20) + #define SHU1_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 GENMASK(26, 24) + #define SHU1_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 GENMASK(30, 28) + #define SHU1_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 BIT(31) +#define SHU1_B1_DQ1 0x00000c84 + #define SHU1_B1_DQ1_RG_TX_ARDQ_DRVP_B1 GENMASK(4, 0) + #define SHU1_B1_DQ1_RG_TX_ARDQ_DRVN_B1 GENMASK(12, 8) + #define SHU1_B1_DQ1_RG_TX_ARDQ_ODTP_B1 GENMASK(20, 16) + #define SHU1_B1_DQ1_RG_TX_ARDQ_ODTN_B1 GENMASK(28, 24) +#define SHU1_B1_DQ2 0x00000c88 + #define SHU1_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 GENMASK(4, 0) + #define SHU1_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 GENMASK(12, 8) + #define SHU1_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 GENMASK(20, 16) + #define SHU1_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 GENMASK(28, 24) +#define SHU1_B1_DQ3 0x00000c8c + #define SHU1_B1_DQ3_RG_TX_ARDQS0_PU_B1 GENMASK(1, 0) + #define SHU1_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 GENMASK(3, 2) + #define SHU1_B1_DQ3_RG_TX_ARDQS0_PDB_B1 GENMASK(5, 4) + #define SHU1_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 GENMASK(7, 6) + #define SHU1_B1_DQ3_RG_TX_ARDQ_PU_B1 GENMASK(9, 8) + #define SHU1_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 GENMASK(11, 10) + #define SHU1_B1_DQ3_RG_TX_ARDQ_PDB_B1 GENMASK(13, 12) + #define SHU1_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 GENMASK(15, 14) +#define SHU1_B1_DQ4 0x00000c90 + #define SHU1_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 GENMASK(5, 0) + #define SHU1_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 GENMASK(13, 8) + #define SHU1_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 GENMASK(21, 16) +#define SHU1_B1_DQ5 0x00000c94 + #define SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 GENMASK(5, 0) + #define SHU1_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 BIT(6) + #define SHU1_B1_DQ5_RG_ARPI_FB_B1 GENMASK(13, 8) + #define SHU1_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 GENMASK(18, 16) + #define SHU1_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1 BIT(19) + #define SHU1_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 GENMASK(22, 20) + #define SHU1_B1_DQ5_RG_ARPI_MCTL_B1 GENMASK(29, 24) +#define SHU1_B1_DQ6 0x00000c98 + #define SHU1_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 GENMASK(5, 0) + #define SHU1_B1_DQ6_RG_ARPI_RESERVE_B1 GENMASK(21, 6) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 GENMASK(23, 22) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 GENMASK(25, 24) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_EN_B1 BIT(26) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 BIT(27) + #define SHU1_B1_DQ6_RG_ARPI_CAP_SEL_B1 GENMASK(29, 28) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1 BIT(31) +#define SHU1_B1_DQ7 0x00000c9c + #define SHU1_B1_DQ7_R_DMRANKRXDVS_B1 GENMASK(3, 0) + #define SHU1_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 BIT(6) + #define SHU1_B1_DQ7_R_DMDQMDBI_SHU_B1 BIT(7) + #define SHU1_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 GENMASK(11, 8) + #define SHU1_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 BIT(12) + #define SHU1_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 BIT(13) + #define SHU1_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 BIT(14) + #define SHU1_B1_DQ7_R_DMRODTEN_B1 BIT(15) + #define SHU1_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 BIT(16) + #define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 BIT(17) + #define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 BIT(18) + #define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 BIT(19) + #define SHU1_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 BIT(20) + #define SHU1_B1_DQ7_R_DMRXRANK_DQ_EN_B1 BIT(24) + #define SHU1_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 GENMASK(27, 25) + #define SHU1_B1_DQ7_R_DMRXRANK_DQS_EN_B1 BIT(28) + #define SHU1_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 GENMASK(31, 29) +#define SHU1_B1_DQ8 0x00000ca0 + #define SHU1_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 GENMASK(14, 0) + #define SHU1_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 BIT(15) + #define SHU1_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 BIT(19) + #define SHU1_B1_DQ8_R_RMRODTEN_CG_IG_B1 BIT(20) + #define SHU1_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 BIT(21) + #define SHU1_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 BIT(22) + #define SHU1_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 BIT(23) + #define SHU1_B1_DQ8_R_DMRXDLY_CG_IG_B1 BIT(24) + #define SHU1_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1 BIT(25) + #define SHU1_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 BIT(26) + #define SHU1_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 BIT(27) + #define SHU1_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 BIT(28) + #define SHU1_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 BIT(29) + #define SHU1_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 BIT(30) + #define SHU1_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 BIT(31) +#define SHU1_B1_DQ9 0x00000ca4 + #define SHU1_B1_DQ9_RESERVED_0XCA4 GENMASK(31, 0) +#define SHU1_B1_DQ10 0x00000ca8 + #define SHU1_B1_DQ10_RESERVED_0XCA8 GENMASK(31, 0) +#define SHU1_B1_DQ11 0x00000cac + #define SHU1_B1_DQ11_RESERVED_0XCAC GENMASK(31, 0) +#define SHU1_B1_DQ12 0x00000cb0 + #define SHU1_B1_DQ12_RESERVED_0XCB0 GENMASK(31, 0) +#define SHU1_B1_DLL0 0x00000cb4 + #define SHU1_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU BIT(0) + #define SHU1_B1_DLL0_B1_DLL0_RFU BIT(3) + #define SHU1_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 BIT(4) + #define SHU1_B1_DLL0_RG_ARDLL_PHDIV_B1 BIT(9) + #define SHU1_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1 BIT(10) + #define SHU1_B1_DLL0_RG_ARDLL_P_GAIN_B1 GENMASK(15, 12) + #define SHU1_B1_DLL0_RG_ARDLL_IDLECNT_B1 GENMASK(19, 16) + #define SHU1_B1_DLL0_RG_ARDLL_GAIN_B1 GENMASK(23, 20) + #define SHU1_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1 BIT(30) + #define SHU1_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1 BIT(31) +#define SHU1_B1_DLL1 0x00000cb8 + #define SHU1_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1 BIT(0) + #define SHU1_B1_DLL1_RG_ARDLL_PS_EN_B1 BIT(1) + #define SHU1_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 BIT(2) + #define SHU1_B1_DLL1_RG_ARDQ_REV_B1 GENMASK(31, 8) +#define SHU1_CA_CMD0 0x00000d00 + #define SHU1_CA_CMD0_RG_TX_ARCLK_PRE_EN BIT(4) + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE GENMASK(10, 8) + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT2 BIT(10)//[10:10] //Francis added + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT1 BIT(9)//[9:9] //Francis added + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT0 BIT(8)//[8:8] //Francis added + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE GENMASK(14, 12) + #define SHU1_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL BIT(17) + #define SHU1_CA_CMD0_RG_FB_CK_MUX GENMASK(19, 18) + #define SHU1_CA_CMD0_RG_TX_ARCMD_PRE_EN BIT(20) + #define SHU1_CA_CMD0_RG_TX_ARCMD_DRVP_PRE GENMASK(26, 24) + #define SHU1_CA_CMD0_RG_TX_ARCMD_DRVN_PRE GENMASK(30, 28) + #define SHU1_CA_CMD0_R_LP4Y_WDN_MODE_CLK BIT(31) +#define SHU1_CA_CMD1 0x00000d04 + #define SHU1_CA_CMD1_RG_TX_ARCMD_DRVP GENMASK(4, 0) + #define SHU1_CA_CMD1_RG_TX_ARCMD_DRVN GENMASK(12, 8) + #define SHU1_CA_CMD1_RG_TX_ARCMD_ODTP GENMASK(20, 16) + #define SHU1_CA_CMD1_RG_TX_ARCMD_ODTN GENMASK(28, 24) +#define SHU1_CA_CMD2 0x00000d08 + #define SHU1_CA_CMD2_RG_TX_ARCLK_DRVP GENMASK(4, 0) + #define SHU1_CA_CMD2_RG_TX_ARCLK_DRVN GENMASK(12, 8) + #define SHU1_CA_CMD2_RG_TX_ARCLK_ODTP GENMASK(20, 16) + #define SHU1_CA_CMD2_RG_TX_ARCLK_ODTN GENMASK(28, 24) +#define SHU1_CA_CMD3 0x00000d0c + #define SHU1_CA_CMD3_RG_TX_ARCLK_PU GENMASK(1, 0) + #define SHU1_CA_CMD3_RG_TX_ARCLK_PU_PRE GENMASK(3, 2) + #define SHU1_CA_CMD3_RG_TX_ARCLK_PDB GENMASK(5, 4) + #define SHU1_CA_CMD3_RG_TX_ARCLK_PDB_PRE GENMASK(7, 6) + #define SHU1_CA_CMD3_RG_TX_ARCMD_PU GENMASK(9, 8) + #define SHU1_CA_CMD3_RG_TX_ARCMD_PU_BIT1 BIT(9)//[9:9] //Francis added + #define SHU1_CA_CMD3_RG_TX_ARCMD_PU_BIT0 BIT(8)//[8:8] //Francis added + #define SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE GENMASK(11, 10) + #define SHU1_CA_CMD3_RG_TX_ARCMD_PDB GENMASK(13, 12) + #define SHU1_CA_CMD3_RG_TX_ARCMD_PDB_PRE GENMASK(15, 14) + #define SHU1_CA_CMD3_ARCMD_REV_BIT_06 BIT(22)//[22:22] //Francis added + #define SHU1_CA_CMD3_ARCMD_REV_BIT_05 BIT(21)//[21:21] //Francis added + #define SHU1_CA_CMD3_ARCMD_REV_BIT_04 BIT(20)//[20:20] //Francis added + #define SHU1_CA_CMD3_ARCMD_REV_BIT_03 BIT(19)//[19:19] //Francis added +#define SHU1_CA_CMD4 0x00000d10 + #define SHU1_CA_CMD4_RG_ARPI_AA_MCK_DL_CA GENMASK(5, 0) + #define SHU1_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA GENMASK(13, 8) + #define SHU1_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA GENMASK(21, 16) +#define SHU1_CA_CMD5 0x00000d14 + #define SHU1_CA_CMD5_RG_RX_ARCMD_VREF_SEL GENMASK(5, 0) + #define SHU1_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS BIT(6) + #define SHU1_CA_CMD5_RG_ARPI_FB_CA GENMASK(13, 8) + #define SHU1_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY GENMASK(18, 16) + #define SHU1_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY BIT(19) + #define SHU1_CA_CMD5_RG_RX_ARCLK_DVS_DLY GENMASK(22, 20) + #define SHU1_CA_CMD5_RG_ARPI_MCTL_CA GENMASK(29, 24) +#define SHU1_CA_CMD6 0x00000d18 + #define SHU1_CA_CMD6_RG_ARPI_OFFSET_CLKIEN GENMASK(5, 0) + #define SHU1_CA_CMD6_RG_ARPI_RESERVE_CA GENMASK(21, 6) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA GENMASK(23, 22) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA GENMASK(25, 24) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_EN_CA BIT(26) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA BIT(27) + #define SHU1_CA_CMD6_RG_ARPI_CAP_SEL_CA GENMASK(29, 28) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA BIT(31) +#define SHU1_CA_CMD7 0x00000d1c + #define SHU1_CA_CMD7_R_DMRANKRXDVS_CA GENMASK(3, 0) + #define SHU1_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA BIT(12) + #define SHU1_CA_CMD7_R_DMRODTEN_CA BIT(15) + #define SHU1_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA BIT(16) + #define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW BIT(17) + #define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW BIT(18) + #define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW BIT(19) + #define SHU1_CA_CMD7_R_LP4Y_SDN_MODE_CLK BIT(20) + #define SHU1_CA_CMD7_R_DMRXRANK_CMD_EN BIT(24) + #define SHU1_CA_CMD7_R_DMRXRANK_CMD_LAT GENMASK(27, 25) + #define SHU1_CA_CMD7_R_DMRXRANK_CLK_EN BIT(28) + #define SHU1_CA_CMD7_R_DMRXRANK_CLK_LAT GENMASK(31, 29) +#define SHU1_CA_CMD8 0x00000d20 + #define SHU1_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA GENMASK(14, 0) + #define SHU1_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA BIT(15) + #define SHU1_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA BIT(19) + #define SHU1_CA_CMD8_R_RMRODTEN_CG_IG_CA BIT(20) + #define SHU1_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA BIT(21) + #define SHU1_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA BIT(22) + #define SHU1_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA BIT(23) + #define SHU1_CA_CMD8_R_DMRXDLY_CG_IG_CA BIT(24) + #define SHU1_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA BIT(25) + #define SHU1_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA BIT(26) + #define SHU1_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA BIT(27) + #define SHU1_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA BIT(28) + #define SHU1_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA BIT(29) + #define SHU1_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA BIT(30) + #define SHU1_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA BIT(31) +#define SHU1_CA_CMD9 0x00000d24 + #define SHU1_CA_CMD9_RESERVED_0XD24 GENMASK(31, 0) +#define SHU1_CA_CMD10 0x00000d28 + #define SHU1_CA_CMD10_RESERVED_0XD28 GENMASK(31, 0) +#define SHU1_CA_CMD11 0x00000d2c + #define SHU1_CA_CMD11_RG_RIMP_REV GENMASK(7, 0) + #define SHU1_CA_CMD11_RG_RIMP_VREF_SEL GENMASK(13, 8) + #define SHU1_CA_CMD11_RG_TX_ARCKE_DRVP GENMASK(21, 17) + #define SHU1_CA_CMD11_RG_TX_ARCKE_DRVN GENMASK(26, 22) +#define SHU1_CA_CMD12 0x00000d30 + #define SHU1_CA_CMD12_RESERVED_0XD30 GENMASK(31, 0) +#define SHU1_CA_DLL0 0x00000d34 + #define SHU1_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU BIT(0) + #define SHU1_CA_DLL0_CA_DLL0_RFU BIT(3) + #define SHU1_CA_DLL0_RG_ARDLL_FAST_PSJP_CA BIT(4) + #define SHU1_CA_DLL0_RG_ARDLL_PHDIV_CA BIT(9) + #define SHU1_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA BIT(10) + #define SHU1_CA_DLL0_RG_ARDLL_P_GAIN_CA GENMASK(15, 12) + #define SHU1_CA_DLL0_RG_ARDLL_IDLECNT_CA GENMASK(19, 16) + #define SHU1_CA_DLL0_RG_ARDLL_GAIN_CA GENMASK(23, 20) + #define SHU1_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA BIT(30) + #define SHU1_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA BIT(31) +#define SHU1_CA_DLL1 0x00000d38 + #define SHU1_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA BIT(0) + #define SHU1_CA_DLL1_RG_ARDLL_PS_EN_CA BIT(1) + #define SHU1_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA BIT(2) + #define SHU1_CA_DLL1_RG_ARCMD_REV GENMASK(31, 8) +#define SHU1_MISC0 0x00000df0 + #define SHU1_MISC0_R_RX_PIPE_BYPASS_EN BIT(1) + #define SHU1_MISC0_RG_CMD_TXPIPE_BYPASS_EN BIT(2) + #define SHU1_MISC0_RG_CK_TXPIPE_BYPASS_EN BIT(3) + #define SHU1_MISC0_RG_RVREF_SEL_DQ GENMASK(21, 16) + #define SHU1_MISC0_RG_RVREF_DDR4_SEL BIT(22) + #define SHU1_MISC0_RG_RVREF_DDR3_SEL BIT(23) + #define SHU1_MISC0_RG_RVREF_SEL_CMD GENMASK(29, 24) +#define SHU1_R0_B0_DQ0 0x00000e00 + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU1_R0_B0_DQ1 0x00000e04 + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU1_R0_B0_DQ2 0x00000e08 + #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R0_B0_DQ3 0x00000e0c + #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R0_B0_DQ4 0x00000e10 + #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R0_B0_DQ5 0x00000e14 + #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R0_B0_DQ6 0x00000e18 + #define SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU1_R0_B0_DQ7 0x00000e1c + #define SHU1_R0_B0_DQ7_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ7_RK0_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0XE20 0x00000e20 + #define RFU_0XE20_RESERVED_0XE20 GENMASK(31, 0) +#define RFU_0XE24 0x00000e24 + #define RFU_0XE24_RESERVED_0XE24 GENMASK(31, 0) +#define RFU_0XE28 0x00000e28 + #define RFU_0XE28_RESERVED_0XE28 GENMASK(31, 0) +#define RFU_0XE2C 0x00000e2c + #define RFU_0XE2C_RESERVED_0XE2C GENMASK(31, 0) +#define SHU1_R0_B1_DQ0 0x00000e50 + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU1_R0_B1_DQ1 0x00000e54 + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU1_R0_B1_DQ2 0x00000e58 + #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R0_B1_DQ3 0x00000e5c + #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R0_B1_DQ4 0x00000e60 + #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R0_B1_DQ5 0x00000e64 + #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R0_B1_DQ6 0x00000e68 + #define SHU1_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU1_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU1_R0_B1_DQ7 0x00000e6c + #define SHU1_R0_B1_DQ7_RK0_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ7_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0XE70 0x00000e70 + #define RFU_0XE70_RESERVED_0XE70 GENMASK(31, 0) +#define RFU_0XE74 0x00000e74 + #define RFU_0XE74_RESERVED_0XE74 GENMASK(31, 0) +#define RFU_0XE78 0x00000e78 + #define RFU_0XE78_RESERVED_0XE78 GENMASK(31, 0) +#define RFU_0XE7C 0x00000e7c + #define RFU_0XE7C_RESERVED_0XE7C GENMASK(31, 0) +#define SHU1_R0_CA_CMD0 0x00000ea0 + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU1_R0_CA_CMD1 0x00000ea4 + #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU1_R0_CA_CMD2 0x00000ea8 + #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD3 0x00000eac + #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD4 0x00000eb0 + #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD5 0x00000eb4 + #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD6 0x00000eb8 + #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD7 0x00000ebc + #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD8 0x00000ec0 + #define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU1_R0_CA_CMD9 0x00000ec4 + #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS GENMASK(5, 0) + #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD GENMASK(13, 8) + #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK GENMASK(29, 24) +#define RFU_0XEC8 0x00000ec8 + #define RFU_0XEC8_RESERVED_0XEC8 GENMASK(31, 0) +#define RFU_0XECC 0x00000ecc + #define RFU_0XECC_RESERVED_0XECC GENMASK(31, 0) +#define SHU1_R1_B0_DQ0 0x00000f00 + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU1_R1_B0_DQ1 0x00000f04 + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU1_R1_B0_DQ2 0x00000f08 + #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R1_B0_DQ3 0x00000f0c + #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R1_B0_DQ4 0x00000f10 + #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R1_B0_DQ5 0x00000f14 + #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R1_B0_DQ6 0x00000f18 + #define SHU1_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU1_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU1_R1_B0_DQ7 0x00000f1c + #define SHU1_R1_B0_DQ7_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ7_RK1_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0XF20 0x00000f20 + #define RFU_0XF20_RESERVED_0XF20 GENMASK(31, 0) +#define RFU_0XF24 0x00000f24 + #define RFU_0XF24_RESERVED_0XF24 GENMASK(31, 0) +#define RFU_0XF28 0x00000f28 + #define RFU_0XF28_RESERVED_0XF28 GENMASK(31, 0) +#define RFU_0XF2C 0x00000f2c + #define RFU_0XF2C_RESERVED_0XF2C GENMASK(31, 0) +#define SHU1_R1_B1_DQ0 0x00000f50 + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU1_R1_B1_DQ1 0x00000f54 + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU1_R1_B1_DQ2 0x00000f58 + #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R1_B1_DQ3 0x00000f5c + #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R1_B1_DQ4 0x00000f60 + #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R1_B1_DQ5 0x00000f64 + #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R1_B1_DQ6 0x00000f68 + #define SHU1_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU1_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU1_R1_B1_DQ7 0x00000f6c + #define SHU1_R1_B1_DQ7_RK1_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ7_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0XF70 0x00000f70 + #define RFU_0XF70_RESERVED_0XF70 GENMASK(31, 0) +#define RFU_0XF74 0x00000f74 + #define RFU_0XF74_RESERVED_0XF74 GENMASK(31, 0) +#define RFU_0XF78 0x00000f78 + #define RFU_0XF78_RESERVED_0XF78 GENMASK(31, 0) +#define RFU_0XF7C 0x00000f7c + #define RFU_0XF7C_RESERVED_0XF7C GENMASK(31, 0) +#define SHU1_R1_CA_CMD0 0x00000fa0 + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU1_R1_CA_CMD1 0x00000fa4 + #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU1_R1_CA_CMD2 0x00000fa8 + #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD3 0x00000fac + #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD4 0x00000fb0 + #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD5 0x00000fb4 + #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD6 0x00000fb8 + #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD7 0x00000fbc + #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD8 0x00000fc0 + #define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU1_R1_CA_CMD9 0x00000fc4 + #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CS GENMASK(5, 0) + #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD GENMASK(13, 8) + #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CLK GENMASK(29, 24) +#define RFU_0XFC8 0x00000fc8 + #define RFU_0XFC8_RESERVED_0XFC8 GENMASK(31, 0) +#define RFU_0XFCC 0x00000fcc + #define RFU_0XFCC_RESERVED_0XFCC GENMASK(31, 0) +#define SHU1_R2_B0_DQ0 0x00001000 + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU1_R2_B0_DQ1 0x00001004 + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU1_R2_B0_DQ2 0x00001008 + #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R2_B0_DQ3 0x0000100c + #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R2_B0_DQ4 0x00001010 + #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R2_B0_DQ5 0x00001014 + #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R2_B0_DQ6 0x00001018 + #define SHU1_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU1_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU1_R2_B0_DQ7 0x0000101c + #define SHU1_R2_B0_DQ7_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ7_RK2_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1020 0x00001020 + #define RFU_0X1020_RESERVED_0X1020 GENMASK(31, 0) +#define RFU_0X1024 0x00001024 + #define RFU_0X1024_RESERVED_0X1024 GENMASK(31, 0) +#define RFU_0X1028 0x00001028 + #define RFU_0X1028_RESERVED_0X1028 GENMASK(31, 0) +#define RFU_0X102C 0x0000102c + #define RFU_0X102C_RESERVED_0X102C GENMASK(31, 0) +#define SHU1_R2_B1_DQ0 0x00001050 + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU1_R2_B1_DQ1 0x00001054 + #define SHU1_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU1_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU1_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU1_R2_B1_DQ2 0x00001058 + #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R2_B1_DQ3 0x0000105c + #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R2_B1_DQ4 0x00001060 + #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R2_B1_DQ5 0x00001064 + #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R2_B1_DQ6 0x00001068 + #define SHU1_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU1_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU1_R2_B1_DQ7 0x0000106c + #define SHU1_R2_B1_DQ7_RK2_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ7_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1070 0x00001070 + #define RFU_0X1070_RESERVED_0X1070 GENMASK(31, 0) +#define RFU_0X1074 0x00001074 + #define RFU_0X1074_RESERVED_0X1074 GENMASK(31, 0) +#define RFU_0X1078 0x00001078 + #define RFU_0X1078_RESERVED_0X1078 GENMASK(31, 0) +#define RFU_0X107C 0x0000107c + #define RFU_0X107C_RESERVED_0X107C GENMASK(31, 0) +#define SHU1_R2_CA_CMD0 0x000010a0 + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU1_R2_CA_CMD1 0x000010a4 + #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU1_R2_CA_CMD2 0x000010a8 + #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD3 0x000010ac + #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD4 0x000010b0 + #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD5 0x000010b4 + #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD6 0x000010b8 + #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD7 0x000010bc + #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD8 0x000010c0 + #define SHU1_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU1_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU1_R2_CA_CMD9 0x000010c4 + #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CS GENMASK(5, 0) + #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CMD GENMASK(13, 8) + #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CLK GENMASK(29, 24) +#define RFU_0X10C8 0x000010c8 + #define RFU_0X10C8_RESERVED_0X10C8 GENMASK(31, 0) +#define RFU_0X10CC 0x000010cc + #define RFU_0X10CC_RESERVED_0X10CC GENMASK(31, 0) +#define SHU2_B0_DQ0 0x00001100 + #define SHU2_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 BIT(4) + #define SHU2_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 GENMASK(10, 8) + #define SHU2_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 GENMASK(14, 12) + #define SHU2_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 BIT(20) + #define SHU2_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 GENMASK(26, 24) + #define SHU2_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 GENMASK(30, 28) + #define SHU2_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 BIT(31) +#define SHU2_B0_DQ1 0x00001104 + #define SHU2_B0_DQ1_RG_TX_ARDQ_DRVP_B0 GENMASK(4, 0) + #define SHU2_B0_DQ1_RG_TX_ARDQ_DRVN_B0 GENMASK(12, 8) + #define SHU2_B0_DQ1_RG_TX_ARDQ_ODTP_B0 GENMASK(20, 16) + #define SHU2_B0_DQ1_RG_TX_ARDQ_ODTN_B0 GENMASK(28, 24) +#define SHU2_B0_DQ2 0x00001108 + #define SHU2_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 GENMASK(4, 0) + #define SHU2_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 GENMASK(12, 8) + #define SHU2_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 GENMASK(20, 16) + #define SHU2_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 GENMASK(28, 24) +#define SHU2_B0_DQ3 0x0000110c + #define SHU2_B0_DQ3_RG_TX_ARDQS0_PU_B0 GENMASK(1, 0) + #define SHU2_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 GENMASK(3, 2) + #define SHU2_B0_DQ3_RG_TX_ARDQS0_PDB_B0 GENMASK(5, 4) + #define SHU2_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 GENMASK(7, 6) + #define SHU2_B0_DQ3_RG_TX_ARDQ_PU_B0 GENMASK(9, 8) + #define SHU2_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 GENMASK(11, 10) + #define SHU2_B0_DQ3_RG_TX_ARDQ_PDB_B0 GENMASK(13, 12) + #define SHU2_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 GENMASK(15, 14) +#define SHU2_B0_DQ4 0x00001110 + #define SHU2_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 GENMASK(5, 0) + #define SHU2_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 GENMASK(13, 8) + #define SHU2_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 GENMASK(21, 16) +#define SHU2_B0_DQ5 0x00001114 + #define SHU2_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 GENMASK(5, 0) + #define SHU2_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 BIT(6) + #define SHU2_B0_DQ5_RG_ARPI_FB_B0 GENMASK(13, 8) + #define SHU2_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 GENMASK(18, 16) + #define SHU2_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0 BIT(19) + #define SHU2_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 GENMASK(22, 20) + #define SHU2_B0_DQ5_RG_ARPI_MCTL_B0 GENMASK(29, 24) +#define SHU2_B0_DQ6 0x00001118 + #define SHU2_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 GENMASK(5, 0) + #define SHU2_B0_DQ6_RG_ARPI_RESERVE_B0 GENMASK(21, 6) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 GENMASK(23, 22) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 GENMASK(25, 24) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_EN_B0 BIT(26) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 BIT(27) + #define SHU2_B0_DQ6_RG_ARPI_CAP_SEL_B0 GENMASK(29, 28) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0 BIT(31) +#define SHU2_B0_DQ7 0x0000111c + #define SHU2_B0_DQ7_R_DMRANKRXDVS_B0 GENMASK(3, 0) + #define SHU2_B0_DQ7_MIDPI_ENABLE BIT(4) + #define SHU2_B0_DQ7_MIDPI_DIV4_ENABLE BIT(5) + #define SHU2_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 BIT(6) + #define SHU2_B0_DQ7_R_DMDQMDBI_SHU_B0 BIT(7) + #define SHU2_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 GENMASK(11, 8) + #define SHU2_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 BIT(12) + #define SHU2_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 BIT(13) + #define SHU2_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 BIT(14) + #define SHU2_B0_DQ7_R_DMRODTEN_B0 BIT(15) + #define SHU2_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 BIT(16) + #define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 BIT(17) + #define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 BIT(18) + #define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 BIT(19) + #define SHU2_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 BIT(20) + #define SHU2_B0_DQ7_R_DMRXRANK_DQ_EN_B0 BIT(24) + #define SHU2_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 GENMASK(27, 25) + #define SHU2_B0_DQ7_R_DMRXRANK_DQS_EN_B0 BIT(28) + #define SHU2_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 GENMASK(31, 29) +#define SHU2_B0_DQ8 0x00001120 + #define SHU2_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 GENMASK(14, 0) + #define SHU2_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 BIT(15) + #define SHU2_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 BIT(19) + #define SHU2_B0_DQ8_R_RMRODTEN_CG_IG_B0 BIT(20) + #define SHU2_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 BIT(21) + #define SHU2_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 BIT(22) + #define SHU2_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 BIT(23) + #define SHU2_B0_DQ8_R_DMRXDLY_CG_IG_B0 BIT(24) + #define SHU2_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0 BIT(25) + #define SHU2_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 BIT(26) + #define SHU2_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 BIT(27) + #define SHU2_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 BIT(28) + #define SHU2_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 BIT(29) + #define SHU2_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 BIT(30) + #define SHU2_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 BIT(31) +#define SHU2_B0_DQ9 0x00001124 + #define SHU2_B0_DQ9_RESERVED_0X1124 GENMASK(31, 0) +#define SHU2_B0_DQ10 0x00001128 + #define SHU2_B0_DQ10_RESERVED_0X1128 GENMASK(31, 0) +#define SHU2_B0_DQ11 0x0000112c + #define SHU2_B0_DQ11_RESERVED_0X112C GENMASK(31, 0) +#define SHU2_B0_DQ12 0x00001130 + #define SHU2_B0_DQ12_RESERVED_0X1130 GENMASK(31, 0) +#define SHU2_B0_DLL0 0x00001134 + #define SHU2_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU BIT(0) + #define SHU2_B0_DLL0_B0_DLL0_RFU BIT(3) + #define SHU2_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 BIT(4) + #define SHU2_B0_DLL0_RG_ARDLL_PHDIV_B0 BIT(9) + #define SHU2_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0 BIT(10) + #define SHU2_B0_DLL0_RG_ARDLL_P_GAIN_B0 GENMASK(15, 12) + #define SHU2_B0_DLL0_RG_ARDLL_IDLECNT_B0 GENMASK(19, 16) + #define SHU2_B0_DLL0_RG_ARDLL_GAIN_B0 GENMASK(23, 20) + #define SHU2_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0 BIT(30) + #define SHU2_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0 BIT(31) +#define SHU2_B0_DLL1 0x00001138 + #define SHU2_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0 BIT(0) + #define SHU2_B0_DLL1_RG_ARDLL_PS_EN_B0 BIT(1) + #define SHU2_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 BIT(2) + #define SHU2_B0_DLL1_RG_ARDQ_REV_B0 GENMASK(31, 8) +#define SHU2_B1_DQ0 0x00001180 + #define SHU2_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 BIT(4) + #define SHU2_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 GENMASK(10, 8) + #define SHU2_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 GENMASK(14, 12) + #define SHU2_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 BIT(20) + #define SHU2_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 GENMASK(26, 24) + #define SHU2_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 GENMASK(30, 28) + #define SHU2_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 BIT(31) +#define SHU2_B1_DQ1 0x00001184 + #define SHU2_B1_DQ1_RG_TX_ARDQ_DRVP_B1 GENMASK(4, 0) + #define SHU2_B1_DQ1_RG_TX_ARDQ_DRVN_B1 GENMASK(12, 8) + #define SHU2_B1_DQ1_RG_TX_ARDQ_ODTP_B1 GENMASK(20, 16) + #define SHU2_B1_DQ1_RG_TX_ARDQ_ODTN_B1 GENMASK(28, 24) +#define SHU2_B1_DQ2 0x00001188 + #define SHU2_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 GENMASK(4, 0) + #define SHU2_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 GENMASK(12, 8) + #define SHU2_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 GENMASK(20, 16) + #define SHU2_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 GENMASK(28, 24) +#define SHU2_B1_DQ3 0x0000118c + #define SHU2_B1_DQ3_RG_TX_ARDQS0_PU_B1 GENMASK(1, 0) + #define SHU2_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 GENMASK(3, 2) + #define SHU2_B1_DQ3_RG_TX_ARDQS0_PDB_B1 GENMASK(5, 4) + #define SHU2_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 GENMASK(7, 6) + #define SHU2_B1_DQ3_RG_TX_ARDQ_PU_B1 GENMASK(9, 8) + #define SHU2_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 GENMASK(11, 10) + #define SHU2_B1_DQ3_RG_TX_ARDQ_PDB_B1 GENMASK(13, 12) + #define SHU2_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 GENMASK(15, 14) +#define SHU2_B1_DQ4 0x00001190 + #define SHU2_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 GENMASK(5, 0) + #define SHU2_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 GENMASK(13, 8) + #define SHU2_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 GENMASK(21, 16) +#define SHU2_B1_DQ5 0x00001194 + #define SHU2_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 GENMASK(5, 0) + #define SHU2_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 BIT(6) + #define SHU2_B1_DQ5_RG_ARPI_FB_B1 GENMASK(13, 8) + #define SHU2_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 GENMASK(18, 16) + #define SHU2_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1 BIT(19) + #define SHU2_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 GENMASK(22, 20) + #define SHU2_B1_DQ5_RG_ARPI_MCTL_B1 GENMASK(29, 24) +#define SHU2_B1_DQ6 0x00001198 + #define SHU2_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 GENMASK(5, 0) + #define SHU2_B1_DQ6_RG_ARPI_RESERVE_B1 GENMASK(21, 6) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 GENMASK(23, 22) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 GENMASK(25, 24) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_EN_B1 BIT(26) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 BIT(27) + #define SHU2_B1_DQ6_RG_ARPI_CAP_SEL_B1 GENMASK(29, 28) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1 BIT(31) +#define SHU2_B1_DQ7 0x0000119c + #define SHU2_B1_DQ7_R_DMRANKRXDVS_B1 GENMASK(3, 0) + #define SHU2_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 BIT(6) + #define SHU2_B1_DQ7_R_DMDQMDBI_SHU_B1 BIT(7) + #define SHU2_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 GENMASK(11, 8) + #define SHU2_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 BIT(12) + #define SHU2_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 BIT(13) + #define SHU2_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 BIT(14) + #define SHU2_B1_DQ7_R_DMRODTEN_B1 BIT(15) + #define SHU2_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 BIT(16) + #define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 BIT(17) + #define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 BIT(18) + #define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 BIT(19) + #define SHU2_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 BIT(20) + #define SHU2_B1_DQ7_R_DMRXRANK_DQ_EN_B1 BIT(24) + #define SHU2_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 GENMASK(27, 25) + #define SHU2_B1_DQ7_R_DMRXRANK_DQS_EN_B1 BIT(28) + #define SHU2_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 GENMASK(31, 29) +#define SHU2_B1_DQ8 0x000011a0 + #define SHU2_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 GENMASK(14, 0) + #define SHU2_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 BIT(15) + #define SHU2_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 BIT(19) + #define SHU2_B1_DQ8_R_RMRODTEN_CG_IG_B1 BIT(20) + #define SHU2_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 BIT(21) + #define SHU2_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 BIT(22) + #define SHU2_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 BIT(23) + #define SHU2_B1_DQ8_R_DMRXDLY_CG_IG_B1 BIT(24) + #define SHU2_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1 BIT(25) + #define SHU2_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 BIT(26) + #define SHU2_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 BIT(27) + #define SHU2_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 BIT(28) + #define SHU2_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 BIT(29) + #define SHU2_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 BIT(30) + #define SHU2_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 BIT(31) +#define SHU2_B1_DQ9 0x000011a4 + #define SHU2_B1_DQ9_RESERVED_0X11A4 GENMASK(31, 0) +#define SHU2_B1_DQ10 0x000011a8 + #define SHU2_B1_DQ10_RESERVED_0X11A8 GENMASK(31, 0) +#define SHU2_B1_DQ11 0x000011ac + #define SHU2_B1_DQ11_RESERVED_0X11AC GENMASK(31, 0) +#define SHU2_B1_DQ12 0x000011b0 + #define SHU2_B1_DQ12_RESERVED_0X11B0 GENMASK(31, 0) +#define SHU2_B1_DLL0 0x000011b4 + #define SHU2_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU BIT(0) + #define SHU2_B1_DLL0_B1_DLL0_RFU BIT(3) + #define SHU2_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 BIT(4) + #define SHU2_B1_DLL0_RG_ARDLL_PHDIV_B1 BIT(9) + #define SHU2_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1 BIT(10) + #define SHU2_B1_DLL0_RG_ARDLL_P_GAIN_B1 GENMASK(15, 12) + #define SHU2_B1_DLL0_RG_ARDLL_IDLECNT_B1 GENMASK(19, 16) + #define SHU2_B1_DLL0_RG_ARDLL_GAIN_B1 GENMASK(23, 20) + #define SHU2_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1 BIT(30) + #define SHU2_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1 BIT(31) +#define SHU2_B1_DLL1 0x000011b8 + #define SHU2_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1 BIT(0) + #define SHU2_B1_DLL1_RG_ARDLL_PS_EN_B1 BIT(1) + #define SHU2_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 BIT(2) + #define SHU2_B1_DLL1_RG_ARDQ_REV_B1 GENMASK(31, 8) +#define SHU2_CA_CMD0 0x00001200 + #define SHU2_CA_CMD0_RG_TX_ARCLK_PRE_EN BIT(4) + #define SHU2_CA_CMD0_RG_TX_ARCLK_DRVP_PRE GENMASK(10, 8) + #define SHU2_CA_CMD0_RG_TX_ARCLK_DRVN_PRE GENMASK(14, 12) + #define SHU2_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL BIT(17) + #define SHU2_CA_CMD0_RG_FB_CK_MUX GENMASK(19, 18) + #define SHU2_CA_CMD0_RG_TX_ARCMD_PRE_EN BIT(20) + #define SHU2_CA_CMD0_RG_TX_ARCMD_DRVP_PRE GENMASK(26, 24) + #define SHU2_CA_CMD0_RG_TX_ARCMD_DRVN_PRE GENMASK(30, 28) + #define SHU2_CA_CMD0_R_LP4Y_WDN_MODE_CLK BIT(31) +#define SHU2_CA_CMD1 0x00001204 + #define SHU2_CA_CMD1_RG_TX_ARCMD_DRVP GENMASK(4, 0) + #define SHU2_CA_CMD1_RG_TX_ARCMD_DRVN GENMASK(12, 8) + #define SHU2_CA_CMD1_RG_TX_ARCMD_ODTP GENMASK(20, 16) + #define SHU2_CA_CMD1_RG_TX_ARCMD_ODTN GENMASK(28, 24) +#define SHU2_CA_CMD2 0x00001208 + #define SHU2_CA_CMD2_RG_TX_ARCLK_DRVP GENMASK(4, 0) + #define SHU2_CA_CMD2_RG_TX_ARCLK_DRVN GENMASK(12, 8) + #define SHU2_CA_CMD2_RG_TX_ARCLK_ODTP GENMASK(20, 16) + #define SHU2_CA_CMD2_RG_TX_ARCLK_ODTN GENMASK(28, 24) +#define SHU2_CA_CMD3 0x0000120c + #define SHU2_CA_CMD3_RG_TX_ARCLK_PU GENMASK(1, 0) + #define SHU2_CA_CMD3_RG_TX_ARCLK_PU_PRE GENMASK(3, 2) + #define SHU2_CA_CMD3_RG_TX_ARCLK_PDB GENMASK(5, 4) + #define SHU2_CA_CMD3_RG_TX_ARCLK_PDB_PRE GENMASK(7, 6) + #define SHU2_CA_CMD3_RG_TX_ARCMD_PU GENMASK(9, 8) + #define SHU2_CA_CMD3_RG_TX_ARCMD_PU_PRE GENMASK(11, 10) + #define SHU2_CA_CMD3_RG_TX_ARCMD_PDB GENMASK(13, 12) + #define SHU2_CA_CMD3_RG_TX_ARCMD_PDB_PRE GENMASK(15, 14) +#define SHU2_CA_CMD4 0x00001210 + #define SHU2_CA_CMD4_RG_ARPI_AA_MCK_DL_CA GENMASK(5, 0) + #define SHU2_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA GENMASK(13, 8) + #define SHU2_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA GENMASK(21, 16) +#define SHU2_CA_CMD5 0x00001214 + #define SHU2_CA_CMD5_RG_RX_ARCMD_VREF_SEL GENMASK(5, 0) + #define SHU2_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS BIT(6) + #define SHU2_CA_CMD5_RG_ARPI_FB_CA GENMASK(13, 8) + #define SHU2_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY GENMASK(18, 16) + #define SHU2_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY BIT(19) + #define SHU2_CA_CMD5_RG_RX_ARCLK_DVS_DLY GENMASK(22, 20) + #define SHU2_CA_CMD5_RG_ARPI_MCTL_CA GENMASK(29, 24) +#define SHU2_CA_CMD6 0x00001218 + #define SHU2_CA_CMD6_RG_ARPI_OFFSET_CLKIEN GENMASK(5, 0) + #define SHU2_CA_CMD6_RG_ARPI_RESERVE_CA GENMASK(21, 6) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA GENMASK(23, 22) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA GENMASK(25, 24) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_EN_CA BIT(26) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA BIT(27) + #define SHU2_CA_CMD6_RG_ARPI_CAP_SEL_CA GENMASK(29, 28) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA BIT(31) +#define SHU2_CA_CMD7 0x0000121c + #define SHU2_CA_CMD7_R_DMRANKRXDVS_CA GENMASK(3, 0) + #define SHU2_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA BIT(12) + #define SHU2_CA_CMD7_R_DMRODTEN_CA BIT(15) + #define SHU2_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA BIT(16) + #define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW BIT(17) + #define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW BIT(18) + #define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW BIT(19) + #define SHU2_CA_CMD7_R_LP4Y_SDN_MODE_CLK BIT(20) + #define SHU2_CA_CMD7_R_DMRXRANK_CMD_EN BIT(24) + #define SHU2_CA_CMD7_R_DMRXRANK_CMD_LAT GENMASK(27, 25) + #define SHU2_CA_CMD7_R_DMRXRANK_CLK_EN BIT(28) + #define SHU2_CA_CMD7_R_DMRXRANK_CLK_LAT GENMASK(31, 29) +#define SHU2_CA_CMD8 0x00001220 + #define SHU2_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA GENMASK(14, 0) + #define SHU2_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA BIT(15) + #define SHU2_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA BIT(19) + #define SHU2_CA_CMD8_R_RMRODTEN_CG_IG_CA BIT(20) + #define SHU2_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA BIT(21) + #define SHU2_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA BIT(22) + #define SHU2_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA BIT(23) + #define SHU2_CA_CMD8_R_DMRXDLY_CG_IG_CA BIT(24) + #define SHU2_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA BIT(25) + #define SHU2_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA BIT(26) + #define SHU2_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA BIT(27) + #define SHU2_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA BIT(28) + #define SHU2_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA BIT(29) + #define SHU2_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA BIT(30) + #define SHU2_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA BIT(31) +#define SHU2_CA_CMD9 0x00001224 + #define SHU2_CA_CMD9_RESERVED_0X1224 GENMASK(31, 0) +#define SHU2_CA_CMD10 0x00001228 + #define SHU2_CA_CMD10_RESERVED_0X1228 GENMASK(31, 0) +#define SHU2_CA_CMD11 0x0000122c + #define SHU2_CA_CMD11_RG_RIMP_REV GENMASK(7, 0) + #define SHU2_CA_CMD11_RG_RIMP_VREF_SEL GENMASK(13, 8) + #define SHU2_CA_CMD11_RG_TX_ARCKE_DRVP GENMASK(21, 17) + #define SHU2_CA_CMD11_RG_TX_ARCKE_DRVN GENMASK(26, 22) +#define SHU2_CA_CMD12 0x00001230 + #define SHU2_CA_CMD12_RESERVED_0X1230 GENMASK(31, 0) +#define SHU2_CA_DLL0 0x00001234 + #define SHU2_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU BIT(0) + #define SHU2_CA_DLL0_CA_DLL0_RFU BIT(3) + #define SHU2_CA_DLL0_RG_ARDLL_FAST_PSJP_CA BIT(4) + #define SHU2_CA_DLL0_RG_ARDLL_PHDIV_CA BIT(9) + #define SHU2_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA BIT(10) + #define SHU2_CA_DLL0_RG_ARDLL_P_GAIN_CA GENMASK(15, 12) + #define SHU2_CA_DLL0_RG_ARDLL_IDLECNT_CA GENMASK(19, 16) + #define SHU2_CA_DLL0_RG_ARDLL_GAIN_CA GENMASK(23, 20) + #define SHU2_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA BIT(30) + #define SHU2_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA BIT(31) +#define SHU2_CA_DLL1 0x00001238 + #define SHU2_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA BIT(0) + #define SHU2_CA_DLL1_RG_ARDLL_PS_EN_CA BIT(1) + #define SHU2_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA BIT(2) + #define SHU2_CA_DLL1_RG_ARCMD_REV GENMASK(31, 8) +#define SHU2_MISC0 0x000012f0 + #define SHU2_MISC0_R_RX_PIPE_BYPASS_EN BIT(1) + #define SHU2_MISC0_RG_CMD_TXPIPE_BYPASS_EN BIT(2) + #define SHU2_MISC0_RG_CK_TXPIPE_BYPASS_EN BIT(3) + #define SHU2_MISC0_RG_RVREF_SEL_DQ GENMASK(21, 16) + #define SHU2_MISC0_RG_RVREF_DDR4_SEL BIT(22) + #define SHU2_MISC0_RG_RVREF_DDR3_SEL BIT(23) + #define SHU2_MISC0_RG_RVREF_SEL_CMD GENMASK(29, 24) +#define SHU2_R0_B0_DQ0 0x00001300 + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU2_R0_B0_DQ1 0x00001304 + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU2_R0_B0_DQ2 0x00001308 + #define SHU2_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R0_B0_DQ3 0x0000130c + #define SHU2_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R0_B0_DQ4 0x00001310 + #define SHU2_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R0_B0_DQ5 0x00001314 + #define SHU2_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R0_B0_DQ6 0x00001318 + #define SHU2_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU2_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU2_R0_B0_DQ7 0x0000131c + #define SHU2_R0_B0_DQ7_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ7_RK0_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1320 0x00001320 + #define RFU_0X1320_RESERVED_0X1320 GENMASK(31, 0) +#define RFU_0X1324 0x00001324 + #define RFU_0X1324_RESERVED_0X1324 GENMASK(31, 0) +#define RFU_0X1328 0x00001328 + #define RFU_0X1328_RESERVED_0X1328 GENMASK(31, 0) +#define RFU_0X132C 0x0000132c + #define RFU_0X132C_RESERVED_0X132C GENMASK(31, 0) +#define SHU2_R0_B1_DQ0 0x00001350 + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU2_R0_B1_DQ1 0x00001354 + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU2_R0_B1_DQ2 0x00001358 + #define SHU2_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R0_B1_DQ3 0x0000135c + #define SHU2_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R0_B1_DQ4 0x00001360 + #define SHU2_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R0_B1_DQ5 0x00001364 + #define SHU2_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R0_B1_DQ6 0x00001368 + #define SHU2_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU2_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU2_R0_B1_DQ7 0x0000136c + #define SHU2_R0_B1_DQ7_RK0_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ7_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1370 0x00001370 + #define RFU_0X1370_RESERVED_0X1370 GENMASK(31, 0) +#define RFU_0X1374 0x00001374 + #define RFU_0X1374_RESERVED_0X1374 GENMASK(31, 0) +#define RFU_0X1378 0x00001378 + #define RFU_0X1378_RESERVED_0X1378 GENMASK(31, 0) +#define RFU_0X137C 0x0000137c + #define RFU_0X137C_RESERVED_0X137C GENMASK(31, 0) +#define SHU2_R0_CA_CMD0 0x000013a0 + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU2_R0_CA_CMD1 0x000013a4 + #define SHU2_R0_CA_CMD1_RK0_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU2_R0_CA_CMD2 0x000013a8 + #define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD3 0x000013ac + #define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD4 0x000013b0 + #define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD5 0x000013b4 + #define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD6 0x000013b8 + #define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD7 0x000013bc + #define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD8 0x000013c0 + #define SHU2_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU2_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU2_R0_CA_CMD9 0x000013c4 + #define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CS GENMASK(5, 0) + #define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CMD GENMASK(13, 8) + #define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CLK GENMASK(29, 24) +#define RFU_0X13C8 0x000013c8 + #define RFU_0X13C8_RESERVED_0X13C8 GENMASK(31, 0) +#define RFU_0X13CC 0x000013cc + #define RFU_0X13CC_RESERVED_0X13CC GENMASK(31, 0) +#define SHU2_R1_B0_DQ0 0x00001400 + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU2_R1_B0_DQ1 0x00001404 + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU2_R1_B0_DQ2 0x00001408 + #define SHU2_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R1_B0_DQ3 0x0000140c + #define SHU2_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R1_B0_DQ4 0x00001410 + #define SHU2_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R1_B0_DQ5 0x00001414 + #define SHU2_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R1_B0_DQ6 0x00001418 + #define SHU2_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU2_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU2_R1_B0_DQ7 0x0000141c + #define SHU2_R1_B0_DQ7_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ7_RK1_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1420 0x00001420 + #define RFU_0X1420_RESERVED_0X1420 GENMASK(31, 0) +#define RFU_0X1424 0x00001424 + #define RFU_0X1424_RESERVED_0X1424 GENMASK(31, 0) +#define RFU_0X1428 0x00001428 + #define RFU_0X1428_RESERVED_0X1428 GENMASK(31, 0) +#define RFU_0X142C 0x0000142c + #define RFU_0X142C_RESERVED_0X142C GENMASK(31, 0) +#define SHU2_R1_B1_DQ0 0x00001450 + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU2_R1_B1_DQ1 0x00001454 + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU2_R1_B1_DQ2 0x00001458 + #define SHU2_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R1_B1_DQ3 0x0000145c + #define SHU2_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R1_B1_DQ4 0x00001460 + #define SHU2_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R1_B1_DQ5 0x00001464 + #define SHU2_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R1_B1_DQ6 0x00001468 + #define SHU2_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU2_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU2_R1_B1_DQ7 0x0000146c + #define SHU2_R1_B1_DQ7_RK1_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ7_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1470 0x00001470 + #define RFU_0X1470_RESERVED_0X1470 GENMASK(31, 0) +#define RFU_0X1474 0x00001474 + #define RFU_0X1474_RESERVED_0X1474 GENMASK(31, 0) +#define RFU_0X1478 0x00001478 + #define RFU_0X1478_RESERVED_0X1478 GENMASK(31, 0) +#define RFU_0X147C 0x0000147c + #define RFU_0X147C_RESERVED_0X147C GENMASK(31, 0) +#define SHU2_R1_CA_CMD0 0x000014a0 + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU2_R1_CA_CMD1 0x000014a4 + #define SHU2_R1_CA_CMD1_RK1_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU2_R1_CA_CMD2 0x000014a8 + #define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD3 0x000014ac + #define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD4 0x000014b0 + #define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD5 0x000014b4 + #define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD6 0x000014b8 + #define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD7 0x000014bc + #define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD8 0x000014c0 + #define SHU2_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU2_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU2_R1_CA_CMD9 0x000014c4 + #define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CS GENMASK(5, 0) + #define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CMD GENMASK(13, 8) + #define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CLK GENMASK(29, 24) +#define RFU_0X14C8 0x000014c8 + #define RFU_0X14C8_RESERVED_0X14C8 GENMASK(31, 0) +#define RFU_0X14CC 0x000014cc + #define RFU_0X14CC_RESERVED_0X14CC GENMASK(31, 0) +#define SHU2_R2_B0_DQ0 0x00001500 + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU2_R2_B0_DQ1 0x00001504 + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU2_R2_B0_DQ2 0x00001508 + #define SHU2_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R2_B0_DQ3 0x0000150c + #define SHU2_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R2_B0_DQ4 0x00001510 + #define SHU2_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R2_B0_DQ5 0x00001514 + #define SHU2_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R2_B0_DQ6 0x00001518 + #define SHU2_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU2_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU2_R2_B0_DQ7 0x0000151c + #define SHU2_R2_B0_DQ7_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ7_RK2_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1520 0x00001520 + #define RFU_0X1520_RESERVED_0X1520 GENMASK(31, 0) +#define RFU_0X1524 0x00001524 + #define RFU_0X1524_RESERVED_0X1524 GENMASK(31, 0) +#define RFU_0X1528 0x00001528 + #define RFU_0X1528_RESERVED_0X1528 GENMASK(31, 0) +#define RFU_0X152C 0x0000152c + #define RFU_0X152C_RESERVED_0X152C GENMASK(31, 0) +#define SHU2_R2_B1_DQ0 0x00001550 + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU2_R2_B1_DQ1 0x00001554 + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU2_R2_B1_DQ2 0x00001558 + #define SHU2_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R2_B1_DQ3 0x0000155c + #define SHU2_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R2_B1_DQ4 0x00001560 + #define SHU2_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R2_B1_DQ5 0x00001564 + #define SHU2_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R2_B1_DQ6 0x00001568 + #define SHU2_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU2_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU2_R2_B1_DQ7 0x0000156c + #define SHU2_R2_B1_DQ7_RK2_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ7_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1570 0x00001570 + #define RFU_0X1570_RESERVED_0X1570 GENMASK(31, 0) +#define RFU_0X1574 0x00001574 + #define RFU_0X1574_RESERVED_0X1574 GENMASK(31, 0) +#define RFU_0X1578 0x00001578 + #define RFU_0X1578_RESERVED_0X1578 GENMASK(31, 0) +#define RFU_0X157C 0x0000157c + #define RFU_0X157C_RESERVED_0X157C GENMASK(31, 0) +#define SHU2_R2_CA_CMD0 0x000015a0 + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU2_R2_CA_CMD1 0x000015a4 + #define SHU2_R2_CA_CMD1_RK2_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU2_R2_CA_CMD2 0x000015a8 + #define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD3 0x000015ac + #define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD4 0x000015b0 + #define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD5 0x000015b4 + #define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD6 0x000015b8 + #define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD7 0x000015bc + #define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD8 0x000015c0 + #define SHU2_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU2_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU2_R2_CA_CMD9 0x000015c4 + #define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CS GENMASK(5, 0) + #define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CMD GENMASK(13, 8) + #define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CLK GENMASK(29, 24) +#define RFU_0X15C8 0x000015c8 + #define RFU_0X15C8_RESERVED_0X15C8 GENMASK(31, 0) +#define RFU_0X15CC 0x000015cc + #define RFU_0X15CC_RESERVED_0X15CC GENMASK(31, 0) +#define SHU3_B0_DQ0 0x00001600 + #define SHU3_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 BIT(4) + #define SHU3_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 GENMASK(10, 8) + #define SHU3_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 GENMASK(14, 12) + #define SHU3_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 BIT(20) + #define SHU3_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 GENMASK(26, 24) + #define SHU3_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 GENMASK(30, 28) + #define SHU3_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 BIT(31) +#define SHU3_B0_DQ1 0x00001604 + #define SHU3_B0_DQ1_RG_TX_ARDQ_DRVP_B0 GENMASK(4, 0) + #define SHU3_B0_DQ1_RG_TX_ARDQ_DRVN_B0 GENMASK(12, 8) + #define SHU3_B0_DQ1_RG_TX_ARDQ_ODTP_B0 GENMASK(20, 16) + #define SHU3_B0_DQ1_RG_TX_ARDQ_ODTN_B0 GENMASK(28, 24) +#define SHU3_B0_DQ2 0x00001608 + #define SHU3_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 GENMASK(4, 0) + #define SHU3_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 GENMASK(12, 8) + #define SHU3_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 GENMASK(20, 16) + #define SHU3_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 GENMASK(28, 24) +#define SHU3_B0_DQ3 0x0000160c + #define SHU3_B0_DQ3_RG_TX_ARDQS0_PU_B0 GENMASK(1, 0) + #define SHU3_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 GENMASK(3, 2) + #define SHU3_B0_DQ3_RG_TX_ARDQS0_PDB_B0 GENMASK(5, 4) + #define SHU3_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 GENMASK(7, 6) + #define SHU3_B0_DQ3_RG_TX_ARDQ_PU_B0 GENMASK(9, 8) + #define SHU3_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 GENMASK(11, 10) + #define SHU3_B0_DQ3_RG_TX_ARDQ_PDB_B0 GENMASK(13, 12) + #define SHU3_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 GENMASK(15, 14) +#define SHU3_B0_DQ4 0x00001610 + #define SHU3_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 GENMASK(5, 0) + #define SHU3_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 GENMASK(13, 8) + #define SHU3_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 GENMASK(21, 16) +#define SHU3_B0_DQ5 0x00001614 + #define SHU3_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 GENMASK(5, 0) + #define SHU3_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 BIT(6) + #define SHU3_B0_DQ5_RG_ARPI_FB_B0 GENMASK(13, 8) + #define SHU3_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 GENMASK(18, 16) + #define SHU3_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0 BIT(19) + #define SHU3_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 GENMASK(22, 20) + #define SHU3_B0_DQ5_RG_ARPI_MCTL_B0 GENMASK(29, 24) +#define SHU3_B0_DQ6 0x00001618 + #define SHU3_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 GENMASK(5, 0) + #define SHU3_B0_DQ6_RG_ARPI_RESERVE_B0 GENMASK(21, 6) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 GENMASK(23, 22) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 GENMASK(25, 24) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_EN_B0 BIT(26) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 BIT(27) + #define SHU3_B0_DQ6_RG_ARPI_CAP_SEL_B0 GENMASK(29, 28) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0 BIT(31) +#define SHU3_B0_DQ7 0x0000161c + #define SHU3_B0_DQ7_R_DMRANKRXDVS_B0 GENMASK(3, 0) + #define SHU3_B0_DQ7_MIDPI_ENABLE BIT(4) + #define SHU3_B0_DQ7_MIDPI_DIV4_ENABLE BIT(5) + #define SHU3_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 BIT(6) + #define SHU3_B0_DQ7_R_DMDQMDBI_SHU_B0 BIT(7) + #define SHU3_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 GENMASK(11, 8) + #define SHU3_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 BIT(12) + #define SHU3_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 BIT(13) + #define SHU3_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 BIT(14) + #define SHU3_B0_DQ7_R_DMRODTEN_B0 BIT(15) + #define SHU3_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 BIT(16) + #define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 BIT(17) + #define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 BIT(18) + #define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 BIT(19) + #define SHU3_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 BIT(20) + #define SHU3_B0_DQ7_R_DMRXRANK_DQ_EN_B0 BIT(24) + #define SHU3_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 GENMASK(27, 25) + #define SHU3_B0_DQ7_R_DMRXRANK_DQS_EN_B0 BIT(28) + #define SHU3_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 GENMASK(31, 29) +#define SHU3_B0_DQ8 0x00001620 + #define SHU3_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 GENMASK(14, 0) + #define SHU3_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 BIT(15) + #define SHU3_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 BIT(19) + #define SHU3_B0_DQ8_R_RMRODTEN_CG_IG_B0 BIT(20) + #define SHU3_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 BIT(21) + #define SHU3_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 BIT(22) + #define SHU3_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 BIT(23) + #define SHU3_B0_DQ8_R_DMRXDLY_CG_IG_B0 BIT(24) + #define SHU3_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0 BIT(25) + #define SHU3_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 BIT(26) + #define SHU3_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 BIT(27) + #define SHU3_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 BIT(28) + #define SHU3_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 BIT(29) + #define SHU3_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 BIT(30) + #define SHU3_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 BIT(31) +#define SHU3_B0_DQ9 0x00001624 + #define SHU3_B0_DQ9_RESERVED_0X1624 GENMASK(31, 0) +#define SHU3_B0_DQ10 0x00001628 + #define SHU3_B0_DQ10_RESERVED_0X1628 GENMASK(31, 0) +#define SHU3_B0_DQ11 0x0000162c + #define SHU3_B0_DQ11_RESERVED_0X162C GENMASK(31, 0) +#define SHU3_B0_DQ12 0x00001630 + #define SHU3_B0_DQ12_RESERVED_0X1630 GENMASK(31, 0) +#define SHU3_B0_DLL0 0x00001634 + #define SHU3_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU BIT(0) + #define SHU3_B0_DLL0_B0_DLL0_RFU BIT(3) + #define SHU3_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 BIT(4) + #define SHU3_B0_DLL0_RG_ARDLL_PHDIV_B0 BIT(9) + #define SHU3_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0 BIT(10) + #define SHU3_B0_DLL0_RG_ARDLL_P_GAIN_B0 GENMASK(15, 12) + #define SHU3_B0_DLL0_RG_ARDLL_IDLECNT_B0 GENMASK(19, 16) + #define SHU3_B0_DLL0_RG_ARDLL_GAIN_B0 GENMASK(23, 20) + #define SHU3_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0 BIT(30) + #define SHU3_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0 BIT(31) +#define SHU3_B0_DLL1 0x00001638 + #define SHU3_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0 BIT(0) + #define SHU3_B0_DLL1_RG_ARDLL_PS_EN_B0 BIT(1) + #define SHU3_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 BIT(2) + #define SHU3_B0_DLL1_RG_ARDQ_REV_B0 GENMASK(31, 8) +#define SHU3_B1_DQ0 0x00001680 + #define SHU3_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 BIT(4) + #define SHU3_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 GENMASK(10, 8) + #define SHU3_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 GENMASK(14, 12) + #define SHU3_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 BIT(20) + #define SHU3_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 GENMASK(26, 24) + #define SHU3_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 GENMASK(30, 28) + #define SHU3_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 BIT(31) +#define SHU3_B1_DQ1 0x00001684 + #define SHU3_B1_DQ1_RG_TX_ARDQ_DRVP_B1 GENMASK(4, 0) + #define SHU3_B1_DQ1_RG_TX_ARDQ_DRVN_B1 GENMASK(12, 8) + #define SHU3_B1_DQ1_RG_TX_ARDQ_ODTP_B1 GENMASK(20, 16) + #define SHU3_B1_DQ1_RG_TX_ARDQ_ODTN_B1 GENMASK(28, 24) +#define SHU3_B1_DQ2 0x00001688 + #define SHU3_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 GENMASK(4, 0) + #define SHU3_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 GENMASK(12, 8) + #define SHU3_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 GENMASK(20, 16) + #define SHU3_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 GENMASK(28, 24) +#define SHU3_B1_DQ3 0x0000168c + #define SHU3_B1_DQ3_RG_TX_ARDQS0_PU_B1 GENMASK(1, 0) + #define SHU3_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 GENMASK(3, 2) + #define SHU3_B1_DQ3_RG_TX_ARDQS0_PDB_B1 GENMASK(5, 4) + #define SHU3_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 GENMASK(7, 6) + #define SHU3_B1_DQ3_RG_TX_ARDQ_PU_B1 GENMASK(9, 8) + #define SHU3_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 GENMASK(11, 10) + #define SHU3_B1_DQ3_RG_TX_ARDQ_PDB_B1 GENMASK(13, 12) + #define SHU3_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 GENMASK(15, 14) +#define SHU3_B1_DQ4 0x00001690 + #define SHU3_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 GENMASK(5, 0) + #define SHU3_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 GENMASK(13, 8) + #define SHU3_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 GENMASK(21, 16) +#define SHU3_B1_DQ5 0x00001694 + #define SHU3_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 GENMASK(5, 0) + #define SHU3_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 BIT(6) + #define SHU3_B1_DQ5_RG_ARPI_FB_B1 GENMASK(13, 8) + #define SHU3_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 GENMASK(18, 16) + #define SHU3_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1 BIT(19) + #define SHU3_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 GENMASK(22, 20) + #define SHU3_B1_DQ5_RG_ARPI_MCTL_B1 GENMASK(29, 24) +#define SHU3_B1_DQ6 0x00001698 + #define SHU3_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 GENMASK(5, 0) + #define SHU3_B1_DQ6_RG_ARPI_RESERVE_B1 GENMASK(21, 6) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 GENMASK(23, 22) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 GENMASK(25, 24) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_EN_B1 BIT(26) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 BIT(27) + #define SHU3_B1_DQ6_RG_ARPI_CAP_SEL_B1 GENMASK(29, 28) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1 BIT(31) +#define SHU3_B1_DQ7 0x0000169c + #define SHU3_B1_DQ7_R_DMRANKRXDVS_B1 GENMASK(3, 0) + #define SHU3_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 BIT(6) + #define SHU3_B1_DQ7_R_DMDQMDBI_SHU_B1 BIT(7) + #define SHU3_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 GENMASK(11, 8) + #define SHU3_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 BIT(12) + #define SHU3_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 BIT(13) + #define SHU3_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 BIT(14) + #define SHU3_B1_DQ7_R_DMRODTEN_B1 BIT(15) + #define SHU3_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 BIT(16) + #define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 BIT(17) + #define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 BIT(18) + #define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 BIT(19) + #define SHU3_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 BIT(20) + #define SHU3_B1_DQ7_R_DMRXRANK_DQ_EN_B1 BIT(24) + #define SHU3_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 GENMASK(27, 25) + #define SHU3_B1_DQ7_R_DMRXRANK_DQS_EN_B1 BIT(28) + #define SHU3_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 GENMASK(31, 29) +#define SHU3_B1_DQ8 0x000016a0 + #define SHU3_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 GENMASK(14, 0) + #define SHU3_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 BIT(15) + #define SHU3_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 BIT(19) + #define SHU3_B1_DQ8_R_RMRODTEN_CG_IG_B1 BIT(20) + #define SHU3_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 BIT(21) + #define SHU3_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 BIT(22) + #define SHU3_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 BIT(23) + #define SHU3_B1_DQ8_R_DMRXDLY_CG_IG_B1 BIT(24) + #define SHU3_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1 BIT(25) + #define SHU3_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 BIT(26) + #define SHU3_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 BIT(27) + #define SHU3_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 BIT(28) + #define SHU3_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 BIT(29) + #define SHU3_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 BIT(30) + #define SHU3_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 BIT(31) +#define SHU3_B1_DQ9 0x000016a4 + #define SHU3_B1_DQ9_RESERVED_0X16A4 GENMASK(31, 0) +#define SHU3_B1_DQ10 0x000016a8 + #define SHU3_B1_DQ10_RESERVED_0X16A8 GENMASK(31, 0) +#define SHU3_B1_DQ11 0x000016ac + #define SHU3_B1_DQ11_RESERVED_0X16AC GENMASK(31, 0) +#define SHU3_B1_DQ12 0x000016b0 + #define SHU3_B1_DQ12_RESERVED_0X16B0 GENMASK(31, 0) +#define SHU3_B1_DLL0 0x000016b4 + #define SHU3_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU BIT(0) + #define SHU3_B1_DLL0_B1_DLL0_RFU BIT(3) + #define SHU3_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 BIT(4) + #define SHU3_B1_DLL0_RG_ARDLL_PHDIV_B1 BIT(9) + #define SHU3_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1 BIT(10) + #define SHU3_B1_DLL0_RG_ARDLL_P_GAIN_B1 GENMASK(15, 12) + #define SHU3_B1_DLL0_RG_ARDLL_IDLECNT_B1 GENMASK(19, 16) + #define SHU3_B1_DLL0_RG_ARDLL_GAIN_B1 GENMASK(23, 20) + #define SHU3_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1 BIT(30) + #define SHU3_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1 BIT(31) +#define SHU3_B1_DLL1 0x000016b8 + #define SHU3_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1 BIT(0) + #define SHU3_B1_DLL1_RG_ARDLL_PS_EN_B1 BIT(1) + #define SHU3_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 BIT(2) + #define SHU3_B1_DLL1_RG_ARDQ_REV_B1 GENMASK(31, 8) +#define SHU3_CA_CMD0 0x00001700 + #define SHU3_CA_CMD0_RG_TX_ARCLK_PRE_EN BIT(4) + #define SHU3_CA_CMD0_RG_TX_ARCLK_DRVP_PRE GENMASK(10, 8) + #define SHU3_CA_CMD0_RG_TX_ARCLK_DRVN_PRE GENMASK(14, 12) + #define SHU3_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL BIT(17) + #define SHU3_CA_CMD0_RG_FB_CK_MUX GENMASK(19, 18) + #define SHU3_CA_CMD0_RG_TX_ARCMD_PRE_EN BIT(20) + #define SHU3_CA_CMD0_RG_TX_ARCMD_DRVP_PRE GENMASK(26, 24) + #define SHU3_CA_CMD0_RG_TX_ARCMD_DRVN_PRE GENMASK(30, 28) + #define SHU3_CA_CMD0_R_LP4Y_WDN_MODE_CLK BIT(31) +#define SHU3_CA_CMD1 0x00001704 + #define SHU3_CA_CMD1_RG_TX_ARCMD_DRVP GENMASK(4, 0) + #define SHU3_CA_CMD1_RG_TX_ARCMD_DRVN GENMASK(12, 8) + #define SHU3_CA_CMD1_RG_TX_ARCMD_ODTP GENMASK(20, 16) + #define SHU3_CA_CMD1_RG_TX_ARCMD_ODTN GENMASK(28, 24) +#define SHU3_CA_CMD2 0x00001708 + #define SHU3_CA_CMD2_RG_TX_ARCLK_DRVP GENMASK(4, 0) + #define SHU3_CA_CMD2_RG_TX_ARCLK_DRVN GENMASK(12, 8) + #define SHU3_CA_CMD2_RG_TX_ARCLK_ODTP GENMASK(20, 16) + #define SHU3_CA_CMD2_RG_TX_ARCLK_ODTN GENMASK(28, 24) +#define SHU3_CA_CMD3 0x0000170c + #define SHU3_CA_CMD3_RG_TX_ARCLK_PU GENMASK(1, 0) + #define SHU3_CA_CMD3_RG_TX_ARCLK_PU_PRE GENMASK(3, 2) + #define SHU3_CA_CMD3_RG_TX_ARCLK_PDB GENMASK(5, 4) + #define SHU3_CA_CMD3_RG_TX_ARCLK_PDB_PRE GENMASK(7, 6) + #define SHU3_CA_CMD3_RG_TX_ARCMD_PU GENMASK(9, 8) + #define SHU3_CA_CMD3_RG_TX_ARCMD_PU_PRE GENMASK(11, 10) + #define SHU3_CA_CMD3_RG_TX_ARCMD_PDB GENMASK(13, 12) + #define SHU3_CA_CMD3_RG_TX_ARCMD_PDB_PRE GENMASK(15, 14) +#define SHU3_CA_CMD4 0x00001710 + #define SHU3_CA_CMD4_RG_ARPI_AA_MCK_DL_CA GENMASK(5, 0) + #define SHU3_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA GENMASK(13, 8) + #define SHU3_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA GENMASK(21, 16) +#define SHU3_CA_CMD5 0x00001714 + #define SHU3_CA_CMD5_RG_RX_ARCMD_VREF_SEL GENMASK(5, 0) + #define SHU3_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS BIT(6) + #define SHU3_CA_CMD5_RG_ARPI_FB_CA GENMASK(13, 8) + #define SHU3_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY GENMASK(18, 16) + #define SHU3_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY BIT(19) + #define SHU3_CA_CMD5_RG_RX_ARCLK_DVS_DLY GENMASK(22, 20) + #define SHU3_CA_CMD5_RG_ARPI_MCTL_CA GENMASK(29, 24) +#define SHU3_CA_CMD6 0x00001718 + #define SHU3_CA_CMD6_RG_ARPI_OFFSET_CLKIEN GENMASK(5, 0) + #define SHU3_CA_CMD6_RG_ARPI_RESERVE_CA GENMASK(21, 6) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA GENMASK(23, 22) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA GENMASK(25, 24) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_EN_CA BIT(26) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA BIT(27) + #define SHU3_CA_CMD6_RG_ARPI_CAP_SEL_CA GENMASK(29, 28) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA BIT(31) +#define SHU3_CA_CMD7 0x0000171c + #define SHU3_CA_CMD7_R_DMRANKRXDVS_CA GENMASK(3, 0) + #define SHU3_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA BIT(12) + #define SHU3_CA_CMD7_R_DMRODTEN_CA BIT(15) + #define SHU3_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA BIT(16) + #define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW BIT(17) + #define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW BIT(18) + #define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW BIT(19) + #define SHU3_CA_CMD7_R_LP4Y_SDN_MODE_CLK BIT(20) + #define SHU3_CA_CMD7_R_DMRXRANK_CMD_EN BIT(24) + #define SHU3_CA_CMD7_R_DMRXRANK_CMD_LAT GENMASK(27, 25) + #define SHU3_CA_CMD7_R_DMRXRANK_CLK_EN BIT(28) + #define SHU3_CA_CMD7_R_DMRXRANK_CLK_LAT GENMASK(31, 29) +#define SHU3_CA_CMD8 0x00001720 + #define SHU3_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA GENMASK(14, 0) + #define SHU3_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA BIT(15) + #define SHU3_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA BIT(19) + #define SHU3_CA_CMD8_R_RMRODTEN_CG_IG_CA BIT(20) + #define SHU3_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA BIT(21) + #define SHU3_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA BIT(22) + #define SHU3_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA BIT(23) + #define SHU3_CA_CMD8_R_DMRXDLY_CG_IG_CA BIT(24) + #define SHU3_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA BIT(25) + #define SHU3_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA BIT(26) + #define SHU3_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA BIT(27) + #define SHU3_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA BIT(28) + #define SHU3_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA BIT(29) + #define SHU3_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA BIT(30) + #define SHU3_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA BIT(31) +#define SHU3_CA_CMD9 0x00001724 + #define SHU3_CA_CMD9_RESERVED_0X1724 GENMASK(31, 0) +#define SHU3_CA_CMD10 0x00001728 + #define SHU3_CA_CMD10_RESERVED_0X1728 GENMASK(31, 0) +#define SHU3_CA_CMD11 0x0000172c + #define SHU3_CA_CMD11_RG_RIMP_REV GENMASK(7, 0) + #define SHU3_CA_CMD11_RG_RIMP_VREF_SEL GENMASK(13, 8) + #define SHU3_CA_CMD11_RG_TX_ARCKE_DRVP GENMASK(21, 17) + #define SHU3_CA_CMD11_RG_TX_ARCKE_DRVN GENMASK(26, 22) +#define SHU3_CA_CMD12 0x00001730 + #define SHU3_CA_CMD12_RESERVED_0X1730 GENMASK(31, 0) +#define SHU3_CA_DLL0 0x00001734 + #define SHU3_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU BIT(0) + #define SHU3_CA_DLL0_CA_DLL0_RFU BIT(3) + #define SHU3_CA_DLL0_RG_ARDLL_FAST_PSJP_CA BIT(4) + #define SHU3_CA_DLL0_RG_ARDLL_PHDIV_CA BIT(9) + #define SHU3_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA BIT(10) + #define SHU3_CA_DLL0_RG_ARDLL_P_GAIN_CA GENMASK(15, 12) + #define SHU3_CA_DLL0_RG_ARDLL_IDLECNT_CA GENMASK(19, 16) + #define SHU3_CA_DLL0_RG_ARDLL_GAIN_CA GENMASK(23, 20) + #define SHU3_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA BIT(30) + #define SHU3_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA BIT(31) +#define SHU3_CA_DLL1 0x00001738 + #define SHU3_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA BIT(0) + #define SHU3_CA_DLL1_RG_ARDLL_PS_EN_CA BIT(1) + #define SHU3_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA BIT(2) + #define SHU3_CA_DLL1_RG_ARCMD_REV GENMASK(31, 8) +#define SHU3_MISC0 0x000017f0 + #define SHU3_MISC0_R_RX_PIPE_BYPASS_EN BIT(1) + #define SHU3_MISC0_RG_CMD_TXPIPE_BYPASS_EN BIT(2) + #define SHU3_MISC0_RG_CK_TXPIPE_BYPASS_EN BIT(3) + #define SHU3_MISC0_RG_RVREF_SEL_DQ GENMASK(21, 16) + #define SHU3_MISC0_RG_RVREF_DDR4_SEL BIT(22) + #define SHU3_MISC0_RG_RVREF_DDR3_SEL BIT(23) + #define SHU3_MISC0_RG_RVREF_SEL_CMD GENMASK(29, 24) +#define SHU3_R0_B0_DQ0 0x00001800 + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU3_R0_B0_DQ1 0x00001804 + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU3_R0_B0_DQ2 0x00001808 + #define SHU3_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R0_B0_DQ3 0x0000180c + #define SHU3_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R0_B0_DQ4 0x00001810 + #define SHU3_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R0_B0_DQ5 0x00001814 + #define SHU3_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R0_B0_DQ6 0x00001818 + #define SHU3_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU3_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU3_R0_B0_DQ7 0x0000181c + #define SHU3_R0_B0_DQ7_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ7_RK0_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1820 0x00001820 + #define RFU_0X1820_RESERVED_0X1820 GENMASK(31, 0) +#define RFU_0X1824 0x00001824 + #define RFU_0X1824_RESERVED_0X1824 GENMASK(31, 0) +#define RFU_0X1828 0x00001828 + #define RFU_0X1828_RESERVED_0X1828 GENMASK(31, 0) +#define RFU_0X182C 0x0000182c + #define RFU_0X182C_RESERVED_0X182C GENMASK(31, 0) +#define SHU3_R0_B1_DQ0 0x00001850 + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU3_R0_B1_DQ1 0x00001854 + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU3_R0_B1_DQ2 0x00001858 + #define SHU3_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R0_B1_DQ3 0x0000185c + #define SHU3_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R0_B1_DQ4 0x00001860 + #define SHU3_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R0_B1_DQ5 0x00001864 + #define SHU3_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R0_B1_DQ6 0x00001868 + #define SHU3_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU3_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU3_R0_B1_DQ7 0x0000186c + #define SHU3_R0_B1_DQ7_RK0_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ7_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1870 0x00001870 + #define RFU_0X1870_RESERVED_0X1870 GENMASK(31, 0) +#define RFU_0X1874 0x00001874 + #define RFU_0X1874_RESERVED_0X1874 GENMASK(31, 0) +#define RFU_0X1878 0x00001878 + #define RFU_0X1878_RESERVED_0X1878 GENMASK(31, 0) +#define RFU_0X187C 0x0000187c + #define RFU_0X187C_RESERVED_0X187C GENMASK(31, 0) +#define SHU3_R0_CA_CMD0 0x000018a0 + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU3_R0_CA_CMD1 0x000018a4 + #define SHU3_R0_CA_CMD1_RK0_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU3_R0_CA_CMD2 0x000018a8 + #define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD3 0x000018ac + #define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD4 0x000018b0 + #define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD5 0x000018b4 + #define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD6 0x000018b8 + #define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD7 0x000018bc + #define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD8 0x000018c0 + #define SHU3_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU3_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU3_R0_CA_CMD9 0x000018c4 + #define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CS GENMASK(5, 0) + #define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CMD GENMASK(13, 8) + #define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CLK GENMASK(29, 24) +#define RFU_0X18C8 0x000018c8 + #define RFU_0X18C8_RESERVED_0X18C8 GENMASK(31, 0) +#define RFU_0X18CC 0x000018cc + #define RFU_0X18CC_RESERVED_0X18CC GENMASK(31, 0) +#define SHU3_R1_B0_DQ0 0x00001900 + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU3_R1_B0_DQ1 0x00001904 + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU3_R1_B0_DQ2 0x00001908 + #define SHU3_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R1_B0_DQ3 0x0000190c + #define SHU3_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R1_B0_DQ4 0x00001910 + #define SHU3_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R1_B0_DQ5 0x00001914 + #define SHU3_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R1_B0_DQ6 0x00001918 + #define SHU3_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU3_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU3_R1_B0_DQ7 0x0000191c + #define SHU3_R1_B0_DQ7_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ7_RK1_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1920 0x00001920 + #define RFU_0X1920_RESERVED_0X1920 GENMASK(31, 0) +#define RFU_0X1924 0x00001924 + #define RFU_0X1924_RESERVED_0X1924 GENMASK(31, 0) +#define RFU_0X1928 0x00001928 + #define RFU_0X1928_RESERVED_0X1928 GENMASK(31, 0) +#define RFU_0X192C 0x0000192c + #define RFU_0X192C_RESERVED_0X192C GENMASK(31, 0) +#define SHU3_R1_B1_DQ0 0x00001950 + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU3_R1_B1_DQ1 0x00001954 + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU3_R1_B1_DQ2 0x00001958 + #define SHU3_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R1_B1_DQ3 0x0000195c + #define SHU3_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R1_B1_DQ4 0x00001960 + #define SHU3_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R1_B1_DQ5 0x00001964 + #define SHU3_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R1_B1_DQ6 0x00001968 + #define SHU3_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU3_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU3_R1_B1_DQ7 0x0000196c + #define SHU3_R1_B1_DQ7_RK1_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ7_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1970 0x00001970 + #define RFU_0X1970_RESERVED_0X1970 GENMASK(31, 0) +#define RFU_0X1974 0x00001974 + #define RFU_0X1974_RESERVED_0X1974 GENMASK(31, 0) +#define RFU_0X1978 0x00001978 + #define RFU_0X1978_RESERVED_0X1978 GENMASK(31, 0) +#define RFU_0X197C 0x0000197c + #define RFU_0X197C_RESERVED_0X197C GENMASK(31, 0) +#define SHU3_R1_CA_CMD0 0x000019a0 + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU3_R1_CA_CMD1 0x000019a4 + #define SHU3_R1_CA_CMD1_RK1_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU3_R1_CA_CMD2 0x000019a8 + #define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD3 0x000019ac + #define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD4 0x000019b0 + #define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD5 0x000019b4 + #define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD6 0x000019b8 + #define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD7 0x000019bc + #define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD8 0x000019c0 + #define SHU3_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU3_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU3_R1_CA_CMD9 0x000019c4 + #define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CS GENMASK(5, 0) + #define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CMD GENMASK(13, 8) + #define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CLK GENMASK(29, 24) +#define RFU_0X19C8 0x000019c8 + #define RFU_0X19C8_RESERVED_0X19C8 GENMASK(31, 0) +#define RFU_0X19CC 0x000019cc + #define RFU_0X19CC_RESERVED_0X19CC GENMASK(31, 0) +#define SHU3_R2_B0_DQ0 0x00001a00 + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU3_R2_B0_DQ1 0x00001a04 + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU3_R2_B0_DQ2 0x00001a08 + #define SHU3_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R2_B0_DQ3 0x00001a0c + #define SHU3_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R2_B0_DQ4 0x00001a10 + #define SHU3_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R2_B0_DQ5 0x00001a14 + #define SHU3_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R2_B0_DQ6 0x00001a18 + #define SHU3_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU3_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU3_R2_B0_DQ7 0x00001a1c + #define SHU3_R2_B0_DQ7_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ7_RK2_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1A20 0x00001a20 + #define RFU_0X1A20_RESERVED_0X1A20 GENMASK(31, 0) +#define RFU_0X1A24 0x00001a24 + #define RFU_0X1A24_RESERVED_0X1A24 GENMASK(31, 0) +#define RFU_0X1A28 0x00001a28 + #define RFU_0X1A28_RESERVED_0X1A28 GENMASK(31, 0) +#define RFU_0X1A2C 0x00001a2c + #define RFU_0X1A2C_RESERVED_0X1A2C GENMASK(31, 0) +#define SHU3_R2_B1_DQ0 0x00001a50 + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU3_R2_B1_DQ1 0x00001a54 + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU3_R2_B1_DQ2 0x00001a58 + #define SHU3_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R2_B1_DQ3 0x00001a5c + #define SHU3_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R2_B1_DQ4 0x00001a60 + #define SHU3_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R2_B1_DQ5 0x00001a64 + #define SHU3_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R2_B1_DQ6 0x00001a68 + #define SHU3_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU3_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU3_R2_B1_DQ7 0x00001a6c + #define SHU3_R2_B1_DQ7_RK2_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ7_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1A70 0x00001a70 + #define RFU_0X1A70_RESERVED_0X1A70 GENMASK(31, 0) +#define RFU_0X1A74 0x00001a74 + #define RFU_0X1A74_RESERVED_0X1A74 GENMASK(31, 0) +#define RFU_0X1A78 0x00001a78 + #define RFU_0X1A78_RESERVED_0X1A78 GENMASK(31, 0) +#define RFU_0X1A7C 0x00001a7c + #define RFU_0X1A7C_RESERVED_0X1A7C GENMASK(31, 0) +#define SHU3_R2_CA_CMD0 0x00001aa0 + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU3_R2_CA_CMD1 0x00001aa4 + #define SHU3_R2_CA_CMD1_RK2_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU3_R2_CA_CMD2 0x00001aa8 + #define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD3 0x00001aac + #define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD4 0x00001ab0 + #define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD5 0x00001ab4 + #define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD6 0x00001ab8 + #define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD7 0x00001abc + #define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD8 0x00001ac0 + #define SHU3_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU3_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU3_R2_CA_CMD9 0x00001ac4 + #define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CS GENMASK(5, 0) + #define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CMD GENMASK(13, 8) + #define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CLK GENMASK(29, 24) +#define RFU_0X1AC8 0x00001ac8 + #define RFU_0X1AC8_RESERVED_0X1AC8 GENMASK(31, 0) +#define RFU_0X1ACC 0x00001acc + #define RFU_0X1ACC_RESERVED_0X1ACC GENMASK(31, 0) +#define SHU4_B0_DQ0 0x00001b00 + #define SHU4_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 BIT(4) + #define SHU4_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 GENMASK(10, 8) + #define SHU4_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 GENMASK(14, 12) + #define SHU4_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 BIT(20) + #define SHU4_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 GENMASK(26, 24) + #define SHU4_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 GENMASK(30, 28) + #define SHU4_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 BIT(31) +#define SHU4_B0_DQ1 0x00001b04 + #define SHU4_B0_DQ1_RG_TX_ARDQ_DRVP_B0 GENMASK(4, 0) + #define SHU4_B0_DQ1_RG_TX_ARDQ_DRVN_B0 GENMASK(12, 8) + #define SHU4_B0_DQ1_RG_TX_ARDQ_ODTP_B0 GENMASK(20, 16) + #define SHU4_B0_DQ1_RG_TX_ARDQ_ODTN_B0 GENMASK(28, 24) +#define SHU4_B0_DQ2 0x00001b08 + #define SHU4_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 GENMASK(4, 0) + #define SHU4_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 GENMASK(12, 8) + #define SHU4_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 GENMASK(20, 16) + #define SHU4_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 GENMASK(28, 24) +#define SHU4_B0_DQ3 0x00001b0c + #define SHU4_B0_DQ3_RG_TX_ARDQS0_PU_B0 GENMASK(1, 0) + #define SHU4_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 GENMASK(3, 2) + #define SHU4_B0_DQ3_RG_TX_ARDQS0_PDB_B0 GENMASK(5, 4) + #define SHU4_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 GENMASK(7, 6) + #define SHU4_B0_DQ3_RG_TX_ARDQ_PU_B0 GENMASK(9, 8) + #define SHU4_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 GENMASK(11, 10) + #define SHU4_B0_DQ3_RG_TX_ARDQ_PDB_B0 GENMASK(13, 12) + #define SHU4_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 GENMASK(15, 14) +#define SHU4_B0_DQ4 0x00001b10 + #define SHU4_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 GENMASK(5, 0) + #define SHU4_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 GENMASK(13, 8) + #define SHU4_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 GENMASK(21, 16) +#define SHU4_B0_DQ5 0x00001b14 + #define SHU4_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 GENMASK(5, 0) + #define SHU4_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 BIT(6) + #define SHU4_B0_DQ5_RG_ARPI_FB_B0 GENMASK(13, 8) + #define SHU4_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 GENMASK(18, 16) + #define SHU4_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0 BIT(19) + #define SHU4_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 GENMASK(22, 20) + #define SHU4_B0_DQ5_RG_ARPI_MCTL_B0 GENMASK(29, 24) +#define SHU4_B0_DQ6 0x00001b18 + #define SHU4_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 GENMASK(5, 0) + #define SHU4_B0_DQ6_RG_ARPI_RESERVE_B0 GENMASK(21, 6) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 GENMASK(23, 22) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 GENMASK(25, 24) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_EN_B0 BIT(26) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 BIT(27) + #define SHU4_B0_DQ6_RG_ARPI_CAP_SEL_B0 GENMASK(29, 28) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0 BIT(31) +#define SHU4_B0_DQ7 0x00001b1c + #define SHU4_B0_DQ7_R_DMRANKRXDVS_B0 GENMASK(3, 0) + #define SHU4_B0_DQ7_MIDPI_ENABLE BIT(4) + #define SHU4_B0_DQ7_MIDPI_DIV4_ENABLE BIT(5) + #define SHU4_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 BIT(6) + #define SHU4_B0_DQ7_R_DMDQMDBI_SHU_B0 BIT(7) + #define SHU4_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 GENMASK(11, 8) + #define SHU4_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 BIT(12) + #define SHU4_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 BIT(13) + #define SHU4_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 BIT(14) + #define SHU4_B0_DQ7_R_DMRODTEN_B0 BIT(15) + #define SHU4_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 BIT(16) + #define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 BIT(17) + #define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 BIT(18) + #define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 BIT(19) + #define SHU4_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 BIT(20) + #define SHU4_B0_DQ7_R_DMRXRANK_DQ_EN_B0 BIT(24) + #define SHU4_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 GENMASK(27, 25) + #define SHU4_B0_DQ7_R_DMRXRANK_DQS_EN_B0 BIT(28) + #define SHU4_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 GENMASK(31, 29) +#define SHU4_B0_DQ8 0x00001b20 + #define SHU4_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 GENMASK(14, 0) + #define SHU4_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 BIT(15) + #define SHU4_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 BIT(19) + #define SHU4_B0_DQ8_R_RMRODTEN_CG_IG_B0 BIT(20) + #define SHU4_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 BIT(21) + #define SHU4_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 BIT(22) + #define SHU4_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 BIT(23) + #define SHU4_B0_DQ8_R_DMRXDLY_CG_IG_B0 BIT(24) + #define SHU4_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0 BIT(25) + #define SHU4_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 BIT(26) + #define SHU4_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 BIT(27) + #define SHU4_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 BIT(28) + #define SHU4_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 BIT(29) + #define SHU4_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 BIT(30) + #define SHU4_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 BIT(31) +#define SHU4_B0_DQ9 0x00001b24 + #define SHU4_B0_DQ9_RESERVED_0X1B24 GENMASK(31, 0) +#define SHU4_B0_DQ10 0x00001b28 + #define SHU4_B0_DQ10_RESERVED_0X1B28 GENMASK(31, 0) +#define SHU4_B0_DQ11 0x00001b2c + #define SHU4_B0_DQ11_RESERVED_0X1B2C GENMASK(31, 0) +#define SHU4_B0_DQ12 0x00001b30 + #define SHU4_B0_DQ12_RESERVED_0X1B30 GENMASK(31, 0) +#define SHU4_B0_DLL0 0x00001b34 + #define SHU4_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU BIT(0) + #define SHU4_B0_DLL0_B0_DLL0_RFU BIT(3) + #define SHU4_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 BIT(4) + #define SHU4_B0_DLL0_RG_ARDLL_PHDIV_B0 BIT(9) + #define SHU4_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0 BIT(10) + #define SHU4_B0_DLL0_RG_ARDLL_P_GAIN_B0 GENMASK(15, 12) + #define SHU4_B0_DLL0_RG_ARDLL_IDLECNT_B0 GENMASK(19, 16) + #define SHU4_B0_DLL0_RG_ARDLL_GAIN_B0 GENMASK(23, 20) + #define SHU4_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0 BIT(30) + #define SHU4_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0 BIT(31) +#define SHU4_B0_DLL1 0x00001b38 + #define SHU4_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0 BIT(0) + #define SHU4_B0_DLL1_RG_ARDLL_PS_EN_B0 BIT(1) + #define SHU4_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 BIT(2) + #define SHU4_B0_DLL1_RG_ARDQ_REV_B0 GENMASK(31, 8) +#define SHU4_B1_DQ0 0x00001b80 + #define SHU4_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 BIT(4) + #define SHU4_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 GENMASK(10, 8) + #define SHU4_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 GENMASK(14, 12) + #define SHU4_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 BIT(20) + #define SHU4_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 GENMASK(26, 24) + #define SHU4_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 GENMASK(30, 28) + #define SHU4_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 BIT(31) +#define SHU4_B1_DQ1 0x00001b84 + #define SHU4_B1_DQ1_RG_TX_ARDQ_DRVP_B1 GENMASK(4, 0) + #define SHU4_B1_DQ1_RG_TX_ARDQ_DRVN_B1 GENMASK(12, 8) + #define SHU4_B1_DQ1_RG_TX_ARDQ_ODTP_B1 GENMASK(20, 16) + #define SHU4_B1_DQ1_RG_TX_ARDQ_ODTN_B1 GENMASK(28, 24) +#define SHU4_B1_DQ2 0x00001b88 + #define SHU4_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 GENMASK(4, 0) + #define SHU4_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 GENMASK(12, 8) + #define SHU4_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 GENMASK(20, 16) + #define SHU4_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 GENMASK(28, 24) +#define SHU4_B1_DQ3 0x00001b8c + #define SHU4_B1_DQ3_RG_TX_ARDQS0_PU_B1 GENMASK(1, 0) + #define SHU4_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 GENMASK(3, 2) + #define SHU4_B1_DQ3_RG_TX_ARDQS0_PDB_B1 GENMASK(5, 4) + #define SHU4_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 GENMASK(7, 6) + #define SHU4_B1_DQ3_RG_TX_ARDQ_PU_B1 GENMASK(9, 8) + #define SHU4_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 GENMASK(11, 10) + #define SHU4_B1_DQ3_RG_TX_ARDQ_PDB_B1 GENMASK(13, 12) + #define SHU4_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 GENMASK(15, 14) +#define SHU4_B1_DQ4 0x00001b90 + #define SHU4_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 GENMASK(5, 0) + #define SHU4_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 GENMASK(13, 8) + #define SHU4_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 GENMASK(21, 16) +#define SHU4_B1_DQ5 0x00001b94 + #define SHU4_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 GENMASK(5, 0) + #define SHU4_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 BIT(6) + #define SHU4_B1_DQ5_RG_ARPI_FB_B1 GENMASK(13, 8) + #define SHU4_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 GENMASK(18, 16) + #define SHU4_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1 BIT(19) + #define SHU4_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 GENMASK(22, 20) + #define SHU4_B1_DQ5_RG_ARPI_MCTL_B1 GENMASK(29, 24) +#define SHU4_B1_DQ6 0x00001b98 + #define SHU4_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 GENMASK(5, 0) + #define SHU4_B1_DQ6_RG_ARPI_RESERVE_B1 GENMASK(21, 6) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 GENMASK(23, 22) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 GENMASK(25, 24) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_EN_B1 BIT(26) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 BIT(27) + #define SHU4_B1_DQ6_RG_ARPI_CAP_SEL_B1 GENMASK(29, 28) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1 BIT(31) +#define SHU4_B1_DQ7 0x00001b9c + #define SHU4_B1_DQ7_R_DMRANKRXDVS_B1 GENMASK(3, 0) + #define SHU4_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 BIT(6) + #define SHU4_B1_DQ7_R_DMDQMDBI_SHU_B1 BIT(7) + #define SHU4_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 GENMASK(11, 8) + #define SHU4_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 BIT(12) + #define SHU4_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 BIT(13) + #define SHU4_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 BIT(14) + #define SHU4_B1_DQ7_R_DMRODTEN_B1 BIT(15) + #define SHU4_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 BIT(16) + #define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 BIT(17) + #define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 BIT(18) + #define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 BIT(19) + #define SHU4_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 BIT(20) + #define SHU4_B1_DQ7_R_DMRXRANK_DQ_EN_B1 BIT(24) + #define SHU4_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 GENMASK(27, 25) + #define SHU4_B1_DQ7_R_DMRXRANK_DQS_EN_B1 BIT(28) + #define SHU4_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 GENMASK(31, 29) +#define SHU4_B1_DQ8 0x00001ba0 + #define SHU4_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 GENMASK(14, 0) + #define SHU4_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 BIT(15) + #define SHU4_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 BIT(19) + #define SHU4_B1_DQ8_R_RMRODTEN_CG_IG_B1 BIT(20) + #define SHU4_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 BIT(21) + #define SHU4_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 BIT(22) + #define SHU4_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 BIT(23) + #define SHU4_B1_DQ8_R_DMRXDLY_CG_IG_B1 BIT(24) + #define SHU4_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1 BIT(25) + #define SHU4_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 BIT(26) + #define SHU4_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 BIT(27) + #define SHU4_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 BIT(28) + #define SHU4_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 BIT(29) + #define SHU4_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 BIT(30) + #define SHU4_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 BIT(31) +#define SHU4_B1_DQ9 0x00001ba4 + #define SHU4_B1_DQ9_RESERVED_0X1BA4 GENMASK(31, 0) +#define SHU4_B1_DQ10 0x00001ba8 + #define SHU4_B1_DQ10_RESERVED_0X1BA8 GENMASK(31, 0) +#define SHU4_B1_DQ11 0x00001bac + #define SHU4_B1_DQ11_RESERVED_0X1BAC GENMASK(31, 0) +#define SHU4_B1_DQ12 0x00001bb0 + #define SHU4_B1_DQ12_RESERVED_0X1BB0 GENMASK(31, 0) +#define SHU4_B1_DLL0 0x00001bb4 + #define SHU4_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU BIT(0) + #define SHU4_B1_DLL0_B1_DLL0_RFU BIT(3) + #define SHU4_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 BIT(4) + #define SHU4_B1_DLL0_RG_ARDLL_PHDIV_B1 BIT(9) + #define SHU4_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1 BIT(10) + #define SHU4_B1_DLL0_RG_ARDLL_P_GAIN_B1 GENMASK(15, 12) + #define SHU4_B1_DLL0_RG_ARDLL_IDLECNT_B1 GENMASK(19, 16) + #define SHU4_B1_DLL0_RG_ARDLL_GAIN_B1 GENMASK(23, 20) + #define SHU4_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1 BIT(30) + #define SHU4_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1 BIT(31) +#define SHU4_B1_DLL1 0x00001bb8 + #define SHU4_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1 BIT(0) + #define SHU4_B1_DLL1_RG_ARDLL_PS_EN_B1 BIT(1) + #define SHU4_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 BIT(2) + #define SHU4_B1_DLL1_RG_ARDQ_REV_B1 GENMASK(31, 8) +#define SHU4_CA_CMD0 0x00001c00 + #define SHU4_CA_CMD0_RG_TX_ARCLK_PRE_EN BIT(4) + #define SHU4_CA_CMD0_RG_TX_ARCLK_DRVP_PRE GENMASK(10, 8) + #define SHU4_CA_CMD0_RG_TX_ARCLK_DRVN_PRE GENMASK(14, 12) + #define SHU4_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL BIT(17) + #define SHU4_CA_CMD0_RG_FB_CK_MUX GENMASK(19, 18) + #define SHU4_CA_CMD0_RG_TX_ARCMD_PRE_EN BIT(20) + #define SHU4_CA_CMD0_RG_TX_ARCMD_DRVP_PRE GENMASK(26, 24) + #define SHU4_CA_CMD0_RG_TX_ARCMD_DRVN_PRE GENMASK(30, 28) + #define SHU4_CA_CMD0_R_LP4Y_WDN_MODE_CLK BIT(31) +#define SHU4_CA_CMD1 0x00001c04 + #define SHU4_CA_CMD1_RG_TX_ARCMD_DRVP GENMASK(4, 0) + #define SHU4_CA_CMD1_RG_TX_ARCMD_DRVN GENMASK(12, 8) + #define SHU4_CA_CMD1_RG_TX_ARCMD_ODTP GENMASK(20, 16) + #define SHU4_CA_CMD1_RG_TX_ARCMD_ODTN GENMASK(28, 24) +#define SHU4_CA_CMD2 0x00001c08 + #define SHU4_CA_CMD2_RG_TX_ARCLK_DRVP GENMASK(4, 0) + #define SHU4_CA_CMD2_RG_TX_ARCLK_DRVN GENMASK(12, 8) + #define SHU4_CA_CMD2_RG_TX_ARCLK_ODTP GENMASK(20, 16) + #define SHU4_CA_CMD2_RG_TX_ARCLK_ODTN GENMASK(28, 24) +#define SHU4_CA_CMD3 0x00001c0c + #define SHU4_CA_CMD3_RG_TX_ARCLK_PU GENMASK(1, 0) + #define SHU4_CA_CMD3_RG_TX_ARCLK_PU_PRE GENMASK(3, 2) + #define SHU4_CA_CMD3_RG_TX_ARCLK_PDB GENMASK(5, 4) + #define SHU4_CA_CMD3_RG_TX_ARCLK_PDB_PRE GENMASK(7, 6) + #define SHU4_CA_CMD3_RG_TX_ARCMD_PU GENMASK(9, 8) + #define SHU4_CA_CMD3_RG_TX_ARCMD_PU_PRE GENMASK(11, 10) + #define SHU4_CA_CMD3_RG_TX_ARCMD_PDB GENMASK(13, 12) + #define SHU4_CA_CMD3_RG_TX_ARCMD_PDB_PRE GENMASK(15, 14) +#define SHU4_CA_CMD4 0x00001c10 + #define SHU4_CA_CMD4_RG_ARPI_AA_MCK_DL_CA GENMASK(5, 0) + #define SHU4_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA GENMASK(13, 8) + #define SHU4_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA GENMASK(21, 16) +#define SHU4_CA_CMD5 0x00001c14 + #define SHU4_CA_CMD5_RG_RX_ARCMD_VREF_SEL GENMASK(5, 0) + #define SHU4_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS BIT(6) + #define SHU4_CA_CMD5_RG_ARPI_FB_CA GENMASK(13, 8) + #define SHU4_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY GENMASK(18, 16) + #define SHU4_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY BIT(19) + #define SHU4_CA_CMD5_RG_RX_ARCLK_DVS_DLY GENMASK(22, 20) + #define SHU4_CA_CMD5_RG_ARPI_MCTL_CA GENMASK(29, 24) +#define SHU4_CA_CMD6 0x00001c18 + #define SHU4_CA_CMD6_RG_ARPI_OFFSET_CLKIEN GENMASK(5, 0) + #define SHU4_CA_CMD6_RG_ARPI_RESERVE_CA GENMASK(21, 6) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA GENMASK(23, 22) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA GENMASK(25, 24) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_EN_CA BIT(26) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA BIT(27) + #define SHU4_CA_CMD6_RG_ARPI_CAP_SEL_CA GENMASK(29, 28) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA BIT(31) +#define SHU4_CA_CMD7 0x00001c1c + #define SHU4_CA_CMD7_R_DMRANKRXDVS_CA GENMASK(3, 0) + #define SHU4_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA BIT(12) + #define SHU4_CA_CMD7_R_DMRODTEN_CA BIT(15) + #define SHU4_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA BIT(16) + #define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW BIT(17) + #define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW BIT(18) + #define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW BIT(19) + #define SHU4_CA_CMD7_R_LP4Y_SDN_MODE_CLK BIT(20) + #define SHU4_CA_CMD7_R_DMRXRANK_CMD_EN BIT(24) + #define SHU4_CA_CMD7_R_DMRXRANK_CMD_LAT GENMASK(27, 25) + #define SHU4_CA_CMD7_R_DMRXRANK_CLK_EN BIT(28) + #define SHU4_CA_CMD7_R_DMRXRANK_CLK_LAT GENMASK(31, 29) +#define SHU4_CA_CMD8 0x00001c20 + #define SHU4_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA GENMASK(14, 0) + #define SHU4_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA BIT(15) + #define SHU4_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA BIT(19) + #define SHU4_CA_CMD8_R_RMRODTEN_CG_IG_CA BIT(20) + #define SHU4_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA BIT(21) + #define SHU4_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA BIT(22) + #define SHU4_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA BIT(23) + #define SHU4_CA_CMD8_R_DMRXDLY_CG_IG_CA BIT(24) + #define SHU4_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA BIT(25) + #define SHU4_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA BIT(26) + #define SHU4_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA BIT(27) + #define SHU4_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA BIT(28) + #define SHU4_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA BIT(29) + #define SHU4_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA BIT(30) + #define SHU4_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA BIT(31) +#define SHU4_CA_CMD9 0x00001c24 + #define SHU4_CA_CMD9_RESERVED_0X1C24 GENMASK(31, 0) +#define SHU4_CA_CMD10 0x00001c28 + #define SHU4_CA_CMD10_RESERVED_0X1C28 GENMASK(31, 0) +#define SHU4_CA_CMD11 0x00001c2c + #define SHU4_CA_CMD11_RG_RIMP_REV GENMASK(7, 0) + #define SHU4_CA_CMD11_RG_RIMP_VREF_SEL GENMASK(13, 8) + #define SHU4_CA_CMD11_RG_TX_ARCKE_DRVP GENMASK(21, 17) + #define SHU4_CA_CMD11_RG_TX_ARCKE_DRVN GENMASK(26, 22) +#define SHU4_CA_CMD12 0x00001c30 + #define SHU4_CA_CMD12_RESERVED_0X1C30 GENMASK(31, 0) +#define SHU4_CA_DLL0 0x00001c34 + #define SHU4_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU BIT(0) + #define SHU4_CA_DLL0_CA_DLL0_RFU BIT(3) + #define SHU4_CA_DLL0_RG_ARDLL_FAST_PSJP_CA BIT(4) + #define SHU4_CA_DLL0_RG_ARDLL_PHDIV_CA BIT(9) + #define SHU4_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA BIT(10) + #define SHU4_CA_DLL0_RG_ARDLL_P_GAIN_CA GENMASK(15, 12) + #define SHU4_CA_DLL0_RG_ARDLL_IDLECNT_CA GENMASK(19, 16) + #define SHU4_CA_DLL0_RG_ARDLL_GAIN_CA GENMASK(23, 20) + #define SHU4_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA BIT(30) + #define SHU4_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA BIT(31) +#define SHU4_CA_DLL1 0x00001c38 + #define SHU4_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA BIT(0) + #define SHU4_CA_DLL1_RG_ARDLL_PS_EN_CA BIT(1) + #define SHU4_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA BIT(2) + #define SHU4_CA_DLL1_RG_ARCMD_REV GENMASK(31, 8) +#define SHU4_MISC0 0x00001cf0 + #define SHU4_MISC0_R_RX_PIPE_BYPASS_EN BIT(1) + #define SHU4_MISC0_RG_CMD_TXPIPE_BYPASS_EN BIT(2) + #define SHU4_MISC0_RG_CK_TXPIPE_BYPASS_EN BIT(3) + #define SHU4_MISC0_RG_RVREF_SEL_DQ GENMASK(21, 16) + #define SHU4_MISC0_RG_RVREF_DDR4_SEL BIT(22) + #define SHU4_MISC0_RG_RVREF_DDR3_SEL BIT(23) + #define SHU4_MISC0_RG_RVREF_SEL_CMD GENMASK(29, 24) +#define SHU4_R0_B0_DQ0 0x00001d00 + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU4_R0_B0_DQ1 0x00001d04 + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU4_R0_B0_DQ2 0x00001d08 + #define SHU4_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R0_B0_DQ3 0x00001d0c + #define SHU4_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R0_B0_DQ4 0x00001d10 + #define SHU4_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R0_B0_DQ5 0x00001d14 + #define SHU4_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R0_B0_DQ6 0x00001d18 + #define SHU4_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU4_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU4_R0_B0_DQ7 0x00001d1c + #define SHU4_R0_B0_DQ7_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ7_RK0_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1D20 0x00001d20 + #define RFU_0X1D20_RESERVED_0X1D20 GENMASK(31, 0) +#define RFU_0X1D24 0x00001d24 + #define RFU_0X1D24_RESERVED_0X1D24 GENMASK(31, 0) +#define RFU_0X1D28 0x00001d28 + #define RFU_0X1D28_RESERVED_0X1D28 GENMASK(31, 0) +#define RFU_0X1D2C 0x00001d2c + #define RFU_0X1D2C_RESERVED_0X1D2C GENMASK(31, 0) +#define SHU4_R0_B1_DQ0 0x00001d50 + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU4_R0_B1_DQ1 0x00001d54 + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU4_R0_B1_DQ2 0x00001d58 + #define SHU4_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R0_B1_DQ3 0x00001d5c + #define SHU4_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R0_B1_DQ4 0x00001d60 + #define SHU4_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R0_B1_DQ5 0x00001d64 + #define SHU4_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R0_B1_DQ6 0x00001d68 + #define SHU4_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU4_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU4_R0_B1_DQ7 0x00001d6c + #define SHU4_R0_B1_DQ7_RK0_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ7_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1D70 0x00001d70 + #define RFU_0X1D70_RESERVED_0X1D70 GENMASK(31, 0) +#define RFU_0X1D74 0x00001d74 + #define RFU_0X1D74_RESERVED_0X1D74 GENMASK(31, 0) +#define RFU_0X1D78 0x00001d78 + #define RFU_0X1D78_RESERVED_0X1D78 GENMASK(31, 0) +#define RFU_0X1D7C 0x00001d7c + #define RFU_0X1D7C_RESERVED_0X1D7C GENMASK(31, 0) +#define SHU4_R0_CA_CMD0 0x00001da0 + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU4_R0_CA_CMD1 0x00001da4 + #define SHU4_R0_CA_CMD1_RK0_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU4_R0_CA_CMD2 0x00001da8 + #define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD3 0x00001dac + #define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD4 0x00001db0 + #define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD5 0x00001db4 + #define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD6 0x00001db8 + #define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD7 0x00001dbc + #define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD8 0x00001dc0 + #define SHU4_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU4_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU4_R0_CA_CMD9 0x00001dc4 + #define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CS GENMASK(5, 0) + #define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CMD GENMASK(13, 8) + #define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CLK GENMASK(29, 24) +#define RFU_0X1DC8 0x00001dc8 + #define RFU_0X1DC8_RESERVED_0X1DC8 GENMASK(31, 0) +#define RFU_0X1DCC 0x00001dcc + #define RFU_0X1DCC_RESERVED_0X1DCC GENMASK(31, 0) +#define SHU4_R1_B0_DQ0 0x00001e00 + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU4_R1_B0_DQ1 0x00001e04 + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU4_R1_B0_DQ2 0x00001e08 + #define SHU4_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R1_B0_DQ3 0x00001e0c + #define SHU4_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R1_B0_DQ4 0x00001e10 + #define SHU4_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R1_B0_DQ5 0x00001e14 + #define SHU4_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R1_B0_DQ6 0x00001e18 + #define SHU4_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU4_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU4_R1_B0_DQ7 0x00001e1c + #define SHU4_R1_B0_DQ7_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ7_RK1_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1E20 0x00001e20 + #define RFU_0X1E20_RESERVED_0X1E20 GENMASK(31, 0) +#define RFU_0X1E24 0x00001e24 + #define RFU_0X1E24_RESERVED_0X1E24 GENMASK(31, 0) +#define RFU_0X1E28 0x00001e28 + #define RFU_0X1E28_RESERVED_0X1E28 GENMASK(31, 0) +#define RFU_0X1E2C 0x00001e2c + #define RFU_0X1E2C_RESERVED_0X1E2C GENMASK(31, 0) +#define SHU4_R1_B1_DQ0 0x00001e50 + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU4_R1_B1_DQ1 0x00001e54 + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU4_R1_B1_DQ2 0x00001e58 + #define SHU4_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R1_B1_DQ3 0x00001e5c + #define SHU4_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R1_B1_DQ4 0x00001e60 + #define SHU4_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R1_B1_DQ5 0x00001e64 + #define SHU4_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R1_B1_DQ6 0x00001e68 + #define SHU4_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU4_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU4_R1_B1_DQ7 0x00001e6c + #define SHU4_R1_B1_DQ7_RK1_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ7_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1E70 0x00001e70 + #define RFU_0X1E70_RESERVED_0X1E70 GENMASK(31, 0) +#define RFU_0X1E74 0x00001e74 + #define RFU_0X1E74_RESERVED_0X1E74 GENMASK(31, 0) +#define RFU_0X1E78 0x00001e78 + #define RFU_0X1E78_RESERVED_0X1E78 GENMASK(31, 0) +#define RFU_0X1E7C 0x00001e7c + #define RFU_0X1E7C_RESERVED_0X1E7C GENMASK(31, 0) +#define SHU4_R1_CA_CMD0 0x00001ea0 + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU4_R1_CA_CMD1 0x00001ea4 + #define SHU4_R1_CA_CMD1_RK1_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU4_R1_CA_CMD2 0x00001ea8 + #define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD3 0x00001eac + #define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD4 0x00001eb0 + #define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD5 0x00001eb4 + #define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD6 0x00001eb8 + #define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD7 0x00001ebc + #define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD8 0x00001ec0 + #define SHU4_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU4_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU4_R1_CA_CMD9 0x00001ec4 + #define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CS GENMASK(5, 0) + #define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CMD GENMASK(13, 8) + #define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CLK GENMASK(29, 24) +#define RFU_0X1EC8 0x00001ec8 + #define RFU_0X1EC8_RESERVED_0X1EC8 GENMASK(31, 0) +#define RFU_0X1ECC 0x00001ecc + #define RFU_0X1ECC_RESERVED_0X1ECC GENMASK(31, 0) +#define SHU4_R2_B0_DQ0 0x00001f00 + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU4_R2_B0_DQ1 0x00001f04 + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU4_R2_B0_DQ2 0x00001f08 + #define SHU4_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R2_B0_DQ3 0x00001f0c + #define SHU4_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R2_B0_DQ4 0x00001f10 + #define SHU4_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R2_B0_DQ5 0x00001f14 + #define SHU4_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R2_B0_DQ6 0x00001f18 + #define SHU4_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU4_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU4_R2_B0_DQ7 0x00001f1c + #define SHU4_R2_B0_DQ7_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ7_RK2_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1F20 0x00001f20 + #define RFU_0X1F20_RESERVED_0X1F20 GENMASK(31, 0) +#define RFU_0X1F24 0x00001f24 + #define RFU_0X1F24_RESERVED_0X1F24 GENMASK(31, 0) +#define RFU_0X1F28 0x00001f28 + #define RFU_0X1F28_RESERVED_0X1F28 GENMASK(31, 0) +#define RFU_0X1F2C 0x00001f2c + #define RFU_0X1F2C_RESERVED_0X1F2C GENMASK(31, 0) +#define SHU4_R2_B1_DQ0 0x00001f50 + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU4_R2_B1_DQ1 0x00001f54 + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU4_R2_B1_DQ2 0x00001f58 + #define SHU4_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R2_B1_DQ3 0x00001f5c + #define SHU4_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R2_B1_DQ4 0x00001f60 + #define SHU4_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R2_B1_DQ5 0x00001f64 + #define SHU4_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R2_B1_DQ6 0x00001f68 + #define SHU4_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU4_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU4_R2_B1_DQ7 0x00001f6c + #define SHU4_R2_B1_DQ7_RK2_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ7_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1F70 0x00001f70 + #define RFU_0X1F70_RESERVED_0X1F70 GENMASK(31, 0) +#define RFU_0X1F74 0x00001f74 + #define RFU_0X1F74_RESERVED_0X1F74 GENMASK(31, 0) +#define RFU_0X1F78 0x00001f78 + #define RFU_0X1F78_RESERVED_0X1F78 GENMASK(31, 0) +#define RFU_0X1F7C 0x00001f7c + #define RFU_0X1F7C_RESERVED_0X1F7C GENMASK(31, 0) +#define SHU4_R2_CA_CMD0 0x00001fa0 + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU4_R2_CA_CMD1 0x00001fa4 + #define SHU4_R2_CA_CMD1_RK2_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU4_R2_CA_CMD2 0x00001fa8 + #define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD3 0x00001fac + #define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD4 0x00001fb0 + #define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD5 0x00001fb4 + #define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD6 0x00001fb8 + #define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD7 0x00001fbc + #define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD8 0x00001fc0 + #define SHU4_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU4_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU4_R2_CA_CMD9 0x00001fc4 + #define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CS GENMASK(5, 0) + #define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CMD GENMASK(13, 8) + #define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CLK GENMASK(29, 24) +#define RFU_0X1FC8 0x00001fc8 + #define RFU_0X1FC8_RESERVED_0X1FC8 GENMASK(31, 0) +#define RFU_0X1FCC 0x00001fcc + #define RFU_0X1FCC_RESERVED_0X1FCC GENMASK(31, 0) + +#endif /*__DDRPHY_WO_PLL_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_actiming.h b/src/vendorcode/mediatek/mt8192/include/dramc_actiming.h new file mode 100644 index 0000000000..43d95d13ef --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_actiming.h @@ -0,0 +1,400 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _ACTIMING_H +#define _ACTIMING_H + +/***********************************************************************/ +/* Includes */ +/***********************************************************************/ +#include "dramc_register.h" + + +//Definitions to enable specific freq's LP4 ACTiming support (To save code size) +#define SUPPORT_LP5_DDR6400_ACTIM 0 +#define SUPPORT_LP5_DDR5500_ACTIM 0 +#define SUPPORT_LP5_DDR4266_ACTIM 0 +#define SUPPORT_LP5_DDR3200_ACTIM 0 +#define SUPPORT_LP4_DDR4266_ACTIM 1 +#define SUPPORT_LP4_DDR3733_ACTIM 1 +#define SUPPORT_LP4_DDR3200_ACTIM 1 +#define SUPPORT_LP4_DDR2667_ACTIM 0 +#define SUPPORT_LP4_DDR2400_ACTIM 1 +#define SUPPORT_LP4_DDR1866_ACTIM 1 +#define SUPPORT_LP4_DDR1600_ACTIM 1 +#define SUPPORT_LP4_DDR1333_ACTIM 0 +#define SUPPORT_LP4_DDR1200_ACTIM 1 +#define SUPPORT_LP4_DDR800_ACTIM 1 +#define SUPPORT_LP4_DDR400_ACTIM 0 + +/* Used to keep track the total number of LP4 ACTimings */ +/* Since READ_DBI is enable/disabled using preprocessor C define + * -> Save code size by excluding unneeded ACTimingTable entries + * Note 1: READ_DBI on/off is for (LP4 data rate >= DDR2667 (FSP1)) + * Must make sure DDR3733 is the 1st entry (DMCATRAIN_INTV is used) + */ +typedef enum +{ +#if SUPPORT_LP4_DDR4266_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP4_BYTE_DDR4266_RDBI_ON = 0, + AC_TIME_LP4_NORM_DDR4266_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP4_BYTE_DDR4266_RDBI_OFF, + AC_TIME_LP4_NORM_DDR4266_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP4_DDR3733_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP4_BYTE_DDR3733_RDBI_ON, + AC_TIME_LP4_NORM_DDR3733_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP4_BYTE_DDR3733_RDBI_OFF, + AC_TIME_LP4_NORM_DDR3733_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP4_DDR3200_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP4_BYTE_DDR3200_RDBI_ON, + AC_TIME_LP4_NORM_DDR3200_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP4_BYTE_DDR3200_RDBI_OFF, + AC_TIME_LP4_NORM_DDR3200_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP4_DDR2667_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP4_BYTE_DDR2667_RDBI_ON, + AC_TIME_LP4_NORM_DDR2667_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP4_BYTE_DDR2667_RDBI_OFF, + AC_TIME_LP4_NORM_DDR2667_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP4_DDR2400_ACTIM + AC_TIME_LP4_BYTE_DDR2400_RDBI_OFF, + AC_TIME_LP4_NORM_DDR2400_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR1866_ACTIM + AC_TIME_LP4_BYTE_DDR1866_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1866_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR1600_ACTIM + AC_TIME_LP4_BYTE_DDR1600_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1600_RDBI_OFF, + AC_TIME_LP4_BYTE_DDR1600_DIV4_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1600_DIV4_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR1333_ACTIM + AC_TIME_LP4_BYTE_DDR1333_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1333_RDBI_OFF, +#endif + + +#if SUPPORT_LP4_DDR1200_ACTIM + AC_TIME_LP4_BYTE_DDR1200_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1200_RDBI_OFF, + AC_TIME_LP4_BYTE_DDR1200_DIV4_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1200_DIV4_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR800_ACTIM + AC_TIME_LP4_BYTE_DDR800_RDBI_OFF, + AC_TIME_LP4_NORM_DDR800_RDBI_OFF, + AC_TIME_LP4_BYTE_DDR800_DIV4_RDBI_OFF, + AC_TIME_LP4_NORM_DDR800_DIV4_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR400_ACTIM + AC_TIME_LP4_BYTE_DDR400_RDBI_OFF, + AC_TIME_LP4_NORM_DDR400_RDBI_OFF, +#endif + + AC_TIMING_NUMBER_LP4 +} AC_TIMING_LP4_COUNT_TYPE_T; + +#if (__LP5_COMBO__) +/* Used to keep track the total number of LP5 ACTimings */ +typedef enum +{ +#if SUPPORT_LP5_DDR6400_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP5_BYTE_DDR6400_RDBI_ON = 0, + AC_TIME_LP5_NORM_DDR6400_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP5_BYTE_DDR6400_RDBI_OFF, + AC_TIME_LP5_NORM_DDR6400_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP5_DDR5500_ACTIM +#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND)) + AC_TIME_LP5_BYTE_DDR5500_RDBI_ON, + AC_TIME_LP5_NORM_DDR5500_RDBI_ON, +#else + AC_TIME_LP5_BYTE_DDR5500_RDBI_OFF, + AC_TIME_LP5_NORM_DDR5500_RDBI_OFF, +#endif +#endif + +#if SUPPORT_LP5_DDR4266_ACTIM +#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND)) + AC_TIME_LP5_BYTE_DDR4266_RDBI_ON, + AC_TIME_LP5_NORM_DDR4266_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP5_BYTE_DDR4266_RDBI_OFF, + AC_TIME_LP5_NORM_DDR4266_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP5_DDR3200_ACTIM + AC_TIME_LP5_BYTE_DDR3200_RDBI_OFF, + AC_TIME_LP5_NORM_DDR3200_RDBI_OFF, +#endif + AC_TIMING_NUMBER_LP5 +} AC_TIMING_LP5_COUNT_TYPE_T; +#else +#define AC_TIMING_NUMBER_LP5 0 +#endif + +/* ACTiming struct declaration (declared here due Fld_wid for each register type) + * Should include all fields from ACTiming excel file (And update the correct values in UpdateACTimingReg() + * Note: DQSINCTL, DATLAT aren't in ACTiming excel file (internal delay parameters) + */ +typedef struct _ACTime_T_LP4 +{ + U8 dramType, cbtMode, readDBI; + U8 DivMode; + U16 freq; + U16 readLat, writeLat; + U16 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file + + U16 tras; + U16 trp; + U16 trpab; + U16 trc; + U16 trfc; + U16 trfcpb; + U16 txp; + U16 trtp; + U16 trcd; + U16 twr; + U16 twtr; + U16 tpbr2pbr; + U16 tpbr2act; + U16 tr2mrw; + U16 tw2mrw; + U16 tmrr2mrw; + U16 tmrw; + U16 tmrd; + U16 tmrwckel; + U16 tpde; + U16 tpdx; + U16 tmrri; + U16 trrd; + U16 trrd_4266; + U16 tfaw; + U16 tfaw_4266; + U16 trtw_odt_off; + U16 trtw_odt_on; + U16 txrefcnt; + U16 tzqcs; + U16 xrtw2w_new_mode; + U16 xrtw2w_old_mode; + U16 xrtw2r_odt_on; + U16 xrtw2r_odt_off; + U16 xrtr2w_odt_on; + U16 xrtr2w_odt_off; + U16 xrtr2r_new_mode; + U16 xrtr2r_old_mode; + U16 tr2mrr; + U16 vrcgdis_prdcnt; + U16 hwset_mr2_op; + U16 hwset_mr13_op; + U16 hwset_vrcg_op; + U16 trcd_derate; + U16 trc_derate; + U16 tras_derate; + U16 trpab_derate; + U16 trp_derate; + U16 trrd_derate; + U16 trtpd; + U16 twtpd; + U16 tmrr2w_odt_off; + U16 tmrr2w_odt_on; + U16 ckeprd; + U16 ckelckcnt; + U16 zqlat2; + + //DRAMC_REG_SHU_AC_TIME_05T =================================== + U16 tras_05T; + U16 trp_05T; + U16 trpab_05T; + U16 trc_05T; + U16 trfc_05T; + U16 trfcpb_05T; + U16 txp_05T; + U16 trtp_05T; + U16 trcd_05T; + U16 twr_05T; + U16 twtr_05T; + U16 tpbr2pbr_05T; + U16 tpbr2act_05T; + U16 tr2mrw_05T; + U16 tw2mrw_05T; + U16 tmrr2mrw_05T; + U16 tmrw_05T; + U16 tmrd_05T; + U16 tmrwckel_05T; + U16 tpde_05T; + U16 tpdx_05T; + U16 tmrri_05T; + U16 trrd_05T; + U16 trrd_4266_05T; + U16 tfaw_05T; + U16 tfaw_4266_05T; + U16 trtw_odt_off_05T; + U16 trtw_odt_on_05T; + U16 trcd_derate_05T; + U16 trc_derate_05T; + U16 tras_derate_05T; + U16 trpab_derate_05T; + U16 trp_derate_05T; + U16 trrd_derate_05T; + U16 trtpd_05T; + U16 twtpd_05T; +} ACTime_T_LP4; + +typedef struct _ACTime_T_LP5 +{ + U8 dramType, cbtMode, readDBI; + U8 DivMode; + U16 freq; + U16 readLat, writeLat; + U16 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file + + U16 tras; + U16 trp; + U16 trpab; + U16 trc; + U16 trfc; + U16 trfcpb; + U16 txp; + U16 trtp; + U16 trcd; + U16 twr; + U16 twtr; + U16 twtr_l; + U16 tpbr2pbr; + U16 tpbr2act; + U16 tr2mrw; + U16 tw2mrw; + U16 tmrr2mrw; + U16 tmrw; + U16 tmrd; + U16 tmrwckel; + U16 tpde; + U16 tpdx; + U16 tmrri; + U16 trrd; + U16 tfaw; + U16 tr2w_odt_off; + U16 tr2w_odt_on; + U16 txrefcnt; + U16 wckrdoff; + U16 wckwroff; + U16 tzqcs; + U16 xrtw2w_odt_off; + U16 xrtw2w_odt_on; + U16 xrtw2r_odt_off_otf_off; + U16 xrtw2r_odt_on_otf_off; + U16 xrtw2r_odt_off_otf_on; + U16 xrtw2r_odt_on_otf_on; + U16 xrtr2w_odt_on; + U16 xrtr2w_odt_off; + U16 xrtr2r_odt_off; + U16 xrtr2r_odt_on; + U16 xrtw2w_odt_off_wck; + U16 xrtw2w_odt_on_wck; + U16 xrtw2r_odt_off_wck; + U16 xrtw2r_odt_on_wck; + U16 xrtr2w_odt_off_wck; + U16 xrtr2w_odt_on_wck; + U16 xrtr2r_wck; + U16 tr2mrr; + U16 hwset_mr2_op; + U16 hwset_mr13_op; + U16 hwset_vrcg_op; + U16 vrcgdis_prdcnt; + U16 lp5_cmd1to2en; + U16 trtpd; + U16 twtpd; + U16 tmrr2w; + U16 ckeprd; + U16 ckelckcnt; + U16 tcsh_cscal; + U16 tcacsh; + U16 tcsh; + U16 trcd_derate; + U16 trc_derate; + U16 tras_derate; + U16 trpab_derate; + U16 trp_derate; + U16 trrd_derate; + U16 zqlat2; + + //DRAMC_REG_SHU_AC_TIME_05T =================================== + U16 tras_05T; + U16 trp_05T; + U16 trpab_05T; + U16 trc_05T; + U16 trfc_05T; + U16 trfcpb_05T; + U16 txp_05T; + U16 trtp_05T; + U16 trcd_05T; + U16 twr_05T; + U16 twtr_05T; + U16 twtr_l_05T; + U16 tr2mrw_05T; + U16 tw2mrw_05T; + U16 tmrr2mrw_05T; + U16 tmrw_05T; + U16 tmrd_05T; + U16 tmrwckel_05T; + U16 tpde_05T; + U16 tpdx_05T; + U16 tmrri_05T; + U16 trrd_05T; + U16 tfaw_05T; + U16 tr2w_odt_off_05T; + U16 tr2w_odt_on_05T; + U16 wckrdoff_05T; + U16 wckwroff_05T; + U16 trtpd_05T; + U16 twtpd_05T; + U16 tpbr2pbr_05T; + U16 tpbr2act_05T; + U16 trcd_derate_05T; + U16 trc_derate_05T; + U16 tras_derate_05T; + U16 trpab_derate_05T; + U16 trp_derate_05T; + U16 trrd_derate_05T; +} ACTime_T_LP5; + +//ACTimingTbl[] forward declaration +extern const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4]; +extern const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5]; + +extern U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p); +extern DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p); +extern void vDramcACTimingOptimize(DRAMC_CTX_T *p); +extern DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p); +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h b/src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h new file mode 100644 index 0000000000..2b9a21768e --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h @@ -0,0 +1,1291 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_CH0_NAO_REG_H__ +#define __DRAMC_CH0_NAO_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define TESTMODE 0x00000000 + #define TESTMODE_TESTM_PAT0 GENMASK(31, 24) +#define LBWDAT0 0x00000004 + #define LBWDAT0_LBWDATA0 GENMASK(31, 0) +#define LBWDAT1 0x00000008 + #define LBWDAT1_LBWDATA1 GENMASK(31, 0) +#define LBWDAT2 0x0000000c + #define LBWDAT2_LBWDATA2 GENMASK(31, 0) +#define LBWDAT3 0x00000010 + #define LBWDAT3_LBWDATA3 GENMASK(31, 0) +#define CKPHCHK 0x00000020 + #define CKPHCHK_CKPHCHKCYC GENMASK(15, 0) + #define CKPHCHK_CKPHCNTEN BIT(31) +#define DMMONITOR 0x00000024 + #define DMMONITOR_JMTR_EN BIT(0) + #define DMMONITOR_MONPAUSE_SW BIT(2) + #define DMMONITOR_BUSMONEN_SW BIT(3) + #define DMMONITOR_WDQ_MON_OPT BIT(4) + #define DMMONITOR_REQQUE_MON_SREF_DIS BIT(8) + #define DMMONITOR_REQQUE_MON_SREF_REOR BIT(9) + #define DMMONITOR_REQQUE_MON_SREF_LLAT BIT(10) + #define DMMONITOR_REQQUE_MON_SREF_HPRI BIT(11) + #define DMMONITOR_REQQUE_MON_SREF_RW BIT(12) + #define DMMONITOR_JMTRCNT GENMASK(31, 16) +#define TESTCHIP_DMA1 0x00000030 + #define TESTCHIP_DMA1_DMAEN BIT(0) + #define TESTCHIP_DMA1_DMAPUREWREN BIT(1) + #define TESTCHIP_DMA1_DMAPURERDEN BIT(2) + #define TESTCHIP_DMA1_DMA_MWR BIT(3) + #define TESTCHIP_DMA1_DMABURSTLEN GENMASK(6, 4) + #define TESTCHIP_DMA1_DMAEN_LOOP BIT(8) + #define TESTCHIP_DMA1_DMAFIXPAT BIT(9) + #define TESTCHIP_DMA1_DMA_LP4MATAB_OPT BIT(12) +#define MISC_STATUSA 0x00000080 + #define MISC_STATUSA_WAIT_DLE BIT(0) + #define MISC_STATUSA_WRITE_DATA_BUFFER_EMPTY BIT(1) + #define MISC_STATUSA_REQQ_EMPTY BIT(2) + #define MISC_STATUSA_PG_VLD BIT(3) + #define MISC_STATUSA_REQQUE_DEPTH GENMASK(7, 4) + #define MISC_STATUSA_REFRESH_RATE GENMASK(10, 8) + #define MISC_STATUSA_DRAM_HWCFG BIT(12) + #define MISC_STATUSA_CKEO_PRE BIT(13) + #define MISC_STATUSA_CKE1O_PRE BIT(14) + #define MISC_STATUSA_SREF_STATE BIT(16) + #define MISC_STATUSA_SELFREF_SM GENMASK(19, 17) + #define MISC_STATUSA_REFRESH_OVER_CNT GENMASK(23, 20) + #define MISC_STATUSA_REFRESH_QUEUE_CNT GENMASK(27, 24) + #define MISC_STATUSA_REQDEPTH_UPD_DONE BIT(28) + #define MISC_STATUSA_MANUTXUPD_DONE BIT(29) + #define MISC_STATUSA_DRAMC_IDLE_STATUS BIT(30) + #define MISC_STATUSA_DRAMC_IDLE_DCM BIT(31) +#define SPECIAL_STATUS 0x00000084 + #define SPECIAL_STATUS_SPECIAL_COMMAND_ENABLE BIT(0) + #define SPECIAL_STATUS_H_ZQLAT_REQ BIT(1) + #define SPECIAL_STATUS_H_ZQLCAL_REQ BIT(2) + #define SPECIAL_STATUS_H_DQSOSCEN_REQ BIT(4) + #define SPECIAL_STATUS_DQSOSCEN_PERIOD BIT(5) + #define SPECIAL_STATUS_H_ZQCS_REQ BIT(6) + #define SPECIAL_STATUS_H_REFR_REQ BIT(7) + #define SPECIAL_STATUS_STBUPD_STOP BIT(8) + #define SPECIAL_STATUS_HW_ZQLAT_REQ BIT(9) + #define SPECIAL_STATUS_HW_ZQCAL_REQ BIT(10) + #define SPECIAL_STATUS_SPECIAL_STATUS BIT(11) + #define SPECIAL_STATUS_SCSM GENMASK(16, 12) + #define SPECIAL_STATUS_SCARB_SM GENMASK(24, 20) + #define SPECIAL_STATUS_SC_DRAMC_QUEUE_ACK BIT(28) + #define SPECIAL_STATUS_SREF_REQ_2Q BIT(30) + #define SPECIAL_STATUS_SREF_REQ BIT(31) +#define SPCMDRESP 0x00000088 + #define SPCMDRESP_MRW_RESPONSE BIT(0) + #define SPCMDRESP_MRR_RESPONSE BIT(1) + #define SPCMDRESP_PREA_RESPONSE BIT(2) + #define SPCMDRESP_AREF_RESPONSE BIT(3) + #define SPCMDRESP_ZQC_RESPONSE BIT(4) + #define SPCMDRESP_TCMD_RESPONSE BIT(5) + #define SPCMDRESP_ZQLAT_RESPONSE BIT(6) + #define SPCMDRESP_RDDQC_RESPONSE BIT(7) + #define SPCMDRESP_STEST_RESPONSE BIT(8) + #define SPCMDRESP_MPCMAN_RESPONSE BIT(9) + #define SPCMDRESP_DQSOSCEN_RESPONSE BIT(10) + #define SPCMDRESP_DQSOSCDIS_RESPONSE BIT(11) + #define SPCMDRESP_ACT_RESPONSE BIT(12) + #define SPCMDRESP_MPRW_RESPONSE BIT(13) + #define SPCMDRESP_DVFS_RESPONSE BIT(16) + #define SPCMDRESP_HW_ZQLAT_POP BIT(17) + #define SPCMDRESP_HW_ZQCAL_POP BIT(18) + #define SPCMDRESP_RDFIFO_RESPONSE BIT(30) + #define SPCMDRESP_WRFIFO_RESPONSE BIT(31) +#define MRR_STATUS 0x0000008c + #define MRR_STATUS_MRR_REG GENMASK(15, 0) + #define MRR_STATUS_MRR_SW_REG GENMASK(31, 16) +#define MRR_STATUS2 0x00000090 + #define MRR_STATUS2_MR4_REG GENMASK(15, 0) + #define MRR_STATUS2_SHUFFLE_MRW_VRCG_NORMAL_OK BIT(16) + #define MRR_STATUS2_TFC_OK BIT(17) + #define MRR_STATUS2_TCKFSPX_OK BIT(18) + #define MRR_STATUS2_TVRCG_EN_OK BIT(19) + #define MRR_STATUS2_TCKFSPE_OK BIT(20) + #define MRR_STATUS2_TVRCG_DIS_OK BIT(21) + #define MRR_STATUS2_PHY_SHUFFLE_PERIOD_GO_ZERO_OK BIT(22) + #define MRR_STATUS2_DVFS_STATE GENMASK(31, 24) +#define MRRDATA0 0x00000094 + #define MRRDATA0_MRR_DATA0 GENMASK(31, 0) +#define MRRDATA1 0x00000098 + #define MRRDATA1_MRR_DATA1 GENMASK(31, 0) +#define MRRDATA2 0x0000009c + #define MRRDATA2_MRR_DATA2 GENMASK(31, 0) +#define MRRDATA3 0x000000a0 + #define MRRDATA3_MRR_DATA3 GENMASK(31, 0) +#define DRS_STATUS 0x000000a8 + #define DRS_STATUS_DRS_MONERR_ACK BIT(8) + #define DRS_STATUS_DRS_MONERR_REQ BIT(9) + #define DRS_STATUS_RK1_DRS_REQ BIT(16) + #define DRS_STATUS_RK1_DRS_2Q BIT(17) + #define DRS_STATUS_RK1_DRSLY_REQ BIT(18) + #define DRS_STATUS_RK1_DRS_RDY BIT(19) + #define DRS_STATUS_RK1_DRS_ACK BIT(20) + #define DRS_STATUS_RK1_DRS_STATUS BIT(21) + #define DRS_STATUS_SELFREF_SM_RK1 GENMASK(26, 24) +#define JMETER_ST 0x000000bc + #define JMETER_ST_ZEROS_CNT GENMASK(14, 0) + #define JMETER_ST_ONES_CNT GENMASK(30, 16) + #define JMETER_ST_JMTR_DONE BIT(31) +#define TCMDO1LAT 0x000000c0 + #define TCMDO1LAT_TCMD_O1_LATCH_DATA0 GENMASK(5, 0) + #define TCMDO1LAT_TCMD_O1_LATCH_DATA1 GENMASK(13, 8) + #define TCMDO1LAT_CATRAIN_CMP_ERR0 GENMASK(21, 16) + #define TCMDO1LAT_CATRAIN_CMP_ERR GENMASK(29, 24) + #define TCMDO1LAT_CATRAIN_CMP_CPT BIT(31) +#define RDQC_CMP 0x000000c4 + #define RDQC_CMP_RDDQC_CMP0_ERR GENMASK(15, 0) + #define RDQC_CMP_RDDQC_CMP1_ERR GENMASK(31, 16) +#define CKPHCHK_STATUS 0x000000c8 + #define CKPHCHK_STATUS_CKPHCHK_STATUS GENMASK(15, 0) +#define HWMRR_PUSH2POP_CNT 0x0000010c + #define HWMRR_PUSH2POP_CNT_HWMRR_PUSH2POP_CNT GENMASK(31, 0) +#define HWMRR_STATUS 0x00000110 + #define HWMRR_STATUS_OV_P2P_CNT GENMASK(7, 0) + #define HWMRR_STATUS_MRR_CNT_UNDER_FULL BIT(30) + #define HWMRR_STATUS_MRR_CNT_OVER_FULL BIT(31) +#define HW_REFRATE_MON 0x00000114 + #define HW_REFRATE_MON_REFRESH_RATE_MIN_MON GENMASK(2, 0) + #define HW_REFRATE_MON_REFRESH_RATE_MAX_MON GENMASK(10, 8) +#define TESTRPT 0x00000120 + #define TESTRPT_DM_CMP_CPT_RK0 BIT(0) + #define TESTRPT_DM_CMP_CPT_RK1 BIT(1) + #define TESTRPT_DM_CMP_ERR_RK0 BIT(4) + #define TESTRPT_DM_CMP_ERR_RK1 BIT(5) + #define TESTRPT_DLE_CNT_OK_RK0 BIT(8) + #define TESTRPT_DLE_CNT_OK_RK1 BIT(9) + #define TESTRPT_TESTSTAT GENMASK(22, 20) + #define TESTRPT_LB_CMP_FAIL BIT(24) + #define TESTRPT_CALI_DONE_MON BIT(28) +#define CMP_ERR 0x00000124 + #define CMP_ERR_CMP_ERR GENMASK(31, 0) +#define TEST_ABIT_STATUS1 0x00000128 + #define TEST_ABIT_STATUS1_TEST_ABIT_ERR1 GENMASK(31, 0) +#define TEST_ABIT_STATUS2 0x0000012c + #define TEST_ABIT_STATUS2_TEST_ABIT_ERR2 GENMASK(31, 0) +#define TEST_ABIT_STATUS3 0x00000130 + #define TEST_ABIT_STATUS3_TEST_ABIT_ERR3 GENMASK(31, 0) +#define TEST_ABIT_STATUS4 0x00000134 + #define TEST_ABIT_STATUS4_TEST_ABIT_ERR4 GENMASK(31, 0) +#define DQSDLY0 0x00000150 + #define DQSDLY0_DEL0DLY GENMASK(6, 0) + #define DQSDLY0_DEL1DLY GENMASK(14, 8) + #define DQSDLY0_DEL2DLY GENMASK(22, 16) + #define DQSDLY0_DEL3DLY GENMASK(30, 24) +#define DQ_CAL_MAX_0 0x00000154 + #define DQ_CAL_MAX_0_DQ0_0_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_0_DQ0_1_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_0_DQ0_2_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_0_DQ0_3_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_1 0x00000158 + #define DQ_CAL_MAX_1_DQ0_4_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_1_DQ0_5_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_1_DQ0_6_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_1_DQ0_7_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_2 0x0000015c + #define DQ_CAL_MAX_2_DQ1_0_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_2_DQ1_1_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_2_DQ1_2_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_2_DQ1_3_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_3 0x00000160 + #define DQ_CAL_MAX_3_DQ1_4_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_3_DQ1_5_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_3_DQ1_6_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_3_DQ1_7_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_4 0x00000164 + #define DQ_CAL_MAX_4_DQ2_0_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_4_DQ2_1_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_4_DQ2_2_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_4_DQ2_3_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_5 0x00000168 + #define DQ_CAL_MAX_5_DQ2_4_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_5_DQ2_5_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_5_DQ2_6_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_5_DQ2_7_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_6 0x0000016c + #define DQ_CAL_MAX_6_DQ3_0_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_6_DQ3_1_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_6_DQ3_2_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_6_DQ3_3_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_7 0x00000170 + #define DQ_CAL_MAX_7_DQ3_4_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_7_DQ3_5_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_7_DQ3_6_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_7_DQ3_7_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MIN_0 0x00000174 + #define DQS_CAL_MIN_0_DQS0_0_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_0_DQS0_1_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_0_DQS0_2_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_0_DQS0_3_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_1 0x00000178 + #define DQS_CAL_MIN_1_DQS0_4_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_1_DQS0_5_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_1_DQS0_6_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_1_DQS0_7_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_2 0x0000017c + #define DQS_CAL_MIN_2_DQS1_0_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_2_DQS1_1_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_2_DQS1_2_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_2_DQS1_3_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_3 0x00000180 + #define DQS_CAL_MIN_3_DQS1_4_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_3_DQS1_5_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_3_DQS1_6_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_3_DQS1_7_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_4 0x00000184 + #define DQS_CAL_MIN_4_DQS2_0_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_4_DQS2_1_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_4_DQS2_2_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_4_DQS2_3_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_5 0x00000188 + #define DQS_CAL_MIN_5_DQS2_4_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_5_DQS2_5_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_5_DQS2_6_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_5_DQS2_7_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_6 0x0000018c + #define DQS_CAL_MIN_6_DQS3_0_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_6_DQS3_1_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_6_DQS3_2_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_6_DQS3_3_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_7 0x00000190 + #define DQS_CAL_MIN_7_DQS3_4_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_7_DQS3_5_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_7_DQS3_6_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_7_DQS3_7_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MAX_0 0x00000194 + #define DQS_CAL_MAX_0_DQS0_0_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_0_DQS0_1_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_0_DQS0_2_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_0_DQS0_3_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_1 0x00000198 + #define DQS_CAL_MAX_1_DQS0_4_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_1_DQS0_5_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_1_DQS0_6_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_1_DQS0_7_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_2 0x0000019c + #define DQS_CAL_MAX_2_DQS1_0_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_2_DQS1_1_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_2_DQS1_2_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_2_DQS1_3_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_3 0x000001a0 + #define DQS_CAL_MAX_3_DQS1_4_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_3_DQS1_5_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_3_DQS1_6_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_3_DQS1_7_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_4 0x000001a4 + #define DQS_CAL_MAX_4_DQS2_0_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_4_DQS2_1_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_4_DQS2_2_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_4_DQS2_3_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_5 0x000001a8 + #define DQS_CAL_MAX_5_DQS2_4_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_5_DQS2_5_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_5_DQS2_6_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_5_DQS2_7_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_6 0x000001ac + #define DQS_CAL_MAX_6_DQS3_0_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_6_DQS3_1_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_6_DQS3_2_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_6_DQS3_3_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_7 0x000001b0 + #define DQS_CAL_MAX_7_DQS3_4_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_7_DQS3_5_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_7_DQS3_6_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_7_DQS3_7_DLY_MAX GENMASK(31, 24) +#define DQICAL0 0x000001b4 + #define DQICAL0_DQ0_DLY_MAX GENMASK(6, 0) + #define DQICAL0_DQ1_DLY_MAX GENMASK(14, 8) + #define DQICAL0_DQ2_DLY_MAX GENMASK(22, 16) + #define DQICAL0_DQ3_DLY_MAX GENMASK(30, 24) +#define DQICAL1 0x000001b8 + #define DQICAL1_DQS0_DLY_MIN GENMASK(6, 0) + #define DQICAL1_DQS1_DLY_MIN GENMASK(14, 8) + #define DQICAL1_DQS2_DLY_MIN GENMASK(22, 16) + #define DQICAL1_DQS3_DLY_MIN GENMASK(30, 24) +#define DQICAL2 0x000001bc + #define DQICAL2_DQS0_DLY_MAX GENMASK(6, 0) + #define DQICAL2_DQS1_DLY_MAX GENMASK(14, 8) + #define DQICAL2_DQS2_DLY_MAX GENMASK(22, 16) + #define DQICAL2_DQS3_DLY_MAX GENMASK(30, 24) +#define DQICAL3 0x000001c0 + #define DQICAL3_DQS0_DLY_AVG GENMASK(6, 0) + #define DQICAL3_DQS1_DLY_AVG GENMASK(14, 8) + #define DQICAL3_DQS2_DLY_AVG GENMASK(22, 16) + #define DQICAL3_DQS3_DLY_AVG GENMASK(30, 24) +#define TESTCHIP_DMA_STATUS1 0x00000200 + #define TESTCHIP_DMA_STATUS1_DMASTATUS BIT(0) + #define TESTCHIP_DMA_STATUS1_DMA_BUF_AVAIL BIT(2) + #define TESTCHIP_DMA_STATUS1_DMACMPERR BIT(3) + #define TESTCHIP_DMA_STATUS1_DMA_STATE GENMASK(7, 4) +#define TESTCHIP_DMA_STATUS2 0x00000204 + #define TESTCHIP_DMA_STATUS2_DMACMPERR_BIT GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS3 0x00000208 + #define TESTCHIP_DMA_STATUS3_DMA_DATA_BUFFER0_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS4 0x0000020c + #define TESTCHIP_DMA_STATUS4_DMA_DATA_BUFFER0_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS5 0x00000210 + #define TESTCHIP_DMA_STATUS5_DMA_DATA_BUFFER0_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS6 0x00000214 + #define TESTCHIP_DMA_STATUS6_DMA_DATA_BUFFER0_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS7 0x00000218 + #define TESTCHIP_DMA_STATUS7_DMA_DATA_BUFFER1_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS8 0x0000021c + #define TESTCHIP_DMA_STATUS8_DMA_DATA_BUFFER1_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS9 0x00000220 + #define TESTCHIP_DMA_STATUS9_DMA_DATA_BUFFER1_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS10 0x00000224 + #define TESTCHIP_DMA_STATUS10_DMA_DATA_BUFFE1_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS11 0x00000228 + #define TESTCHIP_DMA_STATUS11_DMA_DATA_BUFFER2_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS12 0x0000022c + #define TESTCHIP_DMA_STATUS12_DMA_DATA_BUFFER2_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS13 0x00000230 + #define TESTCHIP_DMA_STATUS13_DMA_DATA_BUFFER2_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS14 0x00000234 + #define TESTCHIP_DMA_STATUS14_DMA_DATA_BUFFER2_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS15 0x00000238 + #define TESTCHIP_DMA_STATUS15_DMA_DATA_BUFFER3_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS16 0x0000023c + #define TESTCHIP_DMA_STATUS16_DMA_DATA_BUFFER3_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS17 0x00000240 + #define TESTCHIP_DMA_STATUS17_DMA_DATA_BUFFER3_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS18 0x00000244 + #define TESTCHIP_DMA_STATUS18_DMA_DATA_BUFFER3_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS19 0x00000248 + #define TESTCHIP_DMA_STATUS19_DMA_DATA_BUFFER4_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS20 0x0000024c + #define TESTCHIP_DMA_STATUS20_DMA_DATA_BUFFER4_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS21 0x00000250 + #define TESTCHIP_DMA_STATUS21_DMA_DATA_BUFFER4_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS22 0x00000254 + #define TESTCHIP_DMA_STATUS22_DMA_DATA_BUFFER4_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS23 0x00000258 + #define TESTCHIP_DMA_STATUS23_DMA_DATA_BUFFER5_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS24 0x0000025c + #define TESTCHIP_DMA_STATUS24_DMA_DATA_BUFFER5_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS25 0x00000260 + #define TESTCHIP_DMA_STATUS25_DMA_DATA_BUFFER5_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS26 0x00000264 + #define TESTCHIP_DMA_STATUS26_DMA_DATA_BUFFER5_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS27 0x00000268 + #define TESTCHIP_DMA_STATUS27_DMA_DATA_BUFFER6_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS28 0x0000026c + #define TESTCHIP_DMA_STATUS28_DMA_DATA_BUFFER6_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS29 0x00000270 + #define TESTCHIP_DMA_STATUS29_DMA_DATA_BUFFER6_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS30 0x00000274 + #define TESTCHIP_DMA_STATUS30_DMA_DATA_BUFFER6_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS31 0x00000278 + #define TESTCHIP_DMA_STATUS31_DMA_DATA_BUFFER7_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS32 0x0000027c + #define TESTCHIP_DMA_STATUS32_DMA_DATA_BUFFER7_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS33 0x00000280 + #define TESTCHIP_DMA_STATUS33_DMA_DATA_BUFFER7_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS34 0x00000284 + #define TESTCHIP_DMA_STATUS34_DMA_DATA_BUFFER7_127_96_ GENMASK(31, 0) +#define REFRESH_POP_COUNTER 0x00000300 + #define REFRESH_POP_COUNTER_REFRESH_POP_COUNTER GENMASK(31, 0) +#define FREERUN_26M_COUNTER 0x00000304 + #define FREERUN_26M_COUNTER_FREERUN_26M_COUNTER GENMASK(31, 0) +#define DRAMC_IDLE_COUNTER 0x00000308 + #define DRAMC_IDLE_COUNTER_DRAMC_IDLE_COUNTER GENMASK(31, 0) +#define R2R_PAGE_HIT_COUNTER 0x0000030c + #define R2R_PAGE_HIT_COUNTER_R2R_PAGE_HIT_COUNTER GENMASK(31, 0) +#define R2R_PAGE_MISS_COUNTER 0x00000310 + #define R2R_PAGE_MISS_COUNTER_R2R_PAGE_MISS_COUNTER GENMASK(31, 0) +#define R2R_INTERBANK_COUNTER 0x00000314 + #define R2R_INTERBANK_COUNTER_R2R_INTERBANK_COUNTER GENMASK(31, 0) +#define R2W_PAGE_HIT_COUNTER 0x00000318 + #define R2W_PAGE_HIT_COUNTER_R2W_PAGE_HIT_COUNTER GENMASK(31, 0) +#define R2W_PAGE_MISS_COUNTER 0x0000031c + #define R2W_PAGE_MISS_COUNTER_R2W_PAGE_MISS_COUNTER GENMASK(31, 0) +#define R2W_INTERBANK_COUNTER 0x00000320 + #define R2W_INTERBANK_COUNTER_R2W_INTERBANK_COUNTER GENMASK(31, 0) +#define W2R_PAGE_HIT_COUNTER 0x00000324 + #define W2R_PAGE_HIT_COUNTER_W2R_PAGE_HIT_COUNTER GENMASK(31, 0) +#define W2R_PAGE_MISS_COUNTER 0x00000328 + #define W2R_PAGE_MISS_COUNTER_W2R_PAGE_MISS_COUNTER GENMASK(31, 0) +#define W2R_INTERBANK_COUNTER 0x0000032c + #define W2R_INTERBANK_COUNTER_W2R_INTERBANK_COUNTER GENMASK(31, 0) +#define W2W_PAGE_HIT_COUNTER 0x00000330 + #define W2W_PAGE_HIT_COUNTER_W2W_PAGE_HIT_COUNTER GENMASK(31, 0) +#define W2W_PAGE_MISS_COUNTER 0x00000334 + #define W2W_PAGE_MISS_COUNTER_W2W_PAGE_MISS_COUNTER GENMASK(31, 0) +#define W2W_INTERBANK_COUNTER 0x00000338 + #define W2W_INTERBANK_COUNTER_W2W_INTERBANK_COUNTER GENMASK(31, 0) +#define RK0_PRE_STANDBY_COUNTER 0x0000033c + #define RK0_PRE_STANDBY_COUNTER_RK0_PRE_STANDBY_COUNTER GENMASK(31, 0) +#define RK0_PRE_POWERDOWN_COUNTER 0x00000340 + #define RK0_PRE_POWERDOWN_COUNTER_RK0_PRE_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK0_ACT_STANDBY_COUNTER 0x00000344 + #define RK0_ACT_STANDBY_COUNTER_RK0_ACT_STANDBY_COUNTER GENMASK(31, 0) +#define RK0_ACT_POWERDOWN_COUNTER 0x00000348 + #define RK0_ACT_POWERDOWN_COUNTER_RK0_ACT_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK1_PRE_STANDBY_COUNTER 0x0000034c + #define RK1_PRE_STANDBY_COUNTER_RK1_PRE_STANDBY_COUNTER GENMASK(31, 0) +#define RK1_PRE_POWERDOWN_COUNTER 0x00000350 + #define RK1_PRE_POWERDOWN_COUNTER_RK1_PRE_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK1_ACT_STANDBY_COUNTER 0x00000354 + #define RK1_ACT_STANDBY_COUNTER_RK1_ACT_STANDBY_COUNTER GENMASK(31, 0) +#define RK1_ACT_POWERDOWN_COUNTER 0x00000358 + #define RK1_ACT_POWERDOWN_COUNTER_RK1_ACT_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK2_PRE_STANDBY_COUNTER 0x0000035c + #define RK2_PRE_STANDBY_COUNTER_RK2_PRE_STANDBY_COUNTER GENMASK(31, 0) +#define RK2_PRE_POWERDOWN_COUNTER 0x00000360 + #define RK2_PRE_POWERDOWN_COUNTER_RK2_PRE_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK2_ACT_STANDBY_COUNTER 0x00000364 + #define RK2_ACT_STANDBY_COUNTER_RK2_ACT_STANDBY_COUNTER GENMASK(31, 0) +#define RK2_ACT_POWERDOWN_COUNTER 0x00000368 + #define RK2_ACT_POWERDOWN_COUNTER_RK2_ACT_POWERDOWN_COUNTER GENMASK(31, 0) +#define DQ0_TOGGLE_COUNTER 0x0000036c + #define DQ0_TOGGLE_COUNTER_DQ0_TOGGLE_COUNTER GENMASK(31, 0) +#define DQ1_TOGGLE_COUNTER 0x00000370 + #define DQ1_TOGGLE_COUNTER_DQ1_TOGGLE_COUNTER GENMASK(31, 0) +#define DQ2_TOGGLE_COUNTER 0x00000374 + #define DQ2_TOGGLE_COUNTER_DQ2_TOGGLE_COUNTER GENMASK(31, 0) +#define DQ3_TOGGLE_COUNTER 0x00000378 + #define DQ3_TOGGLE_COUNTER_DQ3_TOGGLE_COUNTER GENMASK(31, 0) +#define DQ0_TOGGLE_COUNTER_R 0x0000037c + #define DQ0_TOGGLE_COUNTER_R_DQ0_TOGGLE_COUNTER_R GENMASK(31, 0) +#define DQ1_TOGGLE_COUNTER_R 0x00000380 + #define DQ1_TOGGLE_COUNTER_R_DQ1_TOGGLE_COUNTER_R GENMASK(31, 0) +#define DQ2_TOGGLE_COUNTER_R 0x00000384 + #define DQ2_TOGGLE_COUNTER_R_DQ2_TOGGLE_COUNTER_R GENMASK(31, 0) +#define DQ3_TOGGLE_COUNTER_R 0x00000388 + #define DQ3_TOGGLE_COUNTER_R_DQ3_TOGGLE_COUNTER_R GENMASK(31, 0) +#define READ_BYTES_COUNTER 0x0000038c + #define READ_BYTES_COUNTER_READ_BYTES_COUNTER GENMASK(31, 0) +#define WRITE_BYTES_COUNTER 0x00000390 + #define WRITE_BYTES_COUNTER_WRITE_BYTES_COUNTER GENMASK(31, 0) +#define MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER 0x00000394 + #define MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER_SREF_REQTOACK_MAX_COUNTER GENMASK(31, 0) +#define MAX_RK1_DRS_LONG_REQ_TO_ACK_LATENCY_COUNTER 0x00000398 + #define MAX_RK1_DRS_LONG_REQ_TO_ACK_LATENCY_COUNTER_DRS_LONG_REQTOACK_MAX_COUNTER GENMASK(31, 0) +#define MAX_RK1_DRS_REQ_TO_ACK_LATENCY_COUNTER 0x0000039c + #define MAX_RK1_DRS_REQ_TO_ACK_LATENCY_COUNTER_DRS_REQTOACK_MAX_COUNTER GENMASK(31, 0) +#define DRAMC_IDLE_DCM_COUNTER 0x000003a0 + #define DRAMC_IDLE_DCM_COUNTER_DRAMC_IDLE_DCM_COUNTER GENMASK(31, 0) +#define DDRPHY_CLK_EN_COUNTER 0x000003a4 + #define DDRPHY_CLK_EN_COUNTER_DDRPHY_CLK_EN_COUNTER GENMASK(31, 0) +#define DDRPHY_CLK_EN_COMB_COUNTER 0x000003a8 + #define DDRPHY_CLK_EN_COMB_COUNTER_DDRPHY_CLK_EN_COMB_COUNTER GENMASK(31, 0) +#define LAT_COUNTER_CMD0 0x000003c0 + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD1 0x000003c4 + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD2 0x000003c8 + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD3 0x000003cc + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD4 0x000003d0 + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD5 0x000003d4 + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD6 0x000003d8 + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD7 0x000003dc + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_AVER 0x000003e0 + #define LAT_COUNTER_AVER_LAT_CMD_AVER_CNT GENMASK(31, 0) +#define LAT_COUNTER_NUM 0x000003e4 + #define LAT_COUNTER_NUM_LAT_CMD_NUM GENMASK(15, 0) +#define LAT_COUNTER_BLOCK_ALE 0x000003e8 + #define LAT_COUNTER_BLOCK_ALE_CTO_BLOCK_CNT_MAX GENMASK(15, 0) +#define DQSSAMPLEV 0x00000400 + #define DQSSAMPLEV_SAMPLE_OUT1_DQS0 BIT(0) + #define DQSSAMPLEV_SAMPLE_OUT1_DQS1 BIT(1) + #define DQSSAMPLEV_SAMPLE_OUT1_DQS2 BIT(2) + #define DQSSAMPLEV_SAMPLE_OUT1_DQS3 BIT(3) + #define DQSSAMPLEV_PI_OVERFLOW GENMASK(15, 12) +#define DQSGNWCNT0 0x00000408 + #define DQSGNWCNT0_DQS0F_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT0_DQS0R_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT0_DQS1F_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT0_DQS1R_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT1 0x0000040c + #define DQSGNWCNT1_DQS2F_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT1_DQS2R_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT1_DQS3F_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT1_DQS3R_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT2 0x00000410 + #define DQSGNWCNT2_DQS0F_POS_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT2_DQS0R_POS_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT2_DQS0F_PRE_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT2_DQS0R_PRE_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT3 0x00000414 + #define DQSGNWCNT3_DQS1F_POS_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT3_DQS1R_POS_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT3_DQS1F_PRE_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT3_DQS1R_PRE_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT4 0x00000418 + #define DQSGNWCNT4_DQS2F_POS_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT4_DQS2R_POS_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT4_DQS2F_PRE_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT4_DQS2R_PRE_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT5 0x0000041c + #define DQSGNWCNT5_DQS3F_POS_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT5_DQS3R_POS_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT5_DQS3F_PRE_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT5_DQS3R_PRE_GATING_COUNTER GENMASK(31, 24) +#define TOGGLE_CNT 0x00000420 + #define TOGGLE_CNT_TOGGLE_CNT GENMASK(31, 0) +#define DQS0_ERR_CNT 0x00000424 + #define DQS0_ERR_CNT_DQS0_ERR_CNT GENMASK(31, 0) +#define DQ_ERR_CNT0 0x00000428 + #define DQ_ERR_CNT0_DQ_ERR_CNT0 GENMASK(31, 0) +#define DQS1_ERR_CNT 0x0000042c + #define DQS1_ERR_CNT_DQS1_ERR_CNT GENMASK(31, 0) +#define DQ_ERR_CNT1 0x00000430 + #define DQ_ERR_CNT1_DQ_ERR_CNT1 GENMASK(31, 0) +#define DQS2_ERR_CNT 0x00000434 + #define DQS2_ERR_CNT_DQS2_ERR_CNT GENMASK(31, 0) +#define DQ_ERR_CNT2 0x00000438 + #define DQ_ERR_CNT2_DQ_ERR_CNT2 GENMASK(31, 0) +#define DQS3_ERR_CNT 0x0000043c + #define DQS3_ERR_CNT_DQS3_ERR_CNT GENMASK(31, 0) +#define DQ_ERR_CNT3 0x00000440 + #define DQ_ERR_CNT3_DQ_ERR_CNT3 GENMASK(31, 0) +#define IORGCNT 0x00000450 + #define IORGCNT_IO_RING_COUNTER_K GENMASK(15, 0) + #define IORGCNT_IO_RING_COUNTER GENMASK(31, 16) +#define DQSG_RETRY_STATE 0x00000454 + #define DQSG_RETRY_STATE_DQSG_RETRY_1ST_ST GENMASK(7, 0) + #define DQSG_RETRY_STATE_DQSG_RETRY_2ND_ST GENMASK(15, 8) + #define DQSG_RETRY_STATE_DQSG_RETRY_3RD_ST GENMASK(23, 16) + #define DQSG_RETRY_STATE_DQSG_RETRY_4TH_ST GENMASK(31, 24) +#define DQSG_RETRY_STATE1 0x00000458 + #define DQSG_RETRY_STATE1_RETRY_DONE_ALL BIT(0) + #define DQSG_RETRY_STATE1_SELPH_RODTEN_USABLE BIT(1) + #define DQSG_RETRY_STATE1_TDQSCK_DONE BIT(4) + #define DQSG_RETRY_STATE1_IMPCAL_N_ERROR BIT(8) + #define DQSG_RETRY_STATE1_IMPCAL_P_ERROR BIT(9) + #define DQSG_RETRY_STATE1_IMPCAL_DONE BIT(10) + #define DQSG_RETRY_STATE1_STB_GATING_ERR BIT(16) + #define DQSG_RETRY_STATE1_R_OTHER_SHU_GP_GATING_ERR GENMASK(18, 17) + #define DQSG_RETRY_STATE1_R_MPDIV_SHU_GP_GATING_ERR GENMASK(21, 19) + #define DQSG_RETRY_STATE1_DQSG_RETRY_5TH_ST GENMASK(31, 24) +#define IMPCAL_STATUS1 0x00000460 + #define IMPCAL_STATUS1_DRVNDQ_SAVE2 GENMASK(4, 0) + #define IMPCAL_STATUS1_DRVPDQ_SAVE2 GENMASK(9, 5) + #define IMPCAL_STATUS1_DRVNDQS_SAVE1 GENMASK(14, 10) + #define IMPCAL_STATUS1_DRVPDQS_SAVE1 GENMASK(19, 15) + #define IMPCAL_STATUS1_DRVNDQS_SAVE2 GENMASK(24, 20) + #define IMPCAL_STATUS1_DRVPDQS_SAVE2 GENMASK(29, 25) +#define IMPCAL_STATUS2 0x00000464 + #define IMPCAL_STATUS2_DRVNCMD_SAVE1 GENMASK(4, 0) + #define IMPCAL_STATUS2_DRVPCMD_SAVE1 GENMASK(9, 5) + #define IMPCAL_STATUS2_DRVNCMD_SAVE2 GENMASK(14, 10) + #define IMPCAL_STATUS2_DRVPCMD_SAVE2 GENMASK(19, 15) + #define IMPCAL_STATUS2_DRVNDQ_SAVE1 GENMASK(24, 20) + #define IMPCAL_STATUS2_DRVPDQ_SAVE1 GENMASK(29, 25) +#define DQDRV_STATUS 0x00000468 + #define DQDRV_STATUS_DRVNDQ_2 GENMASK(4, 0) + #define DQDRV_STATUS_DRVPDQ_2 GENMASK(9, 5) + #define DQDRV_STATUS_DRVNDQS_1 GENMASK(14, 10) + #define DQDRV_STATUS_DRVPDQS_1 GENMASK(19, 15) + #define DQDRV_STATUS_DRVNDQS_2 GENMASK(24, 20) + #define DQDRV_STATUS_DRVPDQS_2 GENMASK(29, 25) +#define CMDDRV_STATUS 0x0000046c + #define CMDDRV_STATUS_DRVNCMD_1 GENMASK(4, 0) + #define CMDDRV_STATUS_DRVPCMD_1 GENMASK(9, 5) + #define CMDDRV_STATUS_DRVNCMD_2 GENMASK(14, 10) + #define CMDDRV_STATUS_DRVPCMD_2 GENMASK(19, 15) + #define CMDDRV_STATUS_DRVNDQ_1 GENMASK(24, 20) + #define CMDDRV_STATUS_DRVPDQ_1 GENMASK(29, 25) +#define CMDDRV1 0x00000470 + #define CMDDRV1_CMDDRV1 GENMASK(31, 0) +#define CMDDRV2 0x00000474 + #define CMDDRV2_CMDDRV2 GENMASK(31, 0) +#define RK0_DQSOSC_STATUS 0x00000600 + #define RK0_DQSOSC_STATUS_MR18_REG GENMASK(15, 0) + #define RK0_DQSOSC_STATUS_MR19_REG GENMASK(31, 16) +#define RK0_DQSOSC_DELTA 0x00000604 + #define RK0_DQSOSC_DELTA_ABS_RK0_DQSOSC_DELTA GENMASK(15, 0) + #define RK0_DQSOSC_DELTA_SIGN_RK0_DQSOSC_DELTA BIT(16) + #define RK0_DQSOSC_DELTA_DQSOCSR_RESPONSE BIT(17) + #define RK0_DQSOSC_DELTA_H_DQSOSCLSBR_REQ BIT(18) + #define RK0_DQSOSC_DELTA_DQSOSC_INT_RK0 BIT(19) +#define RK0_DQSOSC_DELTA2 0x00000608 + #define RK0_DQSOSC_DELTA2_ABS_RK0_DQSOSC_B1_DELTA GENMASK(15, 0) + #define RK0_DQSOSC_DELTA2_SIGN_RK0_DQSOSC_B1_DELTA BIT(16) +#define RK0_CURRENT_TX_SETTING1 0x00000610 + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ0_MOD GENMASK(2, 0) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ1_MOD GENMASK(6, 4) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ2_MOD GENMASK(10, 8) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ3_MOD GENMASK(14, 12) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM0_MOD GENMASK(18, 16) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM1_MOD GENMASK(22, 20) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM2_MOD GENMASK(26, 24) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM3_MOD GENMASK(30, 28) +#define RK0_CURRENT_TX_SETTING2 0x00000614 + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ0_MOD GENMASK(2, 0) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ1_MOD GENMASK(6, 4) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ2_MOD GENMASK(10, 8) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ3_MOD GENMASK(14, 12) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM0_MOD GENMASK(18, 16) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM1_MOD GENMASK(22, 20) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM2_MOD GENMASK(26, 24) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM3_MOD GENMASK(30, 28) +#define RK0_CURRENT_TX_SETTING3 0x00000618 + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ0_MOD GENMASK(2, 0) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ1_MOD GENMASK(6, 4) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ2_MOD GENMASK(10, 8) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ3_MOD GENMASK(14, 12) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM0_MOD GENMASK(18, 16) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM1_MOD GENMASK(22, 20) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM2_MOD GENMASK(26, 24) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM3_MOD GENMASK(30, 28) +#define RK0_CURRENT_TX_SETTING4 0x0000061c + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ0_MOD GENMASK(2, 0) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ1_MOD GENMASK(6, 4) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ2_MOD GENMASK(10, 8) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ3_MOD GENMASK(14, 12) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM0_MOD GENMASK(18, 16) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM1_MOD GENMASK(22, 20) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM2_MOD GENMASK(26, 24) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM3_MOD GENMASK(30, 28) +#define RK0_DUMMY_RD_DATA0 0x00000620 + #define RK0_DUMMY_RD_DATA0_DUMMY_RD_RK0_DATA0 GENMASK(31, 0) +#define RK0_DUMMY_RD_DATA1 0x00000624 + #define RK0_DUMMY_RD_DATA1_DUMMY_RD_RK0_DATA1 GENMASK(31, 0) +#define RK0_DUMMY_RD_DATA2 0x00000628 + #define RK0_DUMMY_RD_DATA2_DUMMY_RD_RK0_DATA2 GENMASK(31, 0) +#define RK0_DUMMY_RD_DATA3 0x0000062c + #define RK0_DUMMY_RD_DATA3_DUMMY_RD_RK0_DATA3 GENMASK(31, 0) +#define RK0_B0_STB_MAX_MIN_DLY 0x00000630 + #define RK0_B0_STB_MAX_MIN_DLY_RK0_B0_STBEN_MIN_DLY GENMASK(11, 0) + #define RK0_B0_STB_MAX_MIN_DLY_RK0_B0_STBEN_MAX_DLY GENMASK(27, 16) +#define RK0_B1_STB_MAX_MIN_DLY 0x00000634 + #define RK0_B1_STB_MAX_MIN_DLY_RK0_B1_STBEN_MIN_DLY GENMASK(11, 0) + #define RK0_B1_STB_MAX_MIN_DLY_RK0_B1_STBEN_MAX_DLY GENMASK(27, 16) +#define RK0_B2_STB_MAX_MIN_DLY 0x00000638 + #define RK0_B2_STB_MAX_MIN_DLY_RK0_B2_STBEN_MIN_DLY GENMASK(11, 0) + #define RK0_B2_STB_MAX_MIN_DLY_RK0_B2_STBEN_MAX_DLY GENMASK(27, 16) +#define RK0_B3_STB_MAX_MIN_DLY 0x0000063c + #define RK0_B3_STB_MAX_MIN_DLY_RK0_B3_STBEN_MIN_DLY GENMASK(11, 0) + #define RK0_B3_STB_MAX_MIN_DLY_RK0_B3_STBEN_MAX_DLY GENMASK(27, 16) +#define RK0_DQSIENDLY 0x00000640 + #define RK0_DQSIENDLY_R0DQS0IENDLY GENMASK(6, 0) + #define RK0_DQSIENDLY_R0DQS1IENDLY GENMASK(14, 8) + #define RK0_DQSIENDLY_R0DQS2IENDLY GENMASK(22, 16) + #define RK0_DQSIENDLY_R0DQS3IENDLY GENMASK(30, 24) +#define RK0_DQSIENUIDLY 0x00000644 + #define RK0_DQSIENUIDLY_R0DQS0IENUIDLY GENMASK(5, 0) + #define RK0_DQSIENUIDLY_R0DQS1IENUIDLY GENMASK(13, 8) + #define RK0_DQSIENUIDLY_R0DQS2IENUIDLY GENMASK(21, 16) + #define RK0_DQSIENUIDLY_R0DQS3IENUIDLY GENMASK(29, 24) +#define RK0_DQSIENUIDLY_P1 0x00000648 + #define RK0_DQSIENUIDLY_P1_R0DQS0IENUIDLY_P1 GENMASK(5, 0) + #define RK0_DQSIENUIDLY_P1_R0DQS1IENUIDLY_P1 GENMASK(13, 8) + #define RK0_DQSIENUIDLY_P1_R0DQS2IENUIDLY_P1 GENMASK(21, 16) + #define RK0_DQSIENUIDLY_P1_R0DQS3IENUIDLY_P1 GENMASK(29, 24) +#define RK0_DQS_STBCALDEC_CNT1 0x00000650 + #define RK0_DQS_STBCALDEC_CNT1_RK0_DQS0_STBCALDEC_CNT GENMASK(15, 0) + #define RK0_DQS_STBCALDEC_CNT1_RK0_DQS1_STBCALDEC_CNT GENMASK(31, 16) +#define RK0_DQS_STBCALDEC_CNT2 0x00000654 + #define RK0_DQS_STBCALDEC_CNT2_RK0_DQS2_STBCALDEC_CNT GENMASK(15, 0) + #define RK0_DQS_STBCALDEC_CNT2_RK0_DQS3_STBCALDEC_CNT GENMASK(31, 16) +#define RK0_DQS_STBCALINC_CNT1 0x00000658 + #define RK0_DQS_STBCALINC_CNT1_RK0_DQS0_STBCALINC_CNT GENMASK(15, 0) + #define RK0_DQS_STBCALINC_CNT1_RK0_DQS1_STBCALINC_CNT GENMASK(31, 16) +#define RK0_DQS_STBCALINC_CNT2 0x0000065c + #define RK0_DQS_STBCALINC_CNT2_RK0_DQS2_STBCALINC_CNT GENMASK(15, 0) + #define RK0_DQS_STBCALINC_CNT2_RK0_DQS3_STBCALINC_CNT GENMASK(31, 16) +#define RK0_PI_DQ_CAL 0x00000660 + #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B0_CAL GENMASK(5, 0) + #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B1_CAL GENMASK(13, 8) + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0 GENMASK(21, 16) + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_OVERFLOW BIT(22) + #define RK0_PI_DQ_CAL_RK0_B0_PI_CHANGE_DBG BIT(23) + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1 GENMASK(29, 24) + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1_OVERFLOW BIT(30) + #define RK0_PI_DQ_CAL_RK0_B1_PI_CHANGE_DBG BIT(31) +#define RK0_DQSG_RETRY_FLAG 0x00000664 + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE0 BIT(0) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE1 BIT(1) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE2 BIT(2) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE3 BIT(3) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL0 BIT(16) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL1 BIT(17) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL2 BIT(18) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL3 BIT(19) +#define RK0_PI_DQM_CAL 0x00000668 + #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B0_CAL GENMASK(5, 0) + #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B1_CAL GENMASK(13, 8) +#define RK0_DQS0_STBCAL_CNT 0x00000670 + #define RK0_DQS0_STBCAL_CNT_R0_DQS0_STBCAL_CNT GENMASK(16, 0) +#define RK0_DQS1_STBCAL_CNT 0x00000674 + #define RK0_DQS1_STBCAL_CNT_R0_DQS1_STBCAL_CNT GENMASK(16, 0) +#define RK0_DQS2_STBCAL_CNT 0x00000678 + #define RK0_DQS2_STBCAL_CNT_R0_DQS2_STBCAL_CNT GENMASK(16, 0) +#define RK0_DQS3_STBCAL_CNT 0x0000067c + #define RK0_DQS3_STBCAL_CNT_R0_DQS3_STBCAL_CNT GENMASK(16, 0) +#define RK0_B01_STB_DBG_INFO_00 0x00000680 + #define RK0_B01_STB_DBG_INFO_00_RK0_B0_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_00_RK0_B1_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_01 0x00000684 + #define RK0_B01_STB_DBG_INFO_01_RK0_B0_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_01_RK0_B1_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_02 0x00000688 + #define RK0_B01_STB_DBG_INFO_02_RK0_B0_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_02_RK0_B1_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_03 0x0000068c + #define RK0_B01_STB_DBG_INFO_03_RK0_B0_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_03_RK0_B1_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_04 0x00000690 + #define RK0_B01_STB_DBG_INFO_04_RK0_B0_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_04_RK0_B1_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_05 0x00000694 + #define RK0_B01_STB_DBG_INFO_05_RK0_B0_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_05_RK0_B1_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_06 0x00000698 + #define RK0_B01_STB_DBG_INFO_06_RK0_B0_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_06_RK0_B1_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_07 0x0000069c + #define RK0_B01_STB_DBG_INFO_07_RK0_B0_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_07_RK0_B1_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_08 0x000006a0 + #define RK0_B01_STB_DBG_INFO_08_RK0_B0_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_08_RK0_B1_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_09 0x000006a4 + #define RK0_B01_STB_DBG_INFO_09_RK0_B0_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_09_RK0_B1_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_10 0x000006a8 + #define RK0_B01_STB_DBG_INFO_10_RK0_B0_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_10_RK0_B1_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_11 0x000006ac + #define RK0_B01_STB_DBG_INFO_11_RK0_B0_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_11_RK0_B1_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_12 0x000006b0 + #define RK0_B01_STB_DBG_INFO_12_RK0_B0_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_12_RK0_B1_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_13 0x000006b4 + #define RK0_B01_STB_DBG_INFO_13_RK0_B0_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_13_RK0_B1_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_14 0x000006b8 + #define RK0_B01_STB_DBG_INFO_14_RK0_B0_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_14_RK0_B1_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_15 0x000006bc + #define RK0_B01_STB_DBG_INFO_15_RK0_B0_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_15_RK0_B1_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_00 0x000006c0 + #define RK0_B23_STB_DBG_INFO_00_RK0_B2_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_00_RK0_B3_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_01 0x000006c4 + #define RK0_B23_STB_DBG_INFO_01_RK0_B2_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_01_RK0_B3_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_02 0x000006c8 + #define RK0_B23_STB_DBG_INFO_02_RK0_B2_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_02_RK0_B3_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_03 0x000006cc + #define RK0_B23_STB_DBG_INFO_03_RK0_B2_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_03_RK0_B3_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_04 0x000006d0 + #define RK0_B23_STB_DBG_INFO_04_RK0_B2_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_04_RK0_B3_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_05 0x000006d4 + #define RK0_B23_STB_DBG_INFO_05_RK0_B2_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_05_RK0_B3_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_06 0x000006d8 + #define RK0_B23_STB_DBG_INFO_06_RK0_B2_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_06_RK0_B3_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_07 0x000006dc + #define RK0_B23_STB_DBG_INFO_07_RK0_B2_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_07_RK0_B3_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_08 0x000006e0 + #define RK0_B23_STB_DBG_INFO_08_RK0_B2_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_08_RK0_B3_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_09 0x000006e4 + #define RK0_B23_STB_DBG_INFO_09_RK0_B2_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_09_RK0_B3_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_10 0x000006e8 + #define RK0_B23_STB_DBG_INFO_10_RK0_B2_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_10_RK0_B3_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_11 0x000006ec + #define RK0_B23_STB_DBG_INFO_11_RK0_B2_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_11_RK0_B3_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_12 0x000006f0 + #define RK0_B23_STB_DBG_INFO_12_RK0_B2_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_12_RK0_B3_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_13 0x000006f4 + #define RK0_B23_STB_DBG_INFO_13_RK0_B2_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_13_RK0_B3_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_14 0x000006f8 + #define RK0_B23_STB_DBG_INFO_14_RK0_B2_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_14_RK0_B3_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_15 0x000006fc + #define RK0_B23_STB_DBG_INFO_15_RK0_B2_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_15_RK0_B3_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK1_DQSOSC_STATUS 0x00000700 + #define RK1_DQSOSC_STATUS_MR18_REG_RK1 GENMASK(15, 0) + #define RK1_DQSOSC_STATUS_MR19_REG_RK1 GENMASK(31, 16) +#define RK1_DQSOSC_DELTA 0x00000704 + #define RK1_DQSOSC_DELTA_ABS_RK1_DQSOSC_DELTA GENMASK(15, 0) + #define RK1_DQSOSC_DELTA_SIGN_RK1_DQSOSC_DELTA BIT(16) + #define RK1_DQSOSC_DELTA_DQSOSCR_RK1_RESPONSE BIT(17) + #define RK1_DQSOSC_DELTA_H_DQSOSCLSBR_RK1_REQ BIT(18) + #define RK1_DQSOSC_DELTA_DQSOSC_INT_RK1 BIT(19) +#define RK1_DQSOSC_DELTA2 0x00000708 + #define RK1_DQSOSC_DELTA2_ABS_RK1_DQSOSC_B1_DELTA GENMASK(15, 0) + #define RK1_DQSOSC_DELTA2_SIGN_RK1_DQSOSC_B1_DELTA BIT(16) +#define RK1_CURRENT_TX_SETTING1 0x00000710 + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ0_MOD GENMASK(2, 0) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ1_MOD GENMASK(6, 4) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ2_MOD GENMASK(10, 8) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ3_MOD GENMASK(14, 12) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM0_MOD GENMASK(18, 16) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM1_MOD GENMASK(22, 20) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM2_MOD GENMASK(26, 24) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM3_MOD GENMASK(30, 28) +#define RK1_CURRENT_TX_SETTING2 0x00000714 + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ0_MOD GENMASK(2, 0) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ1_MOD GENMASK(6, 4) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ2_MOD GENMASK(10, 8) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ3_MOD GENMASK(14, 12) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM0_MOD GENMASK(18, 16) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM1_MOD GENMASK(22, 20) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM2_MOD GENMASK(26, 24) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM3_MOD GENMASK(30, 28) +#define RK1_CURRENT_TX_SETTING3 0x00000718 + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ0_MOD GENMASK(2, 0) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ1_MOD GENMASK(6, 4) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ2_MOD GENMASK(10, 8) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ3_MOD GENMASK(14, 12) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM0_MOD GENMASK(18, 16) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM1_MOD GENMASK(22, 20) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM2_MOD GENMASK(26, 24) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM3_MOD GENMASK(30, 28) +#define RK1_CURRENT_TX_SETTING4 0x0000071c + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ0_MOD GENMASK(2, 0) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ1_MOD GENMASK(6, 4) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ2_MOD GENMASK(10, 8) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ3_MOD GENMASK(14, 12) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM0_MOD GENMASK(18, 16) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM1_MOD GENMASK(22, 20) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM2_MOD GENMASK(26, 24) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM3_MOD GENMASK(30, 28) +#define RK1_DUMMY_RD_DATA0 0x00000720 + #define RK1_DUMMY_RD_DATA0_DUMMY_RD_RK1_DATA0 GENMASK(31, 0) +#define RK1_DUMMY_RD_DATA1 0x00000724 + #define RK1_DUMMY_RD_DATA1_DUMMY_RD_RK1_DATA1 GENMASK(31, 0) +#define RK1_DUMMY_RD_DATA2 0x00000728 + #define RK1_DUMMY_RD_DATA2_DUMMY_RD_RK1_DATA2 GENMASK(31, 0) +#define RK1_DUMMY_RD_DATA3 0x0000072c + #define RK1_DUMMY_RD_DATA3_DUMMY_RD_RK1_DATA3 GENMASK(31, 0) +#define RK1_B0_STB_MAX_MIN_DLY 0x00000730 + #define RK1_B0_STB_MAX_MIN_DLY_RK1_B0_STBEN_MIN_DLY GENMASK(11, 0) + #define RK1_B0_STB_MAX_MIN_DLY_RK1_B0_STBEN_MAX_DLY GENMASK(27, 16) +#define RK1_B1_STB_MAX_MIN_DLY 0x00000734 + #define RK1_B1_STB_MAX_MIN_DLY_RK1_B1_STBEN_MIN_DLY GENMASK(11, 0) + #define RK1_B1_STB_MAX_MIN_DLY_RK1_B1_STBEN_MAX_DLY GENMASK(27, 16) +#define RK1_B2_STB_MAX_MIN_DLY 0x00000738 + #define RK1_B2_STB_MAX_MIN_DLY_RK1_B2_STBEN_MIN_DLY GENMASK(11, 0) + #define RK1_B2_STB_MAX_MIN_DLY_RK1_B2_STBEN_MAX_DLY GENMASK(27, 16) +#define RK1_B3_STB_MAX_MIN_DLY 0x0000073c + #define RK1_B3_STB_MAX_MIN_DLY_RK1_B3_STBEN_MIN_DLY GENMASK(11, 0) + #define RK1_B3_STB_MAX_MIN_DLY_RK1_B3_STBEN_MAX_DLY GENMASK(27, 16) +#define RK1_DQSIENDLY 0x00000740 + #define RK1_DQSIENDLY_R1DQS0IENDLY GENMASK(6, 0) + #define RK1_DQSIENDLY_R1DQS1IENDLY GENMASK(14, 8) + #define RK1_DQSIENDLY_R1DQS2IENDLY GENMASK(22, 16) + #define RK1_DQSIENDLY_R1DQS3IENDLY GENMASK(30, 24) +#define RK1_DQSIENUIDLY 0x00000744 + #define RK1_DQSIENUIDLY_R1DQS0IENUIDLY GENMASK(5, 0) + #define RK1_DQSIENUIDLY_R1DQS1IENUIDLY GENMASK(13, 8) + #define RK1_DQSIENUIDLY_R1DQS2IENUIDLY GENMASK(21, 16) + #define RK1_DQSIENUIDLY_R1DQS3IENUIDLY GENMASK(29, 24) +#define RK1_DQSIENUIDLY_P1 0x00000748 + #define RK1_DQSIENUIDLY_P1_R1DQS0IENUIDLY_P1 GENMASK(5, 0) + #define RK1_DQSIENUIDLY_P1_R1DQS1IENUIDLY_P1 GENMASK(13, 8) + #define RK1_DQSIENUIDLY_P1_R1DQS2IENUIDLY_P1 GENMASK(21, 16) + #define RK1_DQSIENUIDLY_P1_R1DQS3IENUIDLY_P1 GENMASK(29, 24) +#define RK1_DQS_STBCALDEC_CNT1 0x00000750 + #define RK1_DQS_STBCALDEC_CNT1_RK1_DQS0_STBCALDEC_CNT GENMASK(15, 0) + #define RK1_DQS_STBCALDEC_CNT1_RK1_DQS1_STBCALDEC_CNT GENMASK(31, 16) +#define RK1_DQS_STBCALDEC_CNT2 0x00000754 + #define RK1_DQS_STBCALDEC_CNT2_RK1_DQS2_STBCALDEC_CNT GENMASK(15, 0) + #define RK1_DQS_STBCALDEC_CNT2_RK1_DQS3_STBCALDEC_CNT GENMASK(31, 16) +#define RK1_DQS_STBCALINC_CNT1 0x00000758 + #define RK1_DQS_STBCALINC_CNT1_RK1_DQS0_STBCALINC_CNT GENMASK(15, 0) + #define RK1_DQS_STBCALINC_CNT1_RK1_DQS1_STBCALINC_CNT GENMASK(31, 16) +#define RK1_DQS_STBCALINC_CNT2 0x0000075c + #define RK1_DQS_STBCALINC_CNT2_RK1_DQS2_STBCALINC_CNT GENMASK(15, 0) + #define RK1_DQS_STBCALINC_CNT2_RK1_DQS3_STBCALINC_CNT GENMASK(31, 16) +#define RK1_PI_DQ_CAL 0x00000760 + #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B0_CAL GENMASK(5, 0) + #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B1_CAL GENMASK(13, 8) + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1 GENMASK(21, 16) + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_FLOW BIT(22) + #define RK1_PI_DQ_CAL_RK1_B0_PI_CHANGE_DBG BIT(23) + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1 GENMASK(29, 24) + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1_FLOW BIT(30) + #define RK1_PI_DQ_CAL_RK1_B1_PI_CHANGE_DBG BIT(31) +#define RK1_DQSG_RETRY_FLAG 0x00000764 + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE0 BIT(0) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE1 BIT(1) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE2 BIT(2) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE3 BIT(3) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL0 BIT(16) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL1 BIT(17) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL2 BIT(18) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL3 BIT(19) +#define RK1_PI_DQM_CAL 0x00000768 + #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B0_CAL GENMASK(5, 0) + #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B1_CAL GENMASK(13, 8) +#define RK1_DQS0_STBCAL_CNT 0x00000770 + #define RK1_DQS0_STBCAL_CNT_R1_DQS0_STBCAL_CNT GENMASK(16, 0) +#define RK1_DQS1_STBCAL_CNT 0x00000774 + #define RK1_DQS1_STBCAL_CNT_R1_DQS1_STBCAL_CNT GENMASK(16, 0) +#define RK1_DQS2_STBCAL_CNT 0x00000778 + #define RK1_DQS2_STBCAL_CNT_R1_DQS2_STBCAL_CNT GENMASK(16, 0) +#define RK1_DQS3_STBCAL_CNT 0x0000077c + #define RK1_DQS3_STBCAL_CNT_R1_DQS3_STBCAL_CNT GENMASK(16, 0) +#define RK1_B01_STB_DBG_INFO_00 0x00000780 + #define RK1_B01_STB_DBG_INFO_00_RK1_B0_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_00_RK1_B1_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_01 0x00000784 + #define RK1_B01_STB_DBG_INFO_01_RK1_B0_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_01_RK1_B1_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_02 0x00000788 + #define RK1_B01_STB_DBG_INFO_02_RK1_B0_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_02_RK1_B1_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_03 0x0000078c + #define RK1_B01_STB_DBG_INFO_03_RK1_B0_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_03_RK1_B1_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_04 0x00000790 + #define RK1_B01_STB_DBG_INFO_04_RK1_B0_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_04_RK1_B1_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_05 0x00000794 + #define RK1_B01_STB_DBG_INFO_05_RK1_B0_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_05_RK1_B1_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_06 0x00000798 + #define RK1_B01_STB_DBG_INFO_06_RK1_B0_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_06_RK1_B1_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_07 0x0000079c + #define RK1_B01_STB_DBG_INFO_07_RK1_B0_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_07_RK1_B1_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_08 0x000007a0 + #define RK1_B01_STB_DBG_INFO_08_RK1_B0_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_08_RK1_B1_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_09 0x000007a4 + #define RK1_B01_STB_DBG_INFO_09_RK1_B0_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_09_RK1_B1_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_10 0x000007a8 + #define RK1_B01_STB_DBG_INFO_10_RK1_B0_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_10_RK1_B1_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_11 0x000007ac + #define RK1_B01_STB_DBG_INFO_11_RK1_B0_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_11_RK1_B1_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_12 0x000007b0 + #define RK1_B01_STB_DBG_INFO_12_RK1_B0_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_12_RK1_B1_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_13 0x000007b4 + #define RK1_B01_STB_DBG_INFO_13_RK1_B0_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_13_RK1_B1_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_14 0x000007b8 + #define RK1_B01_STB_DBG_INFO_14_RK1_B0_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_14_RK1_B1_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_15 0x000007bc + #define RK1_B01_STB_DBG_INFO_15_RK1_B0_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_15_RK1_B1_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_00 0x000007c0 + #define RK1_B23_STB_DBG_INFO_00_RK1_B2_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_00_RK1_B3_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_01 0x000007c4 + #define RK1_B23_STB_DBG_INFO_01_RK1_B2_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_01_RK1_B3_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_02 0x000007c8 + #define RK1_B23_STB_DBG_INFO_02_RK1_B2_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_02_RK1_B3_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_03 0x000007cc + #define RK1_B23_STB_DBG_INFO_03_RK1_B2_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_03_RK1_B3_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_04 0x000007d0 + #define RK1_B23_STB_DBG_INFO_04_RK1_B2_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_04_RK1_B3_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_05 0x000007d4 + #define RK1_B23_STB_DBG_INFO_05_RK1_B2_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_05_RK1_B3_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_06 0x000007d8 + #define RK1_B23_STB_DBG_INFO_06_RK1_B2_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_06_RK1_B3_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_07 0x000007dc + #define RK1_B23_STB_DBG_INFO_07_RK1_B2_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_07_RK1_B3_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_08 0x000007e0 + #define RK1_B23_STB_DBG_INFO_08_RK1_B2_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_08_RK1_B3_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_09 0x000007e4 + #define RK1_B23_STB_DBG_INFO_09_RK1_B2_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_09_RK1_B3_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_10 0x000007e8 + #define RK1_B23_STB_DBG_INFO_10_RK1_B2_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_10_RK1_B3_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_11 0x000007ec + #define RK1_B23_STB_DBG_INFO_11_RK1_B2_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_11_RK1_B3_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_12 0x000007f0 + #define RK1_B23_STB_DBG_INFO_12_RK1_B2_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_12_RK1_B3_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_13 0x000007f4 + #define RK1_B23_STB_DBG_INFO_13_RK1_B2_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_13_RK1_B3_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_14 0x000007f8 + #define RK1_B23_STB_DBG_INFO_14_RK1_B2_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_14_RK1_B3_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_15 0x000007fc + #define RK1_B23_STB_DBG_INFO_15_RK1_B2_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_15_RK1_B3_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK2_DQSOSC_STATUS 0x00000800 + #define RK2_DQSOSC_STATUS_MR18_REG_RK2 GENMASK(15, 0) + #define RK2_DQSOSC_STATUS_MR19_REG_RK2 GENMASK(31, 16) +#define RK2_DQSOSC_DELTA 0x00000804 + #define RK2_DQSOSC_DELTA_ABS_RK2_DQSOSC_DELTA GENMASK(15, 0) + #define RK2_DQSOSC_DELTA_SIGN_RK2_DQSOSC_DELTA BIT(16) + #define RK2_DQSOSC_DELTA_DQSOSCR_RK2_RESPONSE BIT(17) + #define RK2_DQSOSC_DELTA_H_DQSOSCLSBR_RK2_REQ BIT(18) + #define RK2_DQSOSC_DELTA_DQSOSC_INT_RK2 BIT(19) +#define RK2_DQSOSC_DELTA2 0x00000808 + #define RK2_DQSOSC_DELTA2_ABS_RK2_DQSOSC_B1_DELTA GENMASK(15, 0) + #define RK2_DQSOSC_DELTA2_SIGN_RK2_DQSOSC_B1_DELTA BIT(16) +#define RK2_CURRENT_TX_SETTING1 0x00000810 + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ0_MOD GENMASK(2, 0) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ1_MOD GENMASK(6, 4) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ2_MOD GENMASK(10, 8) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ3_MOD GENMASK(14, 12) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM0_MOD GENMASK(18, 16) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM1_MOD GENMASK(22, 20) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM2_MOD GENMASK(26, 24) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM3_MOD GENMASK(30, 28) +#define RK2_CURRENT_TX_SETTING2 0x00000814 + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ0_MOD GENMASK(2, 0) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ1_MOD GENMASK(6, 4) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ2_MOD GENMASK(10, 8) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ3_MOD GENMASK(14, 12) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM0_MOD GENMASK(18, 16) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM1_MOD GENMASK(22, 20) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM2_MOD GENMASK(26, 24) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM3_MOD GENMASK(30, 28) +#define RK2_CURRENT_TX_SETTING3 0x00000818 + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ0_MOD GENMASK(2, 0) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ1_MOD GENMASK(6, 4) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ2_MOD GENMASK(10, 8) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ3_MOD GENMASK(14, 12) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM0_MOD GENMASK(18, 16) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM1_MOD GENMASK(22, 20) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM2_MOD GENMASK(26, 24) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM3_MOD GENMASK(30, 28) +#define RK2_CURRENT_TX_SETTING4 0x0000081c + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ0_MOD GENMASK(2, 0) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ1_MOD GENMASK(6, 4) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ2_MOD GENMASK(10, 8) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ3_MOD GENMASK(14, 12) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM0_MOD GENMASK(18, 16) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM1_MOD GENMASK(22, 20) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM2_MOD GENMASK(26, 24) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM3_MOD GENMASK(30, 28) +#define RK2_DUMMY_RD_DATA0 0x00000820 + #define RK2_DUMMY_RD_DATA0_DUMMY_RD_RK2_DATA0 GENMASK(31, 0) +#define RK2_DUMMY_RD_DATA1 0x00000824 + #define RK2_DUMMY_RD_DATA1_DUMMY_RD_RK2_DATA1 GENMASK(31, 0) +#define RK2_DUMMY_RD_DATA2 0x00000828 + #define RK2_DUMMY_RD_DATA2_DUMMY_RD_RK2_DATA2 GENMASK(31, 0) +#define RK2_DUMMY_RD_DATA3 0x0000082c + #define RK2_DUMMY_RD_DATA3_DUMMY_RD_RK2_DATA3 GENMASK(31, 0) +#define RK2_B0_STB_MAX_MIN_DLY 0x00000830 + #define RK2_B0_STB_MAX_MIN_DLY_RK2_B0_STBEN_MIN_DLY GENMASK(11, 0) + #define RK2_B0_STB_MAX_MIN_DLY_RK2_B0_STBEN_MAX_DLY GENMASK(27, 16) +#define RK2_B1_STB_MAX_MIN_DLY 0x00000834 + #define RK2_B1_STB_MAX_MIN_DLY_RK2_B1_STBEN_MIN_DLY GENMASK(11, 0) + #define RK2_B1_STB_MAX_MIN_DLY_RK2_B1_STBEN_MAX_DLY GENMASK(27, 16) +#define RK2_B2_STB_MAX_MIN_DLY 0x00000838 + #define RK2_B2_STB_MAX_MIN_DLY_RK2_B2_STBEN_MIN_DLY GENMASK(11, 0) + #define RK2_B2_STB_MAX_MIN_DLY_RK2_B2_STBEN_MAX_DLY GENMASK(27, 16) +#define RK2_B3_STB_MAX_MIN_DLY 0x0000083c + #define RK2_B3_STB_MAX_MIN_DLY_RK2_B3_STBEN_MIN_DLY GENMASK(11, 0) + #define RK2_B3_STB_MAX_MIN_DLY_RK2_B3_STBEN_MAX_DLY GENMASK(27, 16) +#define RK2_DQSIENDLY 0x00000840 + #define RK2_DQSIENDLY_R2DQS0IENDLY GENMASK(6, 0) + #define RK2_DQSIENDLY_R2DQS1IENDLY GENMASK(14, 8) + #define RK2_DQSIENDLY_R2DQS2IENDLY GENMASK(22, 16) + #define RK2_DQSIENDLY_R2DQS3IENDLY GENMASK(30, 24) +#define RK2_DQSIENUIDLY 0x00000844 + #define RK2_DQSIENUIDLY_R2DQS0IENUIDLY GENMASK(5, 0) + #define RK2_DQSIENUIDLY_R2DQS1IENUIDLY GENMASK(13, 8) + #define RK2_DQSIENUIDLY_R2DQS2IENUIDLY GENMASK(21, 16) + #define RK2_DQSIENUIDLY_R2DQS3IENUIDLY GENMASK(29, 24) +#define RK2_DQSIENUIDLY_P1 0x00000848 + #define RK2_DQSIENUIDLY_P1_R2DQS0IENUIDLY_P1 GENMASK(5, 0) + #define RK2_DQSIENUIDLY_P1_R2DQS1IENUIDLY_P1 GENMASK(13, 8) + #define RK2_DQSIENUIDLY_P1_R2DQS2IENUIDLY_P1 GENMASK(21, 16) + #define RK2_DQSIENUIDLY_P1_R2DQS3IENUIDLY_P1 GENMASK(29, 24) +#define RK2_DQS_STBCALDEC_CNT1 0x00000850 + #define RK2_DQS_STBCALDEC_CNT1_RK2_DQS0_STBCALDEC_CNT GENMASK(15, 0) + #define RK2_DQS_STBCALDEC_CNT1_RK2_DQS1_STBCALDEC_CNT GENMASK(31, 16) +#define RK2_DQS_STBCALDEC_CNT2 0x00000854 + #define RK2_DQS_STBCALDEC_CNT2_RK2_DQS2_STBCALDEC_CNT GENMASK(15, 0) + #define RK2_DQS_STBCALDEC_CNT2_RK2_DQS3_STBCALDEC_CNT GENMASK(31, 16) +#define RK2_DQS_STBCALINC_CNT1 0x00000858 + #define RK2_DQS_STBCALINC_CNT1_RK2_DQS0_STBCALINC_CNT GENMASK(15, 0) + #define RK2_DQS_STBCALINC_CNT1_RK2_DQS1_STBCALINC_CNT GENMASK(31, 16) +#define RK2_DQS_STBCALINC_CNT2 0x0000085c + #define RK2_DQS_STBCALINC_CNT2_RK2_DQS2_STBCALINC_CNT GENMASK(15, 0) + #define RK2_DQS_STBCALINC_CNT2_RK2_DQS3_STBCALINC_CNT GENMASK(31, 16) +#define RK2_PI_DQ_CAL 0x00000860 + #define RK2_PI_DQ_CAL_RK2_ARPI_DQ_B0_CAL GENMASK(5, 0) + #define RK2_PI_DQ_CAL_RK2_ARPI_DQ_B1_CAL GENMASK(13, 8) + #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2 GENMASK(21, 16) + #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_OVERFLOW BIT(22) + #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_B1 GENMASK(29, 24) + #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_B1_OVERFLOW BIT(30) +#define RK2_DQSG_RETRY_FLAG 0x00000864 + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE0 BIT(0) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE1 BIT(1) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE2 BIT(2) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE3 BIT(3) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL0 BIT(16) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL1 BIT(17) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL2 BIT(18) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL3 BIT(19) +#define RK2_PI_DQM_CAL 0x00000868 + #define RK2_PI_DQM_CAL_RK2_ARPI_DQM_B0_CAL GENMASK(5, 0) + #define RK2_PI_DQM_CAL_RK2_ARPI_DQM_B1_CAL GENMASK(13, 8) +#define RK2_DQS0_STBCAL_CNT 0x00000870 + #define RK2_DQS0_STBCAL_CNT_R2_DQS0_STBCAL_CNT GENMASK(16, 0) +#define RK2_DQS1_STBCAL_CNT 0x00000874 + #define RK2_DQS1_STBCAL_CNT_R2_DQS1_STBCAL_CNT GENMASK(16, 0) +#define RK2_DQS2_STBCAL_CNT 0x00000878 + #define RK2_DQS2_STBCAL_CNT_R2_DQS2_STBCAL_CNT GENMASK(16, 0) +#define RK2_DQS3_STBCAL_CNT 0x0000087c + #define RK2_DQS3_STBCAL_CNT_R2_DQS3_STBCAL_CNT GENMASK(16, 0) +#define RK2_B01_STB_DBG_INFO_00 0x00000880 + #define RK2_B01_STB_DBG_INFO_00_RK2_B0_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_00_RK2_B1_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_01 0x00000884 + #define RK2_B01_STB_DBG_INFO_01_RK2_B0_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_01_RK2_B1_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_02 0x00000888 + #define RK2_B01_STB_DBG_INFO_02_RK2_B0_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_02_RK2_B1_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_03 0x0000088c + #define RK2_B01_STB_DBG_INFO_03_RK2_B0_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_03_RK2_B1_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_04 0x00000890 + #define RK2_B01_STB_DBG_INFO_04_RK2_B0_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_04_RK2_B1_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_05 0x00000894 + #define RK2_B01_STB_DBG_INFO_05_RK2_B0_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_05_RK2_B1_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_06 0x00000898 + #define RK2_B01_STB_DBG_INFO_06_RK2_B0_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_06_RK2_B1_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_07 0x0000089c + #define RK2_B01_STB_DBG_INFO_07_RK2_B0_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_07_RK2_B1_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_08 0x000008a0 + #define RK2_B01_STB_DBG_INFO_08_RK2_B0_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_08_RK2_B1_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_09 0x000008a4 + #define RK2_B01_STB_DBG_INFO_09_RK2_B0_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_09_RK2_B1_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_10 0x000008a8 + #define RK2_B01_STB_DBG_INFO_10_RK2_B0_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_10_RK2_B1_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_11 0x000008ac + #define RK2_B01_STB_DBG_INFO_11_RK2_B0_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_11_RK2_B1_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_12 0x000008b0 + #define RK2_B01_STB_DBG_INFO_12_RK2_B0_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_12_RK2_B1_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_13 0x000008b4 + #define RK2_B01_STB_DBG_INFO_13_RK2_B0_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_13_RK2_B1_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_14 0x000008b8 + #define RK2_B01_STB_DBG_INFO_14_RK2_B0_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_14_RK2_B1_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_15 0x000008bc + #define RK2_B01_STB_DBG_INFO_15_RK2_B0_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_15_RK2_B1_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_00 0x000008c0 + #define RK2_B23_STB_DBG_INFO_00_RK2_B2_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_00_RK2_B3_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_01 0x000008c4 + #define RK2_B23_STB_DBG_INFO_01_RK2_B2_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_01_RK2_B3_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_02 0x000008c8 + #define RK2_B23_STB_DBG_INFO_02_RK2_B2_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_02_RK2_B3_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_03 0x000008cc + #define RK2_B23_STB_DBG_INFO_03_RK2_B2_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_03_RK2_B3_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_04 0x000008d0 + #define RK2_B23_STB_DBG_INFO_04_RK2_B2_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_04_RK2_B3_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_05 0x000008d4 + #define RK2_B23_STB_DBG_INFO_05_RK2_B2_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_05_RK2_B3_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_06 0x000008d8 + #define RK2_B23_STB_DBG_INFO_06_RK2_B2_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_06_RK2_B3_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_07 0x000008dc + #define RK2_B23_STB_DBG_INFO_07_RK2_B2_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_07_RK2_B3_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_08 0x000008e0 + #define RK2_B23_STB_DBG_INFO_08_RK2_B2_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_08_RK2_B3_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_09 0x000008e4 + #define RK2_B23_STB_DBG_INFO_09_RK2_B2_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_09_RK2_B3_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_10 0x000008e8 + #define RK2_B23_STB_DBG_INFO_10_RK2_B2_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_10_RK2_B3_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_11 0x000008ec + #define RK2_B23_STB_DBG_INFO_11_RK2_B2_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_11_RK2_B3_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_12 0x000008f0 + #define RK2_B23_STB_DBG_INFO_12_RK2_B2_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_12_RK2_B3_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_13 0x000008f4 + #define RK2_B23_STB_DBG_INFO_13_RK2_B2_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_13_RK2_B3_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_14 0x000008f8 + #define RK2_B23_STB_DBG_INFO_14_RK2_B2_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_14_RK2_B3_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_15 0x000008fc + #define RK2_B23_STB_DBG_INFO_15_RK2_B2_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_15_RK2_B3_STB_DBG_INFO_15 GENMASK(31, 16) +#define DVFS_DBG0 0x00000c00 + #define DVFS_DBG0_CUT_PHY_ST_SHU_MASK GENMASK(18, 0) +#define DVFS_DBG1 0x00000c04 + #define DVFS_DBG1_PLL_SEL_MASK BIT(0) + #define DVFS_DBG1_MPDIV_SHU_GP_MASK GENMASK(6, 4) + #define DVFS_DBG1_PICG_SHUFFLE_MASK BIT(8) + #define DVFS_DBG1_SHUFFLE_PHY_STATE_START_MASK BIT(9) + #define DVFS_DBG1_SHUFFLE_PHY_STATE_DONE_MASK BIT(10) + #define DVFS_DBG1_SHUFFLE_PERIOD_MASK BIT(11) + +#endif /*__DRAMC_CH0_NAO_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h b/src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h new file mode 100644 index 0000000000..4e9eae40e9 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h @@ -0,0 +1,3922 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_CH0_REG_H__ +#define __DRAMC_CH0_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define DDRCONF0 0x00000000 + #define DDRCONF0_RDATRST BIT(0) + #define DDRCONF0_DMSW_RST BIT(1) + #define DDRCONF0_WDT_DBG_RST BIT(2) + #define DDRCONF0_FIFOLEN GENMASK(5, 4) + #define DDRCONF0_DRAMEN BIT(7) + #define DDRCONF0_RDQSIEN BIT(8) + #define DDRCONF0_DQSGCGM BIT(9) + #define DDRCONF0_APBL2 BIT(10) + #define DDRCONF0_BG4EN BIT(11) + #define DDRCONF0_BK8EN BIT(12) + #define DDRCONF0_BC4OTF_OPT BIT(13) + #define DDRCONF0_AG0MWR BIT(14) + #define DDRCONF0_BC4OTF BIT(15) + #define DDRCONF0_GDDR3RST BIT(16) + #define DDRCONF0_DM16BPHSEL BIT(17) + #define DDRCONF0_DM16BITSWAP BIT(18) + #define DDRCONF0_DQ4BMUX BIT(19) + #define DDRCONF0_DM64BITEN BIT(20) + #define DDRCONF0_DM16BITFULL BIT(21) + #define DDRCONF0_DM4TO1MODE BIT(22) + #define DDRCONF0_GDDR3EN BIT(23) + #define DDRCONF0_LPDDR2EN BIT(24) + #define DDRCONF0_LPDDR3EN BIT(25) + #define DDRCONF0_LPDDR4EN BIT(26) + #define DDRCONF0_LPDDR2_NO_INT BIT(27) + #define DDRCONF0_DDR2EN BIT(28) + #define DDRCONF0_DDR3EN BIT(29) + #define DDRCONF0_DDR4EN BIT(30) + #define DDRCONF0_DRAMC_SW_RST BIT(31) +#define DRAMCTRL 0x00000004 + #define DRAMCTRL_CTOREQ_HPRI_OPT BIT(0) + #define DRAMCTRL_ADRDECEN_TARKMODE BIT(1) + #define DRAMCTRL_ADRDECEN BIT(2) + #define DRAMCTRL_ADRBIT3DEC BIT(3) + #define DRAMCTRL_TMRR2WDIS BIT(4) + #define DRAMCTRL_RANK_ASYM BIT(7) + #define DRAMCTRL_WDATRGO BIT(8) + #define DRAMCTRL_CLKWITRFC BIT(9) + #define DRAMCTRL_CHKFORPRE BIT(10) + #define DRAMCTRL_ASYNCEN BIT(12) + #define DRAMCTRL_DYNMWREN BIT(13) + #define DRAMCTRL_ALEBLOCK BIT(14) + #define DRAMCTRL_TMRRICHKDIS BIT(15) + #define DRAMCTRL_DMRCDRSV BIT(16) + #define DRAMCTRL_TMRRIBYRK_DIS BIT(17) + #define DRAMCTRL_ZQCALL BIT(18) + #define DRAMCTRL_PREALL_OPTION BIT(19) + #define DRAMCTRL_TCMD GENMASK(22, 20) + #define DRAMCTRL_MRRIOPT BIT(23) + #define DRAMCTRL_FW2R BIT(24) + #define DRAMCTRL_REQQUE_DEPTH_UPD BIT(25) + #define DRAMCTRL_REQQUE_THD_EN BIT(26) + #define DRAMCTRL_REQQUE_MAXCNT_CHG BIT(27) + #define DRAMCTRL_PREA_RK GENMASK(29, 28) + #define DRAMCTRL_IDLE_COND_OPT BIT(30) +#define MISCTL0 0x00000008 + #define MISCTL0_R_DMCA_IDLE_EN BIT(0) + #define MISCTL0_IDLE_CNT_OPT BIT(16) + #define MISCTL0_PAGDIS BIT(17) + #define MISCTL0_IDLEDCM_CNT_OPT BIT(18) + #define MISCTL0_REFA_ARB_EN2 BIT(19) + #define MISCTL0_WRBYTE_CNT_OPT BIT(20) + #define MISCTL0_REFA_ARB_EN_OPTION BIT(21) + #define MISCTL0_REORDER_MASK_E1T BIT(22) + #define MISCTL0_PBC_ARB_E1T BIT(23) + #define MISCTL0_PBC_ARB_EN BIT(24) + #define MISCTL0_REFA_ARB_EN BIT(25) + #define MISCTL0_REFP_ARB_EN BIT(26) + #define MISCTL0_EMIPREEN BIT(27) + #define MISCTL0_REFP_ARB_EN2 BIT(31) +#define PERFCTL0 0x0000000c + #define PERFCTL0_DUALSCHEN BIT(0) + #define PERFCTL0_DISRDPHASE1 BIT(1) + #define PERFCTL0_XRT_05T_OPT BIT(2) + #define PERFCTL0_AIDCHKEN BIT(3) + #define PERFCTL0_RWOFOEN BIT(4) + #define PERFCTL0_RWOFOWNUM GENMASK(7, 5) + #define PERFCTL0_RWHPRIEN BIT(8) + #define PERFCTL0_RWLLATEN BIT(9) + #define PERFCTL0_RWAGEEN BIT(10) + #define PERFCTL0_EMILLATEN BIT(11) + #define PERFCTL0_LASTCMDOPT BIT(12) + #define PERFCTL0_RWHPRICTL BIT(13) + #define PERFCTL0_WFLUSHEN BIT(14) + #define PERFCTL0_RWSPLIT BIT(15) + #define PERFCTL0_MWHPRIEN BIT(17) + #define PERFCTL0_REORDER_MODE BIT(18) + #define PERFCTL0_REORDEREN BIT(19) + #define PERFCTL0_SBR_MASK_OPT BIT(20) + #define PERFCTL0_SBR_MASK_OPT2 BIT(21) + #define PERFCTL0_MAFIXHIGH BIT(22) + #define PERFCTL0_TESTWRHIGH BIT(23) + #define PERFCTL0_RECORDER_MASK_OPT BIT(24) + #define PERFCTL0_MDMCU_MASK_EN BIT(25) + #define PERFCTL0_WRFIFO_OPT BIT(26) + #define PERFCTL0_WRFIO_MODE2 BIT(27) + #define PERFCTL0_RDFIFOEN BIT(30) + #define PERFCTL0_WRFIFOEN BIT(31) +#define ARBCTL 0x00000010 + #define ARBCTL_MAXPENDCNT GENMASK(7, 0) + #define ARBCTL_RDATACNTDIS BIT(8) + #define ARBCTL_WDATACNTDIS BIT(9) + #define ARBCTL_RSV_SA0 BIT(10) + #define ARBCTL_RSV_SA1 BIT(11) + #define ARBCTL_RSV_SA2 BIT(12) + #define ARBCTL_RSV_SA3 BIT(13) + #define ARBCTL_RSV_DRAM_CBT BIT(13) //cc add + #define ARBCTL_RSV_DRAM_TYPE GENMASK(12, 10)//cc add + #define ARBCTL_DBIWR_IMP_EN BIT(14) + #define ARBCTL_DBIWR_PINMUX_EN BIT(15) + #define ARBCTL_DBIWR_OPT_B0 GENMASK(23, 16) + #define ARBCTL_DBIWR_OPT_bit1_0 GENMASK(17, 16)//cc add + #define ARBCTL_DBIWR_OPT_bit7 GENMASK(23, 23)//cc add + #define ARBCTL_DBIWR_OPT_B1 GENMASK(31, 24) + #define ARBCTL_DBIWR_OPT_bit9_8 GENMASK(25, 24)//cc add + #define ARBCTL_DBIWR_OPT_bit15 GENMASK(31, 31)//cc add +#define RSTMASK 0x0000001c + #define RSTMASK_WDATKEY0 BIT(0) + #define RSTMASK_WDATKEY1 BIT(1) + #define RSTMASK_WDATKEY2 BIT(2) + #define RSTMASK_WDATKEY3 BIT(3) + #define RSTMASK_WDATKEY4 BIT(4) + #define RSTMASK_WDATKEY5 BIT(5) + #define RSTMASK_WDATKEY6 BIT(6) + #define RSTMASK_WDATKEY7 BIT(7) + #define RSTMASK_WDATITLV BIT(8) + #define RSTMASK_RSV_SA_BU2 GENMASK(15, 12) //cc add + #define RSTMASK_RSV_DRAM_CBT_MIXED GENMASK(14, 13) //cc add + #define RSTMASK_RSV_DRAM_SUPPORT_RANK_NUM BIT(12) //cc add + #define RSTMASK_RETRY_DATRST_MASK BIT(21) + #define RSTMASK_DVFS_SYNC_MASK_FOR_PHY BIT(24) + #define RSTMASK_GT_SYNC_MASK_FOR_PHY BIT(25) + #define RSTMASK_DVFS_SYNC_MASK BIT(26) + #define RSTMASK_GTDMW_SYNC_MASK BIT(27) + #define RSTMASK_GT_SYNC_MASK BIT(28) + #define RSTMASK_DAT_SYNC_MASK BIT(29) + #define RSTMASK_PHY_SYNC_MASK BIT(30) + #define RSTMASK_R_DMSHU_RDATRST_MASK BIT(31) +#define PADCTRL 0x00000020 + #define PADCTRL_DQIENQKEND GENMASK(1, 0) + #define PADCTRL_DQIENLATEBEGIN BIT(3) + #define PADCTRL_DISDMOEDIS BIT(8) + #define PADCTRL_DRAMOEN BIT(12) + #define PADCTRL_FIXDQIEN GENMASK(19, 16) + #define PADCTRL_DISDQIEN GENMASK(23, 20) + #define PADCTRL_PINMUX GENMASK(30, 28) +#define CKECTRL 0x00000024 + #define CKECTRL_CKEBYCTL BIT(0) + #define CKECTRL_CKE2RANK_OPT3 BIT(1) + #define CKECTRL_CKE2FIXON BIT(2) + #define CKECTRL_CKE2FIXOFF BIT(3) + #define CKECTRL_CKE1FIXON BIT(4) + #define CKECTRL_CKE1FIXOFF BIT(5) + #define CKECTRL_CKEFIXON BIT(6) + #define CKECTRL_CKEFIXOFF BIT(7) + #define CKECTRL_CKE2RANK_OPT5 BIT(8) + #define CKECTRL_CKE2RANK_OPT6 BIT(9) + #define CKECTRL_CKE2RANK_OPT7 BIT(10) + #define CKECTRL_CKE2RANK_OPT8 BIT(11) + #define CKECTRL_CKEEXTEND BIT(12) + #define CKECTRL_CKETIMER_SEL BIT(13) + #define CKECTRL_FASTWAKE_SEL BIT(14) + #define CKECTRL_CKEWAKE_SEL BIT(15) + #define CKECTRL_CKEWAKE_SEL2 BIT(16) + #define CKECTRL_CKE2RANK_OPT9 BIT(17) + #define CKECTRL_CKE2RANK_OPT10 BIT(18) + #define CKECTRL_CKE2RANK_OPT11 BIT(19) + #define CKECTRL_CKE2RANK_OPT12 BIT(20) + #define CKECTRL_CKE2RANK_OPT13 BIT(21) + #define CKECTRL_CKEPBDIS BIT(22) + #define CKECTRL_CKELCKFIX BIT(23) + #define CKECTRL_CKELCKCNT GENMASK(26, 24) + #define CKECTRL_RUNTIMEMRRCKEFIX BIT(27) + #define CKECTRL_RUNTIMEMRRMIODIS BIT(28) + #define CKECTRL_CKE_H2L_OPT BIT(29) + #define CKECTRL_CKEON BIT(31) +#define DRSCTRL 0x00000028 + #define DRSCTRL_DRSDIS BIT(0) + #define DRSCTRL_DRSBLOCKOPT BIT(1) + #define DRSCTRL_DRSPB2AB_OPT BIT(2) + #define DRSCTRL_DRSRK1_SW BIT(3) + #define DRSCTRL_DRSMON_CLR BIT(4) + #define DRSCTRL_DRSCLR_EN BIT(5) + #define DRSCTRL_DRSACKWAITREF BIT(6) + #define DRSCTRL_DRSCLR_RK0_EN BIT(7) + #define DRSCTRL_DRSDLY GENMASK(11, 8) + #define DRSCTRL_DRS_CNTX GENMASK(18, 12) + #define DRSCTRL_DRS_SELFWAKE_DMYRD_DIS BIT(19) + #define DRSCTRL_DRS_DMYRD_MIOCK_OPT BIT(20) + #define DRSCTRL_DRSOPT2 BIT(21) + #define DRSCTRL_DRS_MR4_OPT_B BIT(24) + #define DRSCTRL_RK_SCINPUT_OPT BIT(29) +#define RKCFG 0x00000034 + #define RKCFG_TXRANK GENMASK(1, 0) + #define RKCFG_CKE2RANK_OPT2 BIT(2) + #define RKCFG_TXRANKFIX BIT(3) + #define RKCFG_RKMODE GENMASK(6, 4) + #define RKCFG_RKSWAP BIT(7) + #define RKCFG_DM3RANK BIT(8) + #define RKCFG_RANKRDY_OPT BIT(9) + #define RKCFG_MRS2RK BIT(10) + #define RKCFG_DQSOSC2RK BIT(11) + #define RKCFG_CKE2RANK BIT(12) + #define RKCFG_CS2RANK BIT(13) + #define RKCFG_SHU2RKOPT BIT(14) + #define RKCFG_CKE2RANK_OPT BIT(15) + #define RKCFG_RKSIZE GENMASK(18, 16) + #define RKCFG_DMCKEWAKE BIT(19) + #define RKCFG_RK0SRF BIT(20) + #define RKCFG_RK1SRF BIT(21) + #define RKCFG_RK2SRF BIT(22) + #define RKCFG_SRF_ENTER_MASK_OPT BIT(23) + #define RKCFG_RK0DPD BIT(24) + #define RKCFG_RK1DPD BIT(25) + #define RKCFG_RK2DPD BIT(26) + #define RKCFG_RK0DPDX BIT(28) + #define RKCFG_RK1DPDX BIT(29) + #define RKCFG_RK2DPDX BIT(30) + #define RKCFG_CS0FORCE BIT(31) +#define DRAMC_PD_CTRL 0x00000038 + #define DRAMC_PD_CTRL_DCMEN BIT(0) + #define DRAMC_PD_CTRL_DCMEN2 BIT(1) + #define DRAMC_PD_CTRL_DCMENNOTRFC BIT(2) + #define DRAMC_PD_CTRL_PHYCLK_REFWKEN BIT(4) + #define DRAMC_PD_CTRL_COMBPHY_CLKENSAME BIT(5) + #define DRAMC_PD_CTRL_DCMREF_OPT BIT(8) + #define DRAMC_PD_CTRL_PG_DCM_OPT BIT(9) + #define DRAMC_PD_CTRL_COMB_DCM BIT(10) + #define DRAMC_PD_CTRL_RDPERIODON BIT(19) + #define DRAMC_PD_CTRL_DQIEN_BUFFEN_OPT GENMASK(21, 20) + #define DRAMC_PD_CTRL_MIOCKCTRLOFF BIT(26) + #define DRAMC_PD_CTRL_DISSTOP26M BIT(27) + #define DRAMC_PD_CTRL_PHYCLKDYNGEN BIT(30) + #define DRAMC_PD_CTRL_COMBCLKCTRL BIT(31) +#define CLKAR 0x0000003c + #define CLKAR_REQQUE_PACG_DIS GENMASK(14, 0) + #define CLKAR_SELPH_CMD_CG_DIS BIT(15) + #define CLKAR_RDATCKAR BIT(16) + #define CLKAR_SRF_CLKRUN BIT(17) + #define CLKAR_IDLE_OPT BIT(18) + #define CLKAR_PSELAR BIT(19) + #define CLKAR_BCLKAR BIT(20) + #define CLKAR_SELPH_4LCG_DIS BIT(21) + #define CLKAR_SELPH_CG_DIS BIT(22) + #define CLKAR_TESTCLKRUN BIT(23) + #define CLKAR_PHYGLUECLKRUN BIT(24) + #define CLKAR_DWCLKRUN BIT(25) + #define CLKAR_REFCLKRUN BIT(26) + #define CLKAR_REQQUECLKRUN BIT(27) + #define CLKAR_SEQCLKRUN BIT(28) + #define CLKAR_CALCKAR BIT(29) + #define CLKAR_CMDCKAR BIT(30) + #define CLKAR_RDYCKAR BIT(31) +#define CLKCTRL 0x00000040 + #define CLKCTRL_PSEL_CNT GENMASK(5, 0) + #define CLKCTRL_SEQCLKRUN3 BIT(7) + #define CLKCTRL_SEQCLKRUN2 BIT(8) + #define CLKCTRL_CLK_EN_0 BIT(28) + #define CLKCTRL_CLK_EN_1 BIT(29) +#define SELFREF_HWSAVE_FLAG 0x00000044 + #define SELFREF_HWSAVE_FLAG_SELFREF_HWSAVE_FLAG_FROM_AO BIT(0) +#define SREFCTRL 0x00000048 + #define SREFCTRL_HMRRSEL_CGAR BIT(12) + #define SREFCTRL_RDDQSOSC_CGAR BIT(13) + #define SREFCTRL_SCARB_SM_CGAR BIT(14) + #define SREFCTRL_SCSM_CGAR BIT(15) + #define SREFCTRL_SRFPD_DIS BIT(16) + #define SREFCTRL_DQSOSC_THRD_OPT BIT(17) + #define SREFCTRL_DQSOSC_C2R_OPT BIT(18) + #define SREFCTRL_SREF3_OPTION BIT(20) + #define SREFCTRL_SREF3_OPTION1 BIT(21) + #define SREFCTRL_SREF2_OPTION BIT(22) + #define SREFCTRL_SREFDLY GENMASK(27, 24) + #define SREFCTRL_SREF_HW_EN BIT(30) + #define SREFCTRL_SELFREF BIT(31) +#define REFCTRL0 0x0000004c + #define REFCTRL0_DLLFRZ BIT(0) + #define REFCTRL0_UPDBYWR BIT(1) + #define REFCTRL0_DRVCGWREF BIT(2) + #define REFCTRL0_DQDRVSWUPD BIT(3) + #define REFCTRL0_RFRINTCTL BIT(5) + #define REFCTRL0_RFRINTEN BIT(6) + #define REFCTRL0_REFOVERCNT_RST BIT(7) + #define REFCTRL0_DMPGVLD_IG BIT(8) + #define REFCTRL0_REFMODE_MANUAL BIT(10) + #define REFCTRL0_REFMODE_MANUAL_TRIG BIT(11) + #define REFCTRL0_DISBYREFNUM GENMASK(14, 12) + #define REFCTRL0_PBREF_DISBYREFNUM BIT(16) + #define REFCTRL0_PBREF_DISBYRATE BIT(17) + #define REFCTRL0_PBREFEN BIT(18) + #define REFCTRL0_ADVREF_CNT GENMASK(23, 20) + #define REFCTRL0_REF_PREGATE_CNT GENMASK(27, 24) + #define REFCTRL0_REFNA_OPT BIT(28) + #define REFCTRL0_REFDIS BIT(29) + #define REFCTRL0_REFFRERUN BIT(30) + #define REFCTRL0_REFBW_FREN BIT(31) +#define REFCTRL1 0x00000050 + #define REFCTRL1_SLEFREF_AUTOSAVE_EN BIT(0) + #define REFCTRL1_SREF_PRD_OPT BIT(1) + #define REFCTRL1_PSEL_OPT2 BIT(2) + #define REFCTRL1_PSEL_OPT3 BIT(3) + #define REFCTRL1_PRE8REF BIT(4) + #define REFCTRL1_REF_QUE_AUTOSAVE_EN BIT(5) + #define REFCTRL1_PSEL_OPT1 BIT(6) + #define REFCTRL1_SREF_CG_OPT BIT(7) + #define REFCTRL1_MPENDREF_CNT GENMASK(10, 8) + #define REFCTRL1_REFRATE_MON_CLR BIT(11) + #define REFCTRL1_REFRATE_MANUAL GENMASK(30, 28) + #define REFCTRL1_REFRATE_MANUAL_RATE_TRIG BIT(31) +#define REFRATRE_FILTER 0x00000054 + #define REFRATRE_FILTER_REFRATE_FIL0 GENMASK(2, 0) + #define REFRATRE_FILTER_REFRATE_FIL1 GENMASK(6, 4) + #define REFRATRE_FILTER_REFRATE_FIL2 GENMASK(10, 8) + #define REFRATRE_FILTER_REFRATE_FIL3 GENMASK(14, 12) + #define REFRATRE_FILTER_PB2AB_OPT BIT(15) + #define REFRATRE_FILTER_REFRATE_FIL4 GENMASK(18, 16) + #define REFRATRE_FILTER_REFRATE_FIL5 GENMASK(22, 20) + #define REFRATRE_FILTER_PB2AB_OPT1 BIT(23) + #define REFRATRE_FILTER_REFRATE_FIL6 GENMASK(26, 24) + #define REFRATRE_FILTER_REFRATE_FIL7 GENMASK(30, 28) + #define REFRATRE_FILTER_REFRATE_FILEN BIT(31) +#define ZQCS 0x00000058 + #define ZQCS_ZQCSOP GENMASK(7, 0) + #define ZQCS_ZQCSAD GENMASK(15, 8) + #define ZQCS_ZQCS_MASK_SEL GENMASK(18, 16) + #define ZQCS_ZQCS_MASK_SEL_CGAR BIT(19) + #define ZQCS_ZQMASK_CGAR BIT(20) + #define ZQCS_ZQCSMASK_OPT BIT(21) + #define ZQCS_ZQ_SRF_OPT BIT(22) + #define ZQCS_ZQCSMASK BIT(30) + #define ZQCS_ZQCSDUAL BIT(31) +#define MRS 0x0000005c + #define MRS_MRSOP GENMASK(7, 0) + #define MRS_MRSMA GENMASK(20, 8) + #define MRS_MRSBA GENMASK(23, 21) + #define MRS_MRSRK GENMASK(25, 24) + #define MRS_MRRRK GENMASK(27, 26) + #define MRS_MPCRK GENMASK(29, 28) + #define MRS_MRSBG GENMASK(31, 30) +#define SPCMD 0x00000060 + #define SPCMD_MRWEN BIT(0) + #define SPCMD_MRREN BIT(1) + #define SPCMD_PREAEN BIT(2) + #define SPCMD_AREFEN BIT(3) + #define SPCMD_ZQCEN BIT(4) + #define SPCMD_TCMDEN BIT(5) + #define SPCMD_ZQLATEN BIT(6) + #define SPCMD_RDDQCEN BIT(7) + #define SPCMD_DQSGCNTEN BIT(8) + #define SPCMD_DQSGCNTRST BIT(9) + #define SPCMD_DQSOSCENEN BIT(10) + #define SPCMD_DQSOSCDISEN BIT(11) + #define SPCMD_ACTEN BIT(12) + #define SPCMD_MPRWEN BIT(13) +#define SPCMDCTRL 0x00000064 + #define SPCMDCTRL_SC_PG_UPD_OPT BIT(0)//cc add + #define SPCMDCTRL_SC_PG_MAN_DIS BIT(1)//cc add + #define SPCMDCTRL_SPREA_EN BIT(2)//cc add + #define SPCMDCTRL_SCARB_PRI_OPT BIT(4) + #define SPCMDCTRL_MRRSWUPD BIT(5) + #define SPCMDCTRL_R_DMDVFSMRW_EN BIT(6) + #define SPCMDCTRL_DPDWOSC BIT(7) + #define SPCMDCTRL_SC_PG_MPRW_DIS BIT(10)//cc add + #define SPCMDCTRL_SC_PG_STCMD_AREF_DIS BIT(9)//cc add + #define SPCMDCTRL_SC_PG_OPT2_DIS BIT(8)//cc add + #define SPCMDCTRL_RDDQCDIS BIT(11) + #define SPCMDCTRL_HMR4_TOG_OPT BIT(18)//cc add + #define SPCMDCTRL_SCPRE BIT(19) + #define SPCMDCTRL_ZQCS_NONMASK_CLR BIT(20) + #define SPCMDCTRL_ZQCS_MASK_FIX BIT(21) + #define SPCMDCTRL_ZQCS_MASK_VALUE BIT(22) + #define SPCMDCTRL_SRFMR4_CNTKEEP_B BIT(24) + #define SPCMDCTRL_MRWWOPRA BIT(25) + #define SPCMDCTRL_CLR_EN BIT(26) + #define SPCMDCTRL_MRRREFUPD_B BIT(27) + #define SPCMDCTRL_REFR_BLOCKEN BIT(28) + #define SPCMDCTRL_REFRDIS BIT(29) + #define SPCMDCTRL_ZQCALDISB BIT(30) + #define SPCMDCTRL_ZQCSDISB BIT(31) +#define PPR_CTRL 0x00000068 + #define PPR_CTRL_ACTEN_BK GENMASK(14, 12) + #define PPR_CTRL_ACTEN_ROW GENMASK(31, 16) +#define MPC_OPTION 0x0000006c + #define MPC_OPTION_MPC_BLOCKALE_OPT BIT(0) + #define MPC_OPTION_MPC_BLOCKALE_OPT1 BIT(1) + #define MPC_OPTION_MPC_BLOCKALE_OPT2 BIT(2) + #define MPC_OPTION_ZQ_BLOCKALE_OPT BIT(3) + #define MPC_OPTION_RW2ZQLAT_OPT BIT(4) + #define MPC_OPTION_MPCOP GENMASK(14, 8) + #define MPC_OPTION_MPCMANEN BIT(15) + #define MPC_OPTION_MPCMAN_CAS2EN BIT(16) + #define MPC_OPTION_MPCRKEN BIT(17) +#define REFQUE_CNT 0x00000070 + #define REFQUE_CNT_REFRESH_QUEUE_CNT_FROM_AO GENMASK(3, 0) +#define HW_MRR_FUN 0x00000074 + #define HW_MRR_FUN_TMRR_ENA BIT(0) + #define HW_MRR_FUN_TRCDMRR_EN BIT(1) + #define HW_MRR_FUN_TRPMRR_EN BIT(2) + #define HW_MRR_FUN_MANTMRR_EN BIT(3) + #define HW_MRR_FUN_MANTMRR GENMASK(7, 4) + #define HW_MRR_FUN_BUFEN_RFC_OPT BIT(8) + #define HW_MRR_FUN_MRR_REQNOPUSH_DIS BIT(9) + #define HW_MRR_FUN_MRR_BLOCK_NOR_DIS BIT(10) + #define HW_MRR_FUN_MRR_HW_HIPRI BIT(11) + #define HW_MRR_FUN_MRR_SPCMD_WAKE_DIS BIT(12) + #define HW_MRR_FUN_TMRR_OE_OPT_DIS BIT(13) + #define HW_MRR_FUN_MRR_PUSH2POP_ENA BIT(16) + #define HW_MRR_FUN_MRR_PUSH2POP_CLR BIT(17) + #define HW_MRR_FUN_MRR_PUSH2POP_ST_CLR BIT(18) + #define HW_MRR_FUN_MRR_PUSH2POP_SEL GENMASK(22, 20) + #define HW_MRR_FUN_MRR_SBR3_BKVA_DIS BIT(23) + #define HW_MRR_FUN_MRR_DDRCLKCOMB_DIS BIT(24) + #define HW_MRR_FUN_TRPRCD_DIS_OPT1 BIT(25) + #define HW_MRR_FUN_TRPRCD_OPT2 BIT(26) + #define HW_MRR_FUN_MRR_SBR2_QHIT_DIS BIT(27) + #define HW_MRR_FUN_MRR_INPUT_BANK GENMASK(30, 28) + #define HW_MRR_FUN_MRR_TZQCS_DIS BIT(31) +#define MRR_BIT_MUX1 0x00000078 + #define MRR_BIT_MUX1_MRR_BIT0_SEL GENMASK(4, 0) + #define MRR_BIT_MUX1_MRR_BIT1_SEL GENMASK(12, 8) + #define MRR_BIT_MUX1_MRR_BIT2_SEL GENMASK(20, 16) + #define MRR_BIT_MUX1_MRR_BIT3_SEL GENMASK(28, 24) +#define MRR_BIT_MUX2 0x0000007c + #define MRR_BIT_MUX2_MRR_BIT4_SEL GENMASK(4, 0) + #define MRR_BIT_MUX2_MRR_BIT5_SEL GENMASK(12, 8) + #define MRR_BIT_MUX2_MRR_BIT6_SEL GENMASK(20, 16) + #define MRR_BIT_MUX2_MRR_BIT7_SEL GENMASK(28, 24) +#define MRR_BIT_MUX3 0x00000080 + #define MRR_BIT_MUX3_MRR_BIT8_SEL GENMASK(4, 0) + #define MRR_BIT_MUX3_MRR_BIT9_SEL GENMASK(12, 8) + #define MRR_BIT_MUX3_MRR_BIT10_SEL GENMASK(20, 16) + #define MRR_BIT_MUX3_MRR_BIT11_SEL GENMASK(28, 24) +#define MRR_BIT_MUX4 0x00000084 + #define MRR_BIT_MUX4_MRR_BIT12_SEL GENMASK(4, 0) + #define MRR_BIT_MUX4_MRR_BIT13_SEL GENMASK(12, 8) + #define MRR_BIT_MUX4_MRR_BIT14_SEL GENMASK(20, 16) + #define MRR_BIT_MUX4_MRR_BIT15_SEL GENMASK(28, 24) +#define TEST2_5 0x0000008c + #define TEST2_5_TEST2_BASE_2 GENMASK(31, 4) +#define TEST2_0 0x00000090 + #define TEST2_0_TEST2_PAT1 GENMASK(7, 0) + #define TEST2_0_TEST2_PAT0 GENMASK(15, 8) +#define TEST2_1 0x00000094 + #define TEST2_1_TEST2_BASE GENMASK(31, 4) +#define TEST2_2 0x00000098 + #define TEST2_2_TEST2_OFF GENMASK(31, 4) +#define TEST2_3 0x0000009c + #define TEST2_3_TESTCNT GENMASK(3, 0) + #define TEST2_3_DQSICALEN BIT(4) + #define TEST2_3_DQSICALUPD BIT(5) + #define TEST2_3_PSTWR2 BIT(6) + #define TEST2_3_TESTAUDPAT BIT(7) + #define TEST2_3_DQSICALSTP GENMASK(10, 8) + #define TEST2_3_DQDLYAUTO BIT(11) + #define TEST2_3_MANUDLLFRZ BIT(12) + #define TEST2_3_MANUDQSUPD BIT(13) + #define TEST2_3_DQSUPDMODE BIT(14) + #define TEST2_3_DRDELSWEN BIT(19) + #define TEST2_3_DRDELSWSEL GENMASK(22, 20) + #define TEST2_3_MDQS BIT(23) + #define TEST2_3_DMPAT32 BIT(24) + #define TEST2_3_TESTADR_SHIFT BIT(25) + #define TEST2_3_TAHPRI_B BIT(26) + #define TEST2_3_TESTLP BIT(27) + #define TEST2_3_TEST2WREN2_HW_EN BIT(28) + #define TEST2_3_TEST1 BIT(29) + #define TEST2_3_TEST2R BIT(30) + #define TEST2_3_TEST2W BIT(31) +#define TEST2_4 0x000000a0 + #define TEST2_4_TESTAUDINC GENMASK(4, 0) + #define TEST2_4_TEST2DISSCRAM BIT(5) + #define TEST2_4_TESTSSOPAT BIT(6) + #define TEST2_4_TESTSSOXTALKPAT BIT(7) + #define TEST2_4_TESTAUDINIT GENMASK(12, 8) + #define TEST2_4_TESTAUDBITINV BIT(14) + #define TEST2_4_TESTAUDMODE BIT(15) + #define TEST2_4_TESTXTALKPAT BIT(16) + #define TEST2_4_TEST_REQ_LEN1 BIT(17) + #define TEST2_4_DISMASK BIT(20) + #define TEST2_4_DQCALDIS BIT(22) + #define TEST2_4_NEGDQS BIT(23) + #define TEST2_4_TESTAGENTRK GENMASK(25, 24) + #define TEST2_4_TESTAGENTRKSEL GENMASK(30, 28) +#define WDT_DBG_SIGNAL 0x000000a4 + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK0 BIT(0) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK1 BIT(1) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK0 BIT(2) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK1 BIT(3) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK0 BIT(4) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK1 BIT(5) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK0 BIT(8) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK1 BIT(9) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK0 BIT(10) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK1 BIT(11) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK0 BIT(12) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK1 BIT(13) + #define WDT_DBG_SIGNAL_LATCH_DRAMC_GATING_ERROR BIT(14) +#define LBTEST 0x000000ac + #define LBTEST_LBTEST_IGB0 BIT(0) + #define LBTEST_LBTEST_IGB1 BIT(1) + #define LBTEST_LBTEST_IGB2 BIT(2) + #define LBTEST_LBTEST_IGB3 BIT(3) + #define LBTEST_LBTEST BIT(4) + #define LBTEST_LBTEST_MODE BIT(5) + #define LBTEST_R_EXTLB_DRAMC_CONF_I GENMASK(12, 8) + #define LBTEST_OCDPAT GENMASK(23, 16) + #define LBTEST_OCDADJ BIT(24) + #define LBTEST_RDCOLADR BIT(29) + #define LBTEST_RDWRDATA BIT(30) + #define LBTEST_RDTGDATA BIT(31) +#define CATRAINING1 0x000000b0 + #define CATRAINING1_CATRAINEN BIT(1) + #define CATRAINING1_CATRAINMRS BIT(2) + #define CATRAINING1_TESTCATRAIN BIT(5) + #define CATRAINING1_CSTRAIN_OPTION BIT(6) + #define CATRAINING1_CATRAINCSEXT BIT(13) + #define CATRAINING1_CATRAINLAT GENMASK(23, 20) + #define CATRAINING1_CATRAIN_INTV GENMASK(31, 24) +#define CATRAINING2 0x000000b4 + #define CATRAINING2_CATRAINCA GENMASK(15, 0) + #define CATRAINING2_CATRAINCA_Y GENMASK(31, 16) +#define WRITE_LEV 0x000000bc + #define WRITE_LEV_WRITE_LEVEL_EN BIT(0) + #define WRITE_LEV_DDRPHY_COMB_CG_SEL BIT(2) + #define WRITE_LEV_BYTEMODECBTEN BIT(3) + #define WRITE_LEV_BTCBTFIXDQSOE BIT(4) + #define WRITE_LEV_CBTMASKDQSOE BIT(5) + #define WRITE_LEV_DQS_OE_WLEV_OP BIT(6) + #define WRITE_LEV_DQS_WLEV BIT(7) + #define WRITE_LEV_DQSBX_G GENMASK(11, 8) + #define WRITE_LEV_DQSBY_G GENMASK(15, 12) + #define WRITE_LEV_DQS_SEL GENMASK(19, 16) + #define WRITE_LEV_DMVREFCA GENMASK(27, 20) + #define WRITE_LEV_DQS_OE_OP1_DIS BIT(28) + #define WRITE_LEV_DQS_OE_OP2_EN BIT(29) +#define MR_GOLDEN 0x000000c0 + #define MR_GOLDEN_MR20_GOLDEN GENMASK(7, 0) + #define MR_GOLDEN_MR15_GOLDEN GENMASK(15, 8) + #define MR_GOLDEN_MR40_GOLDEN GENMASK(23, 16) + #define MR_GOLDEN_MR32_GOLDEN GENMASK(31, 24) +#define SLP4_TESTMODE 0x000000c4 + #define SLP4_TESTMODE_CA0_TEST GENMASK(3, 0) + #define SLP4_TESTMODE_CA1_TEST GENMASK(7, 4) + #define SLP4_TESTMODE_CA2_TEST GENMASK(11, 8) + #define SLP4_TESTMODE_CA3_TEST GENMASK(15, 12) + #define SLP4_TESTMODE_CA4_TEST GENMASK(19, 16) + #define SLP4_TESTMODE_CA5_TEST GENMASK(23, 20) + #define SLP4_TESTMODE_STESTEN BIT(24) + #define SLP4_TESTMODE_SPEC_MODE BIT(25) + #define SLP4_TESTMODE_ARPI_CAL_E2OPT BIT(26) + #define SLP4_TESTMODE_TX_DLY_CAL_E2OPT BIT(27) +#define DQSOSCR 0x000000c8 + #define DQSOSCR_DQSOSC_INTEN BIT(0) + #define DQSOSCR_RK2_BYTE_MODE BIT(1) + #define DQSOSCR_TXUPD_BLOCK_SEL GENMASK(3, 2) + #define DQSOSCR_TXUPD_BLOCK_OPT BIT(4) + #define DQSOSCR_TXUPDMODE BIT(5) + #define DQSOSCR_MANUTXUPD BIT(6) + #define DQSOSCR_ARUIDQ_SW BIT(7) + #define DQSOSCR_DQS2DQ_UPD_BLOCK_CNT GENMASK(12, 8) + #define DQSOSCR_TDQS2DQ_UPD_BLOCKING BIT(13) + #define DQSOSCR_DQS2DQ_UPD_MON_OPT BIT(14) + #define DQSOSCR_DQS2DQ_UPD_MON_CNT_SEL GENMASK(16, 15) + #define DQSOSCR_TXUPD_IDLE_SEL GENMASK(18, 17) + #define DQSOSCR_TXUPD_ABREF_SEL GENMASK(20, 19) + #define DQSOSCR_TXUPD_IDLE_OPT BIT(21) + #define DQSOSCR_DQS2DQ_SHU_HW_CAL_DIS BIT(22) + #define DQSOSCR_SREF_TXUI_RELOAD_OPT BIT(23) + #define DQSOSCR_DQSOSCRDIS BIT(24) + #define DQSOSCR_RK1_BYTE_MODE BIT(25) + #define DQSOSCR_RK0_BYTE_MODE BIT(26) + #define DQSOSCR_SREF_TXPI_RELOAD_OPT BIT(27) + #define DQSOSCR_EMPTY_WRITE_OPT BIT(28) + #define DQSOSCR_TXUPD_ABREF_OPT BIT(29) + #define DQSOSCR_DQSOSCLOPAD BIT(30) + #define DQSOSCR_DQSOSC_CALEN BIT(31) +#define DUMMY_RD 0x000000d0 + #define DUMMY_RD_SREF_DMYRD_MASK BIT(0) + #define DUMMY_RD_DMYRDOFOEN BIT(1) + #define DUMMY_RD_DUMMY_RD_SW BIT(4) + #define DUMMY_RD_DMYWR_LPRI_EN BIT(5) + #define DUMMY_RD_DMY_WR_DBG BIT(6) + #define DUMMY_RD_DMY_RD_DBG BIT(7) + #define DUMMY_RD_DUMMY_RD_CNT0 BIT(8) + #define DUMMY_RD_DUMMY_RD_CNT1 BIT(9) + #define DUMMY_RD_DUMMY_RD_CNT2 BIT(10) + #define DUMMY_RD_DUMMY_RD_CNT3 BIT(11) + #define DUMMY_RD_DUMMY_RD_CNT4 BIT(12) + #define DUMMY_RD_DUMMY_RD_CNT5 BIT(13) + #define DUMMY_RD_DUMMY_RD_CNT6 BIT(14) + #define DUMMY_RD_DUMMY_RD_CNT7 BIT(15) + #define DUMMY_RD_RANK_NUM GENMASK(17, 16) + #define DUMMY_RD_DUMMY_RD_EN BIT(20) + #define DUMMY_RD_SREF_DMYRD_EN BIT(21) + #define DUMMY_RD_DQSG_DMYRD_EN BIT(22) + #define DUMMY_RD_DQSG_DMYWR_EN BIT(23) + #define DUMMY_RD_DUMMY_RD_PA_OPT BIT(24) + #define DUMMY_RD_DMY_RD_RX_TRACK BIT(25) + #define DUMMY_RD_DMYRD_HPRI_DIS BIT(26) + #define DUMMY_RD_DMYRD_REORDER_DIS BIT(27) +#define SHUCTRL 0x000000d4 + #define SHUCTRL_R_SHUFFLE_BLOCK_OPT GENMASK(1, 0) + #define SHUCTRL_DVFS_CG_OPT BIT(2) + #define SHUCTRL_VRCG_EN BIT(4) + #define SHUCTRL_SHU_PHYRST_SEL BIT(5) + #define SHUCTRL_R_DVFS_PICG_MARGIN2 GENMASK(7, 6) + #define SHUCTRL_DMSHU_CNT GENMASK(13, 8) + #define SHUCTRL_SHUCTRL_RESERVED GENMASK(15, 14) + #define SHUCTRL_LPSM_BYPASS_B BIT(16) + #define SHUCTRL_R_DRAMC_CHA BIT(17) + #define SHUCTRL_DVFS_CHB_SEL_B BIT(18) + #define SHUCTRL_R_NEW_SHU_MUX_SPM BIT(19) + #define SHUCTRL_R_MPDIV_SHU_GP GENMASK(22, 20) + #define SHUCTRL_R_OTHER_SHU_GP GENMASK(25, 24) + #define SHUCTRL_R_DVFS_PICG_MARGIN3 GENMASK(27, 26) + #define SHUCTRL_DMSHU_LOW BIT(29) + #define SHUCTRL_DMSHU_DRAMC BIT(31) +#define SHUCTRL1 0x000000d8 + #define SHUCTRL1_FC_PRDCNT GENMASK(7, 0) + #define SHUCTRL1_CKFSPE_PRDCNT GENMASK(15, 8) + #define SHUCTRL1_CKFSPX_PRDCNT GENMASK(23, 16) + #define SHUCTRL1_VRCGEN_PRDCNT GENMASK(31, 24) +#define SHUCTRL2 0x000000dc + #define SHUCTRL2_R_DLL_IDLE GENMASK(6, 0) + #define SHUCTRL2_R_DVFS_FSM_CLR BIT(7) + #define SHUCTRL2_R_DVFS_SREF_OPT BIT(8) + #define SHUCTRL2_R_DVFS_CDC_OPTION BIT(9) + #define SHUCTRL2_R_DVFS_PICG_MARGIN GENMASK(11, 10) + #define SHUCTRL2_R_DVFS_DLL_CHA BIT(12) + #define SHUCTRL2_R_CDC_MUX_SEL_OPTION BIT(13) + #define SHUCTRL2_R_DVFS_PARK_N BIT(14) + #define SHUCTRL2_R_DVFS_OPTION BIT(15) + #define SHUCTRL2_SHU_PERIOD_GO_ZERO_CNT GENMASK(23, 16) + #define SHUCTRL2_HWSET_WLRL BIT(24) + #define SHUCTRL2_MR13_SHU_EN BIT(25) + #define SHUCTRL2_R_DVFS_RG_CDC_TX_SEL BIT(26) + #define SHUCTRL2_R_DVFS_RG_CDC_SYNC_ENABLE BIT(27) + #define SHUCTRL2_R_SHU_RESTORE BIT(28) + #define SHUCTRL2_SHU_CLK_MASK BIT(29) + #define SHUCTRL2_DVFS_CKE_OPT BIT(30) + #define SHUCTRL2_SHORTQ_OPT BIT(31) +#define SHUCTRL3 0x000000e0 + #define SHUCTRL3_VRCGDIS_MRSMA GENMASK(12, 0) + #define SHUCTRL3_VRCGDISOP GENMASK(23, 16) + #define SHUCTRL3_VRCGDIS_PRDCNT GENMASK(31, 24) +#define SHUSTATUS 0x000000e4 + #define SHUSTATUS_SHUFFLE_END BIT(0) + #define SHUSTATUS_SHUFFLE_START_LOW BIT(1) + #define SHUSTATUS_SHUFFLE_START_LOW_THREE BIT(2) + #define SHUSTATUS_SHUFFLE_LEVEL GENMASK(2, 1) //cc add + #define SHUSTATUS_MPDIV_SHU_GP GENMASK(6, 4) +#define BYPASS_FSPOP 0x00000100 + #define BYPASS_FSPOP_BPFSP_SHU0 GENMASK(3, 0) + #define BYPASS_FSPOP_BPFSP_SHU1 GENMASK(7, 4) + #define BYPASS_FSPOP_BPFSP_SHU2 GENMASK(11, 8) + #define BYPASS_FSPOP_BPFSP_SHU3 GENMASK(15, 12) + #define BYPASS_FSPOP_BPFSP_OPT BIT(16) +#define STBCAL 0x00000200 + #define STBCAL_PIMASK_RKCHG_OPT BIT(0) + #define STBCAL_PIMASK_RKCHG_EXT GENMASK(3, 1) + #define STBCAL_STBDLELAST_OPT BIT(4) + #define STBCAL_DLLFRZIDLE4XUPD BIT(5) + #define STBCAL_FASTDQSG2X BIT(6) + #define STBCAL_FASTDQSGUPD BIT(7) + #define STBCAL_STBDLELAST_PULSE GENMASK(11, 8) + #define STBCAL_STBDLELAST_FILTER BIT(12) + #define STBCAL_STBUPDSTOP BIT(13) + #define STBCAL_CG_RKEN BIT(14) + #define STBCAL_STBSTATE_OPT BIT(15) + #define STBCAL_PHYVALID_IG BIT(16) + #define STBCAL_SREF_DQSGUPD BIT(17) + #define STBCAL_STBCNTRST BIT(18) + #define STBCAL_RKCHGMASKDIS BIT(19) + #define STBCAL_PICGEN BIT(20) + #define STBCAL_REFUICHG BIT(21) + #define STBCAL_STB_SELPHYCALEN BIT(22) + #define STBCAL_STBCAL2R BIT(23) + #define STBCAL_STBCALEN BIT(24) + #define STBCAL_STBDLYOUT_OPT BIT(25) + #define STBCAL_PICHGBLOCK_NORD BIT(26) + #define STBCAL_STB_DQIEN_IG BIT(27) + #define STBCAL_DQSIENCG_CHG_EN BIT(28) + #define STBCAL_DQSIENCG_NORMAL_EN BIT(29) + #define STBCAL_DQSIENMODE_SELPH BIT(30) + #define STBCAL_DQSIENMODE BIT(31) +#define STBCAL1 0x00000204 + #define STBCAL1_DIS_PI_TRACK_AS_NOT_RD BIT(2) + #define STBCAL1_STBEN_LP3_DIV2_EN BIT(3) + #define STBCAL1_STBCNT_MODESEL BIT(4) + #define STBCAL1_DQSIEN_7UI_EN BIT(5) + #define STBCAL1_STB_SHIFT_DTCOUT_IG BIT(6) + #define STBCAL1_INPUTRXTRACK_BLOCK BIT(7) + #define STBCAL1_STB_FLAGCLR BIT(8) + #define STBCAL1_STB_DLLFRZ_IG BIT(9) + #define STBCAL1_STBENCMPEN BIT(10) + #define STBCAL1_STBCNT_LATCH_EN BIT(11) + #define STBCAL1_DLLFRZ_MON_PBREF_OPT BIT(12) + #define STBCAL1_DLLFRZ_BLOCKLONG BIT(13) + #define STBCAL1_DQSERRCNT_DIS BIT(14) + #define STBCAL1_STBCNT_SW_RST BIT(15) + #define STBCAL1_STBCAL_FILTER GENMASK(31, 16) +#define STBCAL2 0x00000208 + #define STBCAL2_STB_PIDLYCG_IG BIT(0) + #define STBCAL2_STB_UIDLYCG_IG BIT(1) + #define STBCAL2_STB_DBG_EN GENMASK(7, 4) + #define STBCAL2_STB_DBG_EN_B1 BIT(5)//[5:5] + #define STBCAL2_STB_DBG_EN_B0 BIT(4)//[4:4] + #define STBCAL2_STB_DBG_CG_AO BIT(8) + #define STBCAL2_STB_DBG_UIPI_UPD_OPT BIT(9) + #define STBCAL2_DQSGCNT_BYP_REF BIT(10) + #define STBCAL2_STB_DRS_MASK_HW_SAVE BIT(12) + #define STBCAL2_STB_DRS_RK1_FLAG_SYNC_RK0_EN BIT(13) + #define STBCAL2_STB_PICG_EARLY_1T_EN BIT(16) + #define STBCAL2_STB_GERRSTOP BIT(28) + #define STBCAL2_STB_GERR_RST BIT(29) + #define STBCAL2_STB_GERR_B01 BIT(30) + #define STBCAL2_STB_GERR_B23 BIT(31) +#define EYESCAN 0x0000020c + #define EYESCAN_REG_SW_RST BIT(0) + #define EYESCAN_RG_RX_EYE_SCAN_EN BIT(1) + #define EYESCAN_RG_RX_MIOCK_JIT_EN BIT(2) + #define EYESCAN_EYESCAN_RD_SEL_OPT BIT(4) + #define EYESCAN_EYESCAN_CHK_OPT BIT(6) + #define EYESCAN_EYESCAN_TOG_OPT BIT(7) + #define EYESCAN_EYESCAN_DQ_SYNC_EN BIT(8) + #define EYESCAN_EYESCAN_NEW_DQ_SYNC_EN BIT(9) + #define EYESCAN_EYESCAN_DQS_SYNC_EN BIT(10) + #define EYESCAN_DCBLNCEN BIT(12) + #define EYESCAN_DCBLNCINS BIT(13) + #define EYESCAN_RX_DQ_EYE_SEL GENMASK(19, 16) + #define EYESCAN_RX_DQ_EYE_SEL_B1 GENMASK(23, 20) + #define EYESCAN_RX_DQ_EYE_SEL_B2 GENMASK(27, 24) + #define EYESCAN_RX_DQ_EYE_SEL_B3 GENMASK(31, 28) +#define DVFSDLL 0x00000210 + #define DVFSDLL_DLL_LOCK_SHU_EN BIT(0) + #define DVFSDLL_R_BYPASS_1ST_DLL_SHU1 BIT(1) + #define DVFSDLL_R_BYPASS_1ST_DLL_SHU2 BIT(2) + #define DVFSDLL_R_BYPASS_1ST_DLL_SHU3 BIT(3) + #define DVFSDLL_R_BYPASS_1ST_DLL_SHU4 BIT(4) + #define DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE BIT(5) + #define DVFSDLL_R_RETRY_SAV_MSK BIT(6) + #define DVFSDLL_RG_DLL_SHUFFLE BIT(7) + #define DVFSDLL_DLL_IDLE_SHU2 GENMASK(14, 8) + #define DVFSDLL_DLL_IDLE_SHU3 GENMASK(22, 16) + #define DVFSDLL_R_DMSHUFFLE_CHANGE_FREQ_OPT BIT(24) + #define DVFSDLL_R_DVFS_DLL_MARGIN GENMASK(29, 28) + #define DVFSDLL_R_DVFS_SYNC_MODULE_RST_SEL BIT(31) +#define PRE_TDQSCK1 0x00000218 + #define PRE_TDQSCK1_FREQ_RATIO_TX_9 GENMASK(4, 0) + #define PRE_TDQSCK1_FREQ_RATIO_TX_10 GENMASK(9, 5) + #define PRE_TDQSCK1_FREQ_RATIO_TX_11 GENMASK(14, 10) + #define PRE_TDQSCK1_TX_TRACKING_OPT BIT(15) + #define PRE_TDQSCK1_SW_UP_TX_NOW_CASE BIT(16) + #define PRE_TDQSCK1_TXUIPI_CAL_CGAR BIT(17) + #define PRE_TDQSCK1_SHU_PRELOAD_TX_START BIT(18) + #define PRE_TDQSCK1_SHU_PRELOAD_TX_HW BIT(19) + #define PRE_TDQSCK1_APHY_CG_OPT1 BIT(20) + #define PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL BIT(22) + #define PRE_TDQSCK1_TDQSCK_SW_UP_CASE BIT(23) + #define PRE_TDQSCK1_TDQSCK_SW_SAVE BIT(24) + #define PRE_TDQSCK1_TDQSCK_REG_DVFS BIT(25) + #define PRE_TDQSCK1_TDQSCK_PRECAL_HW BIT(26) + #define PRE_TDQSCK1_TDQSCK_PRECAL_START BIT(27) + #define PRE_TDQSCK1_R_DQBUG_RANK_SEL GENMASK(29, 28) + #define PRE_TDQSCK1_R_DQBUG_BYTE_SEL GENMASK(31, 30) +#define PRE_TDQSCK2 0x0000021c + #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3 GENMASK(7, 0) + #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2 GENMASK(15, 8) + #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1 GENMASK(23, 16) + #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0 GENMASK(31, 24) +#define PRE_TDQSCK3 0x00000220 + #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7 GENMASK(7, 0) + #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6 GENMASK(15, 8) + #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5 GENMASK(23, 16) + #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4 GENMASK(31, 24) +#define PRE_TDQSCK4 0x00000224 + #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11 GENMASK(7, 0) + #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10 GENMASK(15, 8) + #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9 GENMASK(23, 16) + #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8 GENMASK(31, 24) +#define IMPCAL 0x0000022c + #define IMPCAL_DRV_ECO_OPT BIT(10) + #define IMPCAL_IMPCAL_CHGDRV_ECO_OPT BIT(11) + #define IMPCAL_IMPCAL_SM_ECO_OPT BIT(12) + #define IMPCAL_IMPCAL_ECO_OPT BIT(13) + #define IMPCAL_DIS_SUS_CH1_DRV BIT(14) + #define IMPCAL_DIS_SUS_CH0_DRV BIT(15) + #define IMPCAL_DIS_SHU_DRV BIT(16) + #define IMPCAL_IMPCAL_DRVUPDOPT BIT(17) + #define IMPCAL_IMPCAL_USING_SYNC BIT(18) + #define IMPCAL_IMPCAL_BYPASS_UP_CA_DRV BIT(19) + #define IMPCAL_IMPCAL_HWSAVE_EN BIT(20) + #define IMPCAL_IMPCAL_CALI_ENN BIT(21) + #define IMPCAL_IMPCAL_CALI_ENP BIT(22) + #define IMPCAL_IMPCAL_CALI_EN BIT(23) + #define IMPCAL_IMPCAL_IMPPDN BIT(24) + #define IMPCAL_IMPCAL_IMPPDP BIT(25) + #define IMPCAL_IMPCAL_NEW_OLD_SL BIT(26) + #define IMPCAL_IMPCAL_CMP_DIREC GENMASK(28, 27) + #define IMPCAL_IMPCAL_SWVALUE_EN BIT(29) + #define IMPCAL_IMPCAL_EN BIT(30) + #define IMPCAL_IMPCAL_HW BIT(31) +#define IMPEDAMCE_CTRL1 0x00000230 + #define IMPEDAMCE_CTRL1_DQS1_OFF GENMASK(9, 0) + #define IMPEDAMCE_CTRL1_DOS2_OFF GENMASK(19, 10) + #define IMPEDAMCE_CTRL1_DQS1_OFF_SUB GENMASK(29, 28) + #define IMPEDAMCE_CTRL1_DQS2_OFF_SUB GENMASK(31, 30) +#define IMPEDAMCE_CTRL2 0x00000234 + #define IMPEDAMCE_CTRL2_DQ1_OFF GENMASK(9, 0) + #define IMPEDAMCE_CTRL2_DQ2_OFF GENMASK(19, 10) + #define IMPEDAMCE_CTRL2_DQ1_OFF_SUB GENMASK(29, 28) + #define IMPEDAMCE_CTRL2_DQ2_OFF_SUB GENMASK(31, 30) +#define IMPEDAMCE_CTRL3 0x00000238 + #define IMPEDAMCE_CTRL3_CMD1_OFF GENMASK(9, 0) + #define IMPEDAMCE_CTRL3_CMD2_OFF GENMASK(19, 10) + #define IMPEDAMCE_CTRL3_CMD1_OFF_SUB GENMASK(29, 28) + #define IMPEDAMCE_CTRL3_CMD2_OFF_SUB GENMASK(31, 30) +#define IMPEDAMCE_CTRL4 0x0000023c + #define IMPEDAMCE_CTRL4_DQC1_OFF GENMASK(9, 0) + #define IMPEDAMCE_CTRL4_DQC2_OFF GENMASK(19, 10) + #define IMPEDAMCE_CTRL4_DQC1_OFF_SUB GENMASK(29, 28) + #define IMPEDAMCE_CTRL4_DQC2_OFF_SUB GENMASK(31, 30) +#define DRAMC_DBG_SEL1 0x00000240 + #define DRAMC_DBG_SEL1_DEBUG_SEL_0 GENMASK(15, 0) + #define DRAMC_DBG_SEL1_DEBUG_SEL_1 GENMASK(31, 16) +#define DRAMC_DBG_SEL2 0x00000244 + #define DRAMC_DBG_SEL2_DEBUG_SEL_2 GENMASK(15, 0) + #define DRAMC_DBG_SEL2_DEBUG_SEL_3 GENMASK(31, 16) +#define RK0_DQSOSC 0x00000300 + #define RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT BIT(29) + #define RK0_DQSOSC_DQSOSCR_RK0EN BIT(30) + #define RK0_DQSOSC_DQSOSC_RK0INTCLR BIT(31) +#define RK0_DUMMY_RD_WDATA0 0x00000318 + #define RK0_DUMMY_RD_WDATA0_DMY_RD_RK0_WDATA0 GENMASK(31, 0) +#define RK0_DUMMY_RD_WDATA1 0x0000031c + #define RK0_DUMMY_RD_WDATA1_DMY_RD_RK0_WDATA1 GENMASK(31, 0) +#define RK0_DUMMY_RD_WDATA2 0x00000320 + #define RK0_DUMMY_RD_WDATA2_DMY_RD_RK0_WDATA2 GENMASK(31, 0) +#define RK0_DUMMY_RD_WDATA3 0x00000324 + #define RK0_DUMMY_RD_WDATA3_DMY_RD_RK0_WDATA3 GENMASK(31, 0) +#define RK0_DUMMY_RD_ADR 0x00000328 + #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR GENMASK(16, 0) + #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR GENMASK(27, 17) + #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN GENMASK(31, 28) +#define RK0_DUMMY_RD_BK 0x0000032c + #define RK0_DUMMY_RD_BK_DMY_RD_RK0_BK GENMASK(2, 0) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT0 BIT(4) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT1 BIT(5) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT2 BIT(6) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT3 BIT(7) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT4 BIT(8) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT5 BIT(9) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT6 BIT(10) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT7 BIT(11) +#define RK0_PRE_TDQSCK1 0x00000330 + #define RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK2 0x00000334 + #define RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK3 0x00000338 + #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0 GENMASK(11, 6) + #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0 GENMASK(17, 12) + #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0 GENMASK(23, 18) +#define RK0_PRE_TDQSCK4 0x0000033c + #define RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK5 0x00000340 + #define RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK6 0x00000344 + #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0 GENMASK(11, 6) + #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0 GENMASK(17, 12) + #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0 GENMASK(23, 18) +#define RK0_PRE_TDQSCK7 0x00000348 + #define RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK8 0x0000034c + #define RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK9 0x00000350 + #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0 GENMASK(11, 6) + #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0 GENMASK(17, 12) + #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R0 GENMASK(23, 18) +#define RK0_PRE_TDQSCK10 0x00000354 + #define RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK11 0x00000358 + #define RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK12 0x0000035c + #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0 GENMASK(11, 6) + #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0 GENMASK(17, 12) + #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R0 GENMASK(23, 18) +#define RK1_DQSOSC 0x00000400 + #define RK1_DQSOSC_DQSOSCR_RK1EN BIT(30) + #define RK1_DQSOSC_DQSOSC_RK1INTCLR BIT(31) +#define RK1_DUMMY_RD_WDATA0 0x00000418 + #define RK1_DUMMY_RD_WDATA0_DMY_RD_RK1_WDATA0 GENMASK(31, 0) +#define RK1_DUMMY_RD_WDATA1 0x0000041c + #define RK1_DUMMY_RD_WDATA1_DMY_RD_RK1_WDATA1 GENMASK(31, 0) +#define RK1_DUMMY_RD_WDATA2 0x00000420 + #define RK1_DUMMY_RD_WDATA2_DMY_RD_RK1_WDATA2 GENMASK(31, 0) +#define RK1_DUMMY_RD_WDATA3 0x00000424 + #define RK1_DUMMY_RD_WDATA3_DMY_RD_RK1_WDATA3 GENMASK(31, 0) +#define RK1_DUMMY_RD_ADR 0x00000428 + #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR GENMASK(16, 0) + #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR GENMASK(27, 17) + #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN GENMASK(31, 28) +#define RK1_DUMMY_RD_BK 0x0000042c + #define RK1_DUMMY_RD_BK_DMY_RD_RK1_BK GENMASK(2, 0) +#define RK1_PRE_TDQSCK1 0x00000430 + #define RK1_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK2 0x00000434 + #define RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK3 0x00000438 + #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1 GENMASK(11, 6) + #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1 GENMASK(17, 12) + #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1 GENMASK(23, 18) +#define RK1_PRE_TDQSCK4 0x0000043c + #define RK1_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK5 0x00000440 + #define RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK6 0x00000444 + #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1 GENMASK(11, 6) + #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1 GENMASK(17, 12) + #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1 GENMASK(23, 18) +#define RK1_PRE_TDQSCK7 0x00000448 + #define RK1_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK8 0x0000044c + #define RK1_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK9 0x00000450 + #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R1 GENMASK(11, 6) + #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R1 GENMASK(17, 12) + #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R1 GENMASK(23, 18) +#define RK1_PRE_TDQSCK10 0x00000454 + #define RK1_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK11 0x00000458 + #define RK1_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK12 0x0000045c + #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R1 GENMASK(11, 6) + #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R1 GENMASK(17, 12) + #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R1 GENMASK(23, 18) +#define RK2_DQSOSC 0x00000500 + #define RK2_DQSOSC_FREQ_RATIO_TX_0 GENMASK(4, 0) + #define RK2_DQSOSC_FREQ_RATIO_TX_1 GENMASK(9, 5) + #define RK2_DQSOSC_FREQ_RATIO_TX_2 GENMASK(14, 10) + #define RK2_DQSOSC_FREQ_RATIO_TX_3 GENMASK(19, 15) + #define RK2_DQSOSC_FREQ_RATIO_TX_4 GENMASK(24, 20) + #define RK2_DQSOSC_FREQ_RATIO_TX_5 GENMASK(29, 25) + #define RK2_DQSOSC_DQSOSCR_RK2EN BIT(30) + #define RK2_DQSOSC_DQSOSC_RK2INTCLR BIT(31) +#define RK2_DUMMY_RD_WDATA0 0x00000518 + #define RK2_DUMMY_RD_WDATA0_DMY_RD_RK2_WDATA0 GENMASK(31, 0) +#define RK2_DUMMY_RD_WDATA1 0x0000051c + #define RK2_DUMMY_RD_WDATA1_DMY_RD_RK2_WDATA1 GENMASK(31, 0) +#define RK2_DUMMY_RD_WDATA2 0x00000520 + #define RK2_DUMMY_RD_WDATA2_DMY_RD_RK2_WDATA2 GENMASK(31, 0) +#define RK2_DUMMY_RD_WDATA3 0x00000524 + #define RK2_DUMMY_RD_WDATA3_DMY_RD_RK2_WDATA3 GENMASK(31, 0) +#define RK2_DUMMY_RD_ADR 0x00000528 + #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_ROW_ADR GENMASK(16, 0) + #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_COL_ADR GENMASK(27, 17) + #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_LEN GENMASK(31, 28) +#define RK2_DUMMY_RD_BK 0x0000052c + #define RK2_DUMMY_RD_BK_DMY_RD_RK2_BK GENMASK(2, 0) + #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6 GENMASK(7, 3) + #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7 GENMASK(12, 8) + #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_8 GENMASK(17, 13) +#define RK2_PRE_TDQSCK1 0x00000530 + #define RK2_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK2 0x00000534 + #define RK2_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK3 0x00000538 + #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R2 GENMASK(11, 6) + #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R2 GENMASK(17, 12) + #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R2 GENMASK(23, 18) +#define RK2_PRE_TDQSCK4 0x0000053c + #define RK2_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK5 0x00000540 + #define RK2_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK6 0x00000544 + #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R2 GENMASK(11, 6) + #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R2 GENMASK(17, 12) + #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R2 GENMASK(23, 18) +#define RK2_PRE_TDQSCK7 0x00000548 + #define RK2_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK8 0x0000054c + #define RK2_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK9 0x00000550 + #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R2 GENMASK(11, 6) + #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R2 GENMASK(17, 12) + #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R2 GENMASK(23, 18) +#define RK2_PRE_TDQSCK10 0x00000554 + #define RK2_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK11 0x00000558 + #define RK2_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK12 0x0000055c + #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R2 GENMASK(11, 6) + #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R2 GENMASK(17, 12) + #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R2 GENMASK(23, 18) +#define SHU_ACTIM0 0x00000800 + #define SHU_ACTIM0_TWTR GENMASK(3, 0) + #define SHU_ACTIM0_TWR GENMASK(12, 8) + #define SHU_ACTIM0_TRRD GENMASK(18, 16) + #define SHU_ACTIM0_TRCD GENMASK(27, 24) +#define SHU_ACTIM1 0x00000804 + #define SHU_ACTIM1_TRPAB GENMASK(2, 0) + #define SHU_ACTIM1_TRP GENMASK(11, 8) + #define SHU_ACTIM1_TRAS GENMASK(19, 16) + #define SHU_ACTIM1_TRC GENMASK(28, 24) +#define SHU_ACTIM2 0x00000808 + #define SHU_ACTIM2_TXP GENMASK(2, 0) + #define SHU_ACTIM2_TRTP GENMASK(10, 8) + #define SHU_ACTIM2_TR2W GENMASK(19, 16) + #define SHU_ACTIM2_TFAW GENMASK(28, 24) +#define SHU_ACTIM3 0x0000080c + #define SHU_ACTIM3_TRFCPB GENMASK(7, 0) + #define SHU_ACTIM3_TRFC GENMASK(23, 16) + #define SHU_ACTIM3_REFCNT GENMASK(31, 24) +#define SHU_ACTIM4 0x00000810 + #define SHU_ACTIM4_TXREFCNT GENMASK(9, 0) + #define SHU_ACTIM4_REFCNT_FR_CLK GENMASK(23, 16) + #define SHU_ACTIM4_TZQCS GENMASK(31, 24) +#define SHU_ACTIM5 0x00000814 + #define SHU_ACTIM5_TR2PD GENMASK(4, 0) + #define SHU_ACTIM5_TWTPD GENMASK(12, 8) + #define SHU_ACTIM5_TMRR2W GENMASK(27, 24) +#define SHU_ACTIM6 0x00000818 + #define SHU_ACTIM6_BGTCCD GENMASK(1, 0) + #define SHU_ACTIM6_BGTWTR GENMASK(7, 4) + #define SHU_ACTIM6_TWRMPR GENMASK(11, 8) + #define SHU_ACTIM6_BGTRRD GENMASK(14, 12) +#define SHU_ACTIM_XRT 0x0000081c + #define SHU_ACTIM_XRT_XRTR2R GENMASK(4, 0) + #define SHU_ACTIM_XRT_XRTR2W GENMASK(11, 8) + #define SHU_ACTIM_XRT_XRTW2R GENMASK(18, 16) + #define SHU_ACTIM_XRT_XRTW2W GENMASK(27, 24) +#define SHU_AC_TIME_05T 0x00000820 + #define SHU_AC_TIME_05T_TRC_05T BIT(0) + #define SHU_AC_TIME_05T_TRFCPB_05T BIT(1) + #define SHU_AC_TIME_05T_TRFC_05T BIT(2) + #define SHU_AC_TIME_05T_TXP_05T BIT(4) + #define SHU_AC_TIME_05T_TRTP_05T BIT(5) + #define SHU_AC_TIME_05T_TRCD_05T BIT(6) + #define SHU_AC_TIME_05T_TRP_05T BIT(7) + #define SHU_AC_TIME_05T_TRPAB_05T BIT(8) + #define SHU_AC_TIME_05T_TRAS_05T BIT(9) + #define SHU_AC_TIME_05T_TWR_M05T BIT(10) + #define SHU_AC_TIME_05T_TRRD_05T BIT(12) + #define SHU_AC_TIME_05T_TFAW_05T BIT(13) + #define SHU_AC_TIME_05T_TR2PD_05T BIT(15) + #define SHU_AC_TIME_05T_TWTPD_M05T BIT(16) + #define SHU_AC_TIME_05T_BGTRRD_05T BIT(21) + #define SHU_AC_TIME_05T_BGTCCD_05T BIT(22) + #define SHU_AC_TIME_05T_BGTWTR_05T BIT(23) + #define SHU_AC_TIME_05T_TR2W_05T BIT(24) + #define SHU_AC_TIME_05T_TWTR_M05T BIT(25) + #define SHU_AC_TIME_05T_XRTR2W_05T BIT(26) + #define SHU_AC_TIME_05T_XRTW2R_M05T BIT(27) +#define SHU_AC_DERATING0 0x00000824 + #define SHU_AC_DERATING0_ACDERATEEN BIT(0) + #define SHU_AC_DERATING0_TRRD_DERATE GENMASK(18, 16) + #define SHU_AC_DERATING0_TRCD_DERATE GENMASK(27, 24) +#define SHU_AC_DERATING1 0x00000828 + #define SHU_AC_DERATING1_TRPAB_DERATE GENMASK(2, 0) + #define SHU_AC_DERATING1_TRP_DERATE GENMASK(11, 8) + #define SHU_AC_DERATING1_TRAS_DERATE GENMASK(19, 16) + #define SHU_AC_DERATING1_TRC_DERATE GENMASK(28, 24) +#define SHU_AC_DERATING_05T 0x00000830 + #define SHU_AC_DERATING_05T_TRC_05T_DERATE BIT(0) + #define SHU_AC_DERATING_05T_TRCD_05T_DERATE BIT(6) + #define SHU_AC_DERATING_05T_TRP_05T_DERATE BIT(7) + #define SHU_AC_DERATING_05T_TRPAB_05T_DERATE BIT(8) + #define SHU_AC_DERATING_05T_TRAS_05T_DERATE BIT(9) + #define SHU_AC_DERATING_05T_TRRD_05T_DERATE BIT(12) +#define SHU_CONF0 0x00000840 + #define SHU_CONF0_DMPGTIM GENMASK(5, 0) + #define SHU_CONF0_ADVREFEN BIT(6) + #define SHU_CONF0_ADVPREEN BIT(7) + #define SHU_CONF0_TRFCPBIG BIT(9) + #define SHU_CONF0_REFTHD GENMASK(15, 12) + #define SHU_CONF0_REQQUE_DEPTH GENMASK(19, 16) + #define SHU_CONF0_FREQDIV4 BIT(24) + #define SHU_CONF0_FDIV2 BIT(25) + #define SHU_CONF0_CL2 BIT(27) + #define SHU_CONF0_BL2 BIT(28) + #define SHU_CONF0_BL4 BIT(29) + #define SHU_CONF0_MATYPE GENMASK(31, 30) +#define SHU_CONF1 0x00000844 + #define SHU_CONF1_DATLAT GENMASK(4, 0) + #define SHU_CONF1_DATLAT_DSEL GENMASK(12, 8) + #define SHU_CONF1_REFBW_FR GENMASK(25, 16) + #define SHU_CONF1_DATLAT_DSEL_PHY GENMASK(30, 26) + #define SHU_CONF1_TREFBWIG BIT(31) +#define SHU_CONF2 0x00000848 + #define SHU_CONF2_TCMDO1LAT GENMASK(7, 0) + #define SHU_CONF2_FSPCHG_PRDCNT GENMASK(15, 8) + #define SHU_CONF2_DCMDLYREF GENMASK(18, 16) + #define SHU_CONF2_DQCMD BIT(25) + #define SHU_CONF2_DQ16COM1 BIT(26) + #define SHU_CONF2_RA15TOCS1 BIT(27) + #define SHU_CONF2_WPRE2T BIT(28) + #define SHU_CONF2_FASTWAKE2 BIT(29) + #define SHU_CONF2_DAREFEN BIT(30) + #define SHU_CONF2_FASTWAKE BIT(31) +#define SHU_CONF3 0x0000084c + #define SHU_CONF3_ZQCSCNT GENMASK(15, 0) + #define SHU_CONF3_REFRCNT GENMASK(24, 16) +#define SHU_STBCAL 0x00000850 + #define SHU_STBCAL_DMSTBLAT GENMASK(1, 0) + #define SHU_STBCAL_PICGLAT GENMASK(6, 4) + #define SHU_STBCAL_DQSG_MODE BIT(8) +#define SHU_DQSOSCTHRD 0x00000854 + #define SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0 GENMASK(11, 0) + #define SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0 GENMASK(23, 12) + #define SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0 GENMASK(31, 24) +#define SHU_RANKCTL 0x00000858 + #define SHU_RANKCTL_RANKINCTL_RXDLY GENMASK(3, 0) + #define SHU_RANKCTL_TXRANKINCTL_TXDLY GENMASK(11, 8) + #define SHU_RANKCTL_TXRANKINCTL GENMASK(15, 12) + #define SHU_RANKCTL_TXRANKINCTL_ROOT GENMASK(19, 16) + #define SHU_RANKCTL_RANKINCTL GENMASK(23, 20) + #define SHU_RANKCTL_RANKINCTL_ROOT1 GENMASK(27, 24) + #define SHU_RANKCTL_RANKINCTL_PHY GENMASK(31, 28) +#define SHU_CKECTRL 0x0000085c + #define SHU_CKECTRL_CMDCKE GENMASK(18, 16) + #define SHU_CKECTRL_CKEPRD GENMASK(22, 20) + #define SHU_CKECTRL_TCKESRX GENMASK(25, 24) + #define SHU_CKECTRL_SREF_CK_DLY GENMASK(29, 28) +#define SHU_ODTCTRL 0x00000860 + #define SHU_ODTCTRL_ROEN BIT(0) + #define SHU_ODTCTRL_WOEN BIT(1) + #define SHU_ODTCTRL_RODTEN_SELPH_CG_IG BIT(2) + #define SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG BIT(3) + #define SHU_ODTCTRL_RODT GENMASK(7, 4) + #define SHU_ODTCTRL_TWODT GENMASK(22, 16) + #define SHU_ODTCTRL_FIXRODT BIT(27) + #define SHU_ODTCTRL_RODTE2 BIT(30) + #define SHU_ODTCTRL_RODTE BIT(31) +#define SHU_IMPCAL1 0x00000864 + #define SHU_IMPCAL1_IMPCAL_CHKCYCLE GENMASK(2, 0) + #define SHU_IMPCAL1_IMPDRVP GENMASK(8, 4) + #define SHU_IMPCAL1_IMPDRVN GENMASK(15, 11) + #define SHU_IMPCAL1_IMPCAL_CALEN_CYCLE GENMASK(19, 17) + #define SHU_IMPCAL1_IMPCALCNT GENMASK(27, 20) + #define SHU_IMPCAL1_IMPCAL_CALICNT GENMASK(31, 28) +#define SHU1_DQSOSC_PRD 0x00000868 + #define SHU1_DQSOSC_PRD_DQSOSC_PRDCNT GENMASK(9, 0) + #define SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8 GENMASK(19, 16) + #define SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1 GENMASK(31, 20) +#define SHU_DQSOSCR 0x0000086c + #define SHU_DQSOSCR_DQSOSCRCNT GENMASK(7, 0) + #define SHU_DQSOSCR_DQSOSC_DELTA GENMASK(31, 16) +#define SHU_DQSOSCR2 0x00000870 + #define SHU_DQSOSCR2_DQSOSCENCNT GENMASK(15, 0) + #define SHU_DQSOSCR2_DQSOSC_ADV_SEL GENMASK(17, 16) + #define SHU_DQSOSCR2_DQSOSC_DRS_ADV_SEL GENMASK(19, 18) +#define SHU_RODTENSTB 0x00000874 + #define SHU_RODTENSTB_RODTEN_MCK_MODESEL BIT(0) + #define SHU_RODTENSTB_RODTEN_P1_ENABLE BIT(1) + #define SHU_RODTENSTB_RODTENSTB_OFFSET GENMASK(7, 2) + #define SHU_RODTENSTB_RODTENSTB_EXT GENMASK(23, 8) + #define SHU_RODTENSTB_RODTENSTB_4BYTE_EN BIT(31) +#define SHU_PIPE 0x00000878 + #define SHU_PIPE_PHYRXPIPE1 BIT(0) + #define SHU_PIPE_PHYRXPIPE2 BIT(1) + #define SHU_PIPE_PHYRXPIPE3 BIT(2) + #define SHU_PIPE_PHYRXRDSLPIPE1 BIT(4) + #define SHU_PIPE_PHYRXRDSLPIPE2 BIT(5) + #define SHU_PIPE_PHYRXRDSLPIPE3 BIT(6) + #define SHU_PIPE_PHYPIPE1EN BIT(8) + #define SHU_PIPE_PHYPIPE2EN BIT(9) + #define SHU_PIPE_PHYPIPE3EN BIT(10) + #define SHU_PIPE_DLE_LAST_EXTEND3 BIT(26) + #define SHU_PIPE_READ_START_EXTEND3 BIT(27) + #define SHU_PIPE_DLE_LAST_EXTEND2 BIT(28) + #define SHU_PIPE_READ_START_EXTEND2 BIT(29) + #define SHU_PIPE_DLE_LAST_EXTEND1 BIT(30) + #define SHU_PIPE_READ_START_EXTEND1 BIT(31) +#define SHU_TEST1 0x0000087c + #define SHU_TEST1_LATNORMPOP GENMASK(12, 8) + #define SHU_TEST1_DQSICALBLCOK_CNT GENMASK(22, 20) + #define SHU_TEST1_DQSICALI_NEW BIT(23) +#define SHU_SELPH_CA1 0x00000880 + #define SHU_SELPH_CA1_TXDLY_CS GENMASK(2, 0) + #define SHU_SELPH_CA1_TXDLY_CKE GENMASK(6, 4) + #define SHU_SELPH_CA1_TXDLY_ODT GENMASK(10, 8) + #define SHU_SELPH_CA1_TXDLY_RESET GENMASK(14, 12) + #define SHU_SELPH_CA1_TXDLY_WE GENMASK(18, 16) + #define SHU_SELPH_CA1_TXDLY_CAS GENMASK(22, 20) + #define SHU_SELPH_CA1_TXDLY_RAS GENMASK(26, 24) + #define SHU_SELPH_CA1_TXDLY_CS1 GENMASK(30, 28) +#define SHU_SELPH_CA2 0x00000884 + #define SHU_SELPH_CA2_TXDLY_BA0 GENMASK(2, 0) + #define SHU_SELPH_CA2_TXDLY_BA1 GENMASK(6, 4) + #define SHU_SELPH_CA2_TXDLY_BA2 GENMASK(10, 8) + #define SHU_SELPH_CA2_TXDLY_CMD GENMASK(20, 16) + #define SHU_SELPH_CA2_TXDLY_CKE1 GENMASK(26, 24) +#define SHU_SELPH_CA3 0x00000888 + #define SHU_SELPH_CA3_TXDLY_RA0 GENMASK(2, 0) + #define SHU_SELPH_CA3_TXDLY_RA1 GENMASK(6, 4) + #define SHU_SELPH_CA3_TXDLY_RA2 GENMASK(10, 8) + #define SHU_SELPH_CA3_TXDLY_RA3 GENMASK(14, 12) + #define SHU_SELPH_CA3_TXDLY_RA4 GENMASK(18, 16) + #define SHU_SELPH_CA3_TXDLY_RA5 GENMASK(22, 20) + #define SHU_SELPH_CA3_TXDLY_RA6 GENMASK(26, 24) + #define SHU_SELPH_CA3_TXDLY_RA7 GENMASK(30, 28) +#define SHU_SELPH_CA4 0x0000088c + #define SHU_SELPH_CA4_TXDLY_RA8 GENMASK(2, 0) + #define SHU_SELPH_CA4_TXDLY_RA9 GENMASK(6, 4) + #define SHU_SELPH_CA4_TXDLY_RA10 GENMASK(10, 8) + #define SHU_SELPH_CA4_TXDLY_RA11 GENMASK(14, 12) + #define SHU_SELPH_CA4_TXDLY_RA12 GENMASK(18, 16) + #define SHU_SELPH_CA4_TXDLY_RA13 GENMASK(22, 20) + #define SHU_SELPH_CA4_TXDLY_RA14 GENMASK(26, 24) + #define SHU_SELPH_CA4_TXDLY_RA15 GENMASK(30, 28) +#define SHU_SELPH_CA5 0x00000890 + #define SHU_SELPH_CA5_DLY_CS GENMASK(2, 0) + #define SHU_SELPH_CA5_DLY_CKE GENMASK(6, 4) + #define SHU_SELPH_CA5_DLY_ODT GENMASK(10, 8) + #define SHU_SELPH_CA5_DLY_RESET GENMASK(14, 12) + #define SHU_SELPH_CA5_DLY_WE GENMASK(18, 16) + #define SHU_SELPH_CA5_DLY_CAS GENMASK(22, 20) + #define SHU_SELPH_CA5_DLY_RAS GENMASK(26, 24) + #define SHU_SELPH_CA5_DLY_CS1 GENMASK(30, 28) +#define SHU_SELPH_CA6 0x00000894 + #define SHU_SELPH_CA6_DLY_BA0 GENMASK(2, 0) + #define SHU_SELPH_CA6_DLY_BA1 GENMASK(6, 4) + #define SHU_SELPH_CA6_DLY_BA2 GENMASK(10, 8) + #define SHU_SELPH_CA6_DLY_CKE1 GENMASK(26, 24) +#define SHU_SELPH_CA7 0x00000898 + #define SHU_SELPH_CA7_DLY_RA0 GENMASK(2, 0) + #define SHU_SELPH_CA7_DLY_RA1 GENMASK(6, 4) + #define SHU_SELPH_CA7_DLY_RA2 GENMASK(10, 8) + #define SHU_SELPH_CA7_DLY_RA3 GENMASK(14, 12) + #define SHU_SELPH_CA7_DLY_RA4 GENMASK(18, 16) + #define SHU_SELPH_CA7_DLY_RA5 GENMASK(22, 20) + #define SHU_SELPH_CA7_DLY_RA6 GENMASK(26, 24) + #define SHU_SELPH_CA7_DLY_RA7 GENMASK(30, 28) +#define SHU_SELPH_CA8 0x0000089c + #define SHU_SELPH_CA8_DLY_RA8 GENMASK(2, 0) + #define SHU_SELPH_CA8_DLY_RA9 GENMASK(6, 4) + #define SHU_SELPH_CA8_DLY_RA10 GENMASK(10, 8) + #define SHU_SELPH_CA8_DLY_RA11 GENMASK(14, 12) + #define SHU_SELPH_CA8_DLY_RA12 GENMASK(18, 16) + #define SHU_SELPH_CA8_DLY_RA13 GENMASK(22, 20) + #define SHU_SELPH_CA8_DLY_RA14 GENMASK(26, 24) + #define SHU_SELPH_CA8_DLY_RA15 GENMASK(30, 28) +#define SHU_SELPH_DQS0 0x000008a0 + #define SHU_SELPH_DQS0_TXDLY_DQS0 GENMASK(2, 0) + #define SHU_SELPH_DQS0_TXDLY_DQS1 GENMASK(6, 4) + #define SHU_SELPH_DQS0_TXDLY_DQS2 GENMASK(10, 8) + #define SHU_SELPH_DQS0_TXDLY_DQS3 GENMASK(14, 12) + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS0 GENMASK(18, 16) + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS1 GENMASK(22, 20) + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS2 GENMASK(26, 24) + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS3 GENMASK(30, 28) +#define SHU_SELPH_DQS1 0x000008a4 + #define SHU_SELPH_DQS1_DLY_DQS0 GENMASK(2, 0) + #define SHU_SELPH_DQS1_DLY_DQS1 GENMASK(6, 4) + #define SHU_SELPH_DQS1_DLY_DQS2 GENMASK(10, 8) + #define SHU_SELPH_DQS1_DLY_DQS3 GENMASK(14, 12) + #define SHU_SELPH_DQS1_DLY_OEN_DQS0 GENMASK(18, 16) + #define SHU_SELPH_DQS1_DLY_OEN_DQS1 GENMASK(22, 20) + #define SHU_SELPH_DQS1_DLY_OEN_DQS2 GENMASK(26, 24) + #define SHU_SELPH_DQS1_DLY_OEN_DQS3 GENMASK(30, 28) +#define SHU1_DRVING1 0x000008a8 + #define SHU1_DRVING1_DQDRVN2 GENMASK(4, 0) + #define SHU1_DRVING1_DQDRVP2 GENMASK(9, 5) + #define SHU1_DRVING1_DQSDRVN1 GENMASK(14, 10) + #define SHU1_DRVING1_DQSDRVP1 GENMASK(19, 15) + #define SHU1_DRVING1_DQSDRVN2 GENMASK(24, 20) + #define SHU1_DRVING1_DQSDRVP2 GENMASK(29, 25) + #define SHU1_DRVING1_DIS_IMP_ODTN_TRACK BIT(30) + #define SHU1_DRVING1_DIS_IMPCAL_HW BIT(31) +#define SHU1_DRVING2 0x000008ac + #define SHU1_DRVING2_CMDDRVN1 GENMASK(4, 0) + #define SHU1_DRVING2_CMDDRVP1 GENMASK(9, 5) + #define SHU1_DRVING2_CMDDRVN2 GENMASK(14, 10) + #define SHU1_DRVING2_CMDDRVP2 GENMASK(19, 15) + #define SHU1_DRVING2_DQDRVN1 GENMASK(24, 20) + #define SHU1_DRVING2_DQDRVP1 GENMASK(29, 25) + #define SHU1_DRVING2_DIS_IMPCAL_ODT_EN BIT(31) +#define SHU1_DRVING3 0x000008b0 + #define SHU1_DRVING3_DQODTN2 GENMASK(4, 0) + #define SHU1_DRVING3_DQODTP2 GENMASK(9, 5) + #define SHU1_DRVING3_DQSODTN GENMASK(14, 10) + #define SHU1_DRVING3_DQSODTP GENMASK(19, 15) + #define SHU1_DRVING3_DQSODTN2 GENMASK(24, 20) + #define SHU1_DRVING3_DQSODTP2 GENMASK(29, 25) +#define SHU1_DRVING4 0x000008b4 + #define SHU1_DRVING4_CMDODTN1 GENMASK(4, 0) + #define SHU1_DRVING4_CMDODTP1 GENMASK(9, 5) + #define SHU1_DRVING4_CMDODTN2 GENMASK(14, 10) + #define SHU1_DRVING4_CMDODTP2 GENMASK(19, 15) + #define SHU1_DRVING4_DQODTN1 GENMASK(24, 20) + #define SHU1_DRVING4_DQODTP1 GENMASK(29, 25) +#define SHU1_DRVING5 0x000008b8 + #define SHU1_DRVING5_DQCODTN2 GENMASK(4, 0) + #define SHU1_DRVING5_DQCODTP2 GENMASK(9, 5) + #define SHU1_DRVING5_DQCDRVN1 GENMASK(14, 10) + #define SHU1_DRVING5_DQCDRVP1 GENMASK(19, 15) + #define SHU1_DRVING5_DQCDRVN2 GENMASK(24, 20) + #define SHU1_DRVING5_DQCDRVP2 GENMASK(29, 25) +#define SHU1_DRVING6 0x000008bc + #define SHU1_DRVING6_DQCODTN1 GENMASK(24, 20) + #define SHU1_DRVING6_DQCODTP1 GENMASK(29, 25) +#define SHU1_WODT 0x000008c0 + #define SHU1_WODT_DISWODT GENMASK(2, 0) + #define SHU1_WODT_WODTFIX BIT(3) + #define SHU1_WODT_WODTFIXOFF BIT(4) + #define SHU1_WODT_DISWODTE BIT(5) + #define SHU1_WODT_DISWODTE2 BIT(6) + #define SHU1_WODT_WODTPDEN BIT(7) + #define SHU1_WODT_DQOE_CNT GENMASK(10, 8) + #define SHU1_WODT_DQOE_OPT BIT(11) + #define SHU1_WODT_TXUPD_SEL GENMASK(13, 12) + #define SHU1_WODT_TXUPD_W2R_SEL GENMASK(16, 14) + #define SHU1_WODT_DBIWR BIT(29) + #define SHU1_WODT_TWPSTEXT BIT(30) + #define SHU1_WODT_WPST2T BIT(31) +#define SHU1_DQSG 0x000008c4 + #define SHU1_DQSG_DLLFRZRFCOPT GENMASK(1, 0) + #define SHU1_DQSG_DLLFRZWROPT GENMASK(5, 4) + #define SHU1_DQSG_R_RSTBCNT_LATCH_OPT GENMASK(10, 8) + #define SHU1_DQSG_STB_UPDMASK_EN BIT(11) + #define SHU1_DQSG_STB_UPDMASKCYC GENMASK(15, 12) + #define SHU1_DQSG_DQSINCTL_PRE_SEL BIT(16) + #define SHU1_DQSG_SCINTV GENMASK(25, 20) +#define SHU_SCINTV 0x000008c8 + #define SHU_SCINTV_ODTREN BIT(0) + #define SHU_SCINTV_TZQLAT GENMASK(5, 1) + #define SHU_SCINTV_TZQLAT2 GENMASK(10, 6) + #define SHU_SCINTV_RDDQC_INTV GENMASK(12, 11) + #define SHU_SCINTV_MRW_INTV GENMASK(17, 13) + #define SHU_SCINTV_DQS2DQ_SHU_PITHRD GENMASK(23, 18) + #define SHU_SCINTV_DQS2DQ_FILT_PITHRD GENMASK(29, 24) + #define SHU_SCINTV_DQSOSCENDIS BIT(30) +#define SHU_MISC 0x000008cc + #define SHU_MISC_REQQUE_MAXCNT GENMASK(3, 0) + #define SHU_MISC_CKEHCMD GENMASK(5, 4) + #define SHU_MISC_NORMPOP_LEN GENMASK(10, 8) + #define SHU_MISC_PREA_INTV GENMASK(16, 12) +#define SHU_DQS2DQ_TX 0x000008d0 + #define SHU_DQS2DQ_TX_OE2DQ_OFFSET GENMASK(4, 0) +#define SHU_HWSET_MR2 0x000008d4 + #define SHU_HWSET_MR2_HWSET_MR2_MRSMA GENMASK(12, 0) + #define SHU_HWSET_MR2_HWSET_MR2_OP GENMASK(23, 16) +#define SHU_HWSET_MR13 0x000008d8 + #define SHU_HWSET_MR13_HWSET_MR13_MRSMA GENMASK(12, 0) + #define SHU_HWSET_MR13_HWSET_MR13_OP GENMASK(23, 16) +#define SHU_HWSET_VRCG 0x000008dc + #define SHU_HWSET_VRCG_HWSET_VRCG_MRSMA GENMASK(12, 0) + #define SHU_HWSET_VRCG_HWSET_VRCG_OP GENMASK(23, 16) +#define SHU_APHY_TX_PICG_CTRL 0x000008e4 + #define SHU_APHY_TX_PICG_CTRL_APHYPI_CG_CK_SEL GENMASK(23, 20) + #define SHU_APHY_TX_PICG_CTRL_APHYPI_CG_CK_OPT BIT(24) + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL GENMASK(30, 27) + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_OPT BIT(31) +#define SHURK0_DQSCTL 0x00000a00 + #define SHURK0_DQSCTL_DQSINCTL GENMASK(3, 0) +#define SHURK0_DQSIEN 0x00000a04 + #define SHURK0_DQSIEN_R0DQS0IEN GENMASK(6, 0) + #define SHURK0_DQSIEN_R0DQS1IEN GENMASK(14, 8) + #define SHURK0_DQSIEN_R0DQS2IEN GENMASK(22, 16) + #define SHURK0_DQSIEN_R0DQS3IEN GENMASK(30, 24) +#define SHURK0_DQSCAL 0x00000a08 + #define SHURK0_DQSCAL_R0DQSIENLLMT GENMASK(6, 0) + #define SHURK0_DQSCAL_R0DQSIENLLMTEN BIT(7) + #define SHURK0_DQSCAL_R0DQSIENHLMT GENMASK(14, 8) + #define SHURK0_DQSCAL_R0DQSIENHLMTEN BIT(15) +#define SHU1RK0_PI 0x00000a0c + #define SHU1RK0_PI_RK0_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU1RK0_PI_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1RK0_PI_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1RK0_PI_RK0_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU1RK0_DQSOSC 0x00000a10 + #define SHU1RK0_DQSOSC_DQSOSC_BASE_RK0 GENMASK(15, 0) + #define SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1 GENMASK(31, 16) +#define SHURK0_SELPH_ODTEN0 0x00000a1c + #define SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN GENMASK(2, 0) + #define SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN GENMASK(10, 8) + #define SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN GENMASK(18, 16) + #define SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN GENMASK(26, 24) + #define SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHURK0_SELPH_ODTEN1 0x00000a20 + #define SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN GENMASK(2, 0) + #define SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN GENMASK(10, 8) + #define SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN GENMASK(18, 16) + #define SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN GENMASK(26, 24) + #define SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHURK0_SELPH_DQSG0 0x00000a24 + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED GENMASK(2, 0) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED GENMASK(10, 8) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED GENMASK(18, 16) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED GENMASK(26, 24) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK0_SELPH_DQSG1 0x00000a28 + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED GENMASK(2, 0) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED GENMASK(10, 8) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED GENMASK(18, 16) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED GENMASK(26, 24) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK0_SELPH_DQ0 0x00000a2c + #define SHURK0_SELPH_DQ0_TXDLY_DQ0 GENMASK(2, 0) + #define SHURK0_SELPH_DQ0_TXDLY_DQ1 GENMASK(6, 4) + #define SHURK0_SELPH_DQ0_TXDLY_DQ2 GENMASK(10, 8) + #define SHURK0_SELPH_DQ0_TXDLY_DQ3 GENMASK(14, 12) + #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0 GENMASK(18, 16) + #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1 GENMASK(22, 20) + #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2 GENMASK(26, 24) + #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3 GENMASK(30, 28) +#define SHURK0_SELPH_DQ1 0x00000a30 + #define SHURK0_SELPH_DQ1_TXDLY_DQM0 GENMASK(2, 0) + #define SHURK0_SELPH_DQ1_TXDLY_DQM1 GENMASK(6, 4) + #define SHURK0_SELPH_DQ1_TXDLY_DQM2 GENMASK(10, 8) + #define SHURK0_SELPH_DQ1_TXDLY_DQM3 GENMASK(14, 12) + #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0 GENMASK(18, 16) + #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1 GENMASK(22, 20) + #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2 GENMASK(26, 24) + #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3 GENMASK(30, 28) +#define SHURK0_SELPH_DQ2 0x00000a34 + #define SHURK0_SELPH_DQ2_DLY_DQ0 GENMASK(2, 0) + #define SHURK0_SELPH_DQ2_DLY_DQ1 GENMASK(6, 4) + #define SHURK0_SELPH_DQ2_DLY_DQ2 GENMASK(10, 8) + #define SHURK0_SELPH_DQ2_DLY_DQ3 GENMASK(14, 12) + #define SHURK0_SELPH_DQ2_DLY_OEN_DQ0 GENMASK(18, 16) + #define SHURK0_SELPH_DQ2_DLY_OEN_DQ1 GENMASK(22, 20) + #define SHURK0_SELPH_DQ2_DLY_OEN_DQ2 GENMASK(26, 24) + #define SHURK0_SELPH_DQ2_DLY_OEN_DQ3 GENMASK(30, 28) +#define SHURK0_SELPH_DQ3 0x00000a38 + #define SHURK0_SELPH_DQ3_DLY_DQM0 GENMASK(2, 0) + #define SHURK0_SELPH_DQ3_DLY_DQM1 GENMASK(6, 4) + #define SHURK0_SELPH_DQ3_DLY_DQM2 GENMASK(10, 8) + #define SHURK0_SELPH_DQ3_DLY_DQM3 GENMASK(14, 12) + #define SHURK0_SELPH_DQ3_DLY_OEN_DQM0 GENMASK(18, 16) + #define SHURK0_SELPH_DQ3_DLY_OEN_DQM1 GENMASK(22, 20) + #define SHURK0_SELPH_DQ3_DLY_OEN_DQM2 GENMASK(26, 24) + #define SHURK0_SELPH_DQ3_DLY_OEN_DQM3 GENMASK(30, 28) +#define SHU1RK0_DQS2DQ_CAL1 0x00000a40 + #define SHU1RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU1RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU1RK0_DQS2DQ_CAL2 0x00000a44 + #define SHU1RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU1RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU1RK0_DQS2DQ_CAL3 0x00000a48 + #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 GENMASK(5, 0) + #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 GENMASK(11, 6) + #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU1RK0_DQS2DQ_CAL4 0x00000a4c + #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 GENMASK(5, 0) + #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 GENMASK(11, 6) + #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU1RK0_DQS2DQ_CAL5 0x00000a50 + #define SHU1RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 GENMASK(10, 0) + #define SHU1RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 GENMASK(26, 16) +#define SHURK1_DQSCTL 0x00000b00 + #define SHURK1_DQSCTL_R1DQSINCTL GENMASK(3, 0) +#define SHURK1_DQSIEN 0x00000b04 + #define SHURK1_DQSIEN_R1DQS0IEN GENMASK(6, 0) + #define SHURK1_DQSIEN_R1DQS1IEN GENMASK(14, 8) + #define SHURK1_DQSIEN_R1DQS2IEN GENMASK(22, 16) + #define SHURK1_DQSIEN_R1DQS3IEN GENMASK(30, 24) +#define SHURK1_DQSCAL 0x00000b08 + #define SHURK1_DQSCAL_R1DQSIENLLMT GENMASK(6, 0) + #define SHURK1_DQSCAL_R1DQSIENLLMTEN BIT(7) + #define SHURK1_DQSCAL_R1DQSIENHLMT GENMASK(14, 8) + #define SHURK1_DQSCAL_R1DQSIENHLMTEN BIT(15) +#define SHU1RK1_PI 0x00000b0c + #define SHU1RK1_PI_RK1_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU1RK1_PI_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1RK1_PI_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1RK1_PI_RK1_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU1RK1_DQSOSC 0x00000b10 + #define SHU1RK1_DQSOSC_DQSOSC_BASE_RK1 GENMASK(15, 0) + #define SHU1RK1_DQSOSC_DQSOSC_BASE_RK1_B1 GENMASK(31, 16) +#define SHURK1_SELPH_ODTEN0 0x00000b1c + #define SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN GENMASK(2, 0) + #define SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN GENMASK(10, 8) + #define SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN GENMASK(18, 16) + #define SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN GENMASK(26, 24) + #define SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHURK1_SELPH_ODTEN1 0x00000b20 + #define SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN GENMASK(2, 0) + #define SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN GENMASK(10, 8) + #define SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN GENMASK(18, 16) + #define SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN GENMASK(26, 24) + #define SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHURK1_SELPH_DQSG0 0x00000b24 + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK1_SELPH_DQSG1 0x00000b28 + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK1_SELPH_DQ0 0x00000b2c + #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ0 GENMASK(2, 0) + #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ1 GENMASK(6, 4) + #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ2 GENMASK(10, 8) + #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ3 GENMASK(14, 12) + #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHURK1_SELPH_DQ1 0x00000b30 + #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM0 GENMASK(2, 0) + #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM1 GENMASK(6, 4) + #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM2 GENMASK(10, 8) + #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM3 GENMASK(14, 12) + #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHURK1_SELPH_DQ2 0x00000b34 + #define SHURK1_SELPH_DQ2_DLY_R1DQ0 GENMASK(2, 0) + #define SHURK1_SELPH_DQ2_DLY_R1DQ1 GENMASK(6, 4) + #define SHURK1_SELPH_DQ2_DLY_R1DQ2 GENMASK(10, 8) + #define SHURK1_SELPH_DQ2_DLY_R1DQ3 GENMASK(14, 12) + #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHURK1_SELPH_DQ3 0x00000b38 + #define SHURK1_SELPH_DQ3_DLY_R1DQM0 GENMASK(2, 0) + #define SHURK1_SELPH_DQ3_DLY_R1DQM1 GENMASK(6, 4) + #define SHURK1_SELPH_DQ3_DLY_R1DQM2 GENMASK(10, 8) + #define SHURK1_SELPH_DQ3_DLY_R1DQM3 GENMASK(14, 12) + #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU1RK1_DQS2DQ_CAL1 0x00000b40 + #define SHU1RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU1RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU1RK1_DQS2DQ_CAL2 0x00000b44 + #define SHU1RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU1RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU1RK1_DQS2DQ_CAL3 0x00000b48 + #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 GENMASK(5, 0) + #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 GENMASK(11, 6) + #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU1RK1_DQS2DQ_CAL4 0x00000b4c + #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 GENMASK(5, 0) + #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 GENMASK(11, 6) + #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU1RK1_DQS2DQ_CAL5 0x00000b50 + #define SHU1RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 GENMASK(10, 0) + #define SHU1RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 GENMASK(26, 16) +#define SHURK2_DQSCTL 0x00000c00 + #define SHURK2_DQSCTL_R2DQSINCTL GENMASK(3, 0) +#define SHURK2_DQSIEN 0x00000c04 + #define SHURK2_DQSIEN_R2DQS0IEN GENMASK(6, 0) + #define SHURK2_DQSIEN_R2DQS1IEN GENMASK(14, 8) + #define SHURK2_DQSIEN_R2DQS2IEN GENMASK(22, 16) + #define SHURK2_DQSIEN_R2DQS3IEN GENMASK(30, 24) +#define SHURK2_DQSCAL 0x00000c08 + #define SHURK2_DQSCAL_R2DQSIENLLMT GENMASK(6, 0) + #define SHURK2_DQSCAL_R2DQSIENLLMTEN BIT(7) + #define SHURK2_DQSCAL_R2DQSIENHLMT GENMASK(14, 8) + #define SHURK2_DQSCAL_R2DQSIENHLMTEN BIT(15) +#define SHU1RK2_PI 0x00000c0c + #define SHU1RK2_PI_RK2_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU1RK2_PI_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1RK2_PI_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1RK2_PI_RK2_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU1RK2_DQSOSC 0x00000c10 + #define SHU1RK2_DQSOSC_DQSOSC_BASE_RK2 GENMASK(15, 0) + #define SHU1RK2_DQSOSC_DQSOSC_BASE_RK2_B1 GENMASK(31, 16) +#define SHURK2_SELPH_ODTEN0 0x00000c1c + #define SHURK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN GENMASK(2, 0) + #define SHURK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHURK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN GENMASK(10, 8) + #define SHURK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHURK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN GENMASK(18, 16) + #define SHURK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHURK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN GENMASK(26, 24) + #define SHURK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHURK2_SELPH_ODTEN1 0x00000c20 + #define SHURK2_SELPH_ODTEN1_DLY_B0_R2RODTEN GENMASK(2, 0) + #define SHURK2_SELPH_ODTEN1_DLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHURK2_SELPH_ODTEN1_DLY_B1_R2RODTEN GENMASK(10, 8) + #define SHURK2_SELPH_ODTEN1_DLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHURK2_SELPH_ODTEN1_DLY_B2_R2RODTEN GENMASK(18, 16) + #define SHURK2_SELPH_ODTEN1_DLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHURK2_SELPH_ODTEN1_DLY_B3_R2RODTEN GENMASK(26, 24) + #define SHURK2_SELPH_ODTEN1_DLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHURK2_SELPH_DQSG0 0x00000c24 + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK2_SELPH_DQSG1 0x00000c28 + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK2_SELPH_DQ0 0x00000c2c + #define SHURK2_SELPH_DQ0_TX_DLY_R2DQ0 GENMASK(2, 0) + #define SHURK2_SELPH_DQ0_TX_DLY_R2DQ1 GENMASK(6, 4) + #define SHURK2_SELPH_DQ0_TX_DLY_R2DQ2 GENMASK(10, 8) + #define SHURK2_SELPH_DQ0_TX_DLY_R2DQ3 GENMASK(14, 12) + #define SHURK2_SELPH_DQ0_TX_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHURK2_SELPH_DQ0_TX_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHURK2_SELPH_DQ0_TX_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHURK2_SELPH_DQ0_TX_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHURK2_SELPH_DQ1 0x00000c30 + #define SHURK2_SELPH_DQ1_TX_DLY_R2DQM0 GENMASK(2, 0) + #define SHURK2_SELPH_DQ1_TX_DLY_R2DQM1 GENMASK(6, 4) + #define SHURK2_SELPH_DQ1_TX_DLY_R2DQM2 GENMASK(10, 8) + #define SHURK2_SELPH_DQ1_TX_DLY_R2DQM3 GENMASK(14, 12) + #define SHURK2_SELPH_DQ1_TX_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHURK2_SELPH_DQ1_TX_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHURK2_SELPH_DQ1_TX_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHURK2_SELPH_DQ1_TX_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHURK2_SELPH_DQ2 0x00000c34 + #define SHURK2_SELPH_DQ2_DLY_R2DQ0 GENMASK(2, 0) + #define SHURK2_SELPH_DQ2_DLY_R2DQ1 GENMASK(6, 4) + #define SHURK2_SELPH_DQ2_DLY_R2DQ2 GENMASK(10, 8) + #define SHURK2_SELPH_DQ2_DLY_R2DQ3 GENMASK(14, 12) + #define SHURK2_SELPH_DQ2_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHURK2_SELPH_DQ2_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHURK2_SELPH_DQ2_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHURK2_SELPH_DQ2_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHURK2_SELPH_DQ3 0x00000c38 + #define SHURK2_SELPH_DQ3_DLY_R2DQM0 GENMASK(2, 0) + #define SHURK2_SELPH_DQ3_DLY_R2DQM1 GENMASK(6, 4) + #define SHURK2_SELPH_DQ3_DLY_R2DQM2 GENMASK(10, 8) + #define SHURK2_SELPH_DQ3_DLY_R2DQM3 GENMASK(14, 12) + #define SHURK2_SELPH_DQ3_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHURK2_SELPH_DQ3_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHURK2_SELPH_DQ3_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHURK2_SELPH_DQ3_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU1RK2_DQS2DQ_CAL1 0x00000c40 + #define SHU1RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU1RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU1RK2_DQS2DQ_CAL2 0x00000c44 + #define SHU1RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU1RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU1RK2_DQS2DQ_CAL3 0x00000c48 + #define SHU1RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ0 GENMASK(5, 0) + #define SHU1RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ1 GENMASK(11, 6) +#define SHU1RK2_DQS2DQ_CAL4 0x00000c4c + #define SHU1RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM0 GENMASK(5, 0) + #define SHU1RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM1 GENMASK(11, 6) +#define SHU1RK2_DQS2DQ_CAL5 0x00000c50 + #define SHU1RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM0 GENMASK(10, 0) + #define SHU1RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM1 GENMASK(26, 16) +#define SHU_DQSG_RETRY 0x00000c54 + #define SHU_DQSG_RETRY_R_DQSGRETRY_SW_RESET BIT(0) + #define SHU_DQSG_RETRY_R_DQSG_RETRY_SW_EN BIT(1) + #define SHU_DQSG_RETRY_R_DDR1866_PLUS BIT(2) + #define SHU_DQSG_RETRY_R_RETRY_ONCE BIT(3) + #define SHU_DQSG_RETRY_R_RETRY_3TIMES BIT(4) + #define SHU_DQSG_RETRY_R_RETRY_1RANK BIT(5) + #define SHU_DQSG_RETRY_R_RETRY_SAV_MSK BIT(6) + #define SHU_DQSG_RETRY_R_DM4BYTE BIT(7) + #define SHU_DQSG_RETRY_R_DQSIENLAT GENMASK(11, 8) + #define SHU_DQSG_RETRY_R_STBENCMP_ALLBYTE BIT(12) + #define SHU_DQSG_RETRY_R_XSR_DQSG_RETRY_EN BIT(13) + #define SHU_DQSG_RETRY_R_XSR_RETRY_SPM_MODE BIT(14) + #define SHU_DQSG_RETRY_R_RETRY_CMP_DATA BIT(15) + #define SHU_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK BIT(20) + #define SHU_DQSG_RETRY_R_RDY_SEL_DLE BIT(21) + #define SHU_DQSG_RETRY_R_RETRY_ROUND_NUM GENMASK(25, 24) + #define SHU_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY BIT(28) + #define SHU_DQSG_RETRY_R_RETRY_PA_DSIABLE BIT(29) + #define SHU_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK BIT(30) + #define SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE BIT(31) +#define SHU2_ACTIM0 0x00000e00 + #define SHU2_ACTIM0_TWTR GENMASK(3, 0) + #define SHU2_ACTIM0_TWR GENMASK(12, 8) + #define SHU2_ACTIM0_TRRD GENMASK(18, 16) + #define SHU2_ACTIM0_TRCD GENMASK(27, 24) +#define SHU2_ACTIM1 0x00000e04 + #define SHU2_ACTIM1_TRPAB GENMASK(2, 0) + #define SHU2_ACTIM1_TRP GENMASK(11, 8) + #define SHU2_ACTIM1_TRAS GENMASK(19, 16) + #define SHU2_ACTIM1_TRC GENMASK(28, 24) +#define SHU2_ACTIM2 0x00000e08 + #define SHU2_ACTIM2_TXP GENMASK(2, 0) + #define SHU2_ACTIM2_TRTP GENMASK(10, 8) + #define SHU2_ACTIM2_TR2W GENMASK(19, 16) + #define SHU2_ACTIM2_TFAW GENMASK(28, 24) +#define SHU2_ACTIM3 0x00000e0c + #define SHU2_ACTIM3_TRFCPB GENMASK(7, 0) + #define SHU2_ACTIM3_TRFC GENMASK(23, 16) + #define SHU2_ACTIM3_REFCNT GENMASK(31, 24) +#define SHU2_ACTIM4 0x00000e10 + #define SHU2_ACTIM4_TXREFCNT GENMASK(9, 0) + #define SHU2_ACTIM4_REFCNT_FR_CLK GENMASK(23, 16) + #define SHU2_ACTIM4_TZQCS GENMASK(31, 24) +#define SHU2_ACTIM5 0x00000e14 + #define SHU2_ACTIM5_TR2PD GENMASK(4, 0) + #define SHU2_ACTIM5_TWTPD GENMASK(12, 8) + #define SHU2_ACTIM5_TMRR2W GENMASK(27, 24) +#define SHU2_ACTIM6 0x00000e18 + #define SHU2_ACTIM6_BGTCCD GENMASK(1, 0) + #define SHU2_ACTIM6_BGTWTR GENMASK(7, 4) + #define SHU2_ACTIM6_TWRMPR GENMASK(11, 8) + #define SHU2_ACTIM6_BGTRRD GENMASK(14, 12) +#define SHU2_ACTIM_XRT 0x00000e1c + #define SHU2_ACTIM_XRT_XRTR2R GENMASK(4, 0) + #define SHU2_ACTIM_XRT_XRTR2W GENMASK(11, 8) + #define SHU2_ACTIM_XRT_XRTW2R GENMASK(18, 16) + #define SHU2_ACTIM_XRT_XRTW2W GENMASK(27, 24) +#define SHU2_AC_TIME_05T 0x00000e20 + #define SHU2_AC_TIME_05T_TRC_05T BIT(0) + #define SHU2_AC_TIME_05T_TRFCPB_05T BIT(1) + #define SHU2_AC_TIME_05T_TRFC_05T BIT(2) + #define SHU2_AC_TIME_05T_TXP_05T BIT(4) + #define SHU2_AC_TIME_05T_TRTP_05T BIT(5) + #define SHU2_AC_TIME_05T_TRCD_05T BIT(6) + #define SHU2_AC_TIME_05T_TRP_05T BIT(7) + #define SHU2_AC_TIME_05T_TRPAB_05T BIT(8) + #define SHU2_AC_TIME_05T_TRAS_05T BIT(9) + #define SHU2_AC_TIME_05T_TWR_M05T BIT(10) + #define SHU2_AC_TIME_05T_TRRD_05T BIT(12) + #define SHU2_AC_TIME_05T_TFAW_05T BIT(13) + #define SHU2_AC_TIME_05T_TR2PD_05T BIT(15) + #define SHU2_AC_TIME_05T_TWTPD_M05T BIT(16) + #define SHU2_AC_TIME_05T_BGTRRD_05T BIT(21) + #define SHU2_AC_TIME_05T_BGTCCD_05T BIT(22) + #define SHU2_AC_TIME_05T_BGTWTR_05T BIT(23) + #define SHU2_AC_TIME_05T_TR2W_05T BIT(24) + #define SHU2_AC_TIME_05T_TWTR_M05T BIT(25) + #define SHU2_AC_TIME_05T_XRTR2W_05T BIT(26) + #define SHU2_AC_TIME_05T_XRTW2R_M05T BIT(27) +#define SHU2_AC_DERATING0 0x00000e24 + #define SHU2_AC_DERATING0_ACDERATEEN BIT(0) + #define SHU2_AC_DERATING0_TRRD_DERATE GENMASK(18, 16) + #define SHU2_AC_DERATING0_TRCD_DERATE GENMASK(27, 24) +#define SHU2_AC_DERATING1 0x00000e28 + #define SHU2_AC_DERATING1_TRPAB_DERATE GENMASK(2, 0) + #define SHU2_AC_DERATING1_TRP_DERATE GENMASK(11, 8) + #define SHU2_AC_DERATING1_TRAS_DERATE GENMASK(19, 16) + #define SHU2_AC_DERATING1_TRC_DERATE GENMASK(28, 24) +#define SHU2_AC_DERATING_05T 0x00000e30 + #define SHU2_AC_DERATING_05T_TRC_05T_DERATE BIT(0) + #define SHU2_AC_DERATING_05T_TRCD_05T_DERATE BIT(6) + #define SHU2_AC_DERATING_05T_TRP_05T_DERATE BIT(7) + #define SHU2_AC_DERATING_05T_TRPAB_05T_DERATE BIT(8) + #define SHU2_AC_DERATING_05T_TRAS_05T_DERATE BIT(9) + #define SHU2_AC_DERATING_05T_TRRD_05T_DERATE BIT(12) +#define SHU2_CONF0 0x00000e40 + #define SHU2_CONF0_DMPGTIM GENMASK(5, 0) + #define SHU2_CONF0_ADVREFEN BIT(6) + #define SHU2_CONF0_ADVPREEN BIT(7) + #define SHU2_CONF0_TRFCPBIG BIT(9) + #define SHU2_CONF0_REFTHD GENMASK(15, 12) + #define SHU2_CONF0_REQQUE_DEPTH GENMASK(19, 16) + #define SHU2_CONF0_FREQDIV4 BIT(24) + #define SHU2_CONF0_FDIV2 BIT(25) + #define SHU2_CONF0_CL2 BIT(27) + #define SHU2_CONF0_BL2 BIT(28) + #define SHU2_CONF0_BL4 BIT(29) + #define SHU2_CONF0_MATYPE GENMASK(31, 30) +#define SHU2_CONF1 0x00000e44 + #define SHU2_CONF1_DATLAT GENMASK(4, 0) + #define SHU2_CONF1_DATLAT_DSEL GENMASK(12, 8) + #define SHU2_CONF1_REFBW_FR GENMASK(25, 16) + #define SHU2_CONF1_DATLAT_DSEL_PHY GENMASK(30, 26) + #define SHU2_CONF1_TREFBWIG BIT(31) +#define SHU2_CONF2 0x00000e48 + #define SHU2_CONF2_TCMDO1LAT GENMASK(7, 0) + #define SHU2_CONF2_FSPCHG_PRDCNT GENMASK(15, 8) + #define SHU2_CONF2_DCMDLYREF GENMASK(18, 16) + #define SHU2_CONF2_DQCMD BIT(25) + #define SHU2_CONF2_DQ16COM1 BIT(26) + #define SHU2_CONF2_RA15TOCS1 BIT(27) + #define SHU2_CONF2_WPRE2T BIT(28) + #define SHU2_CONF2_FASTWAKE2 BIT(29) + #define SHU2_CONF2_DAREFEN BIT(30) + #define SHU2_CONF2_FASTWAKE BIT(31) +#define SHU2_CONF3 0x00000e4c + #define SHU2_CONF3_ZQCSCNT GENMASK(15, 0) + #define SHU2_CONF3_REFRCNT GENMASK(24, 16) +#define SHU2_STBCAL 0x00000e50 + #define SHU2_STBCAL_DMSTBLAT GENMASK(1, 0) + #define SHU2_STBCAL_PICGLAT GENMASK(6, 4) + #define SHU2_STBCAL_DQSG_MODE BIT(8) +#define SHU2_DQSOSCTHRD 0x00000e54 + #define SHU2_DQSOSCTHRD_DQSOSCTHRD_INC_RK0 GENMASK(11, 0) + #define SHU2_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0 GENMASK(23, 12) + #define SHU2_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0 GENMASK(31, 24) +#define SHU2_RANKCTL 0x00000e58 + #define SHU2_RANKCTL_RANKINCTL_RXDLY GENMASK(3, 0) + #define SHU2_RANKCTL_TXRANKINCTL_TXDLY GENMASK(11, 8) + #define SHU2_RANKCTL_TXRANKINCTL GENMASK(15, 12) + #define SHU2_RANKCTL_TXRANKINCTL_ROOT GENMASK(19, 16) + #define SHU2_RANKCTL_RANKINCTL GENMASK(23, 20) + #define SHU2_RANKCTL_RANKINCTL_ROOT1 GENMASK(27, 24) + #define SHU2_RANKCTL_RANKINCTL_PHY GENMASK(31, 28) +#define SHU2_CKECTRL 0x00000e5c + #define SHU2_CKECTRL_CMDCKE GENMASK(18, 16) + #define SHU2_CKECTRL_CKEPRD GENMASK(22, 20) + #define SHU2_CKECTRL_TCKESRX GENMASK(25, 24) + #define SHU2_CKECTRL_SREF_CK_DLY GENMASK(29, 28) +#define SHU2_ODTCTRL 0x00000e60 + #define SHU2_ODTCTRL_ROEN BIT(0) + #define SHU2_ODTCTRL_WOEN BIT(1) + #define SHU2_ODTCTRL_RODTEN_SELPH_CG_IG BIT(2) + #define SHU2_ODTCTRL_RODTENSTB_SELPH_CG_IG BIT(3) + #define SHU2_ODTCTRL_RODT GENMASK(7, 4) + #define SHU2_ODTCTRL_TWODT GENMASK(22, 16) + #define SHU2_ODTCTRL_FIXRODT BIT(27) + #define SHU2_ODTCTRL_RODTE2 BIT(30) + #define SHU2_ODTCTRL_RODTE BIT(31) +#define SHU2_IMPCAL1 0x00000e64 + #define SHU2_IMPCAL1_IMPCAL_CHKCYCLE GENMASK(2, 0) + #define SHU2_IMPCAL1_IMPDRVP GENMASK(8, 4) + #define SHU2_IMPCAL1_IMPDRVN GENMASK(15, 11) + #define SHU2_IMPCAL1_IMPCAL_CALEN_CYCLE GENMASK(19, 17) + #define SHU2_IMPCAL1_IMPCALCNT GENMASK(27, 20) + #define SHU2_IMPCAL1_IMPCAL_CALICNT GENMASK(31, 28) +#define SHU2_DQSOSC_PRD 0x00000e68 + #define SHU2_DQSOSC_PRD_DQSOSC_PRDCNT GENMASK(9, 0) + #define SHU2_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8 GENMASK(19, 16) + #define SHU2_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1 GENMASK(31, 20) +#define SHU2_DQSOSCR 0x00000e6c + #define SHU2_DQSOSCR_DQSOSCRCNT GENMASK(7, 0) + #define SHU2_DQSOSCR_DQSOSC_DELTA GENMASK(31, 16) +#define SHU2_DQSOSCR2 0x00000e70 + #define SHU2_DQSOSCR2_DQSOSCENCNT GENMASK(15, 0) + #define SHU2_DQSOSCR2_DQSOSC_ADV_SEL GENMASK(17, 16) + #define SHU2_DQSOSCR2_DQSOSC_DRS_ADV_SEL GENMASK(19, 18) +#define SHU2_RODTENSTB 0x00000e74 + #define SHU2_RODTENSTB_RODTEN_MCK_MODESEL BIT(0) + #define SHU2_RODTENSTB_RODTEN_P1_ENABLE BIT(1) + #define SHU2_RODTENSTB_RODTENSTB_OFFSET GENMASK(7, 2) + #define SHU2_RODTENSTB_RODTENSTB_EXT GENMASK(23, 8) + #define SHU2_RODTENSTB_RODTENSTB_4BYTE_EN BIT(31) +#define SHU2_PIPE 0x00000e78 + #define SHU2_PIPE_PHYRXPIPE1 BIT(0) + #define SHU2_PIPE_PHYRXPIPE2 BIT(1) + #define SHU2_PIPE_PHYRXPIPE3 BIT(2) + #define SHU2_PIPE_PHYRXRDSLPIPE1 BIT(4) + #define SHU2_PIPE_PHYRXRDSLPIPE2 BIT(5) + #define SHU2_PIPE_PHYRXRDSLPIPE3 BIT(6) + #define SHU2_PIPE_PHYPIPE1EN BIT(8) + #define SHU2_PIPE_PHYPIPE2EN BIT(9) + #define SHU2_PIPE_PHYPIPE3EN BIT(10) + #define SHU2_PIPE_DLE_LAST_EXTEND3 BIT(26) + #define SHU2_PIPE_READ_START_EXTEND3 BIT(27) + #define SHU2_PIPE_DLE_LAST_EXTEND2 BIT(28) + #define SHU2_PIPE_READ_START_EXTEND2 BIT(29) + #define SHU2_PIPE_DLE_LAST_EXTEND1 BIT(30) + #define SHU2_PIPE_READ_START_EXTEND1 BIT(31) +#define SHU2_TEST1 0x00000e7c + #define SHU2_TEST1_LATNORMPOP GENMASK(12, 8) + #define SHU2_TEST1_DQSICALBLCOK_CNT GENMASK(22, 20) + #define SHU2_TEST1_DQSICALI_NEW BIT(23) +#define SHU2_SELPH_CA1 0x00000e80 + #define SHU2_SELPH_CA1_TXDLY_CS GENMASK(2, 0) + #define SHU2_SELPH_CA1_TXDLY_CKE GENMASK(6, 4) + #define SHU2_SELPH_CA1_TXDLY_ODT GENMASK(10, 8) + #define SHU2_SELPH_CA1_TXDLY_RESET GENMASK(14, 12) + #define SHU2_SELPH_CA1_TXDLY_WE GENMASK(18, 16) + #define SHU2_SELPH_CA1_TXDLY_CAS GENMASK(22, 20) + #define SHU2_SELPH_CA1_TXDLY_RAS GENMASK(26, 24) + #define SHU2_SELPH_CA1_TXDLY_CS1 GENMASK(30, 28) +#define SHU2_SELPH_CA2 0x00000e84 + #define SHU2_SELPH_CA2_TXDLY_BA0 GENMASK(2, 0) + #define SHU2_SELPH_CA2_TXDLY_BA1 GENMASK(6, 4) + #define SHU2_SELPH_CA2_TXDLY_BA2 GENMASK(10, 8) + #define SHU2_SELPH_CA2_TXDLY_CMD GENMASK(20, 16) + #define SHU2_SELPH_CA2_TXDLY_CKE1 GENMASK(26, 24) +#define SHU2_SELPH_CA3 0x00000e88 + #define SHU2_SELPH_CA3_TXDLY_RA0 GENMASK(2, 0) + #define SHU2_SELPH_CA3_TXDLY_RA1 GENMASK(6, 4) + #define SHU2_SELPH_CA3_TXDLY_RA2 GENMASK(10, 8) + #define SHU2_SELPH_CA3_TXDLY_RA3 GENMASK(14, 12) + #define SHU2_SELPH_CA3_TXDLY_RA4 GENMASK(18, 16) + #define SHU2_SELPH_CA3_TXDLY_RA5 GENMASK(22, 20) + #define SHU2_SELPH_CA3_TXDLY_RA6 GENMASK(26, 24) + #define SHU2_SELPH_CA3_TXDLY_RA7 GENMASK(30, 28) +#define SHU2_SELPH_CA4 0x00000e8c + #define SHU2_SELPH_CA4_TXDLY_RA8 GENMASK(2, 0) + #define SHU2_SELPH_CA4_TXDLY_RA9 GENMASK(6, 4) + #define SHU2_SELPH_CA4_TXDLY_RA10 GENMASK(10, 8) + #define SHU2_SELPH_CA4_TXDLY_RA11 GENMASK(14, 12) + #define SHU2_SELPH_CA4_TXDLY_RA12 GENMASK(18, 16) + #define SHU2_SELPH_CA4_TXDLY_RA13 GENMASK(22, 20) + #define SHU2_SELPH_CA4_TXDLY_RA14 GENMASK(26, 24) + #define SHU2_SELPH_CA4_TXDLY_RA15 GENMASK(30, 28) +#define SHU2_SELPH_CA5 0x00000e90 + #define SHU2_SELPH_CA5_DLY_CS GENMASK(2, 0) + #define SHU2_SELPH_CA5_DLY_CKE GENMASK(6, 4) + #define SHU2_SELPH_CA5_DLY_ODT GENMASK(10, 8) + #define SHU2_SELPH_CA5_DLY_RESET GENMASK(14, 12) + #define SHU2_SELPH_CA5_DLY_WE GENMASK(18, 16) + #define SHU2_SELPH_CA5_DLY_CAS GENMASK(22, 20) + #define SHU2_SELPH_CA5_DLY_RAS GENMASK(26, 24) + #define SHU2_SELPH_CA5_DLY_CS1 GENMASK(30, 28) +#define SHU2_SELPH_CA6 0x00000e94 + #define SHU2_SELPH_CA6_DLY_BA0 GENMASK(2, 0) + #define SHU2_SELPH_CA6_DLY_BA1 GENMASK(6, 4) + #define SHU2_SELPH_CA6_DLY_BA2 GENMASK(10, 8) + #define SHU2_SELPH_CA6_DLY_CKE1 GENMASK(26, 24) +#define SHU2_SELPH_CA7 0x00000e98 + #define SHU2_SELPH_CA7_DLY_RA0 GENMASK(2, 0) + #define SHU2_SELPH_CA7_DLY_RA1 GENMASK(6, 4) + #define SHU2_SELPH_CA7_DLY_RA2 GENMASK(10, 8) + #define SHU2_SELPH_CA7_DLY_RA3 GENMASK(14, 12) + #define SHU2_SELPH_CA7_DLY_RA4 GENMASK(18, 16) + #define SHU2_SELPH_CA7_DLY_RA5 GENMASK(22, 20) + #define SHU2_SELPH_CA7_DLY_RA6 GENMASK(26, 24) + #define SHU2_SELPH_CA7_DLY_RA7 GENMASK(30, 28) +#define SHU2_SELPH_CA8 0x00000e9c + #define SHU2_SELPH_CA8_DLY_RA8 GENMASK(2, 0) + #define SHU2_SELPH_CA8_DLY_RA9 GENMASK(6, 4) + #define SHU2_SELPH_CA8_DLY_RA10 GENMASK(10, 8) + #define SHU2_SELPH_CA8_DLY_RA11 GENMASK(14, 12) + #define SHU2_SELPH_CA8_DLY_RA12 GENMASK(18, 16) + #define SHU2_SELPH_CA8_DLY_RA13 GENMASK(22, 20) + #define SHU2_SELPH_CA8_DLY_RA14 GENMASK(26, 24) + #define SHU2_SELPH_CA8_DLY_RA15 GENMASK(30, 28) +#define SHU2_SELPH_DQS0 0x00000ea0 + #define SHU2_SELPH_DQS0_TXDLY_DQS0 GENMASK(2, 0) + #define SHU2_SELPH_DQS0_TXDLY_DQS1 GENMASK(6, 4) + #define SHU2_SELPH_DQS0_TXDLY_DQS2 GENMASK(10, 8) + #define SHU2_SELPH_DQS0_TXDLY_DQS3 GENMASK(14, 12) + #define SHU2_SELPH_DQS0_TXDLY_OEN_DQS0 GENMASK(18, 16) + #define SHU2_SELPH_DQS0_TXDLY_OEN_DQS1 GENMASK(22, 20) + #define SHU2_SELPH_DQS0_TXDLY_OEN_DQS2 GENMASK(26, 24) + #define SHU2_SELPH_DQS0_TXDLY_OEN_DQS3 GENMASK(30, 28) +#define SHU2_SELPH_DQS1 0x00000ea4 + #define SHU2_SELPH_DQS1_DLY_DQS0 GENMASK(2, 0) + #define SHU2_SELPH_DQS1_DLY_DQS1 GENMASK(6, 4) + #define SHU2_SELPH_DQS1_DLY_DQS2 GENMASK(10, 8) + #define SHU2_SELPH_DQS1_DLY_DQS3 GENMASK(14, 12) + #define SHU2_SELPH_DQS1_DLY_OEN_DQS0 GENMASK(18, 16) + #define SHU2_SELPH_DQS1_DLY_OEN_DQS1 GENMASK(22, 20) + #define SHU2_SELPH_DQS1_DLY_OEN_DQS2 GENMASK(26, 24) + #define SHU2_SELPH_DQS1_DLY_OEN_DQS3 GENMASK(30, 28) +#define SHU2_DRVING1 0x00000ea8 + #define SHU2_DRVING1_DQDRVN2 GENMASK(4, 0) + #define SHU2_DRVING1_DQDRVP2 GENMASK(9, 5) + #define SHU2_DRVING1_DQSDRVN1 GENMASK(14, 10) + #define SHU2_DRVING1_DQSDRVP1 GENMASK(19, 15) + #define SHU2_DRVING1_DQSDRVN2 GENMASK(24, 20) + #define SHU2_DRVING1_DQSDRVP2 GENMASK(29, 25) + #define SHU2_DRVING1_DIS_IMP_ODTN_TRACK BIT(30) + #define SHU2_DRVING1_DIS_IMPCAL_HW BIT(31) +#define SHU2_DRVING2 0x00000eac + #define SHU2_DRVING2_CMDDRVN1 GENMASK(4, 0) + #define SHU2_DRVING2_CMDDRVP1 GENMASK(9, 5) + #define SHU2_DRVING2_CMDDRVN2 GENMASK(14, 10) + #define SHU2_DRVING2_CMDDRVP2 GENMASK(19, 15) + #define SHU2_DRVING2_DQDRVN1 GENMASK(24, 20) + #define SHU2_DRVING2_DQDRVP1 GENMASK(29, 25) + #define SHU2_DRVING2_DIS_IMPCAL_ODT_EN BIT(31) +#define SHU2_DRVING3 0x00000eb0 + #define SHU2_DRVING3_DQODTN2 GENMASK(4, 0) + #define SHU2_DRVING3_DQODTP2 GENMASK(9, 5) + #define SHU2_DRVING3_DQSODTN GENMASK(14, 10) + #define SHU2_DRVING3_DQSODTP GENMASK(19, 15) + #define SHU2_DRVING3_DQSODTN2 GENMASK(24, 20) + #define SHU2_DRVING3_DQSODTP2 GENMASK(29, 25) +#define SHU2_DRVING4 0x00000eb4 + #define SHU2_DRVING4_CMDODTN1 GENMASK(4, 0) + #define SHU2_DRVING4_CMDODTP1 GENMASK(9, 5) + #define SHU2_DRVING4_CMDODTN2 GENMASK(14, 10) + #define SHU2_DRVING4_CMDODTP2 GENMASK(19, 15) + #define SHU2_DRVING4_DQODTN1 GENMASK(24, 20) + #define SHU2_DRVING4_DQODTP1 GENMASK(29, 25) +#define SHU2_DRVING5 0x00000eb8 + #define SHU2_DRVING5_DQCODTN2 GENMASK(4, 0) + #define SHU2_DRVING5_DQCODTP2 GENMASK(9, 5) + #define SHU2_DRVING5_DQCDRVN1 GENMASK(14, 10) + #define SHU2_DRVING5_DQCDRVP1 GENMASK(19, 15) + #define SHU2_DRVING5_DQCDRVN2 GENMASK(24, 20) + #define SHU2_DRVING5_DQCDRVP2 GENMASK(29, 25) +#define SHU2_DRVING6 0x00000ebc + #define SHU2_DRVING6_DQCODTN1 GENMASK(24, 20) + #define SHU2_DRVING6_DQCODTP1 GENMASK(29, 25) +#define SHU2_WODT 0x00000ec0 + #define SHU2_WODT_DISWODT GENMASK(2, 0) + #define SHU2_WODT_WODTFIX BIT(3) + #define SHU2_WODT_WODTFIXOFF BIT(4) + #define SHU2_WODT_DISWODTE BIT(5) + #define SHU2_WODT_DISWODTE2 BIT(6) + #define SHU2_WODT_WODTPDEN BIT(7) + #define SHU2_WODT_DQOE_CNT GENMASK(10, 8) + #define SHU2_WODT_DQOE_OPT BIT(11) + #define SHU2_WODT_TXUPD_SEL GENMASK(13, 12) + #define SHU2_WODT_TXUPD_W2R_SEL GENMASK(16, 14) + #define SHU2_WODT_DBIWR BIT(29) + #define SHU2_WODT_TWPSTEXT BIT(30) + #define SHU2_WODT_WPST2T BIT(31) +#define SHU2_DQSG 0x00000ec4 + #define SHU2_DQSG_DLLFRZRFCOPT GENMASK(1, 0) + #define SHU2_DQSG_DLLFRZWROPT GENMASK(5, 4) + #define SHU2_DQSG_R_RSTBCNT_LATCH_OPT GENMASK(10, 8) + #define SHU2_DQSG_STB_UPDMASK_EN BIT(11) + #define SHU2_DQSG_STB_UPDMASKCYC GENMASK(15, 12) + #define SHU2_DQSG_DQSINCTL_PRE_SEL BIT(16) + #define SHU2_DQSG_SCINTV GENMASK(25, 20) +#define SHU2_SCINTV 0x00000ec8 + #define SHU2_SCINTV_ODTREN BIT(0) + #define SHU2_SCINTV_TZQLAT GENMASK(5, 1) + #define SHU2_SCINTV_TZQLAT2 GENMASK(10, 6) + #define SHU2_SCINTV_RDDQC_INTV GENMASK(12, 11) + #define SHU2_SCINTV_MRW_INTV GENMASK(17, 13) + #define SHU2_SCINTV_DQS2DQ_SHU_PITHRD GENMASK(23, 18) + #define SHU2_SCINTV_DQS2DQ_FILT_PITHRD GENMASK(29, 24) + #define SHU2_SCINTV_DQSOSCENDIS BIT(30) +#define SHU2_MISC 0x00000ecc + #define SHU2_MISC_REQQUE_MAXCNT GENMASK(3, 0) + #define SHU2_MISC_CKEHCMD GENMASK(5, 4) + #define SHU2_MISC_NORMPOP_LEN GENMASK(10, 8) + #define SHU2_MISC_PREA_INTV GENMASK(16, 12) +#define SHU2_DQS2DQ_TX 0x00000ed0 + #define SHU2_DQS2DQ_TX_OE2DQ_OFFSET GENMASK(4, 0) +#define SHU2_HWSET_MR2 0x00000ed4 + #define SHU2_HWSET_MR2_HWSET_MR2_MRSMA GENMASK(12, 0) + #define SHU2_HWSET_MR2_HWSET_MR2_OP GENMASK(23, 16) +#define SHU2_HWSET_MR13 0x00000ed8 + #define SHU2_HWSET_MR13_HWSET_MR13_MRSMA GENMASK(12, 0) + #define SHU2_HWSET_MR13_HWSET_MR13_OP GENMASK(23, 16) +#define SHU2_HWSET_VRCG 0x00000edc + #define SHU2_HWSET_VRCG_HWSET_VRCG_MRSMA GENMASK(12, 0) + #define SHU2_HWSET_VRCG_HWSET_VRCG_OP GENMASK(23, 16) +#define SHU2_APHY_TX_PICG_CTRL 0x00000ee4 + #define SHU2_APHY_TX_PICG_CTRL_APHYPI_CG_CK_SEL GENMASK(23, 20) + #define SHU2_APHY_TX_PICG_CTRL_APHYPI_CG_CK_OPT BIT(24) + #define SHU2_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL GENMASK(30, 27) + #define SHU2_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_OPT BIT(31) +#define SHU2RK0_DQSCTL 0x00001000 + #define SHU2RK0_DQSCTL_DQSINCTL GENMASK(3, 0) +#define SHU2RK0_DQSIEN 0x00001004 + #define SHU2RK0_DQSIEN_R0DQS0IEN GENMASK(6, 0) + #define SHU2RK0_DQSIEN_R0DQS1IEN GENMASK(14, 8) + #define SHU2RK0_DQSIEN_R0DQS2IEN GENMASK(22, 16) + #define SHU2RK0_DQSIEN_R0DQS3IEN GENMASK(30, 24) +#define SHU2RK0_DQSCAL 0x00001008 + #define SHU2RK0_DQSCAL_R0DQSIENLLMT GENMASK(6, 0) + #define SHU2RK0_DQSCAL_R0DQSIENLLMTEN BIT(7) + #define SHU2RK0_DQSCAL_R0DQSIENHLMT GENMASK(14, 8) + #define SHU2RK0_DQSCAL_R0DQSIENHLMTEN BIT(15) +#define SHU2RK0_PI 0x0000100c + #define SHU2RK0_PI_RK0_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU2RK0_PI_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2RK0_PI_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2RK0_PI_RK0_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU2RK0_DQSOSC 0x00001010 + #define SHU2RK0_DQSOSC_DQSOSC_BASE_RK0 GENMASK(15, 0) + #define SHU2RK0_DQSOSC_DQSOSC_BASE_RK0_B1 GENMASK(31, 16) +#define SHU2RK0_SELPH_ODTEN0 0x0000101c + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN GENMASK(2, 0) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN GENMASK(10, 8) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN GENMASK(18, 16) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN GENMASK(26, 24) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU2RK0_SELPH_ODTEN1 0x00001020 + #define SHU2RK0_SELPH_ODTEN1_DLY_B0_RODTEN GENMASK(2, 0) + #define SHU2RK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU2RK0_SELPH_ODTEN1_DLY_B1_RODTEN GENMASK(10, 8) + #define SHU2RK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU2RK0_SELPH_ODTEN1_DLY_B2_RODTEN GENMASK(18, 16) + #define SHU2RK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU2RK0_SELPH_ODTEN1_DLY_B3_RODTEN GENMASK(26, 24) + #define SHU2RK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQSG0 0x00001024 + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQSG1 0x00001028 + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQ0 0x0000102c + #define SHU2RK0_SELPH_DQ0_TXDLY_DQ0 GENMASK(2, 0) + #define SHU2RK0_SELPH_DQ0_TXDLY_DQ1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQ0_TXDLY_DQ2 GENMASK(10, 8) + #define SHU2RK0_SELPH_DQ0_TXDLY_DQ3 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQ0_TXDLY_OEN_DQ0 GENMASK(18, 16) + #define SHU2RK0_SELPH_DQ0_TXDLY_OEN_DQ1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQ0_TXDLY_OEN_DQ2 GENMASK(26, 24) + #define SHU2RK0_SELPH_DQ0_TXDLY_OEN_DQ3 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQ1 0x00001030 + #define SHU2RK0_SELPH_DQ1_TXDLY_DQM0 GENMASK(2, 0) + #define SHU2RK0_SELPH_DQ1_TXDLY_DQM1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQ1_TXDLY_DQM2 GENMASK(10, 8) + #define SHU2RK0_SELPH_DQ1_TXDLY_DQM3 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQ1_TXDLY_OEN_DQM0 GENMASK(18, 16) + #define SHU2RK0_SELPH_DQ1_TXDLY_OEN_DQM1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQ1_TXDLY_OEN_DQM2 GENMASK(26, 24) + #define SHU2RK0_SELPH_DQ1_TXDLY_OEN_DQM3 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQ2 0x00001034 + #define SHU2RK0_SELPH_DQ2_DLY_DQ0 GENMASK(2, 0) + #define SHU2RK0_SELPH_DQ2_DLY_DQ1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQ2_DLY_DQ2 GENMASK(10, 8) + #define SHU2RK0_SELPH_DQ2_DLY_DQ3 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQ2_DLY_OEN_DQ0 GENMASK(18, 16) + #define SHU2RK0_SELPH_DQ2_DLY_OEN_DQ1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQ2_DLY_OEN_DQ2 GENMASK(26, 24) + #define SHU2RK0_SELPH_DQ2_DLY_OEN_DQ3 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQ3 0x00001038 + #define SHU2RK0_SELPH_DQ3_DLY_DQM0 GENMASK(2, 0) + #define SHU2RK0_SELPH_DQ3_DLY_DQM1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQ3_DLY_DQM2 GENMASK(10, 8) + #define SHU2RK0_SELPH_DQ3_DLY_DQM3 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQ3_DLY_OEN_DQM0 GENMASK(18, 16) + #define SHU2RK0_SELPH_DQ3_DLY_OEN_DQM1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQ3_DLY_OEN_DQM2 GENMASK(26, 24) + #define SHU2RK0_SELPH_DQ3_DLY_OEN_DQM3 GENMASK(30, 28) +#define SHU2RK0_DQS2DQ_CAL1 0x00001040 + #define SHU2RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU2RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU2RK0_DQS2DQ_CAL2 0x00001044 + #define SHU2RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU2RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU2RK0_DQS2DQ_CAL3 0x00001048 + #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 GENMASK(5, 0) + #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 GENMASK(11, 6) + #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU2RK0_DQS2DQ_CAL4 0x0000104c + #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 GENMASK(5, 0) + #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 GENMASK(11, 6) + #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU2RK0_DQS2DQ_CAL5 0x00001050 + #define SHU2RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 GENMASK(10, 0) + #define SHU2RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 GENMASK(26, 16) +#define SHU2RK1_DQSCTL 0x00001100 + #define SHU2RK1_DQSCTL_R1DQSINCTL GENMASK(3, 0) +#define SHU2RK1_DQSIEN 0x00001104 + #define SHU2RK1_DQSIEN_R1DQS0IEN GENMASK(6, 0) + #define SHU2RK1_DQSIEN_R1DQS1IEN GENMASK(14, 8) + #define SHU2RK1_DQSIEN_R1DQS2IEN GENMASK(22, 16) + #define SHU2RK1_DQSIEN_R1DQS3IEN GENMASK(30, 24) +#define SHU2RK1_DQSCAL 0x00001108 + #define SHU2RK1_DQSCAL_R1DQSIENLLMT GENMASK(6, 0) + #define SHU2RK1_DQSCAL_R1DQSIENLLMTEN BIT(7) + #define SHU2RK1_DQSCAL_R1DQSIENHLMT GENMASK(14, 8) + #define SHU2RK1_DQSCAL_R1DQSIENHLMTEN BIT(15) +#define SHU2RK1_PI 0x0000110c + #define SHU2RK1_PI_RK1_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU2RK1_PI_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2RK1_PI_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2RK1_PI_RK1_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU2RK1_DQSOSC 0x00001110 + #define SHU2RK1_DQSOSC_DQSOSC_BASE_RK1 GENMASK(15, 0) + #define SHU2RK1_DQSOSC_DQSOSC_BASE_RK1_B1 GENMASK(31, 16) +#define SHU2RK1_SELPH_ODTEN0 0x0000111c + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU2RK1_SELPH_ODTEN1 0x00001120 + #define SHU2RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU2RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU2RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU2RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU2RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU2RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU2RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU2RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQSG0 0x00001124 + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQSG1 0x00001128 + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQ0 0x0000112c + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1DQ0 GENMASK(2, 0) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1DQ1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1DQ2 GENMASK(10, 8) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1DQ3 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQ1 0x00001130 + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1DQM0 GENMASK(2, 0) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1DQM1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1DQM2 GENMASK(10, 8) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1DQM3 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQ2 0x00001134 + #define SHU2RK1_SELPH_DQ2_DLY_R1DQ0 GENMASK(2, 0) + #define SHU2RK1_SELPH_DQ2_DLY_R1DQ1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQ2_DLY_R1DQ2 GENMASK(10, 8) + #define SHU2RK1_SELPH_DQ2_DLY_R1DQ3 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQ2_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU2RK1_SELPH_DQ2_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQ2_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU2RK1_SELPH_DQ2_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQ3 0x00001138 + #define SHU2RK1_SELPH_DQ3_DLY_R1DQM0 GENMASK(2, 0) + #define SHU2RK1_SELPH_DQ3_DLY_R1DQM1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQ3_DLY_R1DQM2 GENMASK(10, 8) + #define SHU2RK1_SELPH_DQ3_DLY_R1DQM3 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQ3_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU2RK1_SELPH_DQ3_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQ3_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU2RK1_SELPH_DQ3_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU2RK1_DQS2DQ_CAL1 0x00001140 + #define SHU2RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU2RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU2RK1_DQS2DQ_CAL2 0x00001144 + #define SHU2RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU2RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU2RK1_DQS2DQ_CAL3 0x00001148 + #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 GENMASK(5, 0) + #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 GENMASK(11, 6) + #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU2RK1_DQS2DQ_CAL4 0x0000114c + #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 GENMASK(5, 0) + #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 GENMASK(11, 6) + #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU2RK1_DQS2DQ_CAL5 0x00001150 + #define SHU2RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 GENMASK(10, 0) + #define SHU2RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 GENMASK(26, 16) +#define SHU2RK2_DQSCTL 0x00001200 + #define SHU2RK2_DQSCTL_R2DQSINCTL GENMASK(3, 0) +#define SHU2RK2_DQSIEN 0x00001204 + #define SHU2RK2_DQSIEN_R2DQS0IEN GENMASK(6, 0) + #define SHU2RK2_DQSIEN_R2DQS1IEN GENMASK(14, 8) + #define SHU2RK2_DQSIEN_R2DQS2IEN GENMASK(22, 16) + #define SHU2RK2_DQSIEN_R2DQS3IEN GENMASK(30, 24) +#define SHU2RK2_DQSCAL 0x00001208 + #define SHU2RK2_DQSCAL_R2DQSIENLLMT GENMASK(6, 0) + #define SHU2RK2_DQSCAL_R2DQSIENLLMTEN BIT(7) + #define SHU2RK2_DQSCAL_R2DQSIENHLMT GENMASK(14, 8) + #define SHU2RK2_DQSCAL_R2DQSIENHLMTEN BIT(15) +#define SHU2RK2_PI 0x0000120c + #define SHU2RK2_PI_RK2_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU2RK2_PI_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2RK2_PI_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2RK2_PI_RK2_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU2RK2_DQSOSC 0x00001210 + #define SHU2RK2_DQSOSC_DQSOSC_BASE_RK2 GENMASK(15, 0) + #define SHU2RK2_DQSOSC_DQSOSC_BASE_RK2_B1 GENMASK(31, 16) +#define SHU2RK2_SELPH_ODTEN0 0x0000121c + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU2RK2_SELPH_ODTEN1 0x00001220 + #define SHU2RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU2RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU2RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU2RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU2RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU2RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU2RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU2RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQSG0 0x00001224 + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQSG1 0x00001228 + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQ0 0x0000122c + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2DQ0 GENMASK(2, 0) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2DQ1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2DQ2 GENMASK(10, 8) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2DQ3 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQ1 0x00001230 + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2DQM0 GENMASK(2, 0) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2DQM1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2DQM2 GENMASK(10, 8) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2DQM3 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQ2 0x00001234 + #define SHU2RK2_SELPH_DQ2_DLY_R2DQ0 GENMASK(2, 0) + #define SHU2RK2_SELPH_DQ2_DLY_R2DQ1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQ2_DLY_R2DQ2 GENMASK(10, 8) + #define SHU2RK2_SELPH_DQ2_DLY_R2DQ3 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQ2_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU2RK2_SELPH_DQ2_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQ2_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU2RK2_SELPH_DQ2_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQ3 0x00001238 + #define SHU2RK2_SELPH_DQ3_DLY_R2DQM0 GENMASK(2, 0) + #define SHU2RK2_SELPH_DQ3_DLY_R2DQM1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQ3_DLY_R2DQM2 GENMASK(10, 8) + #define SHU2RK2_SELPH_DQ3_DLY_R2DQM3 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQ3_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU2RK2_SELPH_DQ3_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQ3_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU2RK2_SELPH_DQ3_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU2RK2_DQS2DQ_CAL1 0x00001240 + #define SHU2RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU2RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU2RK2_DQS2DQ_CAL2 0x00001244 + #define SHU2RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU2RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU2RK2_DQS2DQ_CAL3 0x00001248 + #define SHU2RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ0 GENMASK(5, 0) + #define SHU2RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ1 GENMASK(11, 6) +#define SHU2RK2_DQS2DQ_CAL4 0x0000124c + #define SHU2RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM0 GENMASK(5, 0) + #define SHU2RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM1 GENMASK(11, 6) +#define SHU2RK2_DQS2DQ_CAL5 0x00001250 + #define SHU2RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM0 GENMASK(10, 0) + #define SHU2RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM1 GENMASK(26, 16) +#define SHU2_DQSG_RETRY 0x00001254 + #define SHU2_DQSG_RETRY_R_DQSGRETRY_SW_RESET BIT(0) + #define SHU2_DQSG_RETRY_R_DQSG_RETRY_SW_EN BIT(1) + #define SHU2_DQSG_RETRY_R_DDR1866_PLUS BIT(2) + #define SHU2_DQSG_RETRY_R_RETRY_ONCE BIT(3) + #define SHU2_DQSG_RETRY_R_RETRY_3TIMES BIT(4) + #define SHU2_DQSG_RETRY_R_RETRY_1RANK BIT(5) + #define SHU2_DQSG_RETRY_R_RETRY_SAV_MSK BIT(6) + #define SHU2_DQSG_RETRY_R_DM4BYTE BIT(7) + #define SHU2_DQSG_RETRY_R_DQSIENLAT GENMASK(11, 8) + #define SHU2_DQSG_RETRY_R_STBENCMP_ALLBYTE BIT(12) + #define SHU2_DQSG_RETRY_R_XSR_DQSG_RETRY_EN BIT(13) + #define SHU2_DQSG_RETRY_R_XSR_RETRY_SPM_MODE BIT(14) + #define SHU2_DQSG_RETRY_R_RETRY_CMP_DATA BIT(15) + #define SHU2_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK BIT(20) + #define SHU2_DQSG_RETRY_R_RDY_SEL_DLE BIT(21) + #define SHU2_DQSG_RETRY_R_RETRY_ROUND_NUM GENMASK(25, 24) + #define SHU2_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY BIT(28) + #define SHU2_DQSG_RETRY_R_RETRY_PA_DSIABLE BIT(29) + #define SHU2_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK BIT(30) + #define SHU2_DQSG_RETRY_R_RETRY_USE_BURST_MDOE BIT(31) +#define SHU3_ACTIM0 0x00001400 + #define SHU3_ACTIM0_TWTR GENMASK(3, 0) + #define SHU3_ACTIM0_TWR GENMASK(12, 8) + #define SHU3_ACTIM0_TRRD GENMASK(18, 16) + #define SHU3_ACTIM0_TRCD GENMASK(27, 24) +#define SHU3_ACTIM1 0x00001404 + #define SHU3_ACTIM1_TRPAB GENMASK(2, 0) + #define SHU3_ACTIM1_TRP GENMASK(11, 8) + #define SHU3_ACTIM1_TRAS GENMASK(19, 16) + #define SHU3_ACTIM1_TRC GENMASK(28, 24) +#define SHU3_ACTIM2 0x00001408 + #define SHU3_ACTIM2_TXP GENMASK(2, 0) + #define SHU3_ACTIM2_TRTP GENMASK(10, 8) + #define SHU3_ACTIM2_TR2W GENMASK(19, 16) + #define SHU3_ACTIM2_TFAW GENMASK(28, 24) +#define SHU3_ACTIM3 0x0000140c + #define SHU3_ACTIM3_TRFCPB GENMASK(7, 0) + #define SHU3_ACTIM3_TRFC GENMASK(23, 16) + #define SHU3_ACTIM3_REFCNT GENMASK(31, 24) +#define SHU3_ACTIM4 0x00001410 + #define SHU3_ACTIM4_TXREFCNT GENMASK(9, 0) + #define SHU3_ACTIM4_REFCNT_FR_CLK GENMASK(23, 16) + #define SHU3_ACTIM4_TZQCS GENMASK(31, 24) +#define SHU3_ACTIM5 0x00001414 + #define SHU3_ACTIM5_TR2PD GENMASK(4, 0) + #define SHU3_ACTIM5_TWTPD GENMASK(12, 8) + #define SHU3_ACTIM5_TMRR2W GENMASK(27, 24) +#define SHU3_ACTIM6 0x00001418 + #define SHU3_ACTIM6_BGTCCD GENMASK(1, 0) + #define SHU3_ACTIM6_BGTWTR GENMASK(7, 4) + #define SHU3_ACTIM6_TWRMPR GENMASK(11, 8) + #define SHU3_ACTIM6_BGTRRD GENMASK(14, 12) +#define SHU3_ACTIM_XRT 0x0000141c + #define SHU3_ACTIM_XRT_XRTR2R GENMASK(4, 0) + #define SHU3_ACTIM_XRT_XRTR2W GENMASK(11, 8) + #define SHU3_ACTIM_XRT_XRTW2R GENMASK(18, 16) + #define SHU3_ACTIM_XRT_XRTW2W GENMASK(27, 24) +#define SHU3_AC_TIME_05T 0x00001420 + #define SHU3_AC_TIME_05T_TRC_05T BIT(0) + #define SHU3_AC_TIME_05T_TRFCPB_05T BIT(1) + #define SHU3_AC_TIME_05T_TRFC_05T BIT(2) + #define SHU3_AC_TIME_05T_TXP_05T BIT(4) + #define SHU3_AC_TIME_05T_TRTP_05T BIT(5) + #define SHU3_AC_TIME_05T_TRCD_05T BIT(6) + #define SHU3_AC_TIME_05T_TRP_05T BIT(7) + #define SHU3_AC_TIME_05T_TRPAB_05T BIT(8) + #define SHU3_AC_TIME_05T_TRAS_05T BIT(9) + #define SHU3_AC_TIME_05T_TWR_M05T BIT(10) + #define SHU3_AC_TIME_05T_TRRD_05T BIT(12) + #define SHU3_AC_TIME_05T_TFAW_05T BIT(13) + #define SHU3_AC_TIME_05T_TR2PD_05T BIT(15) + #define SHU3_AC_TIME_05T_TWTPD_M05T BIT(16) + #define SHU3_AC_TIME_05T_BGTRRD_05T BIT(21) + #define SHU3_AC_TIME_05T_BGTCCD_05T BIT(22) + #define SHU3_AC_TIME_05T_BGTWTR_05T BIT(23) + #define SHU3_AC_TIME_05T_TR2W_05T BIT(24) + #define SHU3_AC_TIME_05T_TWTR_M05T BIT(25) + #define SHU3_AC_TIME_05T_XRTR2W_05T BIT(26) + #define SHU3_AC_TIME_05T_XRTW2R_M05T BIT(27) +#define SHU3_AC_DERATING0 0x00001424 + #define SHU3_AC_DERATING0_ACDERATEEN BIT(0) + #define SHU3_AC_DERATING0_TRRD_DERATE GENMASK(18, 16) + #define SHU3_AC_DERATING0_TRCD_DERATE GENMASK(27, 24) +#define SHU3_AC_DERATING1 0x00001428 + #define SHU3_AC_DERATING1_TRPAB_DERATE GENMASK(2, 0) + #define SHU3_AC_DERATING1_TRP_DERATE GENMASK(11, 8) + #define SHU3_AC_DERATING1_TRAS_DERATE GENMASK(19, 16) + #define SHU3_AC_DERATING1_TRC_DERATE GENMASK(28, 24) +#define SHU3_AC_DERATING_05T 0x00001430 + #define SHU3_AC_DERATING_05T_TRC_05T_DERATE BIT(0) + #define SHU3_AC_DERATING_05T_TRCD_05T_DERATE BIT(6) + #define SHU3_AC_DERATING_05T_TRP_05T_DERATE BIT(7) + #define SHU3_AC_DERATING_05T_TRPAB_05T_DERATE BIT(8) + #define SHU3_AC_DERATING_05T_TRAS_05T_DERATE BIT(9) + #define SHU3_AC_DERATING_05T_TRRD_05T_DERATE BIT(12) +#define SHU3_CONF0 0x00001440 + #define SHU3_CONF0_DMPGTIM GENMASK(5, 0) + #define SHU3_CONF0_ADVREFEN BIT(6) + #define SHU3_CONF0_ADVPREEN BIT(7) + #define SHU3_CONF0_TRFCPBIG BIT(9) + #define SHU3_CONF0_REFTHD GENMASK(15, 12) + #define SHU3_CONF0_REQQUE_DEPTH GENMASK(19, 16) + #define SHU3_CONF0_FREQDIV4 BIT(24) + #define SHU3_CONF0_FDIV2 BIT(25) + #define SHU3_CONF0_CL2 BIT(27) + #define SHU3_CONF0_BL2 BIT(28) + #define SHU3_CONF0_BL4 BIT(29) + #define SHU3_CONF0_MATYPE GENMASK(31, 30) +#define SHU3_CONF1 0x00001444 + #define SHU3_CONF1_DATLAT GENMASK(4, 0) + #define SHU3_CONF1_DATLAT_DSEL GENMASK(12, 8) + #define SHU3_CONF1_REFBW_FR GENMASK(25, 16) + #define SHU3_CONF1_DATLAT_DSEL_PHY GENMASK(30, 26) + #define SHU3_CONF1_TREFBWIG BIT(31) +#define SHU3_CONF2 0x00001448 + #define SHU3_CONF2_TCMDO1LAT GENMASK(7, 0) + #define SHU3_CONF2_FSPCHG_PRDCNT GENMASK(15, 8) + #define SHU3_CONF2_DCMDLYREF GENMASK(18, 16) + #define SHU3_CONF2_DQCMD BIT(25) + #define SHU3_CONF2_DQ16COM1 BIT(26) + #define SHU3_CONF2_RA15TOCS1 BIT(27) + #define SHU3_CONF2_WPRE2T BIT(28) + #define SHU3_CONF2_FASTWAKE2 BIT(29) + #define SHU3_CONF2_DAREFEN BIT(30) + #define SHU3_CONF2_FASTWAKE BIT(31) +#define SHU3_CONF3 0x0000144c + #define SHU3_CONF3_ZQCSCNT GENMASK(15, 0) + #define SHU3_CONF3_REFRCNT GENMASK(24, 16) +#define SHU3_STBCAL 0x00001450 + #define SHU3_STBCAL_DMSTBLAT GENMASK(1, 0) + #define SHU3_STBCAL_PICGLAT GENMASK(6, 4) + #define SHU3_STBCAL_DQSG_MODE BIT(8) +#define SHU3_DQSOSCTHRD 0x00001454 + #define SHU3_DQSOSCTHRD_DQSOSCTHRD_INC_RK0 GENMASK(11, 0) + #define SHU3_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0 GENMASK(23, 12) + #define SHU3_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0 GENMASK(31, 24) +#define SHU3_RANKCTL 0x00001458 + #define SHU3_RANKCTL_RANKINCTL_RXDLY GENMASK(3, 0) + #define SHU3_RANKCTL_TXRANKINCTL_TXDLY GENMASK(11, 8) + #define SHU3_RANKCTL_TXRANKINCTL GENMASK(15, 12) + #define SHU3_RANKCTL_TXRANKINCTL_ROOT GENMASK(19, 16) + #define SHU3_RANKCTL_RANKINCTL GENMASK(23, 20) + #define SHU3_RANKCTL_RANKINCTL_ROOT1 GENMASK(27, 24) + #define SHU3_RANKCTL_RANKINCTL_PHY GENMASK(31, 28) +#define SHU3_CKECTRL 0x0000145c + #define SHU3_CKECTRL_CMDCKE GENMASK(18, 16) + #define SHU3_CKECTRL_CKEPRD GENMASK(22, 20) + #define SHU3_CKECTRL_TCKESRX GENMASK(25, 24) + #define SHU3_CKECTRL_SREF_CK_DLY GENMASK(29, 28) +#define SHU3_ODTCTRL 0x00001460 + #define SHU3_ODTCTRL_ROEN BIT(0) + #define SHU3_ODTCTRL_WOEN BIT(1) + #define SHU3_ODTCTRL_RODTEN_SELPH_CG_IG BIT(2) + #define SHU3_ODTCTRL_RODTENSTB_SELPH_CG_IG BIT(3) + #define SHU3_ODTCTRL_RODT GENMASK(7, 4) + #define SHU3_ODTCTRL_TWODT GENMASK(22, 16) + #define SHU3_ODTCTRL_FIXRODT BIT(27) + #define SHU3_ODTCTRL_RODTE2 BIT(30) + #define SHU3_ODTCTRL_RODTE BIT(31) +#define SHU3_IMPCAL1 0x00001464 + #define SHU3_IMPCAL1_IMPCAL_CHKCYCLE GENMASK(2, 0) + #define SHU3_IMPCAL1_IMPDRVP GENMASK(8, 4) + #define SHU3_IMPCAL1_IMPDRVN GENMASK(15, 11) + #define SHU3_IMPCAL1_IMPCAL_CALEN_CYCLE GENMASK(19, 17) + #define SHU3_IMPCAL1_IMPCALCNT GENMASK(27, 20) + #define SHU3_IMPCAL1_IMPCAL_CALICNT GENMASK(31, 28) +#define SHU3_DQSOSC_PRD 0x00001468 + #define SHU3_DQSOSC_PRD_DQSOSC_PRDCNT GENMASK(9, 0) + #define SHU3_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8 GENMASK(19, 16) + #define SHU3_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1 GENMASK(31, 20) +#define SHU3_DQSOSCR 0x0000146c + #define SHU3_DQSOSCR_DQSOSCRCNT GENMASK(7, 0) + #define SHU3_DQSOSCR_DQSOSC_DELTA GENMASK(31, 16) +#define SHU3_DQSOSCR2 0x00001470 + #define SHU3_DQSOSCR2_DQSOSCENCNT GENMASK(15, 0) + #define SHU3_DQSOSCR2_DQSOSC_ADV_SEL GENMASK(17, 16) + #define SHU3_DQSOSCR2_DQSOSC_DRS_ADV_SEL GENMASK(19, 18) +#define SHU3_RODTENSTB 0x00001474 + #define SHU3_RODTENSTB_RODTEN_MCK_MODESEL BIT(0) + #define SHU3_RODTENSTB_RODTEN_P1_ENABLE BIT(1) + #define SHU3_RODTENSTB_RODTENSTB_OFFSET GENMASK(7, 2) + #define SHU3_RODTENSTB_RODTENSTB_EXT GENMASK(23, 8) + #define SHU3_RODTENSTB_RODTENSTB_4BYTE_EN BIT(31) +#define SHU3_PIPE 0x00001478 + #define SHU3_PIPE_PHYRXPIPE1 BIT(0) + #define SHU3_PIPE_PHYRXPIPE2 BIT(1) + #define SHU3_PIPE_PHYRXPIPE3 BIT(2) + #define SHU3_PIPE_PHYRXRDSLPIPE1 BIT(4) + #define SHU3_PIPE_PHYRXRDSLPIPE2 BIT(5) + #define SHU3_PIPE_PHYRXRDSLPIPE3 BIT(6) + #define SHU3_PIPE_PHYPIPE1EN BIT(8) + #define SHU3_PIPE_PHYPIPE2EN BIT(9) + #define SHU3_PIPE_PHYPIPE3EN BIT(10) + #define SHU3_PIPE_DLE_LAST_EXTEND3 BIT(26) + #define SHU3_PIPE_READ_START_EXTEND3 BIT(27) + #define SHU3_PIPE_DLE_LAST_EXTEND2 BIT(28) + #define SHU3_PIPE_READ_START_EXTEND2 BIT(29) + #define SHU3_PIPE_DLE_LAST_EXTEND1 BIT(30) + #define SHU3_PIPE_READ_START_EXTEND1 BIT(31) +#define SHU3_TEST1 0x0000147c + #define SHU3_TEST1_LATNORMPOP GENMASK(12, 8) + #define SHU3_TEST1_DQSICALBLCOK_CNT GENMASK(22, 20) + #define SHU3_TEST1_DQSICALI_NEW BIT(23) +#define SHU3_SELPH_CA1 0x00001480 + #define SHU3_SELPH_CA1_TXDLY_CS GENMASK(2, 0) + #define SHU3_SELPH_CA1_TXDLY_CKE GENMASK(6, 4) + #define SHU3_SELPH_CA1_TXDLY_ODT GENMASK(10, 8) + #define SHU3_SELPH_CA1_TXDLY_RESET GENMASK(14, 12) + #define SHU3_SELPH_CA1_TXDLY_WE GENMASK(18, 16) + #define SHU3_SELPH_CA1_TXDLY_CAS GENMASK(22, 20) + #define SHU3_SELPH_CA1_TXDLY_RAS GENMASK(26, 24) + #define SHU3_SELPH_CA1_TXDLY_CS1 GENMASK(30, 28) +#define SHU3_SELPH_CA2 0x00001484 + #define SHU3_SELPH_CA2_TXDLY_BA0 GENMASK(2, 0) + #define SHU3_SELPH_CA2_TXDLY_BA1 GENMASK(6, 4) + #define SHU3_SELPH_CA2_TXDLY_BA2 GENMASK(10, 8) + #define SHU3_SELPH_CA2_TXDLY_CMD GENMASK(20, 16) + #define SHU3_SELPH_CA2_TXDLY_CKE1 GENMASK(26, 24) +#define SHU3_SELPH_CA3 0x00001488 + #define SHU3_SELPH_CA3_TXDLY_RA0 GENMASK(2, 0) + #define SHU3_SELPH_CA3_TXDLY_RA1 GENMASK(6, 4) + #define SHU3_SELPH_CA3_TXDLY_RA2 GENMASK(10, 8) + #define SHU3_SELPH_CA3_TXDLY_RA3 GENMASK(14, 12) + #define SHU3_SELPH_CA3_TXDLY_RA4 GENMASK(18, 16) + #define SHU3_SELPH_CA3_TXDLY_RA5 GENMASK(22, 20) + #define SHU3_SELPH_CA3_TXDLY_RA6 GENMASK(26, 24) + #define SHU3_SELPH_CA3_TXDLY_RA7 GENMASK(30, 28) +#define SHU3_SELPH_CA4 0x0000148c + #define SHU3_SELPH_CA4_TXDLY_RA8 GENMASK(2, 0) + #define SHU3_SELPH_CA4_TXDLY_RA9 GENMASK(6, 4) + #define SHU3_SELPH_CA4_TXDLY_RA10 GENMASK(10, 8) + #define SHU3_SELPH_CA4_TXDLY_RA11 GENMASK(14, 12) + #define SHU3_SELPH_CA4_TXDLY_RA12 GENMASK(18, 16) + #define SHU3_SELPH_CA4_TXDLY_RA13 GENMASK(22, 20) + #define SHU3_SELPH_CA4_TXDLY_RA14 GENMASK(26, 24) + #define SHU3_SELPH_CA4_TXDLY_RA15 GENMASK(30, 28) +#define SHU3_SELPH_CA5 0x00001490 + #define SHU3_SELPH_CA5_DLY_CS GENMASK(2, 0) + #define SHU3_SELPH_CA5_DLY_CKE GENMASK(6, 4) + #define SHU3_SELPH_CA5_DLY_ODT GENMASK(10, 8) + #define SHU3_SELPH_CA5_DLY_RESET GENMASK(14, 12) + #define SHU3_SELPH_CA5_DLY_WE GENMASK(18, 16) + #define SHU3_SELPH_CA5_DLY_CAS GENMASK(22, 20) + #define SHU3_SELPH_CA5_DLY_RAS GENMASK(26, 24) + #define SHU3_SELPH_CA5_DLY_CS1 GENMASK(30, 28) +#define SHU3_SELPH_CA6 0x00001494 + #define SHU3_SELPH_CA6_DLY_BA0 GENMASK(2, 0) + #define SHU3_SELPH_CA6_DLY_BA1 GENMASK(6, 4) + #define SHU3_SELPH_CA6_DLY_BA2 GENMASK(10, 8) + #define SHU3_SELPH_CA6_DLY_CKE1 GENMASK(26, 24) +#define SHU3_SELPH_CA7 0x00001498 + #define SHU3_SELPH_CA7_DLY_RA0 GENMASK(2, 0) + #define SHU3_SELPH_CA7_DLY_RA1 GENMASK(6, 4) + #define SHU3_SELPH_CA7_DLY_RA2 GENMASK(10, 8) + #define SHU3_SELPH_CA7_DLY_RA3 GENMASK(14, 12) + #define SHU3_SELPH_CA7_DLY_RA4 GENMASK(18, 16) + #define SHU3_SELPH_CA7_DLY_RA5 GENMASK(22, 20) + #define SHU3_SELPH_CA7_DLY_RA6 GENMASK(26, 24) + #define SHU3_SELPH_CA7_DLY_RA7 GENMASK(30, 28) +#define SHU3_SELPH_CA8 0x0000149c + #define SHU3_SELPH_CA8_DLY_RA8 GENMASK(2, 0) + #define SHU3_SELPH_CA8_DLY_RA9 GENMASK(6, 4) + #define SHU3_SELPH_CA8_DLY_RA10 GENMASK(10, 8) + #define SHU3_SELPH_CA8_DLY_RA11 GENMASK(14, 12) + #define SHU3_SELPH_CA8_DLY_RA12 GENMASK(18, 16) + #define SHU3_SELPH_CA8_DLY_RA13 GENMASK(22, 20) + #define SHU3_SELPH_CA8_DLY_RA14 GENMASK(26, 24) + #define SHU3_SELPH_CA8_DLY_RA15 GENMASK(30, 28) +#define SHU3_SELPH_DQS0 0x000014a0 + #define SHU3_SELPH_DQS0_TXDLY_DQS0 GENMASK(2, 0) + #define SHU3_SELPH_DQS0_TXDLY_DQS1 GENMASK(6, 4) + #define SHU3_SELPH_DQS0_TXDLY_DQS2 GENMASK(10, 8) + #define SHU3_SELPH_DQS0_TXDLY_DQS3 GENMASK(14, 12) + #define SHU3_SELPH_DQS0_TXDLY_OEN_DQS0 GENMASK(18, 16) + #define SHU3_SELPH_DQS0_TXDLY_OEN_DQS1 GENMASK(22, 20) + #define SHU3_SELPH_DQS0_TXDLY_OEN_DQS2 GENMASK(26, 24) + #define SHU3_SELPH_DQS0_TXDLY_OEN_DQS3 GENMASK(30, 28) +#define SHU3_SELPH_DQS1 0x000014a4 + #define SHU3_SELPH_DQS1_DLY_DQS0 GENMASK(2, 0) + #define SHU3_SELPH_DQS1_DLY_DQS1 GENMASK(6, 4) + #define SHU3_SELPH_DQS1_DLY_DQS2 GENMASK(10, 8) + #define SHU3_SELPH_DQS1_DLY_DQS3 GENMASK(14, 12) + #define SHU3_SELPH_DQS1_DLY_OEN_DQS0 GENMASK(18, 16) + #define SHU3_SELPH_DQS1_DLY_OEN_DQS1 GENMASK(22, 20) + #define SHU3_SELPH_DQS1_DLY_OEN_DQS2 GENMASK(26, 24) + #define SHU3_SELPH_DQS1_DLY_OEN_DQS3 GENMASK(30, 28) +#define SHU3_DRVING1 0x000014a8 + #define SHU3_DRVING1_DQDRVN2 GENMASK(4, 0) + #define SHU3_DRVING1_DQDRVP2 GENMASK(9, 5) + #define SHU3_DRVING1_DQSDRVN1 GENMASK(14, 10) + #define SHU3_DRVING1_DQSDRVP1 GENMASK(19, 15) + #define SHU3_DRVING1_DQSDRVN2 GENMASK(24, 20) + #define SHU3_DRVING1_DQSDRVP2 GENMASK(29, 25) + #define SHU3_DRVING1_DIS_IMP_ODTN_TRACK BIT(30) + #define SHU3_DRVING1_DIS_IMPCAL_HW BIT(31) +#define SHU3_DRVING2 0x000014ac + #define SHU3_DRVING2_CMDDRVN1 GENMASK(4, 0) + #define SHU3_DRVING2_CMDDRVP1 GENMASK(9, 5) + #define SHU3_DRVING2_CMDDRVN2 GENMASK(14, 10) + #define SHU3_DRVING2_CMDDRVP2 GENMASK(19, 15) + #define SHU3_DRVING2_DQDRVN1 GENMASK(24, 20) + #define SHU3_DRVING2_DQDRVP1 GENMASK(29, 25) + #define SHU3_DRVING2_DIS_IMPCAL_ODT_EN BIT(31) +#define SHU3_DRVING3 0x000014b0 + #define SHU3_DRVING3_DQODTN2 GENMASK(4, 0) + #define SHU3_DRVING3_DQODTP2 GENMASK(9, 5) + #define SHU3_DRVING3_DQSODTN GENMASK(14, 10) + #define SHU3_DRVING3_DQSODTP GENMASK(19, 15) + #define SHU3_DRVING3_DQSODTN2 GENMASK(24, 20) + #define SHU3_DRVING3_DQSODTP2 GENMASK(29, 25) +#define SHU3_DRVING4 0x000014b4 + #define SHU3_DRVING4_CMDODTN1 GENMASK(4, 0) + #define SHU3_DRVING4_CMDODTP1 GENMASK(9, 5) + #define SHU3_DRVING4_CMDODTN2 GENMASK(14, 10) + #define SHU3_DRVING4_CMDODTP2 GENMASK(19, 15) + #define SHU3_DRVING4_DQODTN1 GENMASK(24, 20) + #define SHU3_DRVING4_DQODTP1 GENMASK(29, 25) +#define SHU3_DRVING5 0x000014b8 + #define SHU3_DRVING5_DQCODTN2 GENMASK(4, 0) + #define SHU3_DRVING5_DQCODTP2 GENMASK(9, 5) + #define SHU3_DRVING5_DQCDRVN1 GENMASK(14, 10) + #define SHU3_DRVING5_DQCDRVP1 GENMASK(19, 15) + #define SHU3_DRVING5_DQCDRVN2 GENMASK(24, 20) + #define SHU3_DRVING5_DQCDRVP2 GENMASK(29, 25) +#define SHU3_DRVING6 0x000014bc + #define SHU3_DRVING6_DQCODTN1 GENMASK(24, 20) + #define SHU3_DRVING6_DQCODTP1 GENMASK(29, 25) +#define SHU3_WODT 0x000014c0 + #define SHU3_WODT_DISWODT GENMASK(2, 0) + #define SHU3_WODT_WODTFIX BIT(3) + #define SHU3_WODT_WODTFIXOFF BIT(4) + #define SHU3_WODT_DISWODTE BIT(5) + #define SHU3_WODT_DISWODTE2 BIT(6) + #define SHU3_WODT_WODTPDEN BIT(7) + #define SHU3_WODT_DQOE_CNT GENMASK(10, 8) + #define SHU3_WODT_DQOE_OPT BIT(11) + #define SHU3_WODT_TXUPD_SEL GENMASK(13, 12) + #define SHU3_WODT_TXUPD_W2R_SEL GENMASK(16, 14) + #define SHU3_WODT_DBIWR BIT(29) + #define SHU3_WODT_TWPSTEXT BIT(30) + #define SHU3_WODT_WPST2T BIT(31) +#define SHU3_DQSG 0x000014c4 + #define SHU3_DQSG_DLLFRZRFCOPT GENMASK(1, 0) + #define SHU3_DQSG_DLLFRZWROPT GENMASK(5, 4) + #define SHU3_DQSG_R_RSTBCNT_LATCH_OPT GENMASK(10, 8) + #define SHU3_DQSG_STB_UPDMASK_EN BIT(11) + #define SHU3_DQSG_STB_UPDMASKCYC GENMASK(15, 12) + #define SHU3_DQSG_DQSINCTL_PRE_SEL BIT(16) + #define SHU3_DQSG_SCINTV GENMASK(25, 20) +#define SHU3_SCINTV 0x000014c8 + #define SHU3_SCINTV_ODTREN BIT(0) + #define SHU3_SCINTV_TZQLAT GENMASK(5, 1) + #define SHU3_SCINTV_TZQLAT2 GENMASK(10, 6) + #define SHU3_SCINTV_RDDQC_INTV GENMASK(12, 11) + #define SHU3_SCINTV_MRW_INTV GENMASK(17, 13) + #define SHU3_SCINTV_DQS2DQ_SHU_PITHRD GENMASK(23, 18) + #define SHU3_SCINTV_DQS2DQ_FILT_PITHRD GENMASK(29, 24) + #define SHU3_SCINTV_DQSOSCENDIS BIT(30) +#define SHU3_MISC 0x000014cc + #define SHU3_MISC_REQQUE_MAXCNT GENMASK(3, 0) + #define SHU3_MISC_CKEHCMD GENMASK(5, 4) + #define SHU3_MISC_NORMPOP_LEN GENMASK(10, 8) + #define SHU3_MISC_PREA_INTV GENMASK(16, 12) +#define SHU3_DQS2DQ_TX 0x000014d0 + #define SHU3_DQS2DQ_TX_OE2DQ_OFFSET GENMASK(4, 0) +#define SHU3_HWSET_MR2 0x000014d4 + #define SHU3_HWSET_MR2_HWSET_MR2_MRSMA GENMASK(12, 0) + #define SHU3_HWSET_MR2_HWSET_MR2_OP GENMASK(23, 16) +#define SHU3_HWSET_MR13 0x000014d8 + #define SHU3_HWSET_MR13_HWSET_MR13_MRSMA GENMASK(12, 0) + #define SHU3_HWSET_MR13_HWSET_MR13_OP GENMASK(23, 16) +#define SHU3_HWSET_VRCG 0x000014dc + #define SHU3_HWSET_VRCG_HWSET_VRCG_MRSMA GENMASK(12, 0) + #define SHU3_HWSET_VRCG_HWSET_VRCG_OP GENMASK(23, 16) +#define SHU3_APHY_TX_PICG_CTRL 0x000014e4 + #define SHU3_APHY_TX_PICG_CTRL_APHYPI_CG_CK_SEL GENMASK(23, 20) + #define SHU3_APHY_TX_PICG_CTRL_APHYPI_CG_CK_OPT BIT(24) + #define SHU3_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL GENMASK(30, 27) + #define SHU3_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_OPT BIT(31) +#define SHU3RK0_DQSCTL 0x00001600 + #define SHU3RK0_DQSCTL_DQSINCTL GENMASK(3, 0) +#define SHU3RK0_DQSIEN 0x00001604 + #define SHU3RK0_DQSIEN_R0DQS0IEN GENMASK(6, 0) + #define SHU3RK0_DQSIEN_R0DQS1IEN GENMASK(14, 8) + #define SHU3RK0_DQSIEN_R0DQS2IEN GENMASK(22, 16) + #define SHU3RK0_DQSIEN_R0DQS3IEN GENMASK(30, 24) +#define SHU3RK0_DQSCAL 0x00001608 + #define SHU3RK0_DQSCAL_R0DQSIENLLMT GENMASK(6, 0) + #define SHU3RK0_DQSCAL_R0DQSIENLLMTEN BIT(7) + #define SHU3RK0_DQSCAL_R0DQSIENHLMT GENMASK(14, 8) + #define SHU3RK0_DQSCAL_R0DQSIENHLMTEN BIT(15) +#define SHU3RK0_PI 0x0000160c + #define SHU3RK0_PI_RK0_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU3RK0_PI_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3RK0_PI_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3RK0_PI_RK0_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU3RK0_DQSOSC 0x00001610 + #define SHU3RK0_DQSOSC_DQSOSC_BASE_RK0 GENMASK(15, 0) + #define SHU3RK0_DQSOSC_DQSOSC_BASE_RK0_B1 GENMASK(31, 16) +#define SHU3RK0_SELPH_ODTEN0 0x0000161c + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN GENMASK(2, 0) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN GENMASK(10, 8) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN GENMASK(18, 16) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN GENMASK(26, 24) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU3RK0_SELPH_ODTEN1 0x00001620 + #define SHU3RK0_SELPH_ODTEN1_DLY_B0_RODTEN GENMASK(2, 0) + #define SHU3RK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU3RK0_SELPH_ODTEN1_DLY_B1_RODTEN GENMASK(10, 8) + #define SHU3RK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU3RK0_SELPH_ODTEN1_DLY_B2_RODTEN GENMASK(18, 16) + #define SHU3RK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU3RK0_SELPH_ODTEN1_DLY_B3_RODTEN GENMASK(26, 24) + #define SHU3RK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQSG0 0x00001624 + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQSG1 0x00001628 + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQ0 0x0000162c + #define SHU3RK0_SELPH_DQ0_TXDLY_DQ0 GENMASK(2, 0) + #define SHU3RK0_SELPH_DQ0_TXDLY_DQ1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQ0_TXDLY_DQ2 GENMASK(10, 8) + #define SHU3RK0_SELPH_DQ0_TXDLY_DQ3 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQ0_TXDLY_OEN_DQ0 GENMASK(18, 16) + #define SHU3RK0_SELPH_DQ0_TXDLY_OEN_DQ1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQ0_TXDLY_OEN_DQ2 GENMASK(26, 24) + #define SHU3RK0_SELPH_DQ0_TXDLY_OEN_DQ3 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQ1 0x00001630 + #define SHU3RK0_SELPH_DQ1_TXDLY_DQM0 GENMASK(2, 0) + #define SHU3RK0_SELPH_DQ1_TXDLY_DQM1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQ1_TXDLY_DQM2 GENMASK(10, 8) + #define SHU3RK0_SELPH_DQ1_TXDLY_DQM3 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQ1_TXDLY_OEN_DQM0 GENMASK(18, 16) + #define SHU3RK0_SELPH_DQ1_TXDLY_OEN_DQM1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQ1_TXDLY_OEN_DQM2 GENMASK(26, 24) + #define SHU3RK0_SELPH_DQ1_TXDLY_OEN_DQM3 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQ2 0x00001634 + #define SHU3RK0_SELPH_DQ2_DLY_DQ0 GENMASK(2, 0) + #define SHU3RK0_SELPH_DQ2_DLY_DQ1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQ2_DLY_DQ2 GENMASK(10, 8) + #define SHU3RK0_SELPH_DQ2_DLY_DQ3 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQ2_DLY_OEN_DQ0 GENMASK(18, 16) + #define SHU3RK0_SELPH_DQ2_DLY_OEN_DQ1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQ2_DLY_OEN_DQ2 GENMASK(26, 24) + #define SHU3RK0_SELPH_DQ2_DLY_OEN_DQ3 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQ3 0x00001638 + #define SHU3RK0_SELPH_DQ3_DLY_DQM0 GENMASK(2, 0) + #define SHU3RK0_SELPH_DQ3_DLY_DQM1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQ3_DLY_DQM2 GENMASK(10, 8) + #define SHU3RK0_SELPH_DQ3_DLY_DQM3 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQ3_DLY_OEN_DQM0 GENMASK(18, 16) + #define SHU3RK0_SELPH_DQ3_DLY_OEN_DQM1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQ3_DLY_OEN_DQM2 GENMASK(26, 24) + #define SHU3RK0_SELPH_DQ3_DLY_OEN_DQM3 GENMASK(30, 28) +#define SHU3RK0_DQS2DQ_CAL1 0x00001640 + #define SHU3RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU3RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU3RK0_DQS2DQ_CAL2 0x00001644 + #define SHU3RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU3RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU3RK0_DQS2DQ_CAL3 0x00001648 + #define SHU3RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 GENMASK(5, 0) + #define SHU3RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 GENMASK(11, 6) + #define SHU3RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU3RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU3RK0_DQS2DQ_CAL4 0x0000164c + #define SHU3RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 GENMASK(5, 0) + #define SHU3RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 GENMASK(11, 6) + #define SHU3RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU3RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU3RK0_DQS2DQ_CAL5 0x00001650 + #define SHU3RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 GENMASK(10, 0) + #define SHU3RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 GENMASK(26, 16) +#define SHU3RK1_DQSCTL 0x00001700 + #define SHU3RK1_DQSCTL_R1DQSINCTL GENMASK(3, 0) +#define SHU3RK1_DQSIEN 0x00001704 + #define SHU3RK1_DQSIEN_R1DQS0IEN GENMASK(6, 0) + #define SHU3RK1_DQSIEN_R1DQS1IEN GENMASK(14, 8) + #define SHU3RK1_DQSIEN_R1DQS2IEN GENMASK(22, 16) + #define SHU3RK1_DQSIEN_R1DQS3IEN GENMASK(30, 24) +#define SHU3RK1_DQSCAL 0x00001708 + #define SHU3RK1_DQSCAL_R1DQSIENLLMT GENMASK(6, 0) + #define SHU3RK1_DQSCAL_R1DQSIENLLMTEN BIT(7) + #define SHU3RK1_DQSCAL_R1DQSIENHLMT GENMASK(14, 8) + #define SHU3RK1_DQSCAL_R1DQSIENHLMTEN BIT(15) +#define SHU3RK1_PI 0x0000170c + #define SHU3RK1_PI_RK1_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU3RK1_PI_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3RK1_PI_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3RK1_PI_RK1_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU3RK1_DQSOSC 0x00001710 + #define SHU3RK1_DQSOSC_DQSOSC_BASE_RK1 GENMASK(15, 0) + #define SHU3RK1_DQSOSC_DQSOSC_BASE_RK1_B1 GENMASK(31, 16) +#define SHU3RK1_SELPH_ODTEN0 0x0000171c + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU3RK1_SELPH_ODTEN1 0x00001720 + #define SHU3RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU3RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU3RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU3RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU3RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU3RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU3RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU3RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQSG0 0x00001724 + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQSG1 0x00001728 + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQ0 0x0000172c + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1DQ0 GENMASK(2, 0) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1DQ1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1DQ2 GENMASK(10, 8) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1DQ3 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQ1 0x00001730 + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1DQM0 GENMASK(2, 0) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1DQM1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1DQM2 GENMASK(10, 8) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1DQM3 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQ2 0x00001734 + #define SHU3RK1_SELPH_DQ2_DLY_R1DQ0 GENMASK(2, 0) + #define SHU3RK1_SELPH_DQ2_DLY_R1DQ1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQ2_DLY_R1DQ2 GENMASK(10, 8) + #define SHU3RK1_SELPH_DQ2_DLY_R1DQ3 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQ2_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU3RK1_SELPH_DQ2_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQ2_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU3RK1_SELPH_DQ2_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQ3 0x00001738 + #define SHU3RK1_SELPH_DQ3_DLY_R1DQM0 GENMASK(2, 0) + #define SHU3RK1_SELPH_DQ3_DLY_R1DQM1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQ3_DLY_R1DQM2 GENMASK(10, 8) + #define SHU3RK1_SELPH_DQ3_DLY_R1DQM3 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQ3_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU3RK1_SELPH_DQ3_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQ3_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU3RK1_SELPH_DQ3_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU3RK1_DQS2DQ_CAL1 0x00001740 + #define SHU3RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU3RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU3RK1_DQS2DQ_CAL2 0x00001744 + #define SHU3RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU3RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU3RK1_DQS2DQ_CAL3 0x00001748 + #define SHU3RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 GENMASK(5, 0) + #define SHU3RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 GENMASK(11, 6) + #define SHU3RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU3RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU3RK1_DQS2DQ_CAL4 0x0000174c + #define SHU3RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 GENMASK(5, 0) + #define SHU3RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 GENMASK(11, 6) + #define SHU3RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU3RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU3RK1_DQS2DQ_CAL5 0x00001750 + #define SHU3RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 GENMASK(10, 0) + #define SHU3RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 GENMASK(26, 16) +#define SHU3RK2_DQSCTL 0x00001800 + #define SHU3RK2_DQSCTL_R2DQSINCTL GENMASK(3, 0) +#define SHU3RK2_DQSIEN 0x00001804 + #define SHU3RK2_DQSIEN_R2DQS0IEN GENMASK(6, 0) + #define SHU3RK2_DQSIEN_R2DQS1IEN GENMASK(14, 8) + #define SHU3RK2_DQSIEN_R2DQS2IEN GENMASK(22, 16) + #define SHU3RK2_DQSIEN_R2DQS3IEN GENMASK(30, 24) +#define SHU3RK2_DQSCAL 0x00001808 + #define SHU3RK2_DQSCAL_R2DQSIENLLMT GENMASK(6, 0) + #define SHU3RK2_DQSCAL_R2DQSIENLLMTEN BIT(7) + #define SHU3RK2_DQSCAL_R2DQSIENHLMT GENMASK(14, 8) + #define SHU3RK2_DQSCAL_R2DQSIENHLMTEN BIT(15) +#define SHU3RK2_PI 0x0000180c + #define SHU3RK2_PI_RK2_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU3RK2_PI_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3RK2_PI_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3RK2_PI_RK2_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU3RK2_DQSOSC 0x00001810 + #define SHU3RK2_DQSOSC_DQSOSC_BASE_RK2 GENMASK(15, 0) + #define SHU3RK2_DQSOSC_DQSOSC_BASE_RK2_B1 GENMASK(31, 16) +#define SHU3RK2_SELPH_ODTEN0 0x0000181c + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU3RK2_SELPH_ODTEN1 0x00001820 + #define SHU3RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU3RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU3RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU3RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU3RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU3RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU3RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU3RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQSG0 0x00001824 + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQSG1 0x00001828 + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQ0 0x0000182c + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2DQ0 GENMASK(2, 0) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2DQ1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2DQ2 GENMASK(10, 8) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2DQ3 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQ1 0x00001830 + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2DQM0 GENMASK(2, 0) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2DQM1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2DQM2 GENMASK(10, 8) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2DQM3 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQ2 0x00001834 + #define SHU3RK2_SELPH_DQ2_DLY_R2DQ0 GENMASK(2, 0) + #define SHU3RK2_SELPH_DQ2_DLY_R2DQ1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQ2_DLY_R2DQ2 GENMASK(10, 8) + #define SHU3RK2_SELPH_DQ2_DLY_R2DQ3 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQ2_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU3RK2_SELPH_DQ2_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQ2_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU3RK2_SELPH_DQ2_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQ3 0x00001838 + #define SHU3RK2_SELPH_DQ3_DLY_R2DQM0 GENMASK(2, 0) + #define SHU3RK2_SELPH_DQ3_DLY_R2DQM1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQ3_DLY_R2DQM2 GENMASK(10, 8) + #define SHU3RK2_SELPH_DQ3_DLY_R2DQM3 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQ3_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU3RK2_SELPH_DQ3_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQ3_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU3RK2_SELPH_DQ3_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU3RK2_DQS2DQ_CAL1 0x00001840 + #define SHU3RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU3RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU3RK2_DQS2DQ_CAL2 0x00001844 + #define SHU3RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU3RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU3RK2_DQS2DQ_CAL3 0x00001848 + #define SHU3RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ0 GENMASK(5, 0) + #define SHU3RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ1 GENMASK(11, 6) +#define SHU3RK2_DQS2DQ_CAL4 0x0000184c + #define SHU3RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM0 GENMASK(5, 0) + #define SHU3RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM1 GENMASK(11, 6) +#define SHU3RK2_DQS2DQ_CAL5 0x00001850 + #define SHU3RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM0 GENMASK(10, 0) + #define SHU3RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM1 GENMASK(26, 16) +#define SHU3_DQSG_RETRY 0x00001854 + #define SHU3_DQSG_RETRY_R_DQSGRETRY_SW_RESET BIT(0) + #define SHU3_DQSG_RETRY_R_DQSG_RETRY_SW_EN BIT(1) + #define SHU3_DQSG_RETRY_R_DDR1866_PLUS BIT(2) + #define SHU3_DQSG_RETRY_R_RETRY_ONCE BIT(3) + #define SHU3_DQSG_RETRY_R_RETRY_3TIMES BIT(4) + #define SHU3_DQSG_RETRY_R_RETRY_1RANK BIT(5) + #define SHU3_DQSG_RETRY_R_RETRY_SAV_MSK BIT(6) + #define SHU3_DQSG_RETRY_R_DM4BYTE BIT(7) + #define SHU3_DQSG_RETRY_R_DQSIENLAT GENMASK(11, 8) + #define SHU3_DQSG_RETRY_R_STBENCMP_ALLBYTE BIT(12) + #define SHU3_DQSG_RETRY_R_XSR_DQSG_RETRY_EN BIT(13) + #define SHU3_DQSG_RETRY_R_XSR_RETRY_SPM_MODE BIT(14) + #define SHU3_DQSG_RETRY_R_RETRY_CMP_DATA BIT(15) + #define SHU3_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK BIT(20) + #define SHU3_DQSG_RETRY_R_RDY_SEL_DLE BIT(21) + #define SHU3_DQSG_RETRY_R_RETRY_ROUND_NUM GENMASK(25, 24) + #define SHU3_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY BIT(28) + #define SHU3_DQSG_RETRY_R_RETRY_PA_DSIABLE BIT(29) + #define SHU3_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK BIT(30) + #define SHU3_DQSG_RETRY_R_RETRY_USE_BURST_MDOE BIT(31) +#define SHU4_ACTIM0 0x00001a00 + #define SHU4_ACTIM0_TWTR GENMASK(3, 0) + #define SHU4_ACTIM0_TWR GENMASK(12, 8) + #define SHU4_ACTIM0_TRRD GENMASK(18, 16) + #define SHU4_ACTIM0_TRCD GENMASK(27, 24) +#define SHU4_ACTIM1 0x00001a04 + #define SHU4_ACTIM1_TRPAB GENMASK(2, 0) + #define SHU4_ACTIM1_TRP GENMASK(11, 8) + #define SHU4_ACTIM1_TRAS GENMASK(19, 16) + #define SHU4_ACTIM1_TRC GENMASK(28, 24) +#define SHU4_ACTIM2 0x00001a08 + #define SHU4_ACTIM2_TXP GENMASK(2, 0) + #define SHU4_ACTIM2_TRTP GENMASK(10, 8) + #define SHU4_ACTIM2_TR2W GENMASK(19, 16) + #define SHU4_ACTIM2_TFAW GENMASK(28, 24) +#define SHU4_ACTIM3 0x00001a0c + #define SHU4_ACTIM3_TRFCPB GENMASK(7, 0) + #define SHU4_ACTIM3_TRFC GENMASK(23, 16) + #define SHU4_ACTIM3_REFCNT GENMASK(31, 24) +#define SHU4_ACTIM4 0x00001a10 + #define SHU4_ACTIM4_TXREFCNT GENMASK(9, 0) + #define SHU4_ACTIM4_REFCNT_FR_CLK GENMASK(23, 16) + #define SHU4_ACTIM4_TZQCS GENMASK(31, 24) +#define SHU4_ACTIM5 0x00001a14 + #define SHU4_ACTIM5_TR2PD GENMASK(4, 0) + #define SHU4_ACTIM5_TWTPD GENMASK(12, 8) + #define SHU4_ACTIM5_TMRR2W GENMASK(27, 24) +#define SHU4_ACTIM6 0x00001a18 + #define SHU4_ACTIM6_BGTCCD GENMASK(1, 0) + #define SHU4_ACTIM6_BGTWTR GENMASK(7, 4) + #define SHU4_ACTIM6_TWRMPR GENMASK(11, 8) + #define SHU4_ACTIM6_BGTRRD GENMASK(14, 12) +#define SHU4_ACTIM_XRT 0x00001a1c + #define SHU4_ACTIM_XRT_XRTR2R GENMASK(4, 0) + #define SHU4_ACTIM_XRT_XRTR2W GENMASK(11, 8) + #define SHU4_ACTIM_XRT_XRTW2R GENMASK(18, 16) + #define SHU4_ACTIM_XRT_XRTW2W GENMASK(27, 24) +#define SHU4_AC_TIME_05T 0x00001a20 + #define SHU4_AC_TIME_05T_TRC_05T BIT(0) + #define SHU4_AC_TIME_05T_TRFCPB_05T BIT(1) + #define SHU4_AC_TIME_05T_TRFC_05T BIT(2) + #define SHU4_AC_TIME_05T_TXP_05T BIT(4) + #define SHU4_AC_TIME_05T_TRTP_05T BIT(5) + #define SHU4_AC_TIME_05T_TRCD_05T BIT(6) + #define SHU4_AC_TIME_05T_TRP_05T BIT(7) + #define SHU4_AC_TIME_05T_TRPAB_05T BIT(8) + #define SHU4_AC_TIME_05T_TRAS_05T BIT(9) + #define SHU4_AC_TIME_05T_TWR_M05T BIT(10) + #define SHU4_AC_TIME_05T_TRRD_05T BIT(12) + #define SHU4_AC_TIME_05T_TFAW_05T BIT(13) + #define SHU4_AC_TIME_05T_TR2PD_05T BIT(15) + #define SHU4_AC_TIME_05T_TWTPD_M05T BIT(16) + #define SHU4_AC_TIME_05T_BGTRRD_05T BIT(21) + #define SHU4_AC_TIME_05T_BGTCCD_05T BIT(22) + #define SHU4_AC_TIME_05T_BGTWTR_05T BIT(23) + #define SHU4_AC_TIME_05T_TR2W_05T BIT(24) + #define SHU4_AC_TIME_05T_TWTR_M05T BIT(25) + #define SHU4_AC_TIME_05T_XRTR2W_05T BIT(26) + #define SHU4_AC_TIME_05T_XRTW2R_M05T BIT(27) +#define SHU4_AC_DERATING0 0x00001a24 + #define SHU4_AC_DERATING0_ACDERATEEN BIT(0) + #define SHU4_AC_DERATING0_TRRD_DERATE GENMASK(18, 16) + #define SHU4_AC_DERATING0_TRCD_DERATE GENMASK(27, 24) +#define SHU4_AC_DERATING1 0x00001a28 + #define SHU4_AC_DERATING1_TRPAB_DERATE GENMASK(2, 0) + #define SHU4_AC_DERATING1_TRP_DERATE GENMASK(11, 8) + #define SHU4_AC_DERATING1_TRAS_DERATE GENMASK(19, 16) + #define SHU4_AC_DERATING1_TRC_DERATE GENMASK(28, 24) +#define SHU4_AC_DERATING_05T 0x00001a30 + #define SHU4_AC_DERATING_05T_TRC_05T_DERATE BIT(0) + #define SHU4_AC_DERATING_05T_TRCD_05T_DERATE BIT(6) + #define SHU4_AC_DERATING_05T_TRP_05T_DERATE BIT(7) + #define SHU4_AC_DERATING_05T_TRPAB_05T_DERATE BIT(8) + #define SHU4_AC_DERATING_05T_TRAS_05T_DERATE BIT(9) + #define SHU4_AC_DERATING_05T_TRRD_05T_DERATE BIT(12) +#define SHU4_CONF0 0x00001a40 + #define SHU4_CONF0_DMPGTIM GENMASK(5, 0) + #define SHU4_CONF0_ADVREFEN BIT(6) + #define SHU4_CONF0_ADVPREEN BIT(7) + #define SHU4_CONF0_TRFCPBIG BIT(9) + #define SHU4_CONF0_REFTHD GENMASK(15, 12) + #define SHU4_CONF0_REQQUE_DEPTH GENMASK(19, 16) + #define SHU4_CONF0_FREQDIV4 BIT(24) + #define SHU4_CONF0_FDIV2 BIT(25) + #define SHU4_CONF0_CL2 BIT(27) + #define SHU4_CONF0_BL2 BIT(28) + #define SHU4_CONF0_BL4 BIT(29) + #define SHU4_CONF0_MATYPE GENMASK(31, 30) +#define SHU4_CONF1 0x00001a44 + #define SHU4_CONF1_DATLAT GENMASK(4, 0) + #define SHU4_CONF1_DATLAT_DSEL GENMASK(12, 8) + #define SHU4_CONF1_REFBW_FR GENMASK(25, 16) + #define SHU4_CONF1_DATLAT_DSEL_PHY GENMASK(30, 26) + #define SHU4_CONF1_TREFBWIG BIT(31) +#define SHU4_CONF2 0x00001a48 + #define SHU4_CONF2_TCMDO1LAT GENMASK(7, 0) + #define SHU4_CONF2_FSPCHG_PRDCNT GENMASK(15, 8) + #define SHU4_CONF2_DCMDLYREF GENMASK(18, 16) + #define SHU4_CONF2_DQCMD BIT(25) + #define SHU4_CONF2_DQ16COM1 BIT(26) + #define SHU4_CONF2_RA15TOCS1 BIT(27) + #define SHU4_CONF2_WPRE2T BIT(28) + #define SHU4_CONF2_FASTWAKE2 BIT(29) + #define SHU4_CONF2_DAREFEN BIT(30) + #define SHU4_CONF2_FASTWAKE BIT(31) +#define SHU4_CONF3 0x00001a4c + #define SHU4_CONF3_ZQCSCNT GENMASK(15, 0) + #define SHU4_CONF3_REFRCNT GENMASK(24, 16) +#define SHU4_STBCAL 0x00001a50 + #define SHU4_STBCAL_DMSTBLAT GENMASK(1, 0) + #define SHU4_STBCAL_PICGLAT GENMASK(6, 4) + #define SHU4_STBCAL_DQSG_MODE BIT(8) +#define SHU4_DQSOSCTHRD 0x00001a54 + #define SHU4_DQSOSCTHRD_DQSOSCTHRD_INC_RK0 GENMASK(11, 0) + #define SHU4_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0 GENMASK(23, 12) + #define SHU4_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0 GENMASK(31, 24) +#define SHU4_RANKCTL 0x00001a58 + #define SHU4_RANKCTL_RANKINCTL_RXDLY GENMASK(3, 0) + #define SHU4_RANKCTL_TXRANKINCTL_TXDLY GENMASK(11, 8) + #define SHU4_RANKCTL_TXRANKINCTL GENMASK(15, 12) + #define SHU4_RANKCTL_TXRANKINCTL_ROOT GENMASK(19, 16) + #define SHU4_RANKCTL_RANKINCTL GENMASK(23, 20) + #define SHU4_RANKCTL_RANKINCTL_ROOT1 GENMASK(27, 24) + #define SHU4_RANKCTL_RANKINCTL_PHY GENMASK(31, 28) +#define SHU4_CKECTRL 0x00001a5c + #define SHU4_CKECTRL_CMDCKE GENMASK(18, 16) + #define SHU4_CKECTRL_CKEPRD GENMASK(22, 20) + #define SHU4_CKECTRL_TCKESRX GENMASK(25, 24) + #define SHU4_CKECTRL_SREF_CK_DLY GENMASK(29, 28) +#define SHU4_ODTCTRL 0x00001a60 + #define SHU4_ODTCTRL_ROEN BIT(0) + #define SHU4_ODTCTRL_WOEN BIT(1) + #define SHU4_ODTCTRL_RODTEN_SELPH_CG_IG BIT(2) + #define SHU4_ODTCTRL_RODTENSTB_SELPH_CG_IG BIT(3) + #define SHU4_ODTCTRL_RODT GENMASK(7, 4) + #define SHU4_ODTCTRL_TWODT GENMASK(22, 16) + #define SHU4_ODTCTRL_FIXRODT BIT(27) + #define SHU4_ODTCTRL_RODTE2 BIT(30) + #define SHU4_ODTCTRL_RODTE BIT(31) +#define SHU4_IMPCAL1 0x00001a64 + #define SHU4_IMPCAL1_IMPCAL_CHKCYCLE GENMASK(2, 0) + #define SHU4_IMPCAL1_IMPDRVP GENMASK(8, 4) + #define SHU4_IMPCAL1_IMPDRVN GENMASK(15, 11) + #define SHU4_IMPCAL1_IMPCAL_CALEN_CYCLE GENMASK(19, 17) + #define SHU4_IMPCAL1_IMPCALCNT GENMASK(27, 20) + #define SHU4_IMPCAL1_IMPCAL_CALICNT GENMASK(31, 28) +#define SHU4_DQSOSC_PRD 0x00001a68 + #define SHU4_DQSOSC_PRD_DQSOSC_PRDCNT GENMASK(9, 0) + #define SHU4_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8 GENMASK(19, 16) + #define SHU4_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1 GENMASK(31, 20) +#define SHU4_DQSOSCR 0x00001a6c + #define SHU4_DQSOSCR_DQSOSCRCNT GENMASK(7, 0) + #define SHU4_DQSOSCR_DQSOSC_DELTA GENMASK(31, 16) +#define SHU4_DQSOSCR2 0x00001a70 + #define SHU4_DQSOSCR2_DQSOSCENCNT GENMASK(15, 0) + #define SHU4_DQSOSCR2_DQSOSC_ADV_SEL GENMASK(17, 16) + #define SHU4_DQSOSCR2_DQSOSC_DRS_ADV_SEL GENMASK(19, 18) +#define SHU4_RODTENSTB 0x00001a74 + #define SHU4_RODTENSTB_RODTEN_MCK_MODESEL BIT(0) + #define SHU4_RODTENSTB_RODTEN_P1_ENABLE BIT(1) + #define SHU4_RODTENSTB_RODTENSTB_OFFSET GENMASK(7, 2) + #define SHU4_RODTENSTB_RODTENSTB_EXT GENMASK(23, 8) + #define SHU4_RODTENSTB_RODTENSTB_4BYTE_EN BIT(31) +#define SHU4_PIPE 0x00001a78 + #define SHU4_PIPE_PHYRXPIPE1 BIT(0) + #define SHU4_PIPE_PHYRXPIPE2 BIT(1) + #define SHU4_PIPE_PHYRXPIPE3 BIT(2) + #define SHU4_PIPE_PHYRXRDSLPIPE1 BIT(4) + #define SHU4_PIPE_PHYRXRDSLPIPE2 BIT(5) + #define SHU4_PIPE_PHYRXRDSLPIPE3 BIT(6) + #define SHU4_PIPE_PHYPIPE1EN BIT(8) + #define SHU4_PIPE_PHYPIPE2EN BIT(9) + #define SHU4_PIPE_PHYPIPE3EN BIT(10) + #define SHU4_PIPE_DLE_LAST_EXTEND3 BIT(26) + #define SHU4_PIPE_READ_START_EXTEND3 BIT(27) + #define SHU4_PIPE_DLE_LAST_EXTEND2 BIT(28) + #define SHU4_PIPE_READ_START_EXTEND2 BIT(29) + #define SHU4_PIPE_DLE_LAST_EXTEND1 BIT(30) + #define SHU4_PIPE_READ_START_EXTEND1 BIT(31) +#define SHU4_TEST1 0x00001a7c + #define SHU4_TEST1_LATNORMPOP GENMASK(12, 8) + #define SHU4_TEST1_DQSICALBLCOK_CNT GENMASK(22, 20) + #define SHU4_TEST1_DQSICALI_NEW BIT(23) +#define SHU4_SELPH_CA1 0x00001a80 + #define SHU4_SELPH_CA1_TXDLY_CS GENMASK(2, 0) + #define SHU4_SELPH_CA1_TXDLY_CKE GENMASK(6, 4) + #define SHU4_SELPH_CA1_TXDLY_ODT GENMASK(10, 8) + #define SHU4_SELPH_CA1_TXDLY_RESET GENMASK(14, 12) + #define SHU4_SELPH_CA1_TXDLY_WE GENMASK(18, 16) + #define SHU4_SELPH_CA1_TXDLY_CAS GENMASK(22, 20) + #define SHU4_SELPH_CA1_TXDLY_RAS GENMASK(26, 24) + #define SHU4_SELPH_CA1_TXDLY_CS1 GENMASK(30, 28) +#define SHU4_SELPH_CA2 0x00001a84 + #define SHU4_SELPH_CA2_TXDLY_BA0 GENMASK(2, 0) + #define SHU4_SELPH_CA2_TXDLY_BA1 GENMASK(6, 4) + #define SHU4_SELPH_CA2_TXDLY_BA2 GENMASK(10, 8) + #define SHU4_SELPH_CA2_TXDLY_CMD GENMASK(20, 16) + #define SHU4_SELPH_CA2_TXDLY_CKE1 GENMASK(26, 24) +#define SHU4_SELPH_CA3 0x00001a88 + #define SHU4_SELPH_CA3_TXDLY_RA0 GENMASK(2, 0) + #define SHU4_SELPH_CA3_TXDLY_RA1 GENMASK(6, 4) + #define SHU4_SELPH_CA3_TXDLY_RA2 GENMASK(10, 8) + #define SHU4_SELPH_CA3_TXDLY_RA3 GENMASK(14, 12) + #define SHU4_SELPH_CA3_TXDLY_RA4 GENMASK(18, 16) + #define SHU4_SELPH_CA3_TXDLY_RA5 GENMASK(22, 20) + #define SHU4_SELPH_CA3_TXDLY_RA6 GENMASK(26, 24) + #define SHU4_SELPH_CA3_TXDLY_RA7 GENMASK(30, 28) +#define SHU4_SELPH_CA4 0x00001a8c + #define SHU4_SELPH_CA4_TXDLY_RA8 GENMASK(2, 0) + #define SHU4_SELPH_CA4_TXDLY_RA9 GENMASK(6, 4) + #define SHU4_SELPH_CA4_TXDLY_RA10 GENMASK(10, 8) + #define SHU4_SELPH_CA4_TXDLY_RA11 GENMASK(14, 12) + #define SHU4_SELPH_CA4_TXDLY_RA12 GENMASK(18, 16) + #define SHU4_SELPH_CA4_TXDLY_RA13 GENMASK(22, 20) + #define SHU4_SELPH_CA4_TXDLY_RA14 GENMASK(26, 24) + #define SHU4_SELPH_CA4_TXDLY_RA15 GENMASK(30, 28) +#define SHU4_SELPH_CA5 0x00001a90 + #define SHU4_SELPH_CA5_DLY_CS GENMASK(2, 0) + #define SHU4_SELPH_CA5_DLY_CKE GENMASK(6, 4) + #define SHU4_SELPH_CA5_DLY_ODT GENMASK(10, 8) + #define SHU4_SELPH_CA5_DLY_RESET GENMASK(14, 12) + #define SHU4_SELPH_CA5_DLY_WE GENMASK(18, 16) + #define SHU4_SELPH_CA5_DLY_CAS GENMASK(22, 20) + #define SHU4_SELPH_CA5_DLY_RAS GENMASK(26, 24) + #define SHU4_SELPH_CA5_DLY_CS1 GENMASK(30, 28) +#define SHU4_SELPH_CA6 0x00001a94 + #define SHU4_SELPH_CA6_DLY_BA0 GENMASK(2, 0) + #define SHU4_SELPH_CA6_DLY_BA1 GENMASK(6, 4) + #define SHU4_SELPH_CA6_DLY_BA2 GENMASK(10, 8) + #define SHU4_SELPH_CA6_DLY_CKE1 GENMASK(26, 24) +#define SHU4_SELPH_CA7 0x00001a98 + #define SHU4_SELPH_CA7_DLY_RA0 GENMASK(2, 0) + #define SHU4_SELPH_CA7_DLY_RA1 GENMASK(6, 4) + #define SHU4_SELPH_CA7_DLY_RA2 GENMASK(10, 8) + #define SHU4_SELPH_CA7_DLY_RA3 GENMASK(14, 12) + #define SHU4_SELPH_CA7_DLY_RA4 GENMASK(18, 16) + #define SHU4_SELPH_CA7_DLY_RA5 GENMASK(22, 20) + #define SHU4_SELPH_CA7_DLY_RA6 GENMASK(26, 24) + #define SHU4_SELPH_CA7_DLY_RA7 GENMASK(30, 28) +#define SHU4_SELPH_CA8 0x00001a9c + #define SHU4_SELPH_CA8_DLY_RA8 GENMASK(2, 0) + #define SHU4_SELPH_CA8_DLY_RA9 GENMASK(6, 4) + #define SHU4_SELPH_CA8_DLY_RA10 GENMASK(10, 8) + #define SHU4_SELPH_CA8_DLY_RA11 GENMASK(14, 12) + #define SHU4_SELPH_CA8_DLY_RA12 GENMASK(18, 16) + #define SHU4_SELPH_CA8_DLY_RA13 GENMASK(22, 20) + #define SHU4_SELPH_CA8_DLY_RA14 GENMASK(26, 24) + #define SHU4_SELPH_CA8_DLY_RA15 GENMASK(30, 28) +#define SHU4_SELPH_DQS0 0x00001aa0 + #define SHU4_SELPH_DQS0_TXDLY_DQS0 GENMASK(2, 0) + #define SHU4_SELPH_DQS0_TXDLY_DQS1 GENMASK(6, 4) + #define SHU4_SELPH_DQS0_TXDLY_DQS2 GENMASK(10, 8) + #define SHU4_SELPH_DQS0_TXDLY_DQS3 GENMASK(14, 12) + #define SHU4_SELPH_DQS0_TXDLY_OEN_DQS0 GENMASK(18, 16) + #define SHU4_SELPH_DQS0_TXDLY_OEN_DQS1 GENMASK(22, 20) + #define SHU4_SELPH_DQS0_TXDLY_OEN_DQS2 GENMASK(26, 24) + #define SHU4_SELPH_DQS0_TXDLY_OEN_DQS3 GENMASK(30, 28) +#define SHU4_SELPH_DQS1 0x00001aa4 + #define SHU4_SELPH_DQS1_DLY_DQS0 GENMASK(2, 0) + #define SHU4_SELPH_DQS1_DLY_DQS1 GENMASK(6, 4) + #define SHU4_SELPH_DQS1_DLY_DQS2 GENMASK(10, 8) + #define SHU4_SELPH_DQS1_DLY_DQS3 GENMASK(14, 12) + #define SHU4_SELPH_DQS1_DLY_OEN_DQS0 GENMASK(18, 16) + #define SHU4_SELPH_DQS1_DLY_OEN_DQS1 GENMASK(22, 20) + #define SHU4_SELPH_DQS1_DLY_OEN_DQS2 GENMASK(26, 24) + #define SHU4_SELPH_DQS1_DLY_OEN_DQS3 GENMASK(30, 28) +#define SHU4_DRVING1 0x00001aa8 + #define SHU4_DRVING1_DQDRVN2 GENMASK(4, 0) + #define SHU4_DRVING1_DQDRVP2 GENMASK(9, 5) + #define SHU4_DRVING1_DQSDRVN1 GENMASK(14, 10) + #define SHU4_DRVING1_DQSDRVP1 GENMASK(19, 15) + #define SHU4_DRVING1_DQSDRVN2 GENMASK(24, 20) + #define SHU4_DRVING1_DQSDRVP2 GENMASK(29, 25) + #define SHU4_DRVING1_DIS_IMP_ODTN_TRACK BIT(30) + #define SHU4_DRVING1_DIS_IMPCAL_HW BIT(31) +#define SHU4_DRVING2 0x00001aac + #define SHU4_DRVING2_CMDDRVN1 GENMASK(4, 0) + #define SHU4_DRVING2_CMDDRVP1 GENMASK(9, 5) + #define SHU4_DRVING2_CMDDRVN2 GENMASK(14, 10) + #define SHU4_DRVING2_CMDDRVP2 GENMASK(19, 15) + #define SHU4_DRVING2_DQDRVN1 GENMASK(24, 20) + #define SHU4_DRVING2_DQDRVP1 GENMASK(29, 25) + #define SHU4_DRVING2_DIS_IMPCAL_ODT_EN BIT(31) +#define SHU4_DRVING3 0x00001ab0 + #define SHU4_DRVING3_DQODTN2 GENMASK(4, 0) + #define SHU4_DRVING3_DQODTP2 GENMASK(9, 5) + #define SHU4_DRVING3_DQSODTN GENMASK(14, 10) + #define SHU4_DRVING3_DQSODTP GENMASK(19, 15) + #define SHU4_DRVING3_DQSODTN2 GENMASK(24, 20) + #define SHU4_DRVING3_DQSODTP2 GENMASK(29, 25) +#define SHU4_DRVING4 0x00001ab4 + #define SHU4_DRVING4_CMDODTN1 GENMASK(4, 0) + #define SHU4_DRVING4_CMDODTP1 GENMASK(9, 5) + #define SHU4_DRVING4_CMDODTN2 GENMASK(14, 10) + #define SHU4_DRVING4_CMDODTP2 GENMASK(19, 15) + #define SHU4_DRVING4_DQODTN1 GENMASK(24, 20) + #define SHU4_DRVING4_DQODTP1 GENMASK(29, 25) +#define SHU4_DRVING5 0x00001ab8 + #define SHU4_DRVING5_DQCODTN2 GENMASK(4, 0) + #define SHU4_DRVING5_DQCODTP2 GENMASK(9, 5) + #define SHU4_DRVING5_DQCDRVN1 GENMASK(14, 10) + #define SHU4_DRVING5_DQCDRVP1 GENMASK(19, 15) + #define SHU4_DRVING5_DQCDRVN2 GENMASK(24, 20) + #define SHU4_DRVING5_DQCDRVP2 GENMASK(29, 25) +#define SHU4_DRVING6 0x00001abc + #define SHU4_DRVING6_DQCODTN1 GENMASK(24, 20) + #define SHU4_DRVING6_DQCODTP1 GENMASK(29, 25) +#define SHU4_WODT 0x00001ac0 + #define SHU4_WODT_DISWODT GENMASK(2, 0) + #define SHU4_WODT_WODTFIX BIT(3) + #define SHU4_WODT_WODTFIXOFF BIT(4) + #define SHU4_WODT_DISWODTE BIT(5) + #define SHU4_WODT_DISWODTE2 BIT(6) + #define SHU4_WODT_WODTPDEN BIT(7) + #define SHU4_WODT_DQOE_CNT GENMASK(10, 8) + #define SHU4_WODT_DQOE_OPT BIT(11) + #define SHU4_WODT_TXUPD_SEL GENMASK(13, 12) + #define SHU4_WODT_TXUPD_W2R_SEL GENMASK(16, 14) + #define SHU4_WODT_DBIWR BIT(29) + #define SHU4_WODT_TWPSTEXT BIT(30) + #define SHU4_WODT_WPST2T BIT(31) +#define SHU4_DQSG 0x00001ac4 + #define SHU4_DQSG_DLLFRZRFCOPT GENMASK(1, 0) + #define SHU4_DQSG_DLLFRZWROPT GENMASK(5, 4) + #define SHU4_DQSG_R_RSTBCNT_LATCH_OPT GENMASK(10, 8) + #define SHU4_DQSG_STB_UPDMASK_EN BIT(11) + #define SHU4_DQSG_STB_UPDMASKCYC GENMASK(15, 12) + #define SHU4_DQSG_DQSINCTL_PRE_SEL BIT(16) + #define SHU4_DQSG_SCINTV GENMASK(25, 20) +#define SHU4_SCINTV 0x00001ac8 + #define SHU4_SCINTV_ODTREN BIT(0) + #define SHU4_SCINTV_TZQLAT GENMASK(5, 1) + #define SHU4_SCINTV_TZQLAT2 GENMASK(10, 6) + #define SHU4_SCINTV_RDDQC_INTV GENMASK(12, 11) + #define SHU4_SCINTV_MRW_INTV GENMASK(17, 13) + #define SHU4_SCINTV_DQS2DQ_SHU_PITHRD GENMASK(23, 18) + #define SHU4_SCINTV_DQS2DQ_FILT_PITHRD GENMASK(29, 24) + #define SHU4_SCINTV_DQSOSCENDIS BIT(30) +#define SHU4_MISC 0x00001acc + #define SHU4_MISC_REQQUE_MAXCNT GENMASK(3, 0) + #define SHU4_MISC_CKEHCMD GENMASK(5, 4) + #define SHU4_MISC_NORMPOP_LEN GENMASK(10, 8) + #define SHU4_MISC_PREA_INTV GENMASK(16, 12) +#define SHU4_DQS2DQ_TX 0x00001ad0 + #define SHU4_DQS2DQ_TX_OE2DQ_OFFSET GENMASK(4, 0) +#define SHU4_HWSET_MR2 0x00001ad4 + #define SHU4_HWSET_MR2_HWSET_MR2_MRSMA GENMASK(12, 0) + #define SHU4_HWSET_MR2_HWSET_MR2_OP GENMASK(23, 16) +#define SHU4_HWSET_MR13 0x00001ad8 + #define SHU4_HWSET_MR13_HWSET_MR13_MRSMA GENMASK(12, 0) + #define SHU4_HWSET_MR13_HWSET_MR13_OP GENMASK(23, 16) +#define SHU4_HWSET_VRCG 0x00001adc + #define SHU4_HWSET_VRCG_HWSET_VRCG_MRSMA GENMASK(12, 0) + #define SHU4_HWSET_VRCG_HWSET_VRCG_OP GENMASK(23, 16) +#define SHU4_APHY_TX_PICG_CTRL 0x00001ae4 + #define SHU4_APHY_TX_PICG_CTRL_APHYPI_CG_CK_SEL GENMASK(23, 20) + #define SHU4_APHY_TX_PICG_CTRL_APHYPI_CG_CK_OPT BIT(24) + #define SHU4_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL GENMASK(30, 27) + #define SHU4_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_OPT BIT(31) +#define SHU4RK0_DQSCTL 0x00001c00 + #define SHU4RK0_DQSCTL_DQSINCTL GENMASK(3, 0) +#define SHU4RK0_DQSIEN 0x00001c04 + #define SHU4RK0_DQSIEN_R0DQS0IEN GENMASK(6, 0) + #define SHU4RK0_DQSIEN_R0DQS1IEN GENMASK(14, 8) + #define SHU4RK0_DQSIEN_R0DQS2IEN GENMASK(22, 16) + #define SHU4RK0_DQSIEN_R0DQS3IEN GENMASK(30, 24) +#define SHU4RK0_DQSCAL 0x00001c08 + #define SHU4RK0_DQSCAL_R0DQSIENLLMT GENMASK(6, 0) + #define SHU4RK0_DQSCAL_R0DQSIENLLMTEN BIT(7) + #define SHU4RK0_DQSCAL_R0DQSIENHLMT GENMASK(14, 8) + #define SHU4RK0_DQSCAL_R0DQSIENHLMTEN BIT(15) +#define SHU4RK0_PI 0x00001c0c + #define SHU4RK0_PI_RK0_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU4RK0_PI_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4RK0_PI_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4RK0_PI_RK0_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU4RK0_DQSOSC 0x00001c10 + #define SHU4RK0_DQSOSC_DQSOSC_BASE_RK0 GENMASK(15, 0) + #define SHU4RK0_DQSOSC_DQSOSC_BASE_RK0_B1 GENMASK(31, 16) +#define SHU4RK0_SELPH_ODTEN0 0x00001c1c + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN GENMASK(2, 0) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN GENMASK(10, 8) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN GENMASK(18, 16) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN GENMASK(26, 24) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU4RK0_SELPH_ODTEN1 0x00001c20 + #define SHU4RK0_SELPH_ODTEN1_DLY_B0_RODTEN GENMASK(2, 0) + #define SHU4RK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU4RK0_SELPH_ODTEN1_DLY_B1_RODTEN GENMASK(10, 8) + #define SHU4RK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU4RK0_SELPH_ODTEN1_DLY_B2_RODTEN GENMASK(18, 16) + #define SHU4RK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU4RK0_SELPH_ODTEN1_DLY_B3_RODTEN GENMASK(26, 24) + #define SHU4RK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQSG0 0x00001c24 + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQSG1 0x00001c28 + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQ0 0x00001c2c + #define SHU4RK0_SELPH_DQ0_TXDLY_DQ0 GENMASK(2, 0) + #define SHU4RK0_SELPH_DQ0_TXDLY_DQ1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQ0_TXDLY_DQ2 GENMASK(10, 8) + #define SHU4RK0_SELPH_DQ0_TXDLY_DQ3 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQ0_TXDLY_OEN_DQ0 GENMASK(18, 16) + #define SHU4RK0_SELPH_DQ0_TXDLY_OEN_DQ1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQ0_TXDLY_OEN_DQ2 GENMASK(26, 24) + #define SHU4RK0_SELPH_DQ0_TXDLY_OEN_DQ3 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQ1 0x00001c30 + #define SHU4RK0_SELPH_DQ1_TXDLY_DQM0 GENMASK(2, 0) + #define SHU4RK0_SELPH_DQ1_TXDLY_DQM1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQ1_TXDLY_DQM2 GENMASK(10, 8) + #define SHU4RK0_SELPH_DQ1_TXDLY_DQM3 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQ1_TXDLY_OEN_DQM0 GENMASK(18, 16) + #define SHU4RK0_SELPH_DQ1_TXDLY_OEN_DQM1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQ1_TXDLY_OEN_DQM2 GENMASK(26, 24) + #define SHU4RK0_SELPH_DQ1_TXDLY_OEN_DQM3 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQ2 0x00001c34 + #define SHU4RK0_SELPH_DQ2_DLY_DQ0 GENMASK(2, 0) + #define SHU4RK0_SELPH_DQ2_DLY_DQ1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQ2_DLY_DQ2 GENMASK(10, 8) + #define SHU4RK0_SELPH_DQ2_DLY_DQ3 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQ2_DLY_OEN_DQ0 GENMASK(18, 16) + #define SHU4RK0_SELPH_DQ2_DLY_OEN_DQ1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQ2_DLY_OEN_DQ2 GENMASK(26, 24) + #define SHU4RK0_SELPH_DQ2_DLY_OEN_DQ3 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQ3 0x00001c38 + #define SHU4RK0_SELPH_DQ3_DLY_DQM0 GENMASK(2, 0) + #define SHU4RK0_SELPH_DQ3_DLY_DQM1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQ3_DLY_DQM2 GENMASK(10, 8) + #define SHU4RK0_SELPH_DQ3_DLY_DQM3 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQ3_DLY_OEN_DQM0 GENMASK(18, 16) + #define SHU4RK0_SELPH_DQ3_DLY_OEN_DQM1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQ3_DLY_OEN_DQM2 GENMASK(26, 24) + #define SHU4RK0_SELPH_DQ3_DLY_OEN_DQM3 GENMASK(30, 28) +#define SHU4RK0_DQS2DQ_CAL1 0x00001c40 + #define SHU4RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU4RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU4RK0_DQS2DQ_CAL2 0x00001c44 + #define SHU4RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU4RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU4RK0_DQS2DQ_CAL3 0x00001c48 + #define SHU4RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 GENMASK(5, 0) + #define SHU4RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 GENMASK(11, 6) + #define SHU4RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU4RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU4RK0_DQS2DQ_CAL4 0x00001c4c + #define SHU4RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 GENMASK(5, 0) + #define SHU4RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 GENMASK(11, 6) + #define SHU4RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU4RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU4RK0_DQS2DQ_CAL5 0x00001c50 + #define SHU4RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 GENMASK(10, 0) + #define SHU4RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 GENMASK(26, 16) +#define SHU4RK1_DQSCTL 0x00001d00 + #define SHU4RK1_DQSCTL_R1DQSINCTL GENMASK(3, 0) +#define SHU4RK1_DQSIEN 0x00001d04 + #define SHU4RK1_DQSIEN_R1DQS0IEN GENMASK(6, 0) + #define SHU4RK1_DQSIEN_R1DQS1IEN GENMASK(14, 8) + #define SHU4RK1_DQSIEN_R1DQS2IEN GENMASK(22, 16) + #define SHU4RK1_DQSIEN_R1DQS3IEN GENMASK(30, 24) +#define SHU4RK1_DQSCAL 0x00001d08 + #define SHU4RK1_DQSCAL_R1DQSIENLLMT GENMASK(6, 0) + #define SHU4RK1_DQSCAL_R1DQSIENLLMTEN BIT(7) + #define SHU4RK1_DQSCAL_R1DQSIENHLMT GENMASK(14, 8) + #define SHU4RK1_DQSCAL_R1DQSIENHLMTEN BIT(15) +#define SHU4RK1_PI 0x00001d0c + #define SHU4RK1_PI_RK1_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU4RK1_PI_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4RK1_PI_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4RK1_PI_RK1_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU4RK1_DQSOSC 0x00001d10 + #define SHU4RK1_DQSOSC_DQSOSC_BASE_RK1 GENMASK(15, 0) + #define SHU4RK1_DQSOSC_DQSOSC_BASE_RK1_B1 GENMASK(31, 16) +#define SHU4RK1_SELPH_ODTEN0 0x00001d1c + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU4RK1_SELPH_ODTEN1 0x00001d20 + #define SHU4RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU4RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU4RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU4RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU4RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU4RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU4RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU4RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQSG0 0x00001d24 + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQSG1 0x00001d28 + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQ0 0x00001d2c + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1DQ0 GENMASK(2, 0) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1DQ1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1DQ2 GENMASK(10, 8) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1DQ3 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQ1 0x00001d30 + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1DQM0 GENMASK(2, 0) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1DQM1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1DQM2 GENMASK(10, 8) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1DQM3 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQ2 0x00001d34 + #define SHU4RK1_SELPH_DQ2_DLY_R1DQ0 GENMASK(2, 0) + #define SHU4RK1_SELPH_DQ2_DLY_R1DQ1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQ2_DLY_R1DQ2 GENMASK(10, 8) + #define SHU4RK1_SELPH_DQ2_DLY_R1DQ3 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQ2_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU4RK1_SELPH_DQ2_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQ2_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU4RK1_SELPH_DQ2_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQ3 0x00001d38 + #define SHU4RK1_SELPH_DQ3_DLY_R1DQM0 GENMASK(2, 0) + #define SHU4RK1_SELPH_DQ3_DLY_R1DQM1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQ3_DLY_R1DQM2 GENMASK(10, 8) + #define SHU4RK1_SELPH_DQ3_DLY_R1DQM3 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQ3_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU4RK1_SELPH_DQ3_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQ3_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU4RK1_SELPH_DQ3_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU4RK1_DQS2DQ_CAL1 0x00001d40 + #define SHU4RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU4RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU4RK1_DQS2DQ_CAL2 0x00001d44 + #define SHU4RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU4RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU4RK1_DQS2DQ_CAL3 0x00001d48 + #define SHU4RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 GENMASK(5, 0) + #define SHU4RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 GENMASK(11, 6) + #define SHU4RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU4RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU4RK1_DQS2DQ_CAL4 0x00001d4c + #define SHU4RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 GENMASK(5, 0) + #define SHU4RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 GENMASK(11, 6) + #define SHU4RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU4RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU4RK1_DQS2DQ_CAL5 0x00001d50 + #define SHU4RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 GENMASK(10, 0) + #define SHU4RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 GENMASK(26, 16) +#define SHU4RK2_DQSCTL 0x00001e00 + #define SHU4RK2_DQSCTL_R2DQSINCTL GENMASK(3, 0) +#define SHU4RK2_DQSIEN 0x00001e04 + #define SHU4RK2_DQSIEN_R2DQS0IEN GENMASK(6, 0) + #define SHU4RK2_DQSIEN_R2DQS1IEN GENMASK(14, 8) + #define SHU4RK2_DQSIEN_R2DQS2IEN GENMASK(22, 16) + #define SHU4RK2_DQSIEN_R2DQS3IEN GENMASK(30, 24) +#define SHU4RK2_DQSCAL 0x00001e08 + #define SHU4RK2_DQSCAL_R2DQSIENLLMT GENMASK(6, 0) + #define SHU4RK2_DQSCAL_R2DQSIENLLMTEN BIT(7) + #define SHU4RK2_DQSCAL_R2DQSIENHLMT GENMASK(14, 8) + #define SHU4RK2_DQSCAL_R2DQSIENHLMTEN BIT(15) +#define SHU4RK2_PI 0x00001e0c + #define SHU4RK2_PI_RK2_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU4RK2_PI_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4RK2_PI_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4RK2_PI_RK2_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU4RK2_DQSOSC 0x00001e10 + #define SHU4RK2_DQSOSC_DQSOSC_BASE_RK2 GENMASK(15, 0) + #define SHU4RK2_DQSOSC_DQSOSC_BASE_RK2_B1 GENMASK(31, 16) +#define SHU4RK2_SELPH_ODTEN0 0x00001e1c + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU4RK2_SELPH_ODTEN1 0x00001e20 + #define SHU4RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU4RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU4RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU4RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU4RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU4RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU4RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU4RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQSG0 0x00001e24 + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQSG1 0x00001e28 + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQ0 0x00001e2c + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2DQ0 GENMASK(2, 0) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2DQ1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2DQ2 GENMASK(10, 8) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2DQ3 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQ1 0x00001e30 + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2DQM0 GENMASK(2, 0) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2DQM1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2DQM2 GENMASK(10, 8) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2DQM3 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQ2 0x00001e34 + #define SHU4RK2_SELPH_DQ2_DLY_R2DQ0 GENMASK(2, 0) + #define SHU4RK2_SELPH_DQ2_DLY_R2DQ1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQ2_DLY_R2DQ2 GENMASK(10, 8) + #define SHU4RK2_SELPH_DQ2_DLY_R2DQ3 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQ2_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU4RK2_SELPH_DQ2_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQ2_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU4RK2_SELPH_DQ2_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQ3 0x00001e38 + #define SHU4RK2_SELPH_DQ3_DLY_R2DQM0 GENMASK(2, 0) + #define SHU4RK2_SELPH_DQ3_DLY_R2DQM1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQ3_DLY_R2DQM2 GENMASK(10, 8) + #define SHU4RK2_SELPH_DQ3_DLY_R2DQM3 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQ3_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU4RK2_SELPH_DQ3_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQ3_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU4RK2_SELPH_DQ3_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU4RK2_DQS2DQ_CAL1 0x00001e40 + #define SHU4RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU4RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU4RK2_DQS2DQ_CAL2 0x00001e44 + #define SHU4RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU4RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU4RK2_DQS2DQ_CAL3 0x00001e48 + #define SHU4RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ0 GENMASK(5, 0) + #define SHU4RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ1 GENMASK(11, 6) +#define SHU4RK2_DQS2DQ_CAL4 0x00001e4c + #define SHU4RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM0 GENMASK(5, 0) + #define SHU4RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM1 GENMASK(11, 6) +#define SHU4RK2_DQS2DQ_CAL5 0x00001e50 + #define SHU4RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM0 GENMASK(10, 0) + #define SHU4RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM1 GENMASK(26, 16) +#define SHU4_DQSG_RETRY 0x00001e54 + #define SHU4_DQSG_RETRY_R_DQSGRETRY_SW_RESET BIT(0) + #define SHU4_DQSG_RETRY_R_DQSG_RETRY_SW_EN BIT(1) + #define SHU4_DQSG_RETRY_R_DDR1866_PLUS BIT(2) + #define SHU4_DQSG_RETRY_R_RETRY_ONCE BIT(3) + #define SHU4_DQSG_RETRY_R_RETRY_3TIMES BIT(4) + #define SHU4_DQSG_RETRY_R_RETRY_1RANK BIT(5) + #define SHU4_DQSG_RETRY_R_RETRY_SAV_MSK BIT(6) + #define SHU4_DQSG_RETRY_R_DM4BYTE BIT(7) + #define SHU4_DQSG_RETRY_R_DQSIENLAT GENMASK(11, 8) + #define SHU4_DQSG_RETRY_R_STBENCMP_ALLBYTE BIT(12) + #define SHU4_DQSG_RETRY_R_XSR_DQSG_RETRY_EN BIT(13) + #define SHU4_DQSG_RETRY_R_XSR_RETRY_SPM_MODE BIT(14) + #define SHU4_DQSG_RETRY_R_RETRY_CMP_DATA BIT(15) + #define SHU4_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK BIT(20) + #define SHU4_DQSG_RETRY_R_RDY_SEL_DLE BIT(21) + #define SHU4_DQSG_RETRY_R_RETRY_ROUND_NUM GENMASK(25, 24) + #define SHU4_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY BIT(28) + #define SHU4_DQSG_RETRY_R_RETRY_PA_DSIABLE BIT(29) + #define SHU4_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK BIT(30) + #define SHU4_DQSG_RETRY_R_RETRY_USE_BURST_MDOE BIT(31) + +#endif /*__DRAMC_CH0_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_common.h b/src/vendorcode/mediatek/mt8192/include/dramc_common.h new file mode 100644 index 0000000000..04d07a025c --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_common.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _DRAMC_COMMON_H_ +#define _DRAMC_COMMON_H_ + +#define __ETT__ 0 + +//#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <stdint.h> +#include <types.h> +#include <reg.h> +#include <string.h> +#include <soc/dramc_common.h> +#include <timer.h> +#include <print.h> + +#include "dramc_register.h" +#include "dramc_pi_api.h" +#include "dramc_int_slt.h" + +#if FOR_DV_SIMULATION_USED == 1 +#include "dramc_dv_init.h" +#endif + +/***********************************************************************/ +/* Public Types */ +/***********************************************************************/ + +/*------------------------------------------------------------*/ +/* macros, defines, typedefs, enums */ +/*------------------------------------------------------------*/ +/************************** Common Macro *********************/ +#define dsb() asm volatile("dsb sy" : : : "memory") + +#define DRV_Reg32(x) read32((const void *)((u64)(x))) +#define DRV_WriteReg32(x, y) write32((void *)((u64)(x)), (y)) + +#define mcDELAY_US(x) udelay(x) +#define mcDELAY_MS(x) udelay(x*1000) +#define mcDELAY_XUS(x) udelay(x) +#define mcDELAY_XNS(x) udelay(1) + +/**********************************************/ +/* Priority of debug log */ +/*--------------------------------------------*/ +/* mcSHOW_DBG_MSG: High */ +/* mcSHOW_DBG_MSG2: Medium High */ +/* mcSHOW_DBG_MSG3: Medium Low */ +/* mcSHOW_DBG_MSG4: Low */ +/**********************************************/ + +#define CALIBRATION_LOG 1 + +#if CALIBRATION_LOG +#define mcSHOW_DBG_MSG(_x_) {print _x_;} +#define mcSHOW_DBG_MSG2(_x_) //{print _x_;} +#define mcSHOW_ERR_MSG(_x_) {print _x_;} +#else +#define mcSHOW_DBG_MSG(_x_) +#define mcSHOW_DBG_MSG2(_x_) +#define mcSHOW_ERR_MSG(_x_) +#endif + +#define mcSHOW_DBG_MSG3(_x_) // {print _x_;} +#define mcSHOW_DBG_MSG4(_x_) +#define mcSHOW_DBG_MSG5(_x_) +#define mcSHOW_JV_LOG_MSG(_x_) +#if EYESCAN_LOG +#define mcSHOW_EYESCAN_MSG(_x_) {print _x_;} +#else +#define mcSHOW_EYESCAN_MSG(_x_) //{print _x_;} +#endif +#define mcSHOW_DBG_MSG5(_x_) +#define mcSHOW_TIME_MSG(_x_) +#define mcDUMP_REG_MSG(_x_) +#define mcFPRINTF(_x_) + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0])) +#endif + +#define enter_function() \ + ({mcSHOW_DBG_MSG(("enter %s\n", __FUNCTION__));}) + +#define exit_function() \ + ({mcSHOW_DBG_MSG(("exit %s\n", __FUNCTION__));}) + +extern int dump_log; +#endif // _DRAMC_COMMON_H_ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h b/src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h new file mode 100644 index 0000000000..bbb9fb2e2d --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _DRAMC_DV_INIT_H_ +#define _DRAMC_DV_INIT_H_ + +#include "dramc_common.h" +#include "dramc_int_global.h" +#include "x_hal_io.h" +#include "sv_c_data_traffic.h" + +//========================================================= +//DRAM CONFIG ELEMENT COLLECTION +//========================================================= +typedef enum { DDR3, DDR4, LPDDR3, LPDDR4, LPDDR5, PSRAM } DRAM_TYPE_T; +typedef enum {BG4BK4, BK8, BK16, BKORG_RFU} e_BKORG; +typedef enum {DIS_both, EN_t, EN_both, EN_c} e_RDQSWCK;//MR20 + +#define SA_CONFIG_EN 1 +#define DV_CONFIG_EN 1 +//========================================================= +//Build Top configuration +//========================================================= +#define DFS_GROUP_NUM 10 +#define CH_NUM 2 +#define RK_NUM_PER_CH 2 +#define DONT_CARE_VALUE 0 +#define PULL_UP 1 +#define PULL_DOWN 1 + + + +typedef struct Gating_config +{ + U8 GAT_TRACK_EN ; + U8 RX_GATING_MODE ; + U8 RX_GATING_TRACK_MODE ; + U8 SELPH_MODE ; + U8 PICG_EARLY_EN ; + U8 VALID_LAT_VALUE ; +}Gating_confg_T; + + +//========================================================= +//DV configuration connection +//========================================================= +#if DV_CONFIG_EN==1 +typedef struct DRAMC_DVFS_GROUP_transfer +{ + U8 CKR ; //LPDDR5 CKR could be 4 and 2 other memory type should be 1 + U8 DQSIEN_MODE ; //ANA DQSG mode config LPDDR4 = 1, LPDDR5 with other modes + U8 DQ_P2S_RATIO; //16-1 8-1 4-1 LPDDR5 could support 16-1 mode + U8 RESERVED_8BIT; + U32 data_rate ; +}DRAMC_DVFS_GROUP_transfer_T; + +typedef struct DV_configuration +{ + U8 EX_ROW_EN_1 ; + U8 EX_ROW_EN_0 ; + U8 BYTE_MODE_1 ; + U8 BYTE_MODE_0 ; + U8 LP4Y_EN ; + U8 LP4_WR_PST ; + U8 LP4_OTF ; + U8 NEW_8X_MODE ; + U8 LP45_APHY_COMB_EN; + U8 DLL_IDLE_MODE ; + U8 NEW_RANK_MODE ; + U8 DLL_ASYNC_EN ; + U8 MD32_EN ; + U8 SRAM_EN ; + U8 GP_NUM ; +} DV_new_config_T; +#endif + + +//========================================================= +//LPDDR4 DRAM config +//========================================================= +typedef struct LP4_DRAM_CONFIG +{ + U8 BYTE_MODE[2]; //diff rank + U8 EX_ROW_EN[2]; //diff rank --density over 10G should 1 + U8 MR_WL ; + U8 MR_RL ; + U8 BL ; + U8 RPST ; + U8 RD_PRE ; + U8 WR_PRE ; + U8 WR_PST ; + U8 DBI_WR ; + U8 DBI_RD ; +// U8 DMI ; //No use default enable + U8 OTF ; + U8 LP4Y_EN ; + U8 WORK_FSP ; +} LP4_DRAM_CONFIG_T; + + + +//========================================================= +//LPDDR5 DRAM config +//========================================================= +typedef struct LP5_DRAM_CONFIG +{ + U8 BYTE_MODE[2] ; + U8 EX_ROW_EN[2] ; + U8 MR_WL ; + U8 MR_RL ; + U8 BL ; + U8 CK_Mode ; + U8 RPST ; + U8 RD_PRE ; + U8 WR_PRE ; + U8 WR_PST ; + U8 DBI_WR ; + U8 DBI_RD ; + U8 DMI ; + U8 OTF ; + U8 WCK_PST ; + U8 RDQS_PRE ; + U8 RDQS_PST ; + U8 CA_ODT ; + U8 DQ_ODT ; + U8 CKR ; + U8 WCK_ON ; + U8 WCK_FM ; + U8 WCK_ODT ; + U8 DVFSQ ; + U8 DVFSC ; + e_RDQSWCK RDQSmode[2] ; + U8 WCKmode[2] ; + U8 RECC ; + U8 WECC ; + e_BKORG BankMode ; + U8 WORK_FSP ; +} LP5_DRAM_CONFIG_T; + +//========================================================= +//Analog PHY config +//========================================================= +typedef struct ANA_top_function_config +{ + U8 DLL_ASYNC_EN ; + U8 ALL_SLAVE_EN ; + U8 NEW_RANK_MODE ; + U8 DLL_IDLE_MODE ; + U8 LP45_APHY_COMB_EN; + U8 TX_ODT_DIS ; + U8 NEW_8X_MODE ; +}ANA_top_config_T; + + +typedef struct ANA_DVFS_core_config +{ + U8 CKR; + U8 DQ_P2S_RATIO; + U8 LP5_1600_DQ_P2S_MODE; + U8 CA_P2S_RATIO; + U8 DQ_CA_OPEN; + U8 DQ_SEMI_OPEN; + U8 CA_SEMI_OPEN; + U8 CA_FULL_RATE; + U8 DQ_CKDIV4_EN; + U8 CA_CKDIV4_EN; + U8 CA_PREDIV_EN; + U8 PH8_DLY; + U8 SEMI_OPEN_CA_PICK_MCK_RATIO; + U8 DQ_AAMCK_DIV; + U8 CA_AAMCK_DIV; + U8 CA_ADMCK_DIV; + U8 DQ_TRACK_CA_EN; + U32 PLL_FREQ; + U8 DQ_UI_PI_RATIO; + U8 CA_UI_PI_RATIO; +} ANA_DVFS_CORE_T; + + +//========================================================= +//DVFS group configuration +//========================================================= +typedef struct DRAMC_DVFS_GROUP_CONFIG +{ + U32 data_rate ; + U8 DQSIEN_MODE ; //ANA DQSG mode config LPDDR4 = 1, LPDDR5 with other modes + U8 DQ_P2S_RATIO; //16-1 8-1 4-1 LPDDR5 could support 16-1 mode + U8 CKR ; //LPDDR5 CKR could be 4 and 2 other memory type should be 1 +}DRAMC_DVFS_GROUP_CONFIG_T; + +//========================================================= +//DRAMC Subsystem config +//========================================================= +typedef struct DRAMC_SUBSYS_CONFIG +{ + U8 GP_NUM ; + U8 SRAM_EN ; + U8 MD32_EN ; + ANA_top_config_T *a_cfg ; + ANA_DVFS_CORE_T *a_opt ; + LP4_DRAM_CONFIG_T *lp4_init ; + LP5_DRAM_CONFIG_T *lp5_init ; + DRAMC_DVFS_GROUP_CONFIG_T *DFS_GP[DFS_GROUP_NUM]; +}DRAMC_SUBSYS_CONFIG_T; + + +typedef struct DUT_shuf_config_T { + U8 CKE_DBE_CNT ; + U8 FASTWAKE2 ; + U8 DMPGTIM ; + U8 ADVPREEN ; + U8 DLE_256EN ; + U8 LECC ; + U8 WPST1P5T_OPT ; + U8 LP4YEN ; + U8 LP5_CAS_MODE ; + U8 LP5_SEP_ACT ; + U8 LP5_BGOTF ; + U8 LP5_BGEN ; + U8 LP5_RDQS_SE_EN ; + U8 CKR ; + U8 DQSIEN_MODE ; + U8 DQ_P2S_RATIO ; + U32 data_rate ; +}__attribute__((packed)) DUT_shuf_config_T; + + +typedef struct DUT_top_set_T { + U8 DVFSRTMRWEN ; + U8 NO_QUEUEFLUSH_EN ; + U8 RG_SPM_MODE ; + U8 MD32_EN ; + U8 SRAM_EN ; + U8 RX_PIPE_BYPASS_EN ; + U8 TX_PIPE_BYPASS_EN ; + U32 WAIT_DLE_EXT_DLY ; + U32 RX_DCM_EXT_DLY ; + U8 old_dcm_mode ; + U8 DPHY_DCM_MODE ; + U8 TX_OE_EXT_OPT ; + U8 TXP_WORKAROUND_OPT ; + U32 VALID_LAT_VALUE ; + U8 RXTRACK_PBYTE_OPT ; + U8 TRACK_UP_MODE ; + U8 TREFBWIG_IGNORE ; + U8 SELPH_MODE ; + U8 RANK_SWAP ; + U8 BGPIPE_EN ; + U8 PICG_MODE ; + U8 RTMRR_MODE ; + U8 TMRRI_MODE ; + U8 DQS_OSC_AT_TIMER ; + U8 WPST1P5T_OPT ; + U8 LP5_ZQ_OPT ; + U8 LP5WRAPEN ; + U8 LP4_SE_MODE ; + U8 LP4Y_EN ; + U8 LP4_WR_PST ; + U8 LP4_OTF ; + U8 PLL_MODE_OPTION ; + U8 NEW_8X_MODE ; + U8 LP45_APHY_COMB_EN ; + U8 DLL_IDLE_MODE ; + U8 NEW_RANK_MODE ; + U8 DLL_ASYNC_EN ; + U32 memory_type ; + U32 GP_NUM ; +}__attribute__((packed)) DUT_top_set_T; + + + +extern Gating_confg_T Gat_p; +extern DRAM_TYPE_T MEM_TYPE; +extern LP4_DRAM_CONFIG_T LP4_INIT; +extern LP5_DRAM_CONFIG_T LP5_INIT; +extern ANA_top_config_T ana_top_p; +extern ANA_DVFS_CORE_T ANA_option; +extern DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM]; +extern DRAMC_SUBSYS_CONFIG_T DV_p; +extern DRAMC_CTX_T *DramcConfig; +extern DUT_top_set_T DUTTopSetGlobal; +extern DUT_shuf_config_T DUTShufConfigGlobal[10]; + +#define A_T DV_p.a_cfg +#define A_D DV_p.a_opt +#define M_LP4 DV_p.lp4_init +#define DFS(i) DV_p.DFS_GP[i] +#define LPDDR5_EN_S ((MEM_TYPE==LPDDR5) ? 1 : 0) +#define LPDDR4_EN_S ((MEM_TYPE==LPDDR4) ? 1 : 0) + +#define DUT_p DUTTopSetGlobal +#define DUT_shu_p DUTShufConfigGlobal + + +#if FOR_DV_SIMULATION_USED==1 +EXTERN void register_write(int address, int data); +EXTERN void register_read(int address, int * data); +EXTERN void delay_us(u32 delta); +EXTERN void delay_ns(u32 delta); +EXTERN void timestamp_show(); +EXTERN void build_api_initial(); +EXTERN void register_write_c(u32 address, u32 data); +EXTERN u32 register_read_c(u32 address); +EXTERN void conf_to_sram_sudo(int ch_id , int group_id, int conf_id); +//================ added by Lingyun Wu 11.14 ===================== +EXTERN void broadcast_on(void); +EXTERN void broadcast_off(void); +//================ added by Lingyun Wu 11.14 ===================== +EXTERN void mygetscope(); +EXTERN void mysetscope(); +#endif + + +#if DV_CONFIG_EN +extern void get_dfs_configuration_from_DV_random(DRAMC_DVFS_GROUP_transfer_T * tr, int group_id); +extern void get_top_configuration_from_DV_random(DV_new_config_T * tr); +#endif +//DRAM LP4 initial configuration +extern U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate); + + + +extern void DPI_SW_main_LP4(DRAMC_CTX_T *p, cal_sv_rand_args_t *psra); +extern void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr); +extern void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr); +extern void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr); +extern void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate); +extern void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs); +extern void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr); +extern void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id); + +#endif // _DRAMC_DV_INIT_H_ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_int_global.h b/src/vendorcode/mediatek/mt8192/include/dramc_int_global.h new file mode 100644 index 0000000000..ed153531ba --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_int_global.h @@ -0,0 +1,652 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _INT_GLOBAL_H +#define _INT_GLOBAL_H + +#include "dramc_pi_api.h" +#include "dramc_int_slt.h" + +/* + **************************************************************************************** + ** macro + **************************************************************************************** + */ +#define DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM 0 +//#define DVT_TEST_DUMMY_READ_FOR_DQS_GATING_TRACKING +//#define DVT_TEST_RX_DLY_HW_TRACKING + + +/* + **************************************************************************************** + ** ANA_init_config.c + **************************************************************************************** + */ +EXTERN void ANA_init(DRAMC_CTX_T *p); +EXTERN void RESETB_PULL_DN(DRAMC_CTX_T *p); + + + +/* + **************************************************************************************** + ** DIG_NONSHUF_config.c + **************************************************************************************** + */ +EXTERN void DIG_STATIC_SETTING(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + * + ** DIG_SHUF_config.c + **************************************************************************************** + */ +EXTERN void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id); + + +/* + **************************************************************************************** + * + ** dramc_debug.c + **************************************************************************************** + */ +EXTERN U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX]; +EXTERN U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2]; +EXTERN U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX]; + +#ifdef FOR_HQA_REPORT_USED +EXTERN U8 gHQALog_flag; +EXTERN U16 gHQALOG_RX_delay_cell_ps_075V; +EXTERN int hqa_vmddr_class; +EXTERN void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str); +#endif + + +// --- Eye scan variables ----- + +EXTERN U8 gCBT_EYE_Scan_flag; +EXTERN U8 gRX_EYE_Scan_flag; +EXTERN U8 gTX_EYE_Scan_flag; +EXTERN U8 gEye_Scan_color_flag; +EXTERN U8 gCBT_EYE_Scan_only_higheset_freq_flag; +EXTERN U8 gRX_EYE_Scan_only_higheset_freq_flag; +EXTERN U8 gTX_EYE_Scan_only_higheset_freq_flag; +EXTERN U8 gEye_Scan_unterm_highest_flag; + +#if ENABLE_EYESCAN_GRAPH +#define VREF_TOTAL_NUM_WITH_RANGE (((51 + 30) + 1) / (EYESCAN_GRAPH_CATX_VREF_STEP < EYESCAN_GRAPH_RX_VREF_STEP ? EYESCAN_GRAPH_CATX_VREF_STEP : EYESCAN_GRAPH_RX_VREF_STEP)) //range0 0~50 + range1 21~50 +#define EYESCAN_BROKEN_NUM 3 +#define EYESCAN_DATA_INVALID 0x7f +EXTERN S16 gEyeScan_Min[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4][EYESCAN_BROKEN_NUM]; +EXTERN S16 gEyeScan_Max[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4][EYESCAN_BROKEN_NUM]; +EXTERN S16 gEyeScan_MinMax_store_delay[DQS_NUMBER]; +EXTERN U16 gEyeScan_CaliDelay[DQS_NUMBER]; +EXTERN U16 gEyeScan_WinSize[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4]; +EXTERN S16 gEyeScan_DelayCellPI[DQ_DATA_WIDTH_LP4]; +EXTERN U16 gEyeScan_ContinueVrefHeight[DQ_DATA_WIDTH_LP4]; +EXTERN U16 gEyeScan_TotalPassCount[DQ_DATA_WIDTH_LP4]; +EXTERN void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p); +EXTERN void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type); +#endif +#if MRW_CHECK_ONLY || MRW_BACKUP +EXTERN U8 gFSPWR_Flag[RANK_MAX]; +#endif +#ifdef FOR_HQA_TEST_USED +EXTERN void HQA_measure_message_reset_all_data(DRAMC_CTX_T *p); +#endif +#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION +void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p); +#endif + + + +/* + **************************************************************************************** + ** dramc_dvfs.c + **************************************************************************************** + */ +EXTERN U8 get_shuffleIndex_by_Freq(DRAMC_CTX_T *p); +EXTERN void vInitMappingFreqArray(DRAMC_CTX_T *p); +EXTERN void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable); +EXTERN DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_shuffleIndex(DRAMC_CTX_T *p, U8 index); +EXTERN void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable); +EXTERN void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG); +EXTERN void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG); +EXTERN void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DVFSSettings(DRAMC_CTX_T *p); +EXTERN void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable); +EXTERN void DPMInit(DRAMC_CTX_T *p); +EXTERN void TransferPLLToSPMControl(DRAMC_CTX_T *p, U32 MD32Offset); +EXTERN void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr); +EXTERN void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr); +EXTERN void EnableDFSHwModeClk(DRAMC_CTX_T *p); +EXTERN void DPHYSaveToSRAMShuWA(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DPHYSRAMShuWAToSHU1(DRAMC_CTX_T *p); +EXTERN void SRAMShuRestoreToDPHYWA(DRAMC_CTX_T *p, U8 sram_shu_level, U8 pingpong_shu_level); + + +/* + **************************************************************************************** + ** dramc_dv_freq_related.c + **************************************************************************************** + */ +EXTERN void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p); +EXTERN void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p); +EXTERN void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** dramc_dv_main.c + **************************************************************************************** + */ +#if (FOR_DV_SIMULATION_USED == 1) +EXTERN void DPI_DRAMC_init_entry(); +EXTERN void DPI_DRAM_INIT(); +#endif + + +/* + **************************************************************************************** + ** dramc_pi_basic.c + **************************************************************************************** + */ +EXTERN U8 u1PrintModeRegWrite; +EXTERN void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p); +EXTERN void SetCKE2RankIndependent(DRAMC_CTX_T *p); +EXTERN void DramcDQSPrecalculation_TrackingOff(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DramcDQSPrecalculation_TrackingOn(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p); +EXTERN void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p); +EXTERN void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p); +#if CBT_MOVE_CA_INSTEAD_OF_CLK +EXTERN void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value); +#endif +EXTERN void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq); +EXTERN DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround); +EXTERN void DramcPowerOnSequence(DRAMC_CTX_T *p); +EXTERN void Global_Option_Init(DRAMC_CTX_T *p); +EXTERN U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p); +EXTERN void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p); +EXTERN void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p); +EXTERN void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff); +EXTERN void DramcHMR4_Presetting(DRAMC_CTX_T *p); +EXTERN void DramcEnablePerBankRefresh(DRAMC_CTX_T *p, bool en); +EXTERN void RXPICGSetting(DRAMC_CTX_T * p); +EXTERN void TXPICGNewModeEnable(DRAMC_CTX_T * p); +EXTERN unsigned int DDRPhyFreqMeter(void); +#ifndef DPM_CONTROL_AFTERK +EXTERN void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p); +#endif + + + +/* + **************************************************************************************** + ** dramc_pi_calibration_api.c + **************************************************************************************** + */ +EXTERN U16 gu2MR0_Value[RANK_MAX]; //read only mode register +EXTERN U32 gDramcSwImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX]; //ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN +EXTERN U16 u2g_num_dlycell_perT_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM]; //TODO: to be removed by Francis +EXTERN U16 u2gdelay_cell_ps_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM]; //TODO: to be removed by Francis +EXTERN U16 u2gdelay_cell_ps; +EXTERN U8 gCBT_VREF_RANGE_SEL; +EXTERN U32 u4gVcore[DRAM_DFS_SHUFFLE_MAX]; +EXTERN U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16]; +EXTERN const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16]; +EXTERN U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6]; +EXTERN const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6]; + +#if __ETT__ +EXTERN U8 gETT_WHILE_1_flag; +#endif + +#ifdef FOR_HQA_REPORT_USED +extern U8 gHQALog_flag; +extern U16 gHQALOG_RX_delay_cell_ps_075V; +#endif + +#ifdef FOR_HQA_TEST_USED +EXTERN U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX]; +EXTERN U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10]; +EXTERN U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; +EXTERN U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; +EXTERN U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX]; +EXTERN U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX]; +EXTERN U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX]; +EXTERN S8 gFinalClkDuty[CHANNEL_NUM]; +EXTERN U32 gFinalClkDutyMinMax[CHANNEL_NUM][2]; +EXTERN S8 gFinalDQSDuty[CHANNEL_NUM][DQS_NUMBER]; +EXTERN U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_NUMBER][2]; +#endif +EXTERN U8 u1MR01Value[FSP_MAX]; +EXTERN U8 u1MR02Value[FSP_MAX]; +EXTERN U8 u1MR03Value[FSP_MAX]; +EXTERN U8 u1MR11Value[FSP_MAX]; +EXTERN U8 u1MR18Value[FSP_MAX]; +EXTERN U8 u1MR19Value[FSP_MAX]; +EXTERN U8 u1MR20Value[FSP_MAX]; +EXTERN U8 u1MR21Value[FSP_MAX]; +EXTERN U8 u1MR22Value[FSP_MAX]; +EXTERN U8 u1MR51Value[FSP_MAX]; +EXTERN U8 u1MR04Value[RANK_MAX]; +EXTERN U8 u1MR13Value[RANK_MAX]; +EXTERN U8 u1MR26Value[RANK_MAX]; +EXTERN U8 u1MR30Value[RANK_MAX]; +EXTERN U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; +EXTERN U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; +#if PINMUX_AUTO_TEST_PER_BIT_RX +EXTERN U8 gRX_check_per_bit_flag; +EXTERN S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; +#endif +#if PINMUX_AUTO_TEST_PER_BIT_TX +EXTERN U8 gTX_check_per_bit_flag; +EXTERN S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; +#endif +EXTERN U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK); +EXTERN DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank); +EXTERN DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok); +EXTERN DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase); +EXTERN DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, u8 autok, U8 use_enhanced_rdqs); +EXTERN DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, RX_PATTERN_OPTION_T eRxPattern, + U8 *u1AssignedVref, u8 isAutoK); +EXTERN DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region); +EXTERN void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where); +EXTERN void vBeforeCalibration(DRAMC_CTX_T *p); +EXTERN void vAfterCalibration(DRAMC_CTX_T *p); +EXTERN void DramcRunTimeConfig(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p); +EXTERN void DramcTxOECalibration(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p); +EXTERN void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); +EXTERN void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); +EXTERN void DramcMiockJmeterHQA(DRAMC_CTX_T *p); +EXTERN U8 u1IsPhaseMode(DRAMC_CTX_T *p); +EXTERN void RODTSettings(DRAMC_CTX_T *p); +EXTERN void DQSSTBSettings(DRAMC_CTX_T *p); +EXTERN void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK); +EXTERN void DramPhyReset(DRAMC_CTX_T *p); +EXTERN U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p); +EXTERN U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p); +EXTERN U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p); +#if BYPASS_CALIBRATION +EXTERN void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val); +EXTERN void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); +EXTERN void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); +EXTERN void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]); +EXTERN void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]); +EXTERN void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[]); +EXTERN void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p); +EXTERN void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p); +#endif +EXTERN void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p); +EXTERN void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p); +EXTERN void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay); +#if __FLASH_TOOL_DA__ +EXTERN void vPrintPinInfoResult(DRAMC_CTX_T *p); +EXTERN DEBUG_PIN_INF_FOR_FLASHTOOL_T PINInfo_flashtool; +#endif + + +/* + **************************************************************************************** + ** dramc_pi_main.c + **************************************************************************************** + */ +EXTERN DRAMC_CTX_T gTimeProfilingDramCtx; +EXTERN U8 gHQA_Test_Freq_Vcore_Level; +#if (FOR_DV_SIMULATION_USED == 1) +EXTERN U8 gu1BroadcastIsLP4; +#endif +EXTERN bool gAndroid_DVFS_en; +EXTERN bool gUpdateHighestFreq; +EXTERN DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX]; +EXTERN void dump_dramc_ctx(DRAMC_CTX_T *p); +#ifdef ENABLE_MIOCK_JMETER +EXTERN void PRE_MIOCK_JMETER_HQA_USED(DRAMC_CTX_T *p); +#endif +EXTERN void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p); +EXTERN void vDramCalibrationAllChannel(DRAMC_CTX_T *p); +EXTERN U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type); + + +/* + **************************************************************************************** + ** dramc_slt.c + **************************************************************************************** + */ +#if ENABLE_EMI_LPBK_TEST +EXTERN U8 gEmiLpbkTest; +#endif +EXTERN void SLT_DramcDFS(DRAMC_CTX_T *p, int iDoDMA); +EXTERN void SLT_DFSTestProgram(DRAMC_CTX_T *p, int iDoDMA); +EXTERN void SLT_Test_DFS_and_Memory_Test(DRAMC_CTX_T*p); + + + +/* + **************************************************************************************** + ** dramc_temp_function.c + **************************************************************************************** + */ +EXTERN DRAMC_CTX_T DramCtx_LPDDR4; + + +/* + **************************************************************************************** + ** dramc_tracking.c + **************************************************************************************** + */ +EXTERN U8 gu1MR23[CHANNEL_NUM][RANK_MAX]; +EXTERN void DramcHWGatingInit(DRAMC_CTX_T *p); +EXTERN void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff); +EXTERN void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff); +EXTERN void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel); +#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS) +EXTERN void FreqJumpRatioCalculation(DRAMC_CTX_T *p); +#endif +#if TDQSCK_PRECALCULATION_FOR_DVFS +EXTERN void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p); +EXTERN void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p); +#endif +EXTERN void DramcDQSOSCInit(void); +EXTERN DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p); +#if ENABLE_TX_TRACKING +EXTERN DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p); +EXTERN void DramcHwDQSOSC(DRAMC_CTX_T *p); +EXTERN void Enable_TX_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); +#endif + +#if RDSEL_TRACKING_EN +EXTERN void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); +EXTERN void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p); +#endif +#ifdef HW_GATING +EXTERN void Enable_Gating_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); +#endif +EXTERN void DramcImpedanceHWSaving(DRAMC_CTX_T *p); +EXTERN void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p); +EXTERN void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p); +EXTERN void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p); +EXTERN void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** dramc_utility.c + **************************************************************************************** + */ +EXTERN U16 gddrphyfmeter_value; +#if FOR_DV_SIMULATION_USED +EXTERN U8 u1BroadcastOnOff; +#endif +#if (fcFOR_CHIP_ID == fcA60868) +EXTERN U8 u1EnterRuntime; +#endif +EXTERN U8 u1MaType; +EXTERN void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p); +EXTERN void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode); +EXTERN void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch); +EXTERN void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable); +EXTERN U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p); +EXTERN void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p); +EXTERN void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option); +EXTERN void vSetRank(DRAMC_CTX_T *p, U8 ucRank); +EXTERN void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel); +EXTERN VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p); +EXTERN u8 lp5heff_save_disable(DRAMC_CTX_T *p); +EXTERN void lp5heff_restore(DRAMC_CTX_T *p); +EXTERN u8 is_lp5_family(DRAMC_CTX_T *p); +EXTERN U32 GetDramcBroadcast(void); +EXTERN void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, + CKE_FIX_CHANNEL WriteChannelNUM); +EXTERN void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num); +EXTERN U8 u1GetRank(DRAMC_CTX_T *p); +EXTERN void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p); +EXTERN void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p); +EXTERN U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 testaudpat); +EXTERN void DramcEngine2End(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift); +EXTERN void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num); +EXTERN DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p); +EXTERN u8 is_heff_mode(DRAMC_CTX_T *p); +EXTERN void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift); +EXTERN void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel); +EXTERN U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); +EXTERN U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type); +EXTERN U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p); +EXTERN DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p); +EXTERN void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); +EXTERN DRAM_DFS_SRAM_SHU_T vGet_Current_ShuLevel(DRAMC_CTX_T *p); +EXTERN void vSetChannelNumber(DRAMC_CTX_T *p); +EXTERN void vSetRankNumber(DRAMC_CTX_T *p); +EXTERN void vSetFSPNumber(DRAMC_CTX_T *p); +EXTERN void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode); +EXTERN DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p); +EXTERN void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); +EXTERN void Temp_TA2_Test_After_K(DRAMC_CTX_T * p); +EXTERN void DramcBroadcastOnOff(U32 bOnOff); +EXTERN DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p); +EXTERN void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listValue, U8 msk, U8 UpdateMode); +EXTERN void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode); +EXTERN void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue); +EXTERN void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u1pValue); +EXTERN void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value); +EXTERN void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff); +EXTERN void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff); +#if MRW_CHECK_ONLY +EXTERN void vPrintFinalModeRegisterSetting(DRAMC_CTX_T *p); +#endif +#if MRW_BACKUP +EXTERN U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank); +#endif +#if QT_GUI_Tool +EXTERN void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 testaudpat, U8 log2loopcount); +EXTERN U32 TestEngineCompare(DRAMC_CTX_T *p); +#endif +EXTERN void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode); +EXTERN void vSet_Current_ShuLevel(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1ShuIndex); +EXTERN void GetPhyPllFrequency(DRAMC_CTX_T *p); +EXTERN void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff); +EXTERN void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff); +EXTERN void CheckDramcWBR(U32 u4address); +EXTERN void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len); +#if PRINT_CALIBRATION_SUMMARY +EXTERN void vPrintCalibrationResult(DRAMC_CTX_T *p); +#endif +EXTERN int dramc_complex_mem_test (unsigned int start, unsigned int len); +EXTERN U16 DDRPhyFMeter(void); +#ifdef DDR_INIT_TIME_PROFILING +void TimeProfileBegin(void); +UINT32 TimeProfileEnd(void); +#endif + + + +/* + **************************************************************************************** + ** Hal_IO.cpp + **************************************************************************************** + */ +#ifdef DUMP_INIT_RG_LOG_TO_DE +EXTERN U8 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag; +#endif + + + +/* + **************************************************************************************** + ** dramc_utility.cpp + **************************************************************************************** + */ +#if (QT_GUI_Tool == 1) +EXTERN MCK_TO_UI_SHIFT_T u1Lp5MCK2WCKUI_DivShift(DRAMC_CTX_T *p); +#endif + + +/* + **************************************************************************************** + ** dramc_debug.cpp + **************************************************************************************** + */ +extern void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str); + + +/* + **************************************************************************************** + ** dramc_utility_QT.cpp + **************************************************************************************** + */ +#if (QT_GUI_Tool == 1) +EXTERN void QT_DRAMCTX_INIT(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDDRPHYInit_FPGA_A60868(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDDRPHYInit_LP5_FPGA_A60868(DRAMC_CTX_T *p); +EXTERN void TA2_Stress_Test(DRAMC_CTX_T *p); +EXTERN void TA2_Stress_Test_2(DRAMC_CTX_T *p); +EXTERN U32 QT_TestEngineCompare(DRAMC_CTX_T *p); +EXTERN void Write_Byte_Counter_Begin(DRAMC_CTX_T *p); +EXTERN U32 Write_Byte_Counter_End(DRAMC_CTX_T *p); +EXTERN void DDRPhyFMeter_Init(DRAMC_CTX_T *p); +EXTERN U32 DDRPhyFreqMeter(void); +#endif + + +/* + **************************************************************************************** + ** fake_engine.c + **************************************************************************************** + */ + + +/* + **************************************************************************************** + ** low_power_test.c + **************************************************************************************** + */ +EXTERN int global_which_test; +EXTERN void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn, U32 u4DramcShuOffset, U32 u4DDRPhyShuOffset); +EXTERN void Enter_Precharge_All(DRAMC_CTX_T *p); +EXTERN void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn); +EXTERN DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p); +EXTERN void Low_Power_Scenarios_Test(DRAMC_CTX_T *p); +#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION +void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff); +#endif + +#define LOW_POWER_SCENARIO_PRECHARGE_ALL 3 //idle(all bank refresh) +#define LOW_POWER_SCENARIO_S1 5 +#define LOW_POWER_SCENARIO_S0 6 +#define LOW_POWER_SCENARIO_PASR 7 +#define LOW_POWER_SCENARIO_ALL 8 +#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ 9 +#define LOW_POWER_SCENARIO_FAKE_ENGINE_WRITE 10 +#define LOW_POWER_SCENARIO_ONLY_SELF_REFRESH 12 +#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0 13 +#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0_METHOD_2 14 +#define LOW_POWER_SCENARIO_PASR_1BANK 15 +#define LOW_POWER_SCENARIO_PASR_2BANK 16 +#define LOW_POWER_SCENARIO_PASR_4BANK 17 +#define LOW_POWER_SCENARIO_PASR_8BANK 18 +#define LOW_POWER_SCENARIO_FAKE_ENGINE_BW 19 +#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ_WRITE 21 +#define AUTO_REFRESH_RESERVE_TEST 22 +/* + **************************************************************************************** + ** low_power_test.c + **************************************************************************************** + */ +EXTERN U8 u1StopMiniStress; +EXTERN void Ett_Mini_Strss_Test(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** LP4_dram_init.c + **************************************************************************************** + */ +EXTERN void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank); +EXTERN void LP4_UpdateInitialSettings(DRAMC_CTX_T *p); +EXTERN void LP4_DRAM_INIT(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** LP5_dram_init.c + **************************************************************************************** + */ +EXTERN void LP5_UpdateInitialSettings(DRAMC_CTX_T *p); +EXTERN void LP5_DRAM_INIT(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** system_init.c + **************************************************************************************** + */ +#if (fcFOR_CHIP_ID == fcA60868) +EXTERN void syspll_init(DRAMC_CTX_T *p); +#endif + + +/* + **************************************************************************************** + ** dramc_utility_QT.cpp + **************************************************************************************** + */ +#if (QT_GUI_Tool == 1) +EXTERN U8 ucDramRegRead_1(U32 reg_addr, U32 *reg_data); +EXTERN U8 ucDramRegWrite_1(U32 reg_addr, U32 reg_data); +#endif + + +/* + **************************************************************************************** + ** svsim_dummy.c + **************************************************************************************** + */ +#if (FOR_DV_SIMULATION_USED == 0) +#define delay_us(x) +#define delay_ns(x) +#define mysetscope() +#define broadcast_on() +#define broadcast_off() +#define timestamp_show() +#define build_api_initial() +#define conf_to_sram_sudo(...) +#endif + +/* + **************************************************************************************** + ** RS232.cpp + **************************************************************************************** + */ +#if (QT_GUI_Tool == 1) +EXTERN U8 ucDramSetReg_1(U32 address, U32 *data, U16 count); +EXTERN U8 ucDramGetReg_1(U32 address, U32 *data, U16 count); +#endif + + +/* + **************************************************************************************** + ** ett_test.c + **************************************************************************************** + */ +extern int hqa_vmddr_voltage, hqa_vmddr_class; + + +#endif //_INT_GLOBAL_H diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h b/src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h new file mode 100644 index 0000000000..356c8176c7 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _INT_SLT_H +#define _INT_SLT_H + + +//======================== EMI LPBK TEST Definition ===================================== + +#if defined(SLT) +#define ENABLE_EMI_LPBK_TEST 1 +#else +#define ENABLE_EMI_LPBK_TEST 0 +#endif + +#define EMI_LPBK_DRAM_USED !ENABLE_EMI_LPBK_TEST // 0: EMI LPBK test, 1: normal K, dram used + +#define EMI_LPBK_USE_THROUGH_IO 0 //test through IO +#define EMI_INT_LPBK_WL_DQS_RINGCNT 0 //DQS Ring cnt: through io @ 800,1600,2400,3200, emi intlpbk wo rx/tx K window +#define EMI_LPBK_ADDRESS_DEFECT 0 //test address defect, MUST use CPU WRITE mode + +#if ENABLE_EMI_LPBK_TEST +#define EMI_USE_TA2 0 // 0:CPU write, 1:TA2, DVsim/Dsim use TA2, but 1:4 mode must use cpu write(because TA2 not support 1:4 mode) +#else +#define EMI_USE_TA2 0 +#endif + +/**************************** +Summary: +1W1R: address offset : 0, 4, 8, c (1:8 mode only), no support 1:4 mode +8W1R: address offset 0x0 ~ 0xC (8W1R), 0x10 ~ 0x1C, (10W1R) (1:8 & 1:4 mode) +****************************/ +#define EMI_LPBK_1W1R 0 //CPU mode 0:8W1R, 1:1W1R + +#define EMI_LPBK_S1 0 + +#define FREQ_METER 1 +#define DQSG_COUNTER 1 + + +#define ADJUST_TXDLY_SCAN_RX_WIN 0 + +#define EMI_LPBK_K_TX 0 +#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2 //0: no pre/post-amble for TA2, 1: need pre/post-amble for cpu write + + +#define EMI_LPBK_DFS_32 0 //DFS 32<->32<->32 +#define EMI_LPBK_DFS_24 0 //DFS 24<->24<->24 +#define EMI_LPBK_DFS_16 0 //DFS 16<->16<->16 +#define EMI_LPBK_USE_LP3_PINMUX 0 +#define EMI_LPBK_8W1R 1 +#if EMI_LPBK_1W1R +#undef EMI_LPBK_8W1R +#define EMI_LPBK_8W1R 0 +#endif + +#if EMI_LPBK_USE_THROUGH_IO +#define EMI_LPBK_USE_DDR_800 1 +#else +#define EMI_LPBK_USE_DDR_800 0 +#endif +//#define K_TX_DQS_DLY 0 + +#define LP4_4266_freq_meter 533 // //shu0 533 +#define LP4_3733_freq_meter 464 // //shu0 464 +#define LP4_3200_freq_meter 386 // //shu8 386 //shu9 386 +#define LP4_2400_freq_meter 299 //shu6 299 shu5 299 +#define LP4_1600_freq_meter 191 //199 //shu4 383 shu3 191 +#define LP4_1200_freq_meter 299 //shu2 299 shu1 299 +#define LP4_800_freq_meter 199 //shu7 199 + + +#if ENABLE_EMI_LPBK_TEST //EMI_LPBK_DRAM_USED==0 +/* +#define SLT +#undef ENABLE_TMRRI_NEW_MODE +#define ENABLE_TMRRI_NEW_MODE 0 +#undef ENABLE_DUTY_SCAN_V2 +#define ENABLE_DUTY_SCAN_V2 0 +#undef ENABLE_RODT_TRACKING +#define ENABLE_RODT_TRACKING 0 +#undef TX_K_DQM_WITH_WDBI +#define TX_K_DQM_WITH_WDBI 0 +#undef ENABLE_WRITE_DBI +#define ENABLE_WRITE_DBI 0 +*/ + +#if EMI_INT_LPBK_WL_DQS_RINGCNT +#undef EMI_LPBK_USE_THROUGH_IO +#define EMI_LPBK_USE_THROUGH_IO 1 +#undef EMI_LPBK_USE_DDR_800 +#define EMI_LPBK_USE_DDR_800 0 +#endif + +#endif +//#if (EMI_LPBK_DRAM_USED) +//#undef ENABLE_MIOCK_JMETER +//#define ENABLE_MIOCK_JMETER // for TX_PER_BIT_DELAY_CELL +//#endif + + +//============================================================================= + + + + +#endif //_INT_GLOBAL_H diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h new file mode 100644 index 0000000000..af6986b6c6 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h @@ -0,0 +1,1482 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _PI_API_H +#define _PI_API_H + +#ifndef __ETT__ +#define __ETT__ 0 +#endif + +#define __FLASH_TOOL_DA__ 0 +#define CFG_DRAM_LOG_TO_STORAGE 0 + +#define FORCE_FASTK + +/***********************************************************************/ +/* Includes */ +/***********************************************************************/ + +/***********************************************************************/ +/* Constant Define */ +/***********************************************************************/ + +#define SW_CHANGE_FOR_SIMULATION 0 //calibration funciton for whole chip simulation. Code changed due to different compiler +#ifndef FOR_DV_SIMULATION_USED +#define FOR_DV_SIMULATION_USED (FALSE) ////calibration funciton for DV simulation. Code changed due to different compiler#define FT_DSIM_USED 0 +#endif +#define DV_SIMULATION_LP4 1 +#define BYPASS_CALIBRATION 0 +//Bring Up Selection : Do Not open it when normal operation +//#define SLT +//#define FIRST_BRING_UP +//#define DUMP_INIT_RG_LOG_TO_DE //dump init RG settings to DE + +#include "dramc_typedefs.h" +#include "dramc_reg_base_addr.h" +#include <soc/addressmap.h> +#include <soc/dramc_soc.h> +#include <soc/dramc_param.h> + +#define CPU_RW_TEST_AFTER_K 0 +#define TA2_RW_TEST_AFTER_K 0 + +#define ENABLE (1) +#define DISABLE (0) +#define ON (1) +#define OFF (0) +#define AUTOK_ON (1) +#define AUTOK_OFF (0) +#define DCM_ON (1) +#define DCM_OFF (0) + + +//Read Chip QT Tool +#ifndef QT_GUI_Tool +#define QT_GUI_Tool 0 //Setting 1 when using QT GUI Tool Compiler. +#define HAPS_FPFG_A60868 0 //Setting 1 when testing HAPS FPGA +#endif + +//DRAMC Chip +#define fcA60868 1 +#define fcPetrus 2 +#define fcIPM 3 +#define fcMargaux 4 +#define fcFOR_CHIP_ID fcMargaux + +#define __A60868_TO_BE_PORTING__ 0 +#define __Petrus_TO_BE_PORTING__ 0 + +#define VENDOR_SAMSUNG 1 +#define VENDOR_HYNIX 6 +#define REVISION_ID_MAGIC 0x9501 + + +#define __LP5_COMBO__ (FALSE) +#define FEATURE_RDDQC_K_DMI (FALSE) // This feature is not supported at A60868 test chip + + +#if __ETT__ +#define __FLASH_TOOL_DA__ 0 +#endif + +#if (FEATURE_RDDQC_K_DMI == TRUE) + #define RDDQC_ADD_DMI_NUM 2 +#else + #define RDDQC_ADD_DMI_NUM 0 +#endif + +#define CHANNEL_NUM 2 // single chhanel for A60868. 1 single channel, 2 dual channel, 4 channel +#define DPM_CH_NUM 2 // CH0/1 is Master, CH2/3 is Slave + +//ZQ calibration +#define ENABLE_LP4_ZQ_CAL 1 +#if ENABLE_LP4_ZQ_CAL //choose one mode to do ZQ calibration +#define ZQ_SWCMD_MODE 1 //suggested SW CMD mode +#define ZQ_RTSWCMD_MODE 0 //run time SW mode +#define ZQ_SCSM_MODE 0 //old mode +#endif + +#define CALIBRATION_SPEED_UP_DEBUG 0 +#define VENDER_JV_LOG 0 + +//SW option +#define DUAL_FREQ_K 0 //If enable, need to define DDR_xxxx the same as DUAL_FREQ_HIGH +#define ENABLE_EYESCAN_GRAPH 0 //__ETT__ //draw eye diagram after calibration, if enable, need to fix code size problem. +#define EYESCAN_GRAPH_CATX_VREF_STEP 1 // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 +#define EYESCAN_GRAPH_RX_VREF_STEP 2 +#define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127 +#if (fcFOR_CHIP_ID == fcA60868) +#define ENABLE_EYESCAN_CBT 0 //TO DO:Forece to draw CBT eye diagram after calibration +#define ENABLE_EYESCAN_RX 0 //TO DO:Forece to draw RX eye diagram after calibration +#define ENABLE_EYESCAN_TX 0 //TO DO:Forece to draw TX eye diagram after calibration +#define ENABLE_VREFSCAN 0 //TO DO:Forece to Vref Scan for calibration +#endif + +#define CHECK_HQA_CRITERIA 0 +#define REDUCE_LOG_FOR_PRELOADER 1 +#define APPLY_LP4_POWER_INIT_SEQUENCE 1 +#define ENABLE_READ_DBI 0 +#define ENABLE_WRITE_DBI 1 +#define ENABLE_WRITE_DBI_Protect 0 +#define ENABLE_TX_WDQS 1 +#define ENABLE_WDQS_MODE_2 0 +#define ENABLE_DRS 0 +#define ENABLE_TX_TRACKING 1 +#define ENABLE_K_WITH_WORST_SI_UI_SHIFT 1 +#define ETT_MINI_STRESS_USE_TA2_LOOP_MODE 1 +#define DUMP_TA2_WINDOW_SIZE_RX_TX 0 +#if ENABLE_TX_TRACKING + #define ENABLE_SW_TX_TRACKING 0 //if SW_TX_TRACKING is 0, using HW_TX_TRACKING +#endif +#define ENABLE_PA_IMPRO_FOR_TX_TRACKING 1 +#define ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK 1 +#define ENABLE_RX_TRACKING 0 +#define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error +#define ENABLE_OPEN_LOOP_MODE_OPTION 1 +#define ENABLE_TMRRI_NEW_MODE 1 +#define ENABLE_8PHASE_CALIBRATION 1 +#define ENABLE_DUTY_SCAN_V2 1 +#define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0 //0: K all Freq 1: K highest Freq +#define APPLY_DQDQM_DUTY_CALIBRATION 1 +#define IMPEDANCE_TRACKING_ENABLE //Impendence tracking +#define IMPEDANCE_HW_SAVING //mask because function fail, it lets clk swing change larger before DVFS occurs +#define ENABLE_MIOCK_JMETER +#define ENABLE_RUNTIME_MRW_FOR_LP5 1 +#define ENABLE_RODT_TRACKING 1 +#define GATING_ADJUST_TXDLY_FOR_TRACKING 1 +#define TDQSCK_PRECALCULATION_FOR_DVFS 1 +#define HW_GATING +#define ENABLE_RX_FIFO_MISMATCH_DEBUG 1 +#define VERIFY_CKE_PWR_DOWN_FLOW 0 //Lewis add for DVT +#define CBT_MOVE_CA_INSTEAD_OF_CLK 1 // need to check on LP5 +#define MRW_CHECK_ONLY 0 +#define MRW_BACKUP 0 +#define ENABLE_SAMSUNG_NT_ODT 0 +#define DRAMC_MODEREG_CHECK 0 +#define DVT_READ_LATENCY_MONITOR 0 + +#define PINMUX_AUTO_TEST_PER_BIT_CA 0 +#define PINMUX_AUTO_TEST_PER_BIT_RX 0 +#define PINMUX_AUTO_TEST_PER_BIT_TX 0 + +#define CA_PER_BIT_DELAY_CELL 1//LP4 +#if PINMUX_AUTO_TEST_PER_BIT_CA +#undef CA_PER_BIT_DELAY_CELL +#define CA_PER_BIT_DELAY_CELL 0 +#endif + +//Gating calibration +#define GATING_LEADLAG_LOW_LEVEL_CHECK 0 + +//#define ENABLE_POST_PACKAGE_REPAIR + +#define DPM_CONTROL_AFTERK +#if __ETT__ +#define ENABLE_DBG_2_0_IRQ +#endif + +//////////////////////////////////// FIXME start ///////////////////////// +#define CMD_CKE_WORKAROUND_FIX 0 +#define DQS_DUTY_SLT_CONDITION_TEST 0 +#define DV_SIMULATION_BEFORE_K 0 +#define DV_SIMULATION_DATLAT 0 +#define DV_SIMULATION_DBI_ON 0 +#define DV_SIMULATION_DFS 0 +#define DV_SIMULATION_GATING 0 +#define ENABLE_APB_MASK_WRITE 0 +#define ENABLE_DVFS_BYPASS_MR13_FSP 0 +#define ENABLE_RODT_TRACKING_SAVE_MCK 0 +#define ETT_NO_DRAM 0 +#define EYESCAN_LOG 0 +#define FSP1_CLKCA_TERM 1 +#define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED //@Darren, Wait DFS ready +#define FT_DSIM_USED 0 +#define GATING_ONLY_FOR_DEBUG 0 +#define MEASURE_DRAM_POWER_INDEX 0 +#define PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER 0 +#define REG_ACCESS_PORTING_DGB 0 +#define RX_PIPE_BYPASS_ENABLE 0 +#define SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER 0 +#define SUPPORT_PICG_MONITOR 0 +#define SUPPORT_REQ_QUEUE_BLOCK_ALE 0 +#define SUPPORT_REQ_QUEUE_READ_LATERNCY_MONITOR 0 +#define REFRESH_OVERHEAD_REDUCTION 1 +#define TEST_LOW_POWER_WITH_1_SEC_DELAY 1 //Add 1 second dealy between suspend and resume to avoid APHY control PATH is not switched to SPM {SPM_CONTROL_AFTERK} +#define TEST_LOW_POWER_WITH_STRESS 0 +#if TEST_LOW_POWER_WITH_STRESS + #undef TEST_LOW_POWER_WITH_1_SEC_DELAY + #define TEST_LOW_POWER_WITH_1_SEC_DELAY 0 +#endif +#define XRTRTR_NEW_CROSS_RK_MODE 1 +#define XRTWTW_NEW_CROSS_RK_MODE 1 +#define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 +#define SUPPORT_HYNIX_RX_DQS_WEAK_PULL 0 +#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 +//Run time config +#define TEMP_SENSOR_ENABLE // Enable rumtime HMR4 +#define ENABLE_REFRESH_RATE_DEBOUNCE 1 +#define ENABLE_PER_BANK_REFRESH 1 +#define PER_BANK_REFRESH_USE_MODE 1 // 0: original mode, 1: hybrid mode, 2: always pb mode +#define IMP_TRACKING_PB_TO_AB_REFRESH_WA 1 +#define DRAMC_MODIFIED_REFRESH_MODE 1 +#define DRAMC_CKE_DEBOUNCE 1 +#define XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + +#define SAMSUNG_LP4_NWR_WORKAROUND 0 +#define AC_TIMING_DERATE_ENABLE 1 +#define ENABLE_EARLY_BG_CMD 0 // 0: Disable 1: Enable, Reduce the CMD latency by CTO_EBG request + +//////////////////////////////////// DVFS ////////////////////////////// +#define ENABLE_DVS 1 //DVS need tracking enable +#define DRAMC_DFS_MODE 1 // 0:Legacy, 1:MD32 RG, 2: PHY RG +#define ENABLE_SRAM_DMA_WA 0 // for Pexxxs/Maxxxx/xxx868 +#define ENABLE_ECO_SRAM_DMA_MISS_REG 1 // for Maxxxx +#define ENABLE_TX_REBASE_ODT_WA 0 // for Pexxxs/xxx868 +#if ENABLE_TX_WDQS +#define ENABLE_TX_REBASE_WDQS_DQS_PI_WA 0 +#endif +#define ENABLE_DFS_DEBUG_MODE 0 +#define DFS_NOQUEUE_FLUSH_WA 1 +#define DFS_NOQUEUE_FLUSH_LATENCY_CNT 0 +#define ENABLE_DFS_NOQUEUE_FLUSH_DBG 0 +#define ENABLE_CONFIG_MCK_4TO1_MUX 0 +#define ENABLE_TPBR2PBR_REFRESH_TIMING 1 +#define ENABLE_DFS_TIMING_ENLARGE 0 +#define ENABLE_DFS_208M_CLOCK 0 +#define ENABLE_DFS_HW_SAVE_MASK 0 +#define ENABLE_LP4Y_DFS 0 +#if ENABLE_LP4Y_DFS +#define ENABLE_LP4Y_WA 1 +#define ENABLE_DFS_RUNTIME_MRW 1 +#else +#define ENABLE_LP4Y_WA 0 +#define ENABLE_DFS_RUNTIME_MRW 0 // for LP4x +#endif +#define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION // Wait overhead refresh enable, @Darren, Entry SREF -> EXIT SREF -> PDE Command violates tXSR time +#define ENABLE_RANK_NUMBER_AUTO_DETECTION 0 +#define DDR_HW_AUTOK_POLLING_CNT 100000 + +//////////////////////////////////// FIXME end///////////////////////// + +#if (fcFOR_CHIP_ID == fcA60868) +#define WORKAROUND_LP5_HEFF 1 //High efficiency mode +#undef ENABLE_RUNTIME_MRW_FOR_LP5 +#define ENABLE_RUNTIME_MRW_FOR_LP5 0 // DV fail in 868, use RTSWCMD_MRW +#endif + +#if ENABLE_RODT_TRACKING +#define GATING_RODT_LATANCY_EN 0 +#else +#define GATING_RODT_LATANCY_EN 1 +#endif + +#define CHECK_GOLDEN_SETTING (FALSE) +#define APPLY_LOWPOWER_GOLDEN_SETTINGS 1 // 0: DCM Off, 1: DCM On +#define LP5_GOLDEN_SETTING_CHECKER (FALSE) // FALSE: enable LP4 checker + +#if APPLY_LOWPOWER_GOLDEN_SETTINGS +#define TX_PICG_NEW_MODE 1 +#define RX_PICG_NEW_MODE 1 +#else +#define TX_PICG_NEW_MODE 0 +#define RX_PICG_NEW_MODE 0 +#endif +#define CMD_PICG_NEW_MODE 0 + +#define DDR_RESERVE_NEW_MODE 1 //0: old mode 1: new mode +//============================================================================= +// for D Sim sumulation used +//============================================================================= +#if QT_GUI_Tool || !FOR_DV_SIMULATION_USED +#define DV_SIMULATION_INIT_C 1 +#define SIMULATION_LP4_ZQ 1 +#define SIMULATION_SW_IMPED 1 +#define SIMULATION_MIOCK_JMETER 0 +#define SIMULATION_8PHASE 0 +#define SIMULATION_RX_INPUT_BUF 0 +#define SIMUILATION_CBT 1 +#define SIMULATION_WRITE_LEVELING 1 +#define SIMULATION_DUTY_CYC_MONITOR 0 +#define SIMULATION_GATING 1 +#define SIMULATION_DATLAT 1 +#define SIMULATION_RX_RDDQC 1 +#define SIMULATION_RX_PERBIT 1 +#define SIMULATION_TX_PERBIT 1 // Please enable with write leveling +#define SIMULATION_RX_DVS 0 +#define SIMULATION_RUNTIME_CONFIG 0 +#else +#define DV_SIMULATION_INIT_C 1 +#define SIMULATION_LP4_ZQ 1 +#define SIMULATION_SW_IMPED 1 +#define SIMULATION_MIOCK_JMETER 0 +#define SIMULATION_8PHASE 0 +#define SIMULATION_RX_INPUT_BUF 0 +#define SIMUILATION_CBT 1 +#define SIMULATION_WRITE_LEVELING 1 +#define SIMULATION_DUTY_CYC_MONITOR 0 +#define SIMULATION_GATING 1 +#define SIMULATION_DATLAT 1 +#define SIMULATION_RX_RDDQC 1 +#define SIMULATION_RX_PERBIT 1 +#define SIMULATION_TX_PERBIT 1 // Please enable with write leveling +#define SIMULATION_RX_DVS 0 +#define SIMULATION_RUNTIME_CONFIG 1 // @Darren for DV sim +#endif +//Used to keep original VREF when doing Rx calibration for RX DVS +#define DVS_CAL_KEEP_VREF 0xf + +//#define DDR_INIT_TIME_PROFILING +#define DDR_INIT_TIME_PROFILING_TEST_CNT 1 +#ifdef DDR_INIT_TIME_PROFILING +extern U16 u2TimeProfileCnt; +#endif + +//============================================================================= +// common +#define DQS_NUMBER 4 +#define DQ_DATA_WIDTH 32 // define max support bus width in the system (to allocate array size) +#define TIME_OUT_CNT 100 //100us +#define HW_REG_SHUFFLE_MAX 4 + +typedef enum +{ + BYTE_0 = 0, + BYTE_1 = 1, + ALL_BYTES +} BYTES_T; + +//Should be removed after A60868 +#define LP5_DDR4266_RDBI_WORKAROUND 0 +#define CBT_O1_PINMUX_WORKAROUND 0 +#define WLEV_O1_PINMUX_WORKAROUND 0 +#define WCK_LEVELING_FM_WORKAROUND 0 + + +/* Gating window */ +#define DQS_GW_COARSE_STEP 1 +#define DQS_GW_FINE_START 0 +#define DQS_GW_FINE_END 32 +#define DQS_GW_FINE_STEP 4 + +#define DQS_GW_UI_PER_MCK 16 +#define DQS_GW_PI_PER_UI 32 + +// DATLAT +#define DATLAT_TAP_NUMBER 32 + +// RX DQ/DQS +#define MAX_RX_DQSDLY_TAPS 508 // 0x018, May set back to 64 if no need. +#define MAX_RX_DQDLY_TAPS 252 +#define RX_VREF_NOT_SPECIFY 0xff +#define RX_VREF_DUAL_RANK_K_FREQ 1866 // if freq >=RX_VREF_DUAL_RANK_K_FREQ, Rank1 rx vref K will be enable. +#define RX_VREF_RANGE_BEGIN 0 +#define RX_VREF_RANGE_BEGIN_ODT_OFF 32 +#define RX_VREF_RANGE_BEGIN_ODT_ON 24 +#define RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63 +#define RX_VREF_RANGE_STEP 1 +#define RX_PASS_WIN_CRITERIA 30 +#define RDDQC_PINMUX_WORKAROUND 1 + +// TX DQ/DQS +#define TX_AUTO_K_ENABLE 1 +#if TX_AUTO_K_ENABLE +#define TX_AUTO_K_DEBUG_ENABLE 0 +#define TX_AUTO_K_WORKAROUND 1 +#define ENABLE_PA_IMPRO_FOR_TX_AUTOK 1 +#endif +#define MAX_TX_DQDLY_TAPS 31 // max DQ TAP number +#define MAX_TX_DQSDLY_TAPS 31 // max DQS TAP number +#define TX_OE_EXTEND 0 +#define TX_DQ_OE_SHIFT_LP5 5 +#if TX_OE_EXTEND +#define TX_DQ_OE_SHIFT_LP4 4 +#else +#define TX_DQ_OE_SHIFT_LP4 3 +#endif +#define TX_DQ_OE_SHIFT_LP3 2 +#define TX_K_DQM_WITH_WDBI 1 +#define TX_OE_CALIBATION (!TX_OE_EXTEND) + +#define TX_RETRY_ENABLE 0 +#if TX_RETRY_ENABLE +#define TX_RETRY_CONTROL_BY_SPM 1 +#define SW_TX_RETRY_ENABLE 0 +#else +#define TX_RETRY_CONTROL_BY_SPM 0 +#endif + +// Sw work around options. +#define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK 1 // work around for clock multi phase problem(cannot move clk or the clk will be bad) +#define DramcHWDQSGatingTracking_JADE_TRACKING_MODE 1 +#define DramcHWDQSGatingTracking_FIFO_MODE 1 +#define DONT_MOVE_CLK_DELAY // don't move clk delay +/* If defined for gFreqTbl and fastK + */ +#define LP4_SHU0_FREQ (1866) +#define LP4_SHU8_FREQ (1600) +#define LP4_SHU9_FREQ (1600) +#define LP4_SHU6_FREQ (1200) +#define LP4_SHU5_FREQ (1200) +#define LP4_SHU4_FREQ (800) +#define LP4_SHU3_FREQ (800) +#define LP4_SHU2_FREQ (600) +#define LP4_SHU1_FREQ (600) +#define LP4_SHU7_FREQ (400) +#define LP4_HIGHEST_FREQ LP4_SHU0_FREQ + +#define LP4_SHU0_FREQSEL (LP4_DDR3733) +#define LP4_SHU8_FREQSEL (LP4_DDR3200) +#define LP4_SHU9_FREQSEL (LP4_DDR3200) +#define LP4_SHU6_FREQSEL (LP4_DDR2400) +#define LP4_SHU5_FREQSEL (LP4_DDR2400) +#define LP4_SHU4_FREQSEL (LP4_DDR1600) +#define LP4_SHU3_FREQSEL (LP4_DDR1600) +#define LP4_SHU2_FREQSEL (LP4_DDR1200) +#define LP4_SHU1_FREQSEL (LP4_DDR1200) +#define LP4_SHU7_FREQSEL (LP4_DDR800) + +#if FOR_DV_SIMULATION_USED +#define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration +#define DEFAULT_TEST2_2_CAL 0xaa000020 // pattern1 and offset address for test engine when we do calibraion +#else +#define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration +#define DEFAULT_TEST2_2_CAL 0xaa000100 // pattern1 and offset address for test engine when we do calibraion +#endif + +//CBT/CA training +#define CATRAINING_NUM_LP4 6 +#define CATRAINING_NUM_LP5 7 +#define CATRAINING_NUM CATRAINING_NUM_LP5 +#define LP4_MRFSP_TERM_FREQ 1333 +#define LP5_MRFSP_TERM_FREQ 1866 + +//Calibration Summary +#define PRINT_CALIBRATION_SUMMARY (!SW_CHANGE_FOR_SIMULATION) +#define PRINT_CALIBRATION_SUMMARY_DETAIL 1 +#define PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 0 + +#if 1 //(FOR_DV_SIMULATION_USED==0) +#define ETT_PRINT_FORMAT // Apply for both preloader and ETT +#endif + +//#define FOR_HQA_TEST_USED // HQA test used, to print result for easy report +//#define FOR_HQA_REPORT_USED +//Run Time Config +//#define DUMMY_READ_FOR_TRACKING +#define ZQCS_ENABLE_LP4 +#ifndef ZQCS_ENABLE_LP4 +#define ENABLE_SW_RUN_TIME_ZQ_WA +#endif + +//============================ For Future DVT Definition ================================= + +#define ENABLE_DVFS_CDC_SYNCHRONIZER_OPTION 1 +#define ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION 1 +#define ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION 1 +#define ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION 1 +#define RDSEL_TRACKING_EN 0 // @Darren, for SHU0 only (DDR3733 or DDR4266) +#define ENABLE_DFS_SSC_WA 0 +#define ENABLE_DDR800_OPEN_LOOP_MODE_OPTION 1 + +//============================================================================= +//#define DDR_BASE 0x40000000ULL //for DV sim and ett_test.c +/***********************************************************************/ +/* Defines */ +/***********************************************************************/ +#define CBT_LOW_FREQ 0 +#define CBT_HIGH_FREQ 1 +#define CBT_UNKNOWN_FREQ 0xFF + + +#if !__ETT__ +// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify +#if (FOR_DV_SIMULATION_USED==0) && !defined(SLT) +// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify +#define SUPPORT_SAVE_TIME_FOR_CALIBRATION 1 + +#if defined(FORCE_FASTK) && !SUPPORT_SAVE_TIME_FOR_CALIBRATION +#error "FORCE_FASTK needs enable SUPPORT_SAVE_TIME_FOR_CALIBRATION!" +#endif + +#else +// DV simulation, use full calibration flow +#define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 +#endif +#define EMMC_READY 1 +#define BYPASS_VREF_CAL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_CBT (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_DATLAT (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_WRITELEVELING (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_RDDQC (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_RXWINDOW (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_TXWINDOW (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_TXOE (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_GatingCal (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_CA_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +//#define BYPASS_TX_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#else +// ETT +#define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 +#define EMMC_READY 0 +#define BYPASS_VREF_CAL 1 +#define BYPASS_CBT 1 +#define BYPASS_DATLAT 1 +#define BYPASS_WRITELEVELING 1 +#define BYPASS_RDDQC 1 +#define BYPASS_RXWINDOW 1 +#define BYPASS_TXWINDOW 1 +#define BYPASS_TXOE 1 +#define BYPASS_GatingCal 1 +#define BYPASS_CA_PER_BIT_DELAY_CELL CA_PER_BIT_DELAY_CELL +//#define BYPASS_TX_PER_BIT_DELAY_CELL 0 +#endif + +#define ENABLE_PINMUX_FOR_RANK_SWAP 0 + +//======================== FIRST_BRING_UP Init Definition ===================== +#ifdef FIRST_BRING_UP + +//#define USE_CLK26M + +#undef TDQSCK_PRECALCULATION_FOR_DVFS +#define TDQSCK_PRECALCULATION_FOR_DVFS 0//DQS pre-calculation + +#undef CHANNEL_NUM +#define CHANNEL_NUM 2 + +#undef ENABLE_DUTY_SCAN_V2 +#define ENABLE_DUTY_SCAN_V2 0 + +#undef ENABLE_DRS +#define ENABLE_DRS 0 + +#undef ENABLE_CA_TRAINING +#define ENABLE_CA_TRAINING 1 +#undef ENABLE_WRITE_LEVELING +#define ENABLE_WRITE_LEVELING 1 +#undef ENABLE_PHY_RX_INPUT_OFFSET +#define ENABLE_PHY_RX_INPUT_OFFSET 0 + +//#undef REDUCE_LOG_FOR_PRELOADER +//#define REDUCE_LOG_FOR_PRELOADER 0 + +#undef REDUCE_CALIBRATION_OLYMPUS_ONLY +#define REDUCE_CALIBRATION_OLYMPUS_ONLY 0 + +#undef APPLY_LOWPOWER_GOLDEN_SETTINGS +#define APPLY_LOWPOWER_GOLDEN_SETTINGS 0 //Should open APPLY_LOWPOWER_GOLDEN_SETTINGS before SB + 3 + +//#undef SPM_CONTROL_AFTERK //Should open SPM_CONTROL_AFTERK before SB + 3 + +#undef TX_K_DQM_WITH_WDBI +#define TX_K_DQM_WITH_WDBI 0 + +#undef ENABLE_EYESCAN_GRAPH +#define ENABLE_EYESCAN_GRAPH 0 + +#undef PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER +#define PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER 0 + +#undef ENABLE_TX_TRACKING +#undef ENABLE_SW_TX_TRACKING +#define ENABLE_TX_TRACKING 0 +#define ENABLE_SW_TX_TRACKING 0 + +#undef ENABLE_RX_TRACKING +#define ENABLE_RX_TRACKING 0 + +#undef ENABLE_PER_BANK_REFRESH +#define ENABLE_PER_BANK_REFRESH 1 + +#undef CMD_PICG_NEW_MODE +#define CMD_PICG_NEW_MODE 0 + +#undef XRTWTW_NEW_CROSS_RK_MODE +#define XRTWTW_NEW_CROSS_RK_MODE 1 +#undef XRTRTR_NEW_CROSS_RK_MODE +#define XRTRTR_NEW_CROSS_RK_MODE 1 + +#undef ENABLE_DVFS_BYPASS_MR13_FSP +#define ENABLE_DVFS_BYPASS_MR13_FSP 0 + +#undef HW_GATING +#undef DUMMY_READ_FOR_TRACKING +#undef ZQCS_ENABLE_LP4 +//#define ZQCS_ENABLE_LP4 + +#undef TEMP_SENSOR_ENABLE +//#define TEMP_SENSOR_ENABLE +#undef IMPEDANCE_TRACKING_ENABLE +//#define IMPEDANCE_TRACKING_ENABLE +#undef ENABLE_SW_RUN_TIME_ZQ_WA + +//#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + +#undef APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST +#define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 + +#undef DFS_NOQUEUE_FLUSH_WA +#define DFS_NOQUEUE_FLUSH_WA 0 + + +#undef TX_PICG_NEW_MODE +#undef RX_PICG_NEW_MODE +#undef ENABLE_RX_DCM_DPHY +#define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error +#if APPLY_LOWPOWER_GOLDEN_SETTINGS +#define TX_PICG_NEW_MODE 1 +#define RX_PICG_NEW_MODE 1 +#else +#define TX_PICG_NEW_MODE 0 +#define RX_PICG_NEW_MODE 0 +#endif + + +#if 0 +#undef XRTW2W_PERFORM_ENHANCE_TX +#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY +#ifdef XRTR2W_PERFORM_ENHANCE_RODTEN +#undef XRTR2W_PERFORM_ENHANCE_RODTEN //conflict with ENABLE_RODT_TRACKING, LP4 support only +#endif +#endif +#endif //FIRST_BRING_UP + +#define CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO 0 +#define RUNTIME_SHMOO_RELEATED_FUNCTION CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO +#define RUNTIME_SHMOO_RG_BACKUP_NUM (100) +#define RUNTIME_SHMOO_TX 0 //TX RX can't be opened simultaneously +#define RUNTIME_SHMOO_RX 0 +#if RUNTIME_SHMOO_RELEATED_FUNCTION //if enable rshmoo, close TX OE calibration +#undef TX_OE_EXTEND +#define TX_OE_EXTEND 1 +#undef TX_DQ_OE_SHIFT_LP4 +#define TX_DQ_OE_SHIFT_LP4 4 +#undef TX_OE_CALIBATION +#define TX_OE_CALIBATION (!TX_OE_EXTEND) +#undef ENABLE_RX_TRACKING_LP4 +#define ENABLE_RX_TRACKING_LP4 0 +#undef ENABLE_TX_TRACKING +#undef ENABLE_SW_TX_TRACKING +#define ENABLE_TX_TRACKING 0 +#define ENABLE_SW_TX_TRACKING 0 +#define RUNTIME_SHMOO_FAST_K 1 +#define RUNTIME_SHMOO_TEST_CHANNEL 0 // 0: CHA, 1: CHB +#define RUNTIME_SHMOO_TEST_RANK 0 // 0: RK0, 1: RK1 +#define RUNTIME_SHMOO_TEST_BYTE 0 // 0: Byte0, 1: Byte1 +#define RUNTIME_SHMOO_TEST_PI_DELAY_START 0 // 0~63 +#define RUNTIME_SHMOO_TEST_PI_DELAY_END 63 // 0~63 +#define RUNTIME_SHMOO_TEST_PI_DELAY_STEP 1 +#define RUNTIME_SHMOO_RX_VREF_RANGE_END 127 //La_fite: 63 +#define RUNTIME_SHMOO_RX_TEST_MARGIN 2 //for RX Delay (start:first_pass-margin, end:last_pass +margin) +#define RUNTIME_SHMOO_TEST_VREF_START 0 // 0~81 : 0~50 is range 0, 51~81 is range 1 +#define RUNTIME_SHMOO_TEST_VREF_END 81 // 0~81 : 0~50 is range 0, 51~81 is range 1 +#define RUNTIME_SHMOO_TEST_VREF_STEP 1 +#endif +typedef enum +{ + CLK_MUX_208M = 0, + CLK_MUX_104M, + CLK_MUX_52M, +} CLK_MUX_T; + +typedef enum +{ + BEF_DFS_MODE = 0, + AFT_DFS_MODE, + CHG_CLK_MODE, +} DFS_DBG_T; + +typedef enum +{ + SHUFFLE_HW_MODE = 0, + SPM_DEBUG_MODE, + RG_DEBUG_MODE, +} DFS_IP_CLOCK_T; + +typedef enum +{ + DutyScan_Calibration_K_CLK= 0, + DutyScan_Calibration_K_DQS, + DutyScan_Calibration_K_DQ, + DutyScan_Calibration_K_DQM, + DutyScan_Calibration_K_WCK +} DUTYSCAN_CALIBRATION_FLOW_K_T; + +typedef enum +{ + DQS_8PH_DEGREE_0 = 0, + DQS_8PH_DEGREE_180, + DQS_8PH_DEGREE_45, + DQS_8PH_DEGREE_MAX, +} DQS_8_PHASE_T; + +typedef enum +{ + DRVP = 0, + DRVN, + ODTP, + ODTN, + IMP_DRV_MAX +} DRAM_IMP_DRV_T; + +typedef enum +{ + IMP_LOW_FREQ = 0, + IMP_HIGH_FREQ, + IMP_NT_ODTN, // Samsung support only for LP4X + IMP_VREF_MAX +} DRAMC_IMP_T; + +typedef enum +{ + GET_MDL_USED = 0, + NORMAL_USED, + SLT_USED +} DRAM_INIT_USED_T; + +typedef enum +{ + PATTERN_RDDQC, + PATTERN_TEST_ENGINE, +} RX_PATTERN_OPTION_T; + +typedef enum +{ + DRAM_OK = 0, // OK + DRAM_FAIL, // FAIL + DRAM_FAST_K, + DRAM_NO_K, +} DRAM_STATUS_T; // DRAM status type + +typedef enum +{ + VREF_RANGE_0= 0, + VREF_RANGE_1, + VREF_RANGE_MAX +}DRAM_VREF_RANGE_T; +#define VREF_VOLTAGE_TABLE_NUM_LP4 51 +#define VREF_VOLTAGE_TABLE_NUM_LP5 128 + +typedef enum +{ + CKE_FIXOFF = 0, + CKE_FIXON, + CKE_DYNAMIC //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) +} CKE_FIX_OPTION; + +typedef enum +{ + CKE_WRITE_TO_ONE_CHANNEL = 0, //just need to write CKE FIX register to current channel + CKE_WRITE_TO_ALL_CHANNEL, //need to write CKE FIX register to all channel + CKE_WRITE_TO_ALL_RANK +} CKE_FIX_CHANNEL; + +typedef enum +{ + LP5_DDR6400 = 0, + LP5_DDR6000, + LP5_DDR5500, + LP5_DDR4800, + LP5_DDR4266, + LP5_DDR3733, + LP5_DDR3200, + LP5_DDR2400, + LP5_DDR1600, + LP5_DDR1200, + LP5_DDR800, + + LP4_DDR4266, + LP4_DDR3733, + LP4_DDR3200, + LP4_DDR2667, + LP4_DDR2400, + LP4_DDR2280, + LP4_DDR1866, + LP4_DDR1600, + LP4_DDR1200, + LP4_DDR800, + LP4_DDR400, + + PLL_FREQ_SEL_MAX +} DRAM_PLL_FREQ_SEL_T; // DRAM DFS type + +typedef enum +{ + MCK_TO_4UI_SHIFT = 2, + MCK_TO_8UI_SHIFT = 3, + MCK_TO_16UI_SHIFT = 4 +} MCK_TO_UI_SHIFT_T; + +typedef enum +{ + AUTOK_CA, + AUTOK_CS, + AUTOK_DQS +} ATUOK_MODE_T; + +typedef enum +{ + AUTOK_RESPI_1 = 0, + AUTOK_RESPI_2 = 1, + AUTOK_RESPI_4 = 2, + AUTOK_RESPI_8 = 3 +} AUTOK_PI_RESOLUTION; + +typedef enum +{ + DRAM_DFS_REG_SHU0 = 0, + DRAM_DFS_REG_SHU1, + DRAM_DFS_REG_MAX +} DRAM_DFS_REG_SHU_T; + +typedef enum +{ + SRAM_SHU0 = 0, + SRAM_SHU1, + SRAM_SHU2, + SRAM_SHU3, + SRAM_SHU4, + SRAM_SHU5, + SRAM_SHU6, + DRAM_DFS_SRAM_MAX +} DRAM_DFS_SRAM_SHU_T; // DRAM SRAM RG type + +typedef enum +{ + SHUFFLE_RG = 0, + NONSHUFFLE_RG, + BOTH_SHU_NONSHU_RG, +} RG_SHU_TYPE_T; // RG SHUFFLE type +typedef enum +{ + DIV16_MODE = 0, + DIV8_MODE, + DIV4_MODE, + UNKNOWN_MODE, +} DIV_MODE_T; + +typedef enum +{ + DUTY_DEFAULT = 0, + DUTY_NEED_K, + DUTY_LAST_K +} DUTY_CALIBRATION_T; + + +typedef enum +{ + VREF_CALI_OFF = 0, + VREF_CALI_ON, +} VREF_CALIBRATION_ENABLE_T; + +typedef enum +{ + DDR800_CLOSE_LOOP = 0, + OPEN_LOOP_MODE, + SEMI_OPEN_LOOP_MODE, + CLOSE_LOOP_MODE, +} DDR800_MODE_T; + +typedef enum +{ + DRAM_CALIBRATION_SW_IMPEDANCE= 0, + DRAM_CALIBRATION_DUTY_SCAN, + DRAM_CALIBRATION_ZQ, + DRAM_CALIBRATION_JITTER_METER, + DRAM_CALIBRATION_CA_TRAIN , + DRAM_CALIBRATION_WRITE_LEVEL, + DRAM_CALIBRATION_GATING, + DRAM_CALIBRATION_RX_RDDQC, + DRAM_CALIBRATION_TX_PERBIT, + DRAM_CALIBRATION_DATLAT, + DRAM_CALIBRATION_RX_PERBIT, + DRAM_CALIBRATION_TX_OE, + DRAM_CALIBRATION_MAX +} DRAM_CALIBRATION_STATUS_T; + +typedef struct _DRAM_DFS_FREQUENCY_TABLE_T +{ + DRAM_PLL_FREQ_SEL_T freq_sel; + DIV_MODE_T divmode; + DRAM_DFS_SRAM_SHU_T shuffleIdx; + DUTY_CALIBRATION_T duty_calibration_mode; + VREF_CALIBRATION_ENABLE_T vref_calibartion_enable; // CBT/RX/TX vref calibration enable or not + DDR800_MODE_T ddr_loop_mode; +} DRAM_DFS_FREQUENCY_TABLE_T; + +typedef enum +{ + CHANNEL_SINGLE = 1, + CHANNEL_DUAL, +#if (CHANNEL_NUM > 2) + CHANNEL_THIRD, + CHANNEL_FOURTH +#endif +} DRAM_CHANNEL_NUMBER_T; + + +typedef enum +{ + RANK_SINGLE = 1, + RANK_DUAL +} DRAM_RANK_NUMBER_T; + + +typedef enum +{ + TYPE_DDR1 = 1, + TYPE_LPDDR2, + TYPE_LPDDR3, + TYPE_PCDDR3, + TYPE_LPDDR4, + TYPE_LPDDR4X, + TYPE_LPDDR4P, + TYPE_LPDDR5 +} DRAM_DRAM_TYPE_T; + +typedef enum +{ + PINMUX_DSC = 0, + PINMUX_LPBK, + PINMUX_EMCP, + PINMUX_MAX +} DRAM_PINMUX; + +/* For faster switching between term and un-term operation + * FSP_0: For un-terminated freq. + * FSP_1: For terminated freq. + */ +typedef enum +{ + FSP_0 = 0, + FSP_1, + FSP_2, + FSP_MAX +} DRAM_FAST_SWITH_POINT_T; + +typedef struct +{ + u8 pat_v[8]; + u8 pat_a[8]; + u8 pat_dmv; + u8 pat_dma; + u8 pat_cs0; + u8 pat_cs1; + u8 ca_golden_sel; + u8 invert_num; +} new_cbt_pat_cfg_t; + +typedef enum +{ + TRAINING_MODE1 = 0, + TRAINING_MODE2 +} lp5_training_mode_t; + +typedef enum +{ + CBT_PHASE_RISING = 0, + CBT_PHASE_FALLING +} lp5_cbt_phase_t; + +/* + * External CBT mode enum + * Due to MDL structure compatibility (single field for dram CBT mode), + * the below enum is used in preloader to differentiate between dram cbt modes + */ +typedef enum +{ + CBT_R0_R1_NORMAL = 0, // Normal mode + CBT_R0_R1_BYTE, // Byte mode + CBT_R0_NORMAL_R1_BYTE, // Mixed mode R0: Normal R1: Byte + CBT_R0_BYTE_R1_NORMAL // Mixed mode R0: Byte R1: Normal +} DRAM_CBT_MODE_EXTERN_T; + +typedef enum +{ + ODT_OFF = 0, + ODT_ON +} DRAM_ODT_MODE_T; + +typedef enum +{ + DBI_OFF = 0, + DBI_ON +} DRAM_DBI_MODE_T; + +typedef enum +{ + DATA_WIDTH_16BIT = 16, + DATA_WIDTH_32BIT = 32 +} DRAM_DATA_WIDTH_T; + +typedef enum +{ + TE_OP_WRITE_READ_CHECK = 0, + TE_OP_READ_CHECK +} DRAM_TE_OP_T; + +typedef enum +{ + TEST_ISI_PATTERN = 0, //don't change + TEST_AUDIO_PATTERN = 1, //don't change + TEST_XTALK_PATTERN = 2, //don't change + TEST_WORST_SI_PATTERN, + TEST_TA1_SIMPLE, + TEST_TESTPAT4, + TEST_TESTPAT4_3, + TEST_MIX_PATTERN, + TEST_DMA, + TEST_SSOXTALK_PATTERN, +} DRAM_TEST_PATTERN_T; + +typedef enum +{ + TE_NO_UI_SHIFT = 0, + TE_UI_SHIFT +} DRAM_TE_UI_SHIFT_T; + +typedef enum +{ + TX_DQ_DQS_MOVE_DQ_ONLY = 0, + TX_DQ_DQS_MOVE_DQM_ONLY, + TX_DQ_DQS_MOVE_DQ_DQM +} DRAM_TX_PER_BIT_CALIBRATION_TYTE_T; + +typedef enum +{ + TX_DQM_WINDOW_SPEC_IN = 0xfe, + TX_DQM_WINDOW_SPEC_OUT = 0xff +} DRAM_TX_PER_BIT_DQM_WINDOW_RESULT_TYPE_T; + +// enum for CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT)) +typedef enum +{ + CKE_RANK_INDEPENDENT = 0, + CKE_RANK_DEPENDENT +} CKE_CTRL_MODE_T; + +typedef enum +{ + TA2_RKSEL_XRT = 3, + TA2_RKSEL_HW = 4, +} TA2_RKSEL_TYPE_T; + +typedef enum +{ + TA2_PAT_SWITCH_OFF = 0, + TA2_PAT_SWITCH_ON, +} TA2_PAT_SWITCH_TYPE_T; + +typedef enum +{ + PHYPLL_MODE = 0, + CLRPLL_MODE, +} PLL_MODE_T; + +typedef enum +{ + RUNTIME_SWCMD_CAS_FS = 0, + RUNTIME_SWCMD_CAS_OFF, + RUNTIME_SWCMD_WCK2DQI_START, + RUNTIME_SWCMD_WCK2DQO_START, + RUNTIME_SWCMD_MRW, + RUNTIME_SWCMD_ZQCAL_START, + RUNTIME_SWCMD_ZQCAL_LATCH +} RUNTIME_SWCMD_SEL_T; + +typedef enum +{ + PI_BASED, + DLY_BASED +} WLEV_DELAY_BASED_T; + +enum lpddr5_rpre_mode { + LPDDR5_RPRE_4S_0T = 0, + LPDDR5_RPRE_2S_2T, + LPDDR5_RPRE_0S_4T, + LPDDR5_RPRE_XS_4T, /* X = 2~4tWCK */ +}; + +enum rxdqs_autok_burst_len { + RXDQS_BURST_LEN_8 = 0, + RXDQS_BURST_LEN_16, + RXDQS_BURST_LEN_32, +}; + +typedef enum +{ + EYESCAN_FLAG_DISABLE= 0, + EYESCAN_FLAG_ENABLE, + EYESCAN_FLAG_ENABLE_BUT_NORMAL_K, +} EYESCAN_FLAG_TYPE_T; + +#ifdef FOR_HQA_REPORT_USED +typedef enum +{ + HQA_REPORT_FORMAT0 = 0, + HQA_REPORT_FORMAT0_1, + HQA_REPORT_FORMAT0_2, + HQA_REPORT_FORMAT1, + HQA_REPORT_FORMAT2, + HQA_REPORT_FORMAT2_1, + HQA_REPORT_FORMAT3, + HQA_REPORT_FORMAT4, + HQA_REPORT_FORMAT5, + HQA_REPORT_FORMAT6 +} HQA_REPORT_FORMAT_T; +#endif + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION +#if RUNTIME_SHMOO_RELEATED_FUNCTION +typedef struct _RUNTIME_SHMOO_SAVE_PARAMETER_T +{ + U8 flag; + U16 TX_PI_delay; + U16 TX_Original_PI_delay; + U16 TX_DQM_PI_delay; + U16 TX_Original_DQM_PI_delay; + S16 RX_delay[8]; + S16 RX_Original_delay; + U8 TX_Vref_Range; + U8 TX_Vref_Value; + U8 TX_Channel; + U8 TX_Rank; + U8 TX_Byte; + U8 Scan_Direction; +} RUNTIME_SHMOO_SAVE_PARAMETER_T; +#endif + +typedef struct _SAVE_TIME_FOR_CALIBRATION_T +{ + //U8 femmc_Ready; + + DRAM_RANK_NUMBER_T support_rank_num; + + U16 u2num_dlycell_perT; + U16 u2DelayCellTimex100; + + // CLK & DQS duty + S8 s1ClockDuty_clk_delay_cell[CHANNEL_NUM][RANK_MAX]; + S8 s1DQSDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; + S8 s1WCKDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; +#if APPLY_DQDQM_DUTY_CALIBRATION + S8 s1DQDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; + S8 s1DQMDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; +#endif + // CBT + U8 u1CBTVref_Save[CHANNEL_NUM][RANK_MAX]; + S8 s1CBTCmdDelay_Save[CHANNEL_NUM][RANK_MAX]; + U8 u1CBTCsDelay_Save[CHANNEL_NUM][RANK_MAX]; + #if CA_PER_BIT_DELAY_CELL + U8 u1CBTCA_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQS_BIT_NUMBER]; + #endif + + // Write leveling + U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; //for bypass writeleveling + + // Gating + U8 u1Gating_MCK_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U8 u1Gating_UI_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U8 u1Gating_PI_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U8 u1Gating_pass_count_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + + // TX perbit + U8 u1TxWindowPerbitVref_Save[CHANNEL_NUM][RANK_MAX]; + U16 u1TxCenter_min_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1TxCenter_max_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1Txwin_center_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + // Datlat + U8 u1RxDatlat_Save[CHANNEL_NUM][RANK_MAX]; + + // RX perbit + U8 u1RxWinPerbitVref_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1RxWinPerbit_DQS[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1RxWinPerbit_DQM[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1RxWinPerbit_DQ[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + //TX OE + U8 u1TX_OE_DQ_MCK[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U8 u1TX_OE_DQ_UI[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + + +#if RUNTIME_SHMOO_RELEATED_FUNCTION + S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; //for bypass rxwindow + U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; //for bypass rxwindow + U8 u1SwImpedanceResule[2][4]; + U32 u4RG_Backup[CHANNEL_NUM][RUNTIME_SHMOO_RG_BACKUP_NUM]; + + RUNTIME_SHMOO_SAVE_PARAMETER_T Runtime_Shmoo_para; +#endif +}SAVE_TIME_FOR_CALIBRATION_T; +#endif // SUPPORT_SAVE_TIME_FOR_CALIBRATION + +#if MRW_CHECK_ONLY +#define MR_NUM 64 +extern U16 u2MRRecord[CHANNEL_NUM][RANK_MAX][FSP_MAX][MR_NUM]; +#endif + +//////////////////////////// +typedef struct _DRAMC_CTX_T +{ + DRAM_CHANNEL_NUMBER_T support_channel_num; + DRAM_CHANNEL_T channel; + DRAM_RANK_NUMBER_T support_rank_num; + DRAM_RANK_T rank; + DRAM_PLL_FREQ_SEL_T freq_sel; + DRAM_DFS_SHUFFLE_TYPE_T shu_type; + DRAM_DRAM_TYPE_T dram_type; + DRAM_FAST_SWITH_POINT_T dram_fsp; // only for LP4, uesless in LP3 + DRAM_ODT_MODE_T odt_onoff;/// only for LP4, uesless in LP3 + DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX]; //only for LP4, useless in LP3 + DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX]; // only for LP4, uesless in LP3 + DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX]; // only for LP4, uesless in LP3 + DRAM_DATA_WIDTH_T data_width; + U32 test2_1; + U32 test2_2; + DRAM_TEST_PATTERN_T test_pattern; + U16 frequency; + U16 freqGroup; /* Used to support freq's that are not in ACTimingTable */ + U16 vendor_id; + U16 revision_id; + U16 density; + U64 ranksize[RANK_MAX]; + U16 u2num_dlycell_perT; + U16 u2DelayCellTimex100; + //U8 enable_cbt_scan_vref; + //U8 enable_rx_scan_vref; + //U8 enable_tx_scan_vref; + + #if PRINT_CALIBRATION_SUMMARY + U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail + U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done + U32 SWImpCalResult; + U32 SWImpCalExecute; + #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK + U32 FastKResultFlag[2][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail + U32 FastKExecuteFlag[2][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done + #endif + #endif + + bool isWLevInitShift[CHANNEL_NUM]; + + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + U8 femmc_Ready; + // Calibration or not + U8 Bypass_TXWINDOW; + U8 Bypass_RXWINDOW; + U8 Bypass_RDDQC; + SAVE_TIME_FOR_CALIBRATION_T *pSavetimeData; + #endif + DRAM_DFS_FREQUENCY_TABLE_T *pDFSTable; + DRAM_DFS_REG_SHU_T ShuRGAccessIdx; + lp5_training_mode_t lp5_training_mode; //only for LP5 + lp5_cbt_phase_t lp5_cbt_phase; //only for LP5 + u8 new_cbt_mode; + U8 u1PLLMode; + DRAM_DBI_MODE_T curDBIState; + DRAM_FAST_SWITH_POINT_T support_fsp_num; + DRAM_PINMUX DRAMPinmux; + U8 u110GBEn[RANK_MAX]; + bool isMaxFreq4266; +} DRAMC_CTX_T; + +typedef struct _DRAM_DVFS_TABLE_T +{ + DRAM_PLL_FREQ_SEL_T freq_sel; + DIV_MODE_T divmode; + DRAM_DFS_SRAM_SHU_T shuffleIdx; + U32 u4Vcore; +} DRAM_DVFS_TABLE_T; + +typedef struct _PASS_WIN_DATA_T +{ + S16 first_pass; + S16 last_pass; + S16 win_center; + U16 win_size; + U16 best_dqdly; +} PASS_WIN_DATA_T; + +typedef struct _FINAL_WIN_DATA_T { + unsigned char final_vref; + signed int final_ca_clk; + unsigned char final_range; +} FINAL_WIN_DATA_T; + +typedef struct _REG_TRANSFER +{ + U32 u4Addr; + U32 u4Fld; +} REG_TRANSFER_T; + +typedef struct _DRAM_INFO_BY_MRR_T +{ + U16 u2MR5VendorID; + U16 u2MR6RevisionID; + U64 u8MR8RankSize[RANK_MAX]; +} DRAM_INFO_BY_MRR_T; + +#if __FLASH_TOOL_DA__ +typedef struct _DEBUG_PIN_INF_FOR_FLASHTOOL_T +{ + U16 TOTAL_ERR;//DQ,CA + U16 IMP_ERR_FLAG; + U8 WL_ERR_FLAG;//DQS + U8 CA_ERR_FLAG[CHANNEL_MAX][RANK_MAX]; + U8 CA_WIN_SIZE[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP4]; + U8 DRAM_PIN_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + U8 DRAM_PIN_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + U8 DQ_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + U8 DQ_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + U16 DQ_RX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + U8 DQ_TX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; +} DEBUG_PIN_INF_FOR_FLASHTOOL_T; +#endif +typedef struct _VCORE_DELAYCELL_T +{ + U32 u2Vcore; + U16 u2DelayCell; +} VCORE_DELAYCELL_T; + +typedef enum +{ + DMA_PREPARE_DATA_ONLY, + DMA_CHECK_DATA_ACCESS_ONLY_AND_NO_WAIT, + DMA_CHECK_COMAPRE_RESULT_ONLY, + DMA_CHECK_DATA_ACCESS_AND_COMPARE, +} DRAM_DMA_CHECK_RESULT_T; + + +//For new register access +#define SHIFT_TO_CHB_ADDR ((U32)CHANNEL_B << POS_BANK_NUM) +#if (CHANNEL_NUM > 2) +#define SHIFT_TO_CHC_ADDR ((U32)CHANNEL_C << POS_BANK_NUM) +#define SHIFT_TO_CHD_ADDR ((U32)CHANNEL_D << POS_BANK_NUM) +#endif +#define DRAMC_REG_ADDR(offset) ((p->channel << POS_BANK_NUM) + (offset)) +#define SYS_REG_ADDR(offset) (offset) + +// Different from Pi_calibration.c due to Base address +//#define mcSET_DRAMC_REG_ADDR(offset) (DRAMC_BASE_ADDRESS | (p->channel << POS_BANK_NUM) | (offset)) +#define mcSET_SYS_REG_ADDR(offset) (DRAMC_BASE_ADDRESS | (offset)) +#define mcSET_DRAMC_NAO_REG_ADDR(offset) (DRAMC_NAO_BASE_ADDRESS | (offset)) +#define mcSET_DRAMC_AO_REG_ADDR(offset) (DRAMC_AO_BASE_ADDRESS | (offset)) +//#define mcSET_DRAMC_AO_REG_ADDR_CHC(offset) ((DRAMC_AO_BASE_ADDRESS + ((U32)CHANNEL_C << POS_BANK_NUM)) | (offset)) +#define mcSET_DDRPHY_REG_ADDR(offset) (DDRPHY_BASE_ADDR | (offset)) +#define mcSET_DDRPHY_REG_ADDR_CHA(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_A << POS_BANK_NUM)) | (offset)) +#define mcSET_DDRPHY_REG_ADDR_CHB(offset) ((DDRPHY_BASE_ADDR + SHIFT_TO_CHB_ADDR) | (offset)) +//#define mcSET_DDRPHY_REG_ADDR_CHC(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_C << POS_BANK_NUM)) | (offset)) +//#define mcSET_DDRPHY_REG_ADDR_CHD(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_D << POS_BANK_NUM)) | (offset)) + +//-------------------------------------------------------------------------- +// Dram Mode Registers Operation +//-------------------------------------------------------------------------- +#define MRWriteFldMulti(p, mr_idx, list, UpdateMode) \ +{ \ + UINT16 upk = 1; \ + U8 msk = (U8)(list); \ + { \ + upk = 0; \ + DramcMRWriteFldMsk(p, mr_idx, (U8)(list), msk, UpdateMode); \ + } \ +} + +#define JUST_TO_GLOBAL_VALUE (0) +#define TO_MR (1) + +// LP5 MR30 +#define MR30_DCAU (Fld(4, 4)) // DCA for upper byte +#define MR30_DCAL (Fld(4, 0)) // DCA for lower byte + +// LP5 MR26 +#define MR26_DCMU1 (Fld(1, 5)) +#define MR26_DCMU0 (Fld(1, 4)) +#define MR26_DCML1 (Fld(1, 3)) +#define MR26_DCML0 (Fld(1, 2)) +#define MR26_DCM_FLIP (Fld(1, 1)) +#define MR26_DCM_START_STOP (Fld(1, 0)) + +// LP4 MR13 +#define MR13_FSP_OP (Fld(1, 7)) +#define MR13_FSP_WR (Fld(1, 6)) +#define MR13_DMD (Fld(1, 5)) +#define MR13_PRO (Fld(1, 4)) +#define MR13_VRCG (Fld(1, 3)) +#define MR13_CBT (Fld(1, 0)) + +#define MR16_FSP_WR_SHIFT (0) +#define MR16_FSP_OP_SHIFT (2) +#define MR16_FSP_CBT (4) +#define MR16_VRCG (6) +#define MR16_CBT_PHASE (7) + +/***********************************************************************/ +/* External declarations */ +/***********************************************************************/ +EXTERN DRAMC_CTX_T *psCurrDramCtx; +#if QT_GUI_Tool +EXTERN FILE *fp_A60868; +EXTERN FILE *fp_A60868_RGDump; +#endif +/***********************************************************************/ +/* Public Functions */ +/***********************************************************************/ +// basic function +EXTERN U8 u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type); +EXTERN int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used); +EXTERN void Dramc_DDR_Reserved_Mode_setting(void); +EXTERN void Dramc_DDR_Reserved_Mode_AfterSR(void); +EXTERN void Before_Init_DRAM_While_Reserve_Mode_fail(DRAM_DRAM_TYPE_T dram_type); +EXTERN void ShuffleDfsToFSP1(DRAMC_CTX_T *p); + +void vSetVcoreByFreq(DRAMC_CTX_T *p); +U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value); +U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p); +void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level); +void UpdateDFSTbltoDDR3200(DRAMC_CTX_T *p); +void DFSInitForCalibration(DRAMC_CTX_T *p); +void mdl_setting(DRAMC_CTX_T *p); +void MPLLInit(void); +void DramcCKEDebounce(DRAMC_CTX_T *p); +void DramcModifiedRefreshMode(DRAMC_CTX_T *p); +void XRTRTR_SHU_Setting(DRAMC_CTX_T * p); +void TXPICGSetting(DRAMC_CTX_T * p); +void XRTWTW_SHU_Setting(DRAMC_CTX_T * p); +DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p); +void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff); +void Get_RX_DelayCell(DRAMC_CTX_T *p); +void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p); +void EnableDFSNoQueueFlush(DRAMC_CTX_T *p); +void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn); +void Enable_TxWDQS(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq); +void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset); +void EnableRxDcmDPhy(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq); +void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p); +void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN); +void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p); + +unsigned int dramc_set_vcore_voltage(unsigned int vcore); +unsigned int dramc_get_vcore_voltage(void); +unsigned int dramc_set_vdram_voltage(unsigned int ddr_type, unsigned int vdram); +unsigned int dramc_get_vdram_voltage(unsigned int ddr_type); +unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq); +unsigned int dramc_get_vddq_voltage(unsigned int ddr_type); +unsigned int dramc_set_vmddr_voltage(unsigned int vmddr); +unsigned int dramc_get_vmddr_voltage(void); +unsigned int dramc_set_vio18_voltage(unsigned int vio18); +unsigned int dramc_get_vio18_voltage(void); + +void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p); + +void DramcNewDutyCalibration(DRAMC_CTX_T *p); +unsigned int mt_get_dram_type_from_hw_trap(void); +U8 Get_MDL_Used_Flag(void); +void Set_MDL_Used_Flag(U8 value); +void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p); +void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq); +void TX_Path_Algorithm(DRAMC_CTX_T *p); +DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq); +U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value); + +#endif // _PI_API_H diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h b/src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h new file mode 100644 index 0000000000..d29c479076 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __REG_BASE_ADDR__ +#define __REG_BASE_ADDR__ + +#include "soc/addressmap.h" +#include "emi_hw.h" + +#ifndef __ETT__ +#define __ETT__ 0 +#endif + +//#define DRAM_BASE 0x40000000ULL +//#define DDR_BASE DRAM_BASE +#define CQ_DMA_BASE (IO_PHYS + 0x212000) +//#define CKSYS_BASE IO_PHYS +//#define EMI_APB_BASE 0x10219000 +//#define EMI_BASE EMI_APB_BASE +//#define EMI_MPU_BASE 0x10226000 +#define CHN0_EMI_BASE (IO_PHYS + 0x235000) +#define CHN1_EMI_BASE (IO_PHYS + 0x245000) +#define INFRA_DRAMC_REG_CONFIG (INFRACFG_AO_BASE + 0xB4) +//#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) +//#define APMIXED_BASE (IO_PHYS + 0x0000C000) + +#define MPLL_CON0 (APMIXED_BASE + 0x390) +#define MPLL_CON1 (APMIXED_BASE + 0x394) +#define MPLL_CON3 (APMIXED_BASE + 0x39C) + +#define PLLON_CON0 (APMIXED_BASE + 0x050) +#define PLLON_CON1 (APMIXED_BASE + 0x054) +#define PLLON_CON2 (APMIXED_BASE + 0x058) +#define PLLON_CON3 (APMIXED_BASE + 0x05C) + +/* TOPCKGEN Register */ +#define CLK_MISC_CFG_0 (CKSYS_BASE + 0x104) +#define CLK_MISC_CFG_1 (CKSYS_BASE + 0x108) +#define CLK_DBG_CFG (CKSYS_BASE + 0x10C) +#define CLK26CALI_0 (CKSYS_BASE + 0x220) +#define CLK26CALI_1 (CKSYS_BASE + 0x224) + +#endif //__REG_BASE_ADDR__ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_register.h b/src/vendorcode/mediatek/mt8192/include/dramc_register.h new file mode 100644 index 0000000000..17cde4cdf3 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_register.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _A60868_REGISTER_H_ +#define _A60868_REGISTER_H_ + +#include "dramc_pi_api.h" + +#define POS_BANK_NUM 16 // SW Virtual base address position + +#if (fcFOR_CHIP_ID == fcMargaux) +#include "Margaux_Register_DDRPHY_MD32.h" +#include "Margaux_Register_DDRPHY_NAO.h" +#include "Margaux_Register_DDRPHY_AO.h" +#include "Margaux_Register_DRAMC_AO.h" +#include "Margaux_Register_DRAMC_NAO.h" +#else +#include "Register_DDRPHY_MD32.h" +#include "Register_DDRPHY_NAO.h" +#include "Register_DDRPHY_AO.h" +#include "Register_DRAMC_AO.h" +#include "Register_DRAMC_NAO.h" +#include "Register_SYSTEM.h" +#endif + +// SW Virtual base address +#define Channel_A_DRAMC_NAO_BASE_VIRTUAL 0x40000 +#define Channel_B_DRAMC_NAO_BASE_VIRTUAL 0x50000 +#define Channel_A_DRAMC_AO_BASE_VIRTUAL 0x60000 +#define Channel_B_DRAMC_AO_BASE_VIRTUAL 0x70000 +#define Channel_A_DDRPHY_NAO_BASE_VIRTUAL 0x80000 +#define Channel_B_DDRPHY_NAO_BASE_VIRTUAL 0x90000 +#define Channel_A_DDRPHY_AO_BASE_VIRTUAL 0xa0000 +#define Channel_B_DDRPHY_AO_BASE_VIRTUAL 0xb0000 +#define Channel_A_DDRPHY_DPM_BASE_VIRTUAL 0xc0000 +#define MAX_BASE_VIRTUAL 0xd0000 + +#define DRAMC_WBR 0x100010B4 +#if (CHANNEL_NUM==4) +#define DRAMC_BROADCAST_ON 0x27f7f //4CH +#else +#define DRAMC_BROADCAST_ON 0x7f //2CH +#endif +#define DRAMC_BROADCAST_OFF 0x0 + +//Definitions indicating DRAMC, DDRPHY register shuffle offset +#define SHU_GRP_DRAMC_OFFSET 0x700 +#define SHU_GRP_DDRPHY_OFFSET 0x700 + +#define DRAMC_REG_AO_SHU_OFFSET (0x700) +#define DRAMC_REG_AO_RANK_OFFSET (0x200) +#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR (DRAMC_REG_RK_TEST2_A1 - DRAMC_AO_BASE_ADDRESS) // 0x0500 +#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR (DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET) +#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200 +#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR (DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET) +#define DRAMC_REG_AO_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200 +#define DRAMC_REG_AO_SHUFFLE0_END_ADDR (DRAMC_REG_SHU_ACTIM7 - DRAMC_AO_BASE_ADDRESS) // 0x16E8 + +#define DDRPHY_AO_B0_B1_OFFSET (0x180) +#define DDRPHY_AO_SHU_OFFSET (0x700) +#define DDRPHY_AO_RANK_OFFSET (0x80) +#define DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_B0_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0060 +#define DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_B1_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x01E0 +#define DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_CA_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0360 +#define DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_B0_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0760 +#define DDRPHY_AO_RANK0_B0_SHU0_END_ADDR (DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_B1_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x08E0 +#define DDRPHY_AO_RANK0_B1_SHU0_END_ADDR (DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_CA_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0A60 +#define DDRPHY_AO_RANK0_CA_SHU0_END_ADDR (DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR (DDRPHY_REG_MISC_SHU_RK_DQSCTL - DDRPHY_AO_BASE_ADDRESS) // 0x0BE0 +#define DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR (DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_SHUFFLE0_BASE_ADDR (DDRPHY_REG_SHU_PHYPLL0 - DDRPHY_AO_BASE_ADDRESS) // 0x700 +#define DDRPHY_AO_SHUFFLE0_END_ADDR (DDRPHY_REG_MISC_SHU_CG_CTRL0 - DDRPHY_AO_BASE_ADDRESS) // 0xDA4 + +#define DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET (0x20) +#define DDRPHY_NAO_GATING_STATUS_RK_OFFSET (0x10) +#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0600 +#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET) +#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0640 +#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET) +#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0680 +#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET) +#define DDRPHY_NAO_RANK0_GATING_STATUS_START (DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0420 +#define DDRPHY_NAO_RANK0_GATING_STATUS_END (DDRPHY_NAO_RANK0_GATING_STATUS_START + DDRPHY_NAO_GATING_STATUS_RK_OFFSET) + +#define DRAMC_REG_NAO_RANK_OFFSET (0x200) +#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR (DRAMC_REG_MR_BACKUP_00_RK0_FSP0 - DRAMC_NAO_BASE_ADDRESS) // 0x0900 +#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR (DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR + DRAMC_REG_NAO_RANK_OFFSET) + +// HW Physical base address +#if defined(__MD32__) +/* MD32 address */ +#undef Channel_A_DRAMC_AO_BASE_ADDRESS +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x300A2000 +#undef Channel_B_DRAMC_AO_BASE_ADDRESS +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x300B2000 +#undef Channel_C_DRAMC_AO_BASE_ADDRESS +#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_AO_BASE_ADDRESS +#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_A_DRAMC_NAO_BASE_ADDRESS +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x300A8000 +#undef Channel_B_DRAMC_NAO_BASE_ADDRESS +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x300B8000 +#undef Channel_C_DRAMC_NAO_BASE_ADDRESS +#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_NAO_BASE_ADDRESS +#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_AO_BASE_ADDRESS +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x300A6000 +#undef Channel_B_DDRPHY_AO_BASE_ADDRESS +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x300B6000 +#undef Channel_C_DDRPHY_AO_BASE_ADDRESS +#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_AO_BASE_ADDRESS +#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x300AA000 +#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x300BA000 +#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS +#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS +#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x30040000 +#elif (FOR_DV_SIMULATION_USED) +#undef Channel_A_DRAMC_AO_BASE_ADDRESS +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10000 +#undef Channel_B_DRAMC_AO_BASE_ADDRESS +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x40000 +#undef Channel_C_DRAMC_AO_BASE_ADDRESS +#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_AO_BASE_ADDRESS +#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0 + +#undef Channel_A_DRAMC_NAO_BASE_ADDRESS +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x20000 +#undef Channel_B_DRAMC_NAO_BASE_ADDRESS +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x50000 +#undef Channel_C_DRAMC_NAO_BASE_ADDRESS +#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_NAO_BASE_ADDRESS +#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0 + +#undef Channel_A_DDRPHY_AO_BASE_ADDRESS +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x30000 +#undef Channel_B_DDRPHY_AO_BASE_ADDRESS +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x60000 +#undef Channel_C_DDRPHY_AO_BASE_ADDRESS +#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_AO_BASE_ADDRESS +#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0 + +#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x70000 +#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x80000 +#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS +#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS +#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0 + +#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0xD0000 //@Darren, 0x90000 + 0x40000 for DV sim +#elif(HAPS_FPFG_A60868 ==0) +#undef Channel_A_DRAMC_AO_BASE_ADDRESS +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000 +#undef Channel_B_DRAMC_AO_BASE_ADDRESS +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x10240000 +#undef Channel_C_DRAMC_AO_BASE_ADDRESS +#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x10250000 +#undef Channel_D_DRAMC_AO_BASE_ADDRESS +#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x10260000 +#undef Channel_A_DRAMC_NAO_BASE_ADDRESS +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10234000 +#undef Channel_B_DRAMC_NAO_BASE_ADDRESS +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x10244000 +#undef Channel_C_DRAMC_NAO_BASE_ADDRESS +#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x10254000 +#undef Channel_D_DRAMC_NAO_BASE_ADDRESS +#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x10264000 +#undef Channel_A_DDRPHY_AO_BASE_ADDRESS +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x10238000 +#undef Channel_B_DDRPHY_AO_BASE_ADDRESS +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x10248000 +#undef Channel_C_DDRPHY_AO_BASE_ADDRESS +#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x10258000 +#undef Channel_D_DDRPHY_AO_BASE_ADDRESS +#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x10268000 +#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x10236000 +#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x10246000 +#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS +#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x10256000 +#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS +#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x10266000 +#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x10940000 +#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS +#define Channel_B_DDRPHY_DPM_BASE_ADDRESS 0x10A40000 +#else // A60868 FPGA Base Address +#undef Channel_A_DRAMC_AO_BASE_ADDRESS +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x40000 +#undef Channel_B_DRAMC_AO_BASE_ADDRESS +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_C_DRAMC_AO_BASE_ADDRESS +#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_AO_BASE_ADDRESS +#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_A_DRAMC_NAO_BASE_ADDRESS +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10000 +#undef Channel_B_DRAMC_NAO_BASE_ADDRESS +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_C_DRAMC_NAO_BASE_ADDRESS +#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_NAO_BASE_ADDRESS +#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_AO_BASE_ADDRESS +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x70000 +#undef Channel_B_DDRPHY_AO_BASE_ADDRESS +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_C_DDRPHY_AO_BASE_ADDRESS +#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_AO_BASE_ADDRESS +#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x80000 +#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS +#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS +#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x100000 +#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS +#define Channel_B_DDRPHY_DPM_BASE_ADDRESS 0x0 +#endif + +#define CHK_INCLUDE_LOCAL_HEADER "\n ==> Include local header but not one at DV SERVER\n\n" + + +#endif // _A60868_REGISTER_H_ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_top.h b/src/vendorcode/mediatek/mt8192/include/dramc_top.h new file mode 100644 index 0000000000..d289adc4e4 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_top.h @@ -0,0 +1,641 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_TOP_H__ +#define __DRAMC_TOP_H__ +#include "dramc_common.h" + +#if !__ETT__ +#if (FOR_DV_SIMULATION_USED==0) +//#define DDR_RESERVE_MODE +#define COMBO_MCP +//#define LAST_DRAMC +//#define VOLTAGE_SEL +//#define ENABLE_DOE +#endif +#endif + +//#define DRAM_BASE 0x40000000ULL +//#define DDR_BASE DRAM_BASE + +#if __ETT__ +#define dramc_crit printf +#define dramc_debug printf +#elif __FLASH_TOOL_DA__ +#define dramc_crit LOGD +#define dramc_debug LOGD +#else +#ifndef dramc_info +#define dramc_info print +#endif +#ifndef dramc_crit +#define dramc_crit print +#endif +#ifndef dramc_debug +#define dramc_debug printf +#endif +#endif + + +#define DRAMC_MAX_CH 2 +#define DRAMC_MAX_RK 2 +#define DRAMC_MR_CNT 4 +#define DRAMC_FREQ_CNT 7 + +struct mr_info_t { + u16 mr_index; + u16 mr_value; +}; + +enum DRAM_TYPE { + DTYPE_DDR1 = 1, + DTYPE_LPDDR2, + DTYPE_LPDDR3, + DTYPE_PCDDR3, + DTYPE_LPDDR4, + DTYPE_LPDDR4X, + DTYPE_LPDDR4P +}; + +extern struct dramc_param *dramc_params; + +int mt_get_dram_type(void); +int get_dram_channel_support_nr(void); +int get_dram_channel_nr(void); +int get_dram_rank_nr(void); +int get_dram_mr_cnt(void); +int get_dram_freq_cnt(void); +#if !__ETT__ +void get_dram_rank_size(u64 dram_rank_size[]); +void get_dram_freq_step(u32 dram_freq_step[]); +void set_dram_mr(unsigned int index, unsigned short value); +unsigned short get_dram_mr(unsigned int index); +void get_dram_mr_info(struct mr_info_t mr_info[]); +void reserve_dramc_dummy_read(void); +#endif +typedef struct _AC_TIMING_EXTERNAL_T +{ + // U 00 + U32 AC_TIME_EMI_FREQUENCY :16; + U32 AC_TIME_EMI_TRAS :8; + U32 AC_TIME_EMI_TRP :8; + + // U 01 + U32 AC_TIME_EMI_TRPAB :8; + U32 AC_TIME_EMI_TRC :8; + U32 AC_TIME_EMI_TRFC :8; + U32 AC_TIME_EMI_TRFCPB :8; + + // U 02 + U32 AC_TIME_EMI_TXP :8; + U32 AC_TIME_EMI_TRTP :8; + U32 AC_TIME_EMI_TRCD :8; + U32 AC_TIME_EMI_TWR :8; + + // U 03 + U32 AC_TIME_EMI_TWTR :8; + U32 AC_TIME_EMI_TRRD :8; + U32 AC_TIME_EMI_TFAW :8; + U32 AC_TIME_EMI_TRTW_ODT_OFF :4; + U32 AC_TIME_EMI_TRTW_ODT_ON :4; + + // U 04 + U32 AC_TIME_EMI_REFCNT :8; //(REFFRERUN = 0) + U32 AC_TIME_EMI_REFCNT_FR_CLK :8; //(REFFRERUN = 1) + U32 AC_TIME_EMI_TXREFCNT :8; + U32 AC_TIME_EMI_TZQCS :8; + + // U 05 + U32 AC_TIME_EMI_TRTPD :8; // LP4/LP3, // Olymp_us new + U32 AC_TIME_EMI_TWTPD :8; // LP4/LP3, // Olymp_us new + U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; // LP4 // Olymp_us new + U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // LP4 // Olymp_us new + + // U 06 + // Byte0 + U32 AC_TIME_EMI_TRAS_05T :2; + U32 AC_TIME_EMI_TRP_05T :2; + U32 AC_TIME_EMI_TRPAB_05T :2; + U32 AC_TIME_EMI_TRC_05T :2; + // Byte1 + U32 AC_TIME_EMI_TRFC_05T :2; + U32 AC_TIME_EMI_TRFCPB_05T :2; + U32 AC_TIME_EMI_TXP_05T :2; + U32 AC_TIME_EMI_TRTP_05T :2; + // Byte2 + U32 AC_TIME_EMI_TRCD_05T :2; + U32 AC_TIME_EMI_TWR_05T :2; + U32 AC_TIME_EMI_TWTR_05T :2; // Olymp_us modified + U32 AC_TIME_EMI_TRRD_05T :2; + // Byte3 + U32 AC_TIME_EMI_TFAW_05T :2; + U32 AC_TIME_EMI_TRTW_ODT_OFF_05T :2; + U32 AC_TIME_EMI_TRTW_ODT_ON_05T :2; + U32 AC_TIME_EMI_TRTPD_05T :2; // LP4/LP3 // Olymp_us new + + // U 07 + // Byte0 + U32 AC_TIME_EMI_TWTPD_05T :2; // LP4/LP3 // Olymp_us new + U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us + U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us + + +}AC_TIMING_EXTERNAL_T; + + +typedef struct +{ + unsigned int sub_version; // sub_version: 0x1 for new version + unsigned int type; /* 0x0000 : Invalid + 0x0001 : Discrete DDR1 + 0x0002 : Discrete LPDDR2 + 0x0003 : Discrete LPDDR3 + 0x0004 : Discrete PCDDR3 + 0x0005 : Discrete LPDDR4 + 0x0006 : Discrete LPDR4X + 0x0101 : MCP(NAND+DDR1) + 0x0102 : MCP(NAND+LPDDR2) + 0x0103 : MCP(NAND+LPDDR3) + 0x0104 : MCP(NAND+PCDDR3) + 0x0201 : MCP(eMMC+DDR1) + 0x0202 : MCP(eMMC+LPDDR2) + 0x0203 : MCP(eMMC+LPDDR3) + 0x0204 : MCP(eMMC+PCDDR3) + 0x0205 : MCP(eMMC+LPDDR4) + 0x0206 : MCP(eMMC+LPDR4X) + */ + unsigned int id_length; // EMMC and NAND ID checking length + unsigned int fw_id_length; // FW ID checking length + unsigned char ID[16]; + unsigned char fw_id[8]; // To save fw id + unsigned int EMI_CONA_VAL; //@0x3000 + unsigned int EMI_CONH_VAL; + + union { + unsigned int DRAMC_ACTIME_UNION[8]; + AC_TIMING_EXTERNAL_T AcTimeEMI; + }; + + u64 DRAM_RANK_SIZE[4]; + unsigned int EMI_CONF_VAL; + unsigned int CHN0_EMI_CONA_VAL; + unsigned int CHN1_EMI_CONA_VAL; + /* Single field to store LP4 dram type (normal, byte, mixed) */ + unsigned int dram_cbt_mode_extern; + unsigned int reserved[6]; + +#if 0 + union + { + struct + { + int iLPDDR2_MODE_REG_1; + int iLPDDR2_MODE_REG_2; + int iLPDDR2_MODE_REG_3; + int iLPDDR2_MODE_REG_5; + int iLPDDR2_MODE_REG_10; + int iLPDDR2_MODE_REG_63; + }; + struct + { + int iDDR1_MODE_REG; + int iDDR1_EXT_MODE_REG; + }; + struct + { + int iPCDDR3_MODE_REG0; + int iPCDDR3_MODE_REG1; + int iPCDDR3_MODE_REG2; + int iPCDDR3_MODE_REG3; + }; + struct + { + int iLPDDR3_MODE_REG_1; + int iLPDDR3_MODE_REG_2; + int iLPDDR3_MODE_REG_3; + int iLPDDR3_MODE_REG_5; + int iLPDDR3_MODE_REG_10; + int iLPDDR3_MODE_REG_63; + }; + }; +#else + unsigned int iLPDDR3_MODE_REG_5; +#endif + unsigned int PIN_MUX_TYPE; +} EMI_SETTINGS; + +//typedef EMI_SETTINGS_v15 EMI_SETTINGS; +#if (FOR_DV_SIMULATION_USED==0) +void setup_dramc_voltage_by_pmic(void); +void switch_dramc_voltage_to_auto_mode(void); +#if ! __ETT__ +uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); //array of emi setting. +#endif +#endif + +extern int emi_setting_index; +extern EMI_SETTINGS emi_settings[]; +extern EMI_SETTINGS default_emi_setting; +extern EMI_SETTINGS emi_setting_default_lpddr3; +extern EMI_SETTINGS emi_setting_default_lpddr4; + +#include "x_hal_io.h" + +#ifdef LAST_DRAMC +#define LAST_DRAMC_MAGIC_PATTERN 0x19870611 +static void update_last_dramc_info(void); +void init_ta2_all_channel(void); +typedef struct { + unsigned int ta2_result_magic; + unsigned int ta2_result_last; + unsigned int ta2_result_past; + unsigned int ta2_result_checksum; + unsigned int reboot_count; + volatile unsigned int last_fatal_err_flag; + volatile unsigned int fatal_err_flag; + volatile unsigned int storage_api_err_flag; + volatile unsigned int last_gating_err[2][2]; // [channel][rank] + volatile unsigned int gating_err[2][2]; // [channel][rank] + unsigned short mr5; + unsigned short mr6; + unsigned short mr7; + unsigned short mr8; +} LAST_DRAMC_INFO_T; +#define DEF_LAST_DRAMC LAST_DRAMC_INFO_T + +#define OFFSET_DRAM_FATAL_ERR (31) +#define OFFSET_DRAM_TA2_ERR (23) +#define OFFSET_DRAM_GATING_ERR (7) +#define OFFSET_CPU_RW_ERR (5) +#define OFFSET_DDR_RSV_MODE_FLOW (4) +#define OFFSET_DDR_RSV_MODE_ERR (3) +#define OFFSET_EMI_DCS_ERR (2) +#define OFFSET_DVFSRC_ERR (1) +#define OFFSET_DRS_ERR (0) + +#define ERR_DRAM_TA2_RK0 (1 << 0) +#define ERR_DRAM_TA2_RK1 (1 << 1) + +#define ERR_DRAM_GATING_RK0_R (1 << 0) +#define ERR_DRAM_GATING_RK0_F (1 << 1) +#define ERR_DRAM_GATING_RK1_R (1 << 2) +#define ERR_DRAM_GATING_RK1_F (1 << 3) + +#define ERR_CPU_RW_RK0 (1 << 0) +#define ERR_CPU_RW_RK1 (1 << 1) + +/* 0x1f -> bit[4:0] is for DDR reserve mode */ +#define DDR_RSV_MODE_ERR_MASK (0x1f) + +unsigned int check_last_dram_fatal_exception(void); +unsigned int check_dram_fatal_exception(void); +void set_err_code_for_storage_api(void); +void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code); +void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code); +void dram_fatal_set_cpu_rw_err(unsigned int err_code); +void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code); + +void dram_fatal_backup_stberr(void); +void dram_fatal_init_stberr(void); +void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset); + +#define dram_fatal_set_cpu_rw_err(err_code)\ + do {\ + dram_fatal_set_err(err_code, 0x3, OFFSET_CPU_RW_ERR);\ + } while(0) + +#define dram_fatal_set_ddr_rsv_mode_err()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_ERR);\ + } while(0) + +#define dram_fatal_set_emi_dcs_err()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_EMI_DCS_ERR);\ + } while(0) + +#define dram_fatal_set_dvfsrc_err()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_DVFSRC_ERR);\ + } while(0) + +#define dram_fatal_set_drs_err()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_DRS_ERR);\ + } while(0) + +#define dram_fatal_set_ddr_rsv_mode_flow()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\ + } while(0) + +#endif //LAST_DRAMC + +typedef enum { + KSHU0 = 0, + KSHU1, + KSHU2, + KSHU3, + KSHU4, + KSHU5, + KSHU6, + KSHU7, + KSHU8, + KSHU9, +} DRAM_KSHU; + +typedef enum { + TYPE_VDRAM = 0, + TYPE_VDDR1, + TYPE_VDDR2, + TYPE_VDDQ, +} TYPE_VOLTAGE; + +typedef enum { + LEVEL_VB = 0, + LEVEL_HV, + LEVEL_NV, + LEVEL_LV, +} LEVEL_VOLTAGE; + +//================================================ +//=============pmic related api for ETT HQA test ============== +//================================================ +#if (__ETT__ || CFG_DRAM_LOG_TO_STORAGE) +#define DRAM_HQA +#endif + +#define MAX_VCORE 1193750 +#define MAX_VDRAM 1300000 +#define MAX_VDDQ 1300000 +#define MAX_VMDDR 2000000 +#define MAX_VIO18 1900000 + +#define UNIT_VCORE 6250 +#define UNIT_VDRAM 5000 +#define UNIT_VDDQ 10000 +#define UNIT_VMDDR 10000 +#define UNIT_VIO18 10000 +#define UNIT_VIO18_STEP 100000 + +#define HQA_VIO18_HV 1950000 +#define HQA_VCORE_HV_LP4_KSHU0_PL 762500 +#define HQA_VCORE_HV_LP4_KSHU1_PL 725000 +#define HQA_VCORE_HV_LP4_KSHU2_PL 700000 +#define HQA_VCORE_HV_LP4_KSHU3_PL 700000 +#define HQA_VCORE_HV_LP4_KSHU4_PL 687500 +#define HQA_VCORE_HV_LP4_KSHU5_PL 687500 +#define HQA_VCORE_HV_LP4_KSHU6_PL 687500 +#define HQA_VCORE_HV_LP4_KSHU0_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU1_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU2_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU3_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU4_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU5_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU6_ETT 762500 +#define HQA_VDRAM_HV_LP4 1170000 +#define HQA_VDDQ_HV_LP4 650000 +#define HQA_VMDDR_HV_LP4 790000 + +#define HQA_VIO18_NV 1800000 +#define HQA_VCORE_NV_LP4_KSHU0_PL 725000 +#define HQA_VCORE_NV_LP4_KSHU1_PL 687500 +#define HQA_VCORE_NV_LP4_KSHU2_PL 662500 +#define HQA_VCORE_NV_LP4_KSHU3_PL 662500 +#define HQA_VCORE_NV_LP4_KSHU4_PL 650000 +#define HQA_VCORE_NV_LP4_KSHU5_PL 650000 +#define HQA_VCORE_NV_LP4_KSHU6_PL 650000 +#define HQA_VCORE_NV_LP4_KSHU0_ETT 725000 +#define HQA_VCORE_NV_LP4_KSHU1_ETT 687500 +#define HQA_VCORE_NV_LP4_KSHU2_ETT 662500 +#define HQA_VCORE_NV_LP4_KSHU3_ETT 662500 +#define HQA_VCORE_NV_LP4_KSHU4_ETT 650000 +#define HQA_VCORE_NV_LP4_KSHU5_ETT 650000 +#define HQA_VCORE_NV_LP4_KSHU6_ETT 650000 +#define HQA_VDRAM_NV_LP4 1125000 +#define HQA_VDDQ_NV_LP4 600000 +#define HQA_VMDDR_NV_LP4 750000 + +#define HQA_VIO18_LV 1730000 +#define HQA_VCORE_LV_LP4_KSHU0_PL 687500 +#define HQA_VCORE_LV_LP4_KSHU1_PL 650000 +#define HQA_VCORE_LV_LP4_KSHU2_PL 625000 +#define HQA_VCORE_LV_LP4_KSHU3_PL 625000 +#define HQA_VCORE_LV_LP4_KSHU4_PL 612500 +#define HQA_VCORE_LV_LP4_KSHU5_PL 612500 +#define HQA_VCORE_LV_LP4_KSHU6_PL 612500 +#define HQA_VCORE_LV_LP4_KSHU0_ETT 687500 +#define HQA_VCORE_LV_LP4_KSHU1_ETT 612500 +#define HQA_VCORE_LV_LP4_KSHU2_ETT 568750 +#define HQA_VCORE_LV_LP4_KSHU3_ETT 568750 +#define HQA_VCORE_LV_LP4_KSHU4_ETT 543750 +#define HQA_VCORE_LV_LP4_KSHU5_ETT 543750 +#define HQA_VCORE_LV_LP4_KSHU6_ETT 543750 +#define HQA_VDRAM_LV_LP4 1060000 +#define HQA_VDDQ_LV_LP4 570000 +#define HQA_VMDDR_LV_LP4 710000 + + +#define _SEL_PREFIX_SHU_PL(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_PL +#define _SEL_PREFIX_SHU_ETT(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_ETT +#define _SEL_PREFIX(type,vol,dtype) HQA_##type##_##vol##_##dtype +#define _SEL_VIO18(vol) HQA_VIO18_##vol + +#define STD_VIO18 _SEL_VIO18(NV) +#define STD_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu) +#define STD_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype) +#define STD_VDDQ _SEL_PREFIX(VDDQ,NV,LP4) +#define STD_VMDDR _SEL_PREFIX(VMDDR,NV,LP4) + +#ifdef DRAM_HQA +//#define HVCORE_HVDRAM +#define NVCORE_NVDRAM +//#define LVCORE_LVDRAM +//#define HVCORE_LVDRAM +//#define LVCORE_HVDRAM + +#if defined(HVCORE_HVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4) + #define HQA_VIO18 _SEL_VIO18(HV) +#elif defined(NVCORE_NVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,NV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,NV,LP4) + #define HQA_VIO18 _SEL_VIO18(NV) +#elif defined(LVCORE_LVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4) + #define HQA_VIO18 _SEL_VIO18(LV) +#elif defined(HVCORE_LVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4) + #define HQA_VIO18 _SEL_VIO18(LV) +#elif defined(LVCORE_HVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4) + #define HQA_VIO18 _SEL_VIO18(HV) +#else + #error "Please set HQA voltage type" +#endif + +#define SEL_PREFIX_VCORE(dtype,shu) HQA_VCORE(dtype,shu) +#define SEL_PREFIX_VDRAM(dtype) HQA_VDRAM(dtype) +#define SEL_PREFIX_VDDQ HQA_VDDQ +#define SEL_PREFIX_VMDDR HQA_VMDDR +#define SEL_VIO18 HQA_VIO18 +#else +#if !__ETT__ +#define VCORE_BIN +#endif +#define SEL_PREFIX_VCORE(dtype,shu) STD_VCORE(dtype,shu) +#define SEL_PREFIX_VDRAM(dtype) STD_VDRAM(dtype) +#define SEL_PREFIX_VDDQ STD_VDDQ +#define SEL_PREFIX_VMDDR STD_VMDDR +#define SEL_VIO18 STD_VIO18 +#endif // #define DRAM_HQA + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + +#define PART_DRAM_DATA_SIZE 0x100000 + +#define DRAM_CALIBRATION_DATA_MAGIC 0x9502 + +typedef struct _DRAM_CALIBRATION_HEADER_T +{ + u32 pl_version; + u16 magic_number; + u32 calib_err_code; +} DRAM_CALIBRATION_HEADER_T; + +typedef struct _DRAM_CALIBRATION_MRR_DATA_T +{ + u16 checksum; + u16 emi_checksum; + DRAM_INFO_BY_MRR_T DramInfo; +} DRAM_CALIBRATION_MRR_DATA_T; + +typedef struct _DRAM_CALIBRATION_SHU_DATA_T +{ + u16 checksum; + u32 calib_err_code; + SAVE_TIME_FOR_CALIBRATION_T calibration_data; +} DRAM_CALIBRATION_SHU_DATA_T; + +typedef struct _DRAM_CALIBRATION_DATA_T +{ + DRAM_CALIBRATION_HEADER_T header; + DRAM_CALIBRATION_MRR_DATA_T mrr_info; + DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SHUFFLE_MAX]; +} DRAM_CALIBRATION_DATA_T; + +/* + * g_dram_storage_api_err_code: + * bit[0:3] -> read api + * bit[4:7] -> write api + * bit[8:11] -> clean api + * bit[12:12] -> data formatted due to fatal exception + */ +#define ERR_NULL_POINTER (0x1) +#define ERR_MAGIC_NUMBER (0x2) +#define ERR_CHECKSUM (0x3) +#define ERR_PL_UPDATED (0x4) +#define ERR_BLKDEV_NOT_FOUND (0x5) +#define ERR_BLKDEV_READ_FAIL (0x6) +#define ERR_BLKDEV_WRITE_FAIL (0x7) +#define ERR_BLKDEV_NO_PART (0x8) + +#define ERR_DATA_FORMATTED_OFFSET (12) + +typedef enum { + DRAM_STORAGE_API_READ = 0, + DRAM_STORAGE_API_WRITE, + DRAM_STORAGE_API_CLEAN, +} DRAM_STORAGE_API_TPYE; + +extern u32 g_dram_storage_api_err_code; +#define SET_DRAM_STORAGE_API_ERR(err_type, api_type) \ +do {\ + g_dram_storage_api_err_code |= (err_type << (api_type * 4));\ +} while(0) + +#define SET_DATA_FORMATTED_STORAGE_API_ERR() \ +do {\ + g_dram_storage_api_err_code |= (1 << ERR_DATA_FORMATTED_OFFSET);\ +} while(0) + +int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData); +int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData); +int clean_dram_calibration_data(void); + +void dram_fatal_exception_detection_start(void); +void dram_fatal_exception_detection_end(void); + +#define CBT_VREF_OFFSET 2 +#define WRITE_LEVELING_OFFSET 5 +#define GATING_START_OFFSET 0 +#define GATING_PASS_WIN_OFFSET 3 +#define RX_WIN_PERBIT_OFFSET 5 +#define RX_WIN_PERBIT_VREF_OFFSET 4 +#define TX_WIN_PERBIT_OFFSET 5 +#define TX_WIN_PERBIT_VREF_OFFSET 4 +#define RX_DATLAT_OFFSET 1 +#define RX_WIN_HIGH_SPEED_TH 10 +#define RX_WIN_LOW_SPEED_TH 100 +#define TX_WIN_TH 12 + +#endif + +#if defined(SLT) + +#define SLT_ERR_NO_DATA (-1) +#define SLT_ERR_NO_DEV (-2) +#define SLT_ERR_NO_ADDR (-3) +#define SLT_ERR_WRITE_FAIL (-4) +#define SLT_ERR_READ_FAIL (-5) + +typedef struct _DRAM_SLT_HEADER_T +{ + u32 pl_version; + int stage_status; +} DRAM_SLT_HEADER_T; + +typedef struct _DRAM_SLT_DATA_T +{ + DRAM_SLT_HEADER_T header; + u32 test_result[10]; +} DRAM_SLT_DATA_T; + +int read_slt_data(DRAM_SLT_DATA_T *data); +int write_slt_data(DRAM_SLT_DATA_T *data); +int clean_slt_data(void); + +#endif + +int doe_get_config(const char* feature); +unsigned long long get_dram_size(void); + +typedef struct { + unsigned long long full_sys_addr; + unsigned int addr; + unsigned int row; + unsigned int col; + unsigned char ch; + unsigned char rk; + unsigned char bk; + unsigned char dummy; +} dram_addr_t; + +unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset); +unsigned int get_dummy_read_addr(dram_addr_t *dram_addr); +unsigned int is_discrete_lpddr4(void); + +#endif /* __DRAMC_TOP_H__ */ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h b/src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h new file mode 100644 index 0000000000..5f92525ab4 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _DRAMC_TYPEDEFS_H_ +#define _DRAMC_TYPEDEFS_H_ + +#include <stdint.h> + +#define IMPORT EXTERN +#ifndef __cplusplus + #define EXTERN extern +#else + #define EXTERN extern "C" +#endif +#define LOCAL static +#define GLOBAL +#define EXPORT GLOBAL + + +#define EQ == +#define NEQ != +#define AND && +#define OR || +#define XOR(A,B) ((!(A) AND (B)) OR ((A) AND !(B))) + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#if 0 +#define ASSERT(expr) \ + do{ if(!(expr)){while(1);} }while(0) +#endif + +#ifndef BOOL +typedef unsigned char BOOL; +#endif + +typedef unsigned long ulong; +typedef unsigned char uchar; +typedef unsigned int uint; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef signed int intx; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef unsigned int uintx; + +typedef signed char S8; +typedef signed short S16; +typedef signed int S32; +typedef signed long long S64; + +typedef unsigned char U8; +typedef unsigned short U16; +typedef unsigned int U32; +typedef unsigned long long U64; + +typedef unsigned char US8; +typedef unsigned short US16; +typedef unsigned int US32; +typedef unsigned long long US64; + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef unsigned long long u64; + +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned short USHORT; +typedef signed char INT8; +typedef signed short INT16; +typedef signed int INT32; + +typedef volatile signed char *P_S8; +typedef volatile signed short *P_S16; +typedef volatile signed int *P_S32; + +typedef long LONG; +typedef unsigned char UBYTE; +typedef short SHORT; + +typedef unsigned int *UINT32P; +typedef volatile unsigned short *UINT16P; +typedef volatile unsigned char *UINT8P; +typedef unsigned char *U8P; + +typedef volatile unsigned char *P_U8; +typedef volatile unsigned short *P_U16; +typedef volatile unsigned int *P_U32; +typedef unsigned long long *P_U64; +typedef signed long long *P_S64; + +typedef unsigned int uint; + +typedef void VOID; +typedef unsigned char BYTE; +typedef float FLOAT; + + +#if FOR_DV_SIMULATION_USED +#include <stdio.h> +#include <string.h> +#endif + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/emi.h b/src/vendorcode/mediatek/mt8192/include/emi.h new file mode 100644 index 0000000000..e94f74161f --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/emi.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __EMI_H__ +#define __EMI_H__ + +#include <soc/addressmap.h> +#include <dramc_top.h> + +#define EMI_APB_BASE EMI_BASE + +#if __ETT__ +#define emi_log printf +#elif __FLASH_TOOL_DA__ +#define emi_log LOGD +#else +#define emi_log(_x_...) printk(BIOS_INFO, _x_) +#endif + +struct isu_info_t { + unsigned int buf_size; + unsigned long long buf_addr; + unsigned long long ver_addr; + unsigned long long con_addr; +}; + +#define EMI_ISU_BUF_SIZE 0x800000 +#define LAST_EMI_MAGIC_PATTERN 0x19870611 +typedef struct { + unsigned int isu_magic; + unsigned int isu_ctrl; + unsigned int isu_dram_type; + unsigned int isu_diff_us; + unsigned int isu_buf_l; + unsigned int isu_buf_h; + unsigned int isu_version; + unsigned int snst_last; + unsigned int snst_past; + unsigned int os_flag_sspm; + unsigned int os_flag_ap; +} LAST_EMI_INFO_T; +#define DEF_LAST_EMI LAST_EMI_INFO_T + +void emi_init(void); +void emi_init2(void); +void clr_emi_mpu_prot(void); +void dis_emi_apb_prot(void); +int get_row_width_by_emi(unsigned int rank); +int get_channel_nr_by_emi(void); +int get_rank_nr_by_emi(void); +void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]); +void set_cen_emi_cona(unsigned int cona_val); +void set_cen_emi_conf(unsigned int conf_val); +void set_cen_emi_conh(unsigned int conh_val); +void set_chn_emi_cona(unsigned int cona_val); +void set_chn_emi_conc(unsigned int conc_val); +unsigned int get_cen_emi_cona(void); +unsigned int get_chn_emi_cona(void); +void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr); +unsigned int set_emi_before_rank1_mem_test(void); +void restore_emi_after_rank1_mem_test(void); +void get_emi_isu_info(struct isu_info_t *isu_info_ptr); +void reserve_emi_isu_buf(void); +void reserve_emi_mbist_buf(void); +void record_emi_snst(void); +unsigned long long platform_memory_size(void); + +#endif /* __EMI_H__ */ + diff --git a/src/vendorcode/mediatek/mt8192/include/emi_hw.h b/src/vendorcode/mediatek/mt8192/include/emi_hw.h new file mode 100644 index 0000000000..f19e1fdf2c --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/emi_hw.h @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __EMI_HW_H__ +#define __EMI_HW_H__ + +/* from EMI golden setting */ +#define MARGAUX_EMI_MP_SETTING +#define MARGAUX_REAL_CHIP_EMI_GOLDEN_SETTING +//#define INFRA_DRAMC_REG_CONFIG (INFRACFG_AO_BASE + 0xB4) +//#define INFRACFG_AO_MEM_BASE (0x10002000) +//#define SUB_INFRACFG_AO_MEM_BASE (0x1030E000) +//#define MCUSYS_PAR_WRAP_BASE (0x0C530000) + +//#define EMI_BASE (0x10219000) +//#define EMI_MPU_BASE (0x10226000) +#define CHN0_EMI_BASE (IO_PHYS + 0x235000) +#define CHN1_EMI_BASE (IO_PHYS + 0x245000) + +#define EMI_CONA (EMI_BASE+0x000) +#define EMI_CONB (EMI_BASE+0x008) +#define EMI_CONC (EMI_BASE+0x010) +#define EMI_COND (EMI_BASE+0x018) +#define EMI_CONE (EMI_BASE+0x020) +#define EMI_CONF (EMI_BASE+0x028) +#define EMI_CONG (EMI_BASE+0x030) +#define EMI_CONH (EMI_BASE+0x038) +#define EMI_CONH_2ND (EMI_BASE+0x03C) +#define EMI_CONI (EMI_BASE+0x040) +#define EMI_CONJ (EMI_BASE+0x048) +#define EMI_CONM (EMI_BASE+0x060) +#define EMI_CONN (EMI_BASE+0x068) +#define EMI_CONO (EMI_BASE+0x070) +#define EMI_MDCT (EMI_BASE+0x078) +#define EMI_MDCT_2ND (EMI_BASE+0x07C) +#define EMI_IOCL (EMI_BASE+0x0D0) +#define EMI_IOCL_2ND (EMI_BASE+0x0D4) +#define EMI_IOCM (EMI_BASE+0x0D8) +#define EMI_IOCM_2ND (EMI_BASE+0x0DC) +#define EMI_TESTB (EMI_BASE+0x0E8) +#define EMI_TESTC (EMI_BASE+0x0F0) +#define EMI_TESTD (EMI_BASE+0x0F8) +#define EMI_ARBA (EMI_BASE+0x100) +#define EMI_ARBB (EMI_BASE+0x108) +#define EMI_ARBC (EMI_BASE+0x110) +#define EMI_ARBD (EMI_BASE+0x118) +#define EMI_ARBE (EMI_BASE+0x120) +#define EMI_ARBF (EMI_BASE+0x128) +#define EMI_ARBG (EMI_BASE+0x130) +#define EMI_ARBH (EMI_BASE+0x138) +#define EMI_ARBI (EMI_BASE+0x140) +#define EMI_ARBI_2ND (EMI_BASE+0x144) +#define EMI_ARBJ_2ND (EMI_BASE+0x14C) +#define EMI_ARBK (EMI_BASE+0x150) +#define EMI_ARBK_2ND (EMI_BASE+0x154) +#define EMI_SLCT (EMI_BASE+0x158) +#define EMI_MPUD0_ST (EMI_BASE+0x160) +#define EMI_MPUD1_ST (EMI_BASE+0x164) +#define EMI_MPUD2_ST (EMI_BASE+0x168) +#define EMI_MPUD3_ST (EMI_BASE+0x16C) +#define EMI_MPUD4_ST (EMI_BASE+0x170) +#define EMI_MPUD5_ST (EMI_BASE+0x174) +#define EMI_MPUD6_ST (EMI_BASE+0x178) +#define EMI_MPUD7_ST (EMI_BASE+0x17C) +#define EMI_MPUD8_ST (EMI_BASE+0x180) +#define EMI_MPUD9_ST (EMI_BASE+0x184) +#define EMI_MPUD10_ST (EMI_BASE+0x188) +#define EMI_MPUD11_ST (EMI_BASE+0x18C) +#define EMI_MPUD12_ST (EMI_BASE+0x190) +#define EMI_MPUD13_ST (EMI_BASE+0x194) +#define EMI_MPUD14_ST (EMI_BASE+0x198) +#define EMI_MPUD15_ST (EMI_BASE+0x19C) +#define EMI_MPUD16_ST (EMI_BASE+0x1A0) +#define EMI_MPUD17_ST (EMI_BASE+0x1A4) +#define EMI_MPUD18_ST (EMI_BASE+0x1A8) +#define EMI_MPUD19_ST (EMI_BASE+0x1AC) +#define EMI_MPUD20_ST (EMI_BASE+0x1B0) +#define EMI_MPUD21_ST (EMI_BASE+0x1B4) +#define EMI_MPUD22_ST (EMI_BASE+0x1B8) +#define EMI_MPUD23_ST (EMI_BASE+0x1BC) +#define EMI_MPUD24_ST (EMI_BASE+0x1C0) +#define EMI_MPUD25_ST (EMI_BASE+0x1C4) +#define EMI_MPUD26_ST (EMI_BASE+0x1C8) +#define EMI_MPUD27_ST (EMI_BASE+0x1CC) +#define EMI_MPUD28_ST (EMI_BASE+0x1D0) +#define EMI_MPUD29_ST (EMI_BASE+0x1D4) +#define EMI_MPUD30_ST (EMI_BASE+0x1D8) +#define EMI_MPUD31_ST (EMI_BASE+0x1DC) +#define EMI_MPUS (EMI_BASE+0x1F0) +#define EMI_MPUT (EMI_BASE+0x1F8) +#define EMI_MPUT_2ND (EMI_BASE+0x1FC) +#define EMI_D0_ST2 (EMI_BASE+0x200) +#define EMI_D1_ST2 (EMI_BASE+0x204) +#define EMI_D2_ST2 (EMI_BASE+0x208) +#define EMI_D3_ST2 (EMI_BASE+0x20C) +#define EMI_D4_ST2 (EMI_BASE+0x210) +#define EMI_D5_ST2 (EMI_BASE+0x214) +#define EMI_D6_ST2 (EMI_BASE+0x218) +#define EMI_D7_ST2 (EMI_BASE+0x21C) +#define EMI_D8_ST2 (EMI_BASE+0x220) +#define EMI_D9_ST2 (EMI_BASE+0x224) +#define EMI_D10_ST2 (EMI_BASE+0x228) +#define EMI_D11_ST2 (EMI_BASE+0x22C) +#define EMI_D12_ST2 (EMI_BASE+0x230) +#define EMI_D13_ST2 (EMI_BASE+0x234) +#define EMI_D14_ST2 (EMI_BASE+0x238) +#define EMI_D15_ST2 (EMI_BASE+0x23C) +#define EMI_D16_ST2 (EMI_BASE+0x240) +#define EMI_D17_ST2 (EMI_BASE+0x244) +#define EMI_D18_ST2 (EMI_BASE+0x248) +#define EMI_D19_ST2 (EMI_BASE+0x24C) +#define EMI_D20_ST2 (EMI_BASE+0x250) +#define EMI_D21_ST2 (EMI_BASE+0x254) +#define EMI_D22_ST2 (EMI_BASE+0x258) +#define EMI_D23_ST2 (EMI_BASE+0x25C) +#define EMI_D24_ST2 (EMI_BASE+0x260) +#define EMI_D25_ST2 (EMI_BASE+0x264) +#define EMI_D26_ST2 (EMI_BASE+0x268) +#define EMI_D27_ST2 (EMI_BASE+0x26C) +#define EMI_D28_ST2 (EMI_BASE+0x270) +#define EMI_D29_ST2 (EMI_BASE+0x274) +#define EMI_D30_ST2 (EMI_BASE+0x278) +#define EMI_D31_ST2 (EMI_BASE+0x27C) +#define EMI_BMEN (EMI_BASE+0x400) +#define EMI_BSTP (EMI_BASE+0x404) +#define EMI_BCNT (EMI_BASE+0x408) +#define EMI_TACT (EMI_BASE+0x410) +#define EMI_TSCT (EMI_BASE+0x418) +#define EMI_WACT (EMI_BASE+0x420) +#define EMI_WSCT (EMI_BASE+0x428) +#define EMI_BACT (EMI_BASE+0x430) +#define EMI_BSCT (EMI_BASE+0x438) +#define EMI_MSEL (EMI_BASE+0x440) +#define EMI_TSCT2 (EMI_BASE+0x448) +#define EMI_TSCT3 (EMI_BASE+0x450) +#define EMI_WSCT2 (EMI_BASE+0x458) +#define EMI_WSCT3 (EMI_BASE+0x460) +#define EMI_WSCT4 (EMI_BASE+0x464) +#define EMI_MSEL2 (EMI_BASE+0x468) +#define EMI_MSEL3 (EMI_BASE+0x470) +#define EMI_MSEL4 (EMI_BASE+0x478) +#define EMI_MSEL5 (EMI_BASE+0x480) +#define EMI_MSEL6 (EMI_BASE+0x488) +#define EMI_MSEL7 (EMI_BASE+0x490) +#define EMI_MSEL8 (EMI_BASE+0x498) +#define EMI_MSEL9 (EMI_BASE+0x4A0) +#define EMI_MSEL10 (EMI_BASE+0x4A8) +#define EMI_BMID0 (EMI_BASE+0x4B0) +#define EMI_BMID1 (EMI_BASE+0x4B4) +#define EMI_BMID2 (EMI_BASE+0x4B8) +#define EMI_BMID3 (EMI_BASE+0x4BC) +#define EMI_BMID4 (EMI_BASE+0x4C0) +#define EMI_BMID5 (EMI_BASE+0x4C4) +#define EMI_BMID6 (EMI_BASE+0x4C8) +#define EMI_BMID7 (EMI_BASE+0x4CC) +#define EMI_BMID8 (EMI_BASE+0x4D0) +#define EMI_BMID9 (EMI_BASE+0x4D4) +#define EMI_BMID10 (EMI_BASE+0x4D8) +#define EMI_BMEN1 (EMI_BASE+0x4E0) +#define EMI_BMEN2 (EMI_BASE+0x4E8) +#define EMI_BMRW0 (EMI_BASE+0x4F8) +#define EMI_BMRW1 (EMI_BASE+0x4FC) +#define EMI_TTYPE1 (EMI_BASE+0x500) +#define EMI_TTYPE2 (EMI_BASE+0x508) +#define EMI_TTYPE3 (EMI_BASE+0x510) +#define EMI_TTYPE4 (EMI_BASE+0x518) +#define EMI_TTYPE5 (EMI_BASE+0x520) +#define EMI_TTYPE6 (EMI_BASE+0x528) +#define EMI_TTYPE7 (EMI_BASE+0x530) +#define EMI_TTYPE8 (EMI_BASE+0x538) +#define EMI_TTYPE9 (EMI_BASE+0x540) +#define EMI_TTYPE10 (EMI_BASE+0x548) +#define EMI_TTYPE11 (EMI_BASE+0x550) +#define EMI_TTYPE12 (EMI_BASE+0x558) +#define EMI_TTYPE13 (EMI_BASE+0x560) +#define EMI_TTYPE14 (EMI_BASE+0x568) +#define EMI_TTYPE15 (EMI_BASE+0x570) +#define EMI_TTYPE16 (EMI_BASE+0x578) +#define EMI_TTYPE17 (EMI_BASE+0x580) +#define EMI_TTYPE18 (EMI_BASE+0x588) +#define EMI_TTYPE19 (EMI_BASE+0x590) +#define EMI_TTYPE20 (EMI_BASE+0x598) +#define EMI_TTYPE21 (EMI_BASE+0x5A0) +#define EMI_BWCT0 (EMI_BASE+0x5B0) +#define EMI_BWCT1 (EMI_BASE+0x5B4) +#define EMI_BWCT2 (EMI_BASE+0x5B8) +#define EMI_BWCT3 (EMI_BASE+0x5BC) +#define EMI_BWCT4 (EMI_BASE+0x5C0) +#define EMI_BWST0 (EMI_BASE+0x5C4) +#define EMI_BWST1 (EMI_BASE+0x5C8) +#define EMI_EX_CON (EMI_BASE+0x5D0) +#define EMI_EX_ST0 (EMI_BASE+0x5D4) +#define EMI_EX_ST1 (EMI_BASE+0x5D8) +#define EMI_EX_ST2 (EMI_BASE+0x5DC) +#define EMI_WP_ADR (EMI_BASE+0x5E0) +#define EMI_WP_ADR_2ND (EMI_BASE+0x5E4) +#define EMI_WP_CTRL (EMI_BASE+0x5E8) +#define EMI_CHKER (EMI_BASE+0x5F0) +#define EMI_CHKER_TYPE (EMI_BASE+0x5F4) +#define EMI_CHKER_ADR (EMI_BASE+0x5F8) +#define EMI_CHKER_ADR_2ND (EMI_BASE+0x5FC) +#define EMI_BWCT0_2ND (EMI_BASE+0x6A0) +#define EMI_LTCT0_2ND (EMI_BASE+0x750) +#define EMI_LTCT1_2ND (EMI_BASE+0x754) +#define EMI_LTCT2_2ND (EMI_BASE+0x758) +#define EMI_LTCT3_2ND (EMI_BASE+0x75C) +#define EMI_BWCT0_3RD (EMI_BASE+0x770) +#define EMI_BWCT0_4TH (EMI_BASE+0x780) +#define EMI_BWCT0_5TH (EMI_BASE+0x7B0) +#define EMI_BWCT0_6TH (EMI_BASE+0x7C8) +#define EMI_SNST (EMI_BASE+0x7F8) +#define EMI_SLVA (EMI_BASE+0x800) +#define EMI_THRO_CTRL1 (EMI_BASE+0x858) +#define EMI_AXI_BIST_ADR0 (EMI_BASE+0x98c) +#define EMI_AXI_BIST_ADR1 (EMI_BASE+0x990) +#define EMI_AXI_BIST_ADR2 (EMI_BASE+0x994) + +#define EMI_MPU_CTRL (EMI_MPU_BASE+0x000) +#define EMI_MPU_DBG (EMI_MPU_BASE+0x004) +#define EMI_MPU_SA0 (EMI_MPU_BASE+0x100) +#define EMI_MPU_EA0 (EMI_MPU_BASE+0x200) +#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region*4)) +#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region*4)) +#define EMI_MPU_APC0 (EMI_MPU_BASE+0x300) +#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100)) +#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE+0x800) +#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain*4)) +#define EMI_RG_MASK_D0 (EMI_MPU_BASE+0x900) +#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain*4)) + +#define CHN_EMI_CONA(base) (base + 0x000) +#define CHN_EMI_CONC(base) (base + 0x010) + +#endif // __EMI_HW_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h b/src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h new file mode 100644 index 0000000000..bbd0730d97 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __EMI_MPU_MT_H__ +#define __EMI_MPU_MT_H__ + +#define ENABLE_MPU 1 + +#define EMI_MPU_ALIGN_BITS 16 +#define EMI_MPU_DOMAIN_NUM 16 +#define EMI_MPU_REGION_NUM 32 +#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS) + +#define SSPM_MPU_REGION_ID 4 + +#include <emi_mpu_v1.h> + +#endif /* __EMI_MPU_MT_H__ */ diff --git a/src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h b/src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h new file mode 100644 index 0000000000..51b835607a --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __EMI_MPU_H__ +#define __EMI_MPU_H__ + +#include <emi_mpu_mt.h> + +#define NO_PROTECTION 0 +#define SEC_RW 1 +#define SEC_RW_NSEC_R 2 +#define SEC_RW_NSEC_W 3 +#define SEC_R_NSEC_R 4 +#define FORBIDDEN 5 +#define SEC_R_NSEC_RW 6 + +#define LOCK 1 +#define UNLOCK 0 + +#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) +#if (EMI_MPU_DGROUP_NUM == 1) +#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \ +do { \ + apc_ary[0] = \ + (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \ + (((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \ + (((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned int) lock << 31); \ +} while (0) +#elif (EMI_MPU_DGROUP_NUM == 2) +#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \ +do { \ + apc_ary[1] = \ + (((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | (((unsigned int) d13) << 15) | \ + (((unsigned int) d12) << 12) | (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \ + (((unsigned int) d9) << 3) | ((unsigned int) d8); \ + apc_ary[0] = \ + (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \ + (((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \ + (((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned int) lock << 31); \ +} while (0) +#endif + +struct emi_region_info_t { + unsigned long long start; + unsigned long long end; + unsigned int region; + unsigned int apc[EMI_MPU_DGROUP_NUM]; +}; + +extern int emi_mpu_set_protection(struct emi_region_info_t *region_info); + +#endif /* __EMI_MPU_H__ */ diff --git a/src/vendorcode/mediatek/mt8192/include/memory.h b/src/vendorcode/mediatek/mt8192/include/memory.h new file mode 100644 index 0000000000..1a981435e8 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/memory.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef MT6516_MEMORY_H +#define MT6516_MEMORY_H + +#include <stdint.h> + +/************************************************************************** +* DEBUG CONTROL +**************************************************************************/ +#define MEM_TEST (1) + +// do not change the test size !!!! +#define MEM_TEST_SIZE (0x2000) + +/************************************************************************** +* DRAM SIZE +**************************************************************************/ +#define E1_DRAM_SIZE (0x10000000) +#define E2_DRAM_SIZE (0x08000000) + +/************************************************************************** +* EXPOSED API +**************************************************************************/ +extern u32 mt6516_get_hardware_ver (void); +extern void mt6516_mem_init (void); + +#if MEM_TEST +extern int complex_mem_test (unsigned int start, unsigned int len); +#endif + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/print.h b/src/vendorcode/mediatek/mt8192/include/print.h new file mode 100644 index 0000000000..78fc840d6f --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/print.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef PRINT_H +#define PRINT_H + +#include <console/console.h> + +//int print(const char *fmt, ...); +#define print(_x_...) printk(BIOS_INFO, _x_) +#define printf print + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/reg.h b/src/vendorcode/mediatek/mt8192/include/reg.h new file mode 100644 index 0000000000..9d3216e875 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/reg.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef REG_H +#define REG_H + +#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr)) + +#define read32(addr) (*REG32(addr)) +#define write32(addr, val) (*REG32(addr) = (val)) + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h b/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h new file mode 100644 index 0000000000..5f48baeb5f --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __SV_C_DATA_TRAFFIC_H +#define __SV_C_DATA_TRAFFIC_H + +//#define STRINGIFY(x) #x +#define TOSTRING(x) STRINGIFY(x) + +#define print_svarg(arg) \ +({ \ + mcSHOW_DBG_MSG((TOSTRING(arg) "=0x%x\n", psra->arg)); \ +}) + +/* + * channel type from sv's view + */ +enum { + SV_CHN_A = 0, + SV_CHN_B +}; + + +/* + * dram type from sv's view + */ +enum { + SV_LPDDR = 0, + SV_LPDDR2, + SV_PCDDR3, + SV_LPDDR3, + SV_LPDDR4, + SV_LPDDR5 +}; + +/* + * data rate from sv's view + */ +enum { + SV_DDR4266 = 0, + SV_DDR3200, + SV_DDR1600, + SV_DDR3733, + SV_DDR2400, + SV_DDR1866, + SV_DDR1200, + SV_DDR1333, + SV_DDR800, + SV_DDR1066, + SV_DDR2667, + SV_DDR4800, + SV_DDR5500, + SV_DDR6000, + SV_DDR6400, + SV_DDR2750, + SV_DDR2133 +}; + +/* + * cal_sv_rand_args is data traffic from sv to c. + * sv randomizes these arguments for c to control + * calibration. + */ +typedef struct cal_sv_rand_args { + +/* >>>>>>>>>> common part begin>>>>>>>>>> */ + /* + * 0x4C503435 + * "LP45" + */ + int magic; + + /* + * 0: channel-a + * 1: channel-b + */ + int calibration_channel; + + /* + * 0: rank0 + * 1: rank1 + */ + int calibration_rank; + + /* + * 0: LPDDR + * 1: LPDDR2 + * 2: PCDDR3 + * 3: LPDDR3 + * 4: LPDDR4 + * 5: LPDDR5 + */ + int dram_type; + + /* + * 0: DDR4266 + * 1: DDR3200 + * 2: DDR1600 + * 3: DDR3733 + * 4: DDR2400 + * 5: DDR1866 + * 6: DDR1200 + * 7: DDR1333 + * 8: DDR800 + * 9: DDR1066 + * 10: DDR2667 + * 11: DDR4800 + * 12: DDR5500 + * 13: DDR6000 + * 14: DDR6400 + * 15: DDR2750 + * 16: DDR2133 + */ + int datarate; + + /* + * Data Mask Disable + * 0: enable + * 1: disable + */ + int dmd; + int mr2_value; /* for lp4-wirteleveling*/ + int mr3_value; + int mr13_value; + int mr12_value; + int mr16_value; + int mr18_value; /* lp5 writeleveling */ + int mr20_value; /* lp5 rddqc */ +/* ============================= */ + + +/* >>>>>>>>>> cbt part begin>>>>>>>>>> */ + /* + * 0: doesn't run cbt calibration + * 1: run cbt calibration + */ + int cbt; + + /* + * 0: rising phase + * 1: falling phase + */ + int cbt_phase; + + /* + * 0: training mode1 + * 1: training mode2 + */ + int cbt_training_mode; + + /* + * 0: normal mode + * 1: byte mode + */ + int rk0_cbt_mode; + + /* + * 0: normal mode + * 1: byte mode + */ + int rk1_cbt_mode; + + /* + * 0: cbt does NOT use autok + * 1: cbt use autok + */ + int cbt_autok; + + /* + * autok respi + * 0/1/2/3 + */ + int cbt_atk_respi; + + /* + * 0: cbt does NOT use new cbt mode + * 1: cbt use new cbt mode + */ + int new_cbt_mode; + + /* + * cbt pat0~7v + */ + int pat_v[8]; + + /* + * cbt pat0~7a + */ + int pat_a[8]; + + /* + * cbt pat_dmv + */ + int pat_dmv; + + /* + * cbt pat_dma + */ + int pat_dma; + + /* + * cbt pat_cs + */ + int pat_cs; + + /* + * new cbt cagolden sel + */ + int cagolden_sel; + + /* + * new cbt invert num + */ + int invert_num; + +/* ============================= */ + +/* >>>>>>>>>> wl part begin>>>>>>>>>> */ + /* + * 0: doesn't run wl calibration + * 1: run wl calibration + */ + int wl; + + /* + * 0: wl does NOT use autok + * 1: wl use autok + */ + int wl_autok; + + /* + * autok respi + * 0/1/2/3 + */ + int wl_atk_respi; +/* ============================= */ + +/* >>>>>>>>>> Gating part begin >>>>>> */ + /* + * 0: does not run gating calibration + * 1: run gating calibration + */ + int gating; + + /* + * 0: SW mode calibration + * 1: HW AUTO calibration + */ + int gating_autok; + + int dqsien_autok_pi_offset; + int dqsien_autok_early_break_en; + int dqsien_autok_dbg_mode_en; +/* ============================= */ + +/* >>>>>>>>>> RDDQC part begin >>>>>> */ + /* + * 0: does not run rddq calibration + * 1: run rddq calibration + */ + int rddqc; + + int low_byte_invert_golden; + int upper_byte_invert_golden; + int mr_dq_a_golden; + int mr_dq_b_golden; + int lp5_mr20_6_golden; + int lp5_mr20_7_golden; +/* ============================= */ + +/* >>>>>>>>>> TX perbit part begin >>>>>> */ + /* + * 0: does not run txperbit calibration + * 1: run txperbit calibration + */ + int tx_perbit; + + /* + * 0: does not run txperbit auto calibration + * 1: run txperbit auto calibration + */ + int tx_auto_cal; + + int tx_atk_pass_pi_thrd; + int tx_atk_early_break; +/* ============================= */ + +/* >>>>>>>>>> TX perbit part begin >>>>>> */ + /* + * 0: does not run rxperbit calibration + * 1: run rxperbit calibration + */ + int rx_perbit; + + /* + * 0: does not run rxperbit auto calibration + * 1: run rxperbit auto calibration + */ + int rx_auto_cal; + + int rx_atk_cal_step; + int rx_atk_cal_out_dbg_en; + int rx_atk_cal_out_dbg_sel; +/* ============================= */ +} cal_sv_rand_args_t; + +void set_psra(cal_sv_rand_args_t *psra); +cal_sv_rand_args_t *get_psra(void); +void print_sv_args(cal_sv_rand_args_t *psra); +u8 valid_magic(cal_sv_rand_args_t *psra); +void set_type_freq_by_svargs(DRAMC_CTX_T *p, + cal_sv_rand_args_t *psra); + +#endif /* __SV_C_DATA_TRAFFIC_H */ diff --git a/src/vendorcode/mediatek/mt8192/include/x_hal_io.h b/src/vendorcode/mediatek/mt8192/include/x_hal_io.h new file mode 100644 index 0000000000..ef75df9f80 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/x_hal_io.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef X_HAL_IO_H +#define X_HAL_IO_H + +#include "dramc_pi_api.h" +//=========================================================================== +#define REG_ACCESS_NAO_DGB 0 +#define REG_ACCESS_PORTING_DGB 0 +#define REG_SHUFFLE_REG_CHECK 0 + +// field access macro----------------------------------------------------------- + +/* field macros */ +#define Fld(wid, shft) (((U32)wid << 16) | (shft << 8)) +#define Fld_wid(fld) ((UINT8)((fld) >> 16)) +#define Fld_shft(fld) ((UINT8)((fld) >> 8)) +#define Fld_ac(fld) (UINT8)(fld) + +/* access method*/ +#define AC_FULLB0 1 +#define AC_FULLB1 2 +#define AC_FULLB2 3 +#define AC_FULLB3 4 +#define AC_FULLW10 5 +#define AC_FULLW21 6 +#define AC_FULLW32 7 +#define AC_FULLDW 8 +#define AC_MSKB0 11 +#define AC_MSKB1 12 +#define AC_MSKB2 13 +#define AC_MSKB3 14 +#define AC_MSKW10 15 +#define AC_MSKW21 16 +#define AC_MSKW32 17 +#define AC_MSKDW 18 + +#define Fld2Msk32(fld) /*lint -save -e504 */ (((U32)0xffffffff>>(32-Fld_wid(fld)))<<Fld_shft(fld)) /*lint -restore */ +#define P_Fld(val, fld) ( upk > 0 ? Fld2Msk32(fld): (((UINT32)(val) & ((1 << Fld_wid(fld)) - 1)) << Fld_shft(fld))) + +extern U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr); +extern void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value); + +extern void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32); +extern void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32); +extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32); + +// ========================= +// public Macro for general use. +//========================== +#define u4IO32Read4B(reg32) u4Dram_Register_Read(p, reg32) +#define vIO32Write4B(reg32, val32) ucDram_Register_Write(p, reg32, val32) +#define vIO32Write4B_All(reg32, val32) vIO32Write4B_All2(p, reg32, val32) +#define vIO32Write4BMsk(reg32, val32, msk32) vIO32Write4BMsk2(p, reg32, val32, msk32) +#define vIO32Write4BMsk_All(reg32, val32, msk32) vIO32Write4BMsk_All2(p, reg32, val32, msk32) + +#define u4IO32ReadFldAlign(reg32, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ + ((u4IO32Read4B(reg32) & Fld2Msk32(fld)) >> Fld_shft(fld)) + +#define vIO32WriteFldAlign(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ + (vIO32Write4BMsk((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld))) + +#define vIO32WriteFldMulti(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ +{ \ + UINT16 upk = 1; \ + INT32 msk = (INT32)(list); \ + { upk = 0; \ + ((U32)msk == 0xffffffff)? (vIO32Write4B(reg32, (list))): (((U32)msk)? vIO32Write4BMsk(reg32, (list), ((U32)msk)):(U32)0); \ + } \ +}/*lint -restore */ + +//========================= +// Public Macro for write all-dramC or all-PHY registers +//========================= +#define vIO32WriteFldAlign_All(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ + (vIO32Write4BMsk_All((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld))) + +#define vIO32WriteFldMulti_All(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ +{ \ + UINT16 upk = 1; \ + INT32 msk = (INT32)(list); \ + { upk = 0; \ + ((U32)msk == 0xffffffff)? (vIO32Write4B_All(reg32, (list))): (((U32)msk)? vIO32Write4BMsk_All(reg32, (list), ((U32)msk)): (void)0); \ + } \ +}/*lint -restore */ + +#ifdef __MD32__ +#include "x_hal_io_dpm.h" +#endif + +#endif // X_HAL_IO_H |