summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2022-12-12mb/google/brya/var/marasov: Disable unused I2C busFrank Chu
Disable unused I2C2/I2C4 bus for marasov. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Id1c41bfdca9b752e3f027e6b071629d67aa06761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70237 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-12drivers/wifi: Move ADL-P CNVi IDs from generic to IA common code CNVi driverKapil Porwal
BUG=b:259716145 TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains the value from the devicetree on google/redrix. Before: Scope (\_SB.PCI0.WFA3) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } After: Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/mediatek/mt8195/Makefile.inc: Remove path to non-existent folderElyes Haouas
The directory src/vendorcode/mediatek/mt8195/dramc/include never existed, and was added in commit b0b8dc37 (vendor/mediatek: Add MT8195 dram initialization code). Found using 'Wmissing-include-dirs' command option. Change-Id: Iec349e816a1b646f1ea5fa1db13e05a78ffe1af8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70464 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/nissa/var/yaviks:Generate SPD ID for supported memory partsWisley Chen
Add new memory parts - H58G56BK7BX068 - MT62F1G32D2DS-026 WT:B - K3KL8L80CM-MGCT BUG=b:261539879 TEST=run part_id_gen to generate SPD id Change-Id: I74f35d1afad90c3b6a79679a8126904565695fbc Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70410 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12util/ifdtool/Makefile.inc: Respect LDFLAGS from environmentReka Norman
The ChromeOS build system performs ASAN builds by appending -fsanitize=address to CFLAGS and LDFLAGS. Currently, the ASAN build of ifdtool fails with linker errors because the Makefile does not respect LDFLAGS. Modify the Makefile to respect LDFLAGS from the environment. This is consistent with the Makefiles of most other coreboot utils. BUG=b:255462682 TEST=`USE=asan emerge-nissa coreboot-utils` now succeeds with CL:4018976 Change-Id: I1a497562d4d979829edb47c4c4b3f2c64266324e Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70054 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/brya: Don't add MPTS to both DSDT and SSDTReka Norman
commit 52ccd293d7 ("mb/google/brya: Implement shutdown function for dGPU") started unconditionally adding MPTS to the SSDT. On variants with HAVE_WWAN_POWER_SEQUENCE selected, MPTS is already added to the DSDT via wwan_power.asl. The duplicate definition results in a kernel error: ERR kernel: [ 0.109237] ACPI BIOS Error (bug): Failure creating named object [\_SB.MPTS], AE_ALREADY_EXISTS (20210730/dswload2-327) ERR kernel: [ 0.109242] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20210730/psobject-220) Don't add MPTS to the SSDT if HAVE_WWAN_POWER_SEQUENCE is selected. There are no variants which use both, so this should only result in empty MPTS methods being removed. BUG=b:260380268 TEST=On pujjo, the SSDT no longer contains an empty MPTS method, there's no kernel error, and the WWAN power-off sequence is met. Change-Id: I9f411aae81ea87aa9c8fc7754c3709e398771a32 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70146 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/alderlake/Kconfig: Sort defaults alphabeticallyAngel Pons
"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions Swap the position of two lines so that defaults are listed in alphabetical order according to the PCH type: M, N, P, S. Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12mb/google/octopus/variants/phaser: Implement variant_memory_sku()Joey Peng
This change override memory ID 3 to 1 to workaround the incorrect memory straps in hardware. We would use board_id 7 to identify the specific boards which need to correct the memory ID. BUG=b:259301885 BRANCH=Octopus TEST=Verified on Phaser Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2330b7e16a09f8cc76ed96e81a6165afa80a03a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70353 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Also make sure that the address of the lcl_usb_phy struct is located below the 4GB boundary, so that the truncation to 32 bits won't result in pointing to a different memory location than intended. In this error case, which I don't expect to happen, print an error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its default values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12drivers/mrc_cache: Prevent printing errors in expected use casesYu-Ping Wu
The following are considered "expected" situations, where we shouldn't print error messages as in other unexpected errors: 1. When the previous boot is in recovery mode, under certain config combination the normal MRC cache would have been invalidated. Therefore the "couldn't read metadata" error is expected to show in the current normal boot. Special-case this situation by printing a different message. 2. If the platform doesn't have recovery cache (!HAS_RECOVERY_MRC_CACHE) and vboot starts before romstage (!VBOOT_STARTS_IN_ROMSTAGE), then there should be no region for recovery cache. In this case, "failed to locate region type 0" will be shown. Since it's pretty clear from the code that this is the only case for the error to happen, simply change it to BIOS_DEBUG. Also remove a duplicate message when mrc_header_valid() fails. BUG=b:257401937 TEST=emerge-corsola coreboot TEST=Ran `cbmem -1 | grep ERROR` in recovery boot TEST=Ran `cbmem -1 | grep ERROR` in normal boot following recovery boot BRANCH=corsola Change-Id: Ia942eeecaca3f6b2b90bac725279d2dc6174e0fd Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69542 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-11mb/google/brya/var/agah: Correct dGPU Power GPIOsTarun Tuli
PP1800_GPU_X should dynamically move from GPP_E18 to GPP_F12 depending on board revision. PP0950_GPU_X (PEX) should remain on GPP_E10 for all board revisions. BUG=b:242752623 TEST=dGPU is functional on both revisions of the board Change-Id: I20994fcac4d7b98ee893d5eb98b096c037d31d6c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70320 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-11sb/intel/common: Move definition of TRAPKyösti Mälkki
Both TRAP and TRP0 are now only defined for i82801gx ASL. This fixes an issue with updating to IASL 20221020, with many intel platform builds failing with: dsdt.asl 38: TRP0 = 0 Error 6084 - ^ Object does not exist (TRP0) The error was ignored with older IASL. Change-Id: Ie8a59803f4a27a8315c16bde401f8ca90ee814a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-10mb/google/brya/var/marasov: Change FSP board type to Type3Frank Chu
Change FSP board type to Type3. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage check MRC log "Maximum requested frequency" is 4800 Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I69365bc726b4faac4cedb94cc7b08baa06056c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70439 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10mb/google/brya/var/marasov: Enable PCIe port 5 for WLANFrank Chu
Enable PCIe port 5 for WLAN device BUG=b:261514079 BRANCH=firmware-brya-14505.B TEST=Build and boot on marasov. Ensure that the WLAN module is enumerated in the output of lspci. localhost ~ # lspci 01:00.0 Network controller: MEDIATEK Corp. MT7921 802.11ax PCI Express Wireless Network Adapter Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I007501bb00e2b7b83de1292f3066874d07646cb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70442 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10cpu/cpu.h: Change the function signatureArthur Heymans
There is no need to pass the CPU index around. Change-Id: Iad8e3cb318e6520ac5877118dbf43597dedb75b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-10/: Update and rewrite README.mdMartin Roth
Update the top level readme file to reflect the updated documentation and project status. This is mostly a rewrite, but some text was just reformatted. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2cd59d75da47b287029a9fc5eeddefaf99198965 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-10include/gpio.h: Add 'IWYU pragma: export' commentElyes Haouas
This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented headers. Change-Id: Iedd798eebf3376b7631fc9aa1ca0ba92867382bd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70520 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10mb/google/skyrim/var/frostflow: Add FW_CONFIG definitionFrank Wu
Based on the SKU plan, add FW_CONFIG definition. BUG=b:260473966 BRANCH=None TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I727f69e8fe340cfe624adb5a49bd080ba9544786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70418 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel: Move TCSS FW latency macros to IA common tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from SoC specific tcss.h to IA common tcss.h Additionally, ensure other structure definitions belonging to the IA common code tcss.h are not causing compilation issues for ASL files (due to including FW latency macros) hence, guarded against `!defined(__ACPI__)`. TEST=Able to build and boot Google/Rex and Google/Kano. Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/tigerlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Volteer. Change-Id: I96416f3b68d853c9a5a44c499719f154aa15f0ca Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70486 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/alderlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Kano. Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Fix typoSubrata Banik
This patch fixes typo mistake `Pyhsical` -> `Physical`. Change-Id: I211a3a710f5b63c4c16d4105f2eac50c992cfcf2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70484 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Update DPTF participants ACPI IDsSubrata Banik
This patch updates DPTF participants' ACPI IDs based on the Intel Meteor Lake Reference Code. TEST=Able to build and boot Google/Rex. Change-Id: Iccc7f3cad26a028a3b11d5e5e761bbefa7776583 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70482 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Drop casts around `soc_read_pmc_base()`Dinesh Gehlot
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then casted to a pointer type for use with `read32()` and/or `write32()`. But since commit b324df6a540d ("arch/x86: Provide readXp/writeXp helpers in arch/mmio.h"), the `read32p()` and `write32p()` functions live in `arch/mmio.h`. These functions use the `uintptr_t type for the address parameter instead of a pointer type, and using them with the `soc_read_pmc_base()` function allows dropping the casts to pointer. BUG=none TEST=Build and Boot verified on google/rex Port of 'commit f585c6eeeafb ("soc/intel: Drop casts around `soc_read_pmc_base()`")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I914190f2d2d0507c84b19340159990f9b62ce101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70272 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Allow configuring 8254 timer via CMOSDinesh Gehlot
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. BUG=none TEST=Build and Boot verified on google/rex Port of 'commit bc35bed18eba ("soc/intel/*: Allow configuring 8254 timer via CMOS")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ibf6c43ddecb3da325c22228205243bb6af00d1d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70423 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Fix `unknown` voltage field in SMBIOS tableSubrata Banik
This patch fixes the `unknown` voltage field issue in processor SMBIOS table. This patch is backported from commit 30e8fc1f4e7d4e79b1403acd3679ce08598687c3 (soc/intel/alderlake: Fix unknown voltage in SMBIOS) TEST=Able to see meaningful voltage data in the SMBIOS table. Without this patch: localhost ~ # dmidecode -t 4 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro ... Voltage: Unknown With this patch: localhost ~ # dmidecode -t 4 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro ... Voltage: 0.8 V Change-Id: I0cd7c1e3c0746309600e4480f4822a4d72147041 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70424 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Support PCIe hardware compliance test modeSubrata Banik
The validation process verifies that hardware components comply with the standard hardware specifications. For instance, PCI express implementation must comply with the hardware PCIe specification requirements: Electrical, Configuration, Link Protocol and Transaction Protocol. To perform these tests the hardware must be configured in a particular state: some feature related to power management need to be turned off, hot plug should be enabled... This patch sets the appropriate FSP Updateable Product Data flags to get the hardware in the proper configuration: - Enable PCIe hotplug on all ports - Set clock sources to run free - Set the FSP compliance test mode flag This patch is backported from commit 096ce1444ec7fa204f331a75c2ac9d00ea00bf12 (soc/intel/alderlake: Support PCIe hardware compliance test mode) Change-Id: Idd7a1adf0f53b014093ba70fee599dbb7887a0fc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70416 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Skip duplicate PCIe RP CLKSRC programmingSubrata Banik
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip PCIe CLKSRC programming without a clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. This patch is backported from commit edf71a08b4cb7bd8683344aa4ad301f1526289c2 (soc/intel/alderlake: Skip PCIe source clock assignment if incorrect) Change-Id: Ie9179880a57796d8595874325203280590d7ee9d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70415 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Check clkreq overlapSubrata Banik
In some cases, partner may assign same clkreq on more than one devices. This could happen when one device is in baseboard dev tree and another one is in override dev tree. This change adds a clkreq overlap check and shows a warning message. This patch is backported from commit ff553ba8b3d39fba6f1ed9b8e3513fc5412ba5a9 (soc/intel/alderlake: Check clkreq overlap) Change-Id: Ifc1c57578eca376685196ad497d9db825d63aa76 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70414 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10mb/google/rex: Implement S0ix hooks aka `MS0X` methodSubrata Banik
This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based on the state of the system while `SLP_S0_L` signal is `low` (while the system is in S0ix). Implemented runtime ASL method (MS0X) being called by PEPD device _DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x75) } Else { \_SB.PCI0.STXS (0x75) } } BUG=b:256807255 TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/70196 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-10mb/google/skyrim: use gpio.h includeFelix Held
Replace the amdblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h in the AMD SoC case. Since baseboard/ec.h and indirectly baseboard/gpio.h files will get included in the DSDT, the soc/gpio.h includes in those aren't replaced with a gpio.h include for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib982e338b5c6bc145ec1a8f6dd75175a42dfb426 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70436 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10mb/google/guybrush: use gpio.h includeFelix Held
Replace the amdblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h in the AMD SoC case. Since baseboard/ec.h and indirectly baseboard/gpio.h files will get included in the DSDT, the soc/gpio.h includes in those aren't replaced with a gpio.h include for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10drivers/siemens/nc_fpga/nc_fpga_early.c: Use write32p()Elyes Haouas
Change-Id: Ic7139f0adc0ce4556268612f5e77eb01738fc068 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70471 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10lib/ramtest.c: Use {read,write}32p()Elyes Haouas
Change-Id: I63abe019490f72bd73bcdbddb974aff2b2bfd803 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09mb/google/{herobrine,peach_pit,trogdor}: Use {read,write}32p()Elyes Haouas
Change-Id: I2e1978f20b085f609cbeb0907374383f2d11fbf0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09drivers/net/atl1e.c: Use {read,write}32p()Elyes Haouas
Change-Id: Idc9dd4434a8023af4758f921f6279d09059166d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09drivers/generic/bayhub/bh720.c: Use {read,write}32p()Elyes Haouas
Change-Id: I97b073bfc291b13719a199b277f22b477647db8e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70470 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/intel/mtlrvp: Add MTL-P RVP board idsJamie Ryu
This adds MTL-P board id definition. Change include, 1. Add board_id.c implementation 2. Add board_id.h implementation 3. Add board_id config in variants.h 4. Makefile changes BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I90b0543d5db208f696d2c2c2dc3d2581514a845b Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66102 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-09mb/intel/mtlrvp: Add initial code for mtlrvp_p_ext_ec variant boardHarsha B R
This patch adds the initial code for mtlrvp_p_ext_ec variant board which includes 1. support for 2 mainboards (Chrome EC and Windows EC) by adding overridetree.cb to corresponding directory 2. Move devicetree to baseboard/mtlrvp_p 3. Update mainboard name in Kconfig and Kconfig.name 4. Add config option to select corresponding overridetree.cb Subsequent patches include patch train starting from (CB - 66102) BUG=b:260654043 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com>
2022-12-09vc/intel/fsp: Update ADL N FSP headers from v3343.04 to v3343.05Shaik Shahina
Update generated FSP headers for Alder Lake N from v3343.04 to v3343.05. Changes include: -FspsUpd.h : Update UfsEnable UPD description in comments BUG=b:228110908 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa. Change-Id: Ieff33df2d2b0884a9788e05e06da5bdae1be08de Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70446 Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/system76/tgl-u/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ie0e31fcdbeb219d3ecbe14a492d3e7824f6a51cc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70397 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09vc/mediatek/mt8192/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I79457d8548700eeb534419f8e41990fad05edb68 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70398 Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09drivers/ipmi/ipmi_ops.c: Fix typo in error messageArthur Heymans
Change-Id: I43c6dc0eb19d9be908c98fb6316f87747605b91e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51798 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-09soc/mediatek/mt8173: Allow BL31 payload not targeting RAMYidi Lin
selfboot.c blocks the payload that does not target RAM. But MT8173 loads and runs BL31 payload in SRAM. Make the exception by implementing `payload_arch_usable_ram_quirk()`. TEST=load and initialize BL31 successfully Change-Id: I8951b1c4673cdae7d1ad0c11d7d6c12376acd328 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70344 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/google/brya/var/marasov: Add the FIVR configurationsFrank Chu
This patch enables V1p05 and Vnn external bypass VRs for Marasov. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-09mb/google/brya/var/marasov: Adjust the bit fields in the FW_CONFIGFrank Chu
Adjust the bit fields in the FW_CONFIG for Proto Phase. BUG=b:254404046 BRANCH=firmware-brya-14505.B TEST=FW_NAME=marasov emerge-brya coreboot Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ia71269918092655c11c2b37a26ec19123f759650 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-09vc/eltan/security/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ia6f72acf0ae90c98ccf1fbbeedd7fbf5f194b4cc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70385 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09sb/intel/ibexpeak/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I7c2217bbe677810d25c5d5d1062320773ee7e0c8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-09sb/intel/i82801jx/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I2e69822575e42b322eb971540821f3b87fb7e903 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-09soc/amd/mendocino: Enable LPC SPI DMAKarthikeyan Ramasubramanian
Enable LPC SPI DMA. This helps with ~20ms boot time improvement while loading various components synchronously. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe a boot time improvement of ~20 ms. Before: Total Time: 1,503,032 After: Total Time: 1,485,536 Change-Id: I4dd57d46ae9bd664d57178d34b5beda872ed2cdb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70383 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09util/ifdtool/Makefile: improve cross-compilation supportMaciej Pijanowski
INSTALL and PREFIX variables will not be overwritten. Also, mkdir was replaced by a tool from the INSTALL variable to be compatible with other cross-compilation buildsystems (like Yocto). Overwriting variables generates problems when we use different buildsystem like Yocto where tool names are stored in environment variables. This change may make building the utility easier - the user of different buildsystem will not have to remember to pass correct tool names when issuing the make command. Also, this change does not affect the rest of users - if the variable was not set before, then it will be configured as before. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Change-Id: Ia8dd67d18392e1e11d9160b187ef1a874d69ff5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70105 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09util/inteltool/Makefile: improve cross-compilation supportMaciej Gabryelski
Use tool from INSTALL variable to create directory instead of mkdir to be compatible with other cross-compilation buildsystems (like Yocto). Signed-off-by: Maciej Gabryelski <maciej.gabryelski@3mdeb.com> Change-Id: I0b0949d07baae1ae1d7b22ac3d0b8913f81d89c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70104 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09util/superiotool/Makefile: improve cross-compilation supportMaciej Gabryelski
Use tool from INSTALL variable to create directory instead of mkdir to be compatible with other cross-compilation buildsystems (like Yocto). Signed-off-by: Maciej Gabryelski <maciej.gabryelski@3mdeb.com> Change-Id: I9d455f3d1a6d86c88b8e22da825fe14f9630e971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70103 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09util/ectool/Makefile: improve cross-compilation supportMaciej Gabryelski
Build variables like CC, INSTALL, and PREFIX, should not be overwritten by the Makefile. This generates problems when we use different buildsystem like Yocto where tool names are stored in environment variables. This change may make building util tool easier - the user of different buildsystem will not have to remember to pass correct tool names during running the make command. Also, this change does not affect the rest of users - if the variable was not set before, then it will be configured as before. Signed-off-by: Maciej Gabryelski <maciej.gabryelski@3mdeb.com> Change-Id: If5c88bde0ae00f0211a250906cbdedfe4f59c67b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70102 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/google/rex: Enable S0ixSubrata Banik
This patch enables S0ix for Google/Rex platform. BUG=b:256807255 TEST=Able to program FADT table Bit 21 (Low Power Idle S0) Change-Id: I79546267d29622c65321f7dfa29d3aac2fa59438 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70430 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-09mb/google/brya/var/marasov: Remove __weak for memory overrideFrank Chu
Drop the __weak qualifier as this function is not overridden. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ica25b2bc4325ff9d27be672926b4e3b550c86e96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-09include/cper.h: Add CPER Memory Error Section definitionsTim Chu
Add Memory Error Section definitions from UEFI Specification rev 2.10 appendix N.2.5. The structure defined here may be used for machine check handling. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-09soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slotsAngel Pons
Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function to allow creating SMBIOS type 17 entries for unpopulated DIMM slots. Change-Id: I1d9c41dd7d981842ca6f0294d9e6b0fedc0c98e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64036 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/siemens/*/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ie9ff43432215ebc89e6c1ea5f86b248e7fecd943 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70396 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09soc/intel/quark/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ie079dcf8c1e662ce6ef068befa43dfe90c89edd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70395 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mem_chip_info: Update to new formatJulius Werner
The original version of the mem_chip_info structure does not record rank information and does not allow precise modeling of certain DDR configurations, so it falls short on its purpose to compile all available memory information. This patch updates the format to a new layout that remedies these issues. Since the structure was introduced so recently that no firmware using it has been finalized and shipped yet, we should be able to get away with this without accounting for backwards compatibility. BRANCH=corsola Cq-Depend: chromium:3980175 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68871 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2022-12-08mb/google/zork: use gpio.h includeFelix Held
Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the AMD SoC case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I37a33dd8821a00b7edfd1e5b593f71bea0e77630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70434 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08mb/google/kahlee: use gpio.h includeFelix Held
Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the AMD SoC case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13bc33b91f6e6d52867da9043bb386f3befac5fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/70433 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configurationFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08mb/google/brya/var/gladios: Update fw_config STORAGE fieldKevin Chiu
option STORAGE_EMMC 0 option STORAGE_NVME 1 BUG=b:239513596 TEST=FW_NAME=gladios emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I27baa2ca8c2b334fb81aa87b22c3b7c028c38cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-08mb/google/skyrim/var/winterhold: Enable Dynamic DPTC configEricKY Cheng
Enable Dynamic DPTC support. Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-08soc/amd/common/acpi, mb/google/skyrim: Implement DTTS ProposalEricKY Cheng
DTTS indicated Dynamic Thermal Table Switching.The proposal would like to develop the schematic for switching 6 thermal table by lid status, machine body mode and temperature. After entering the OS, the thermal table would be table A. If the “Motion” or “Lid status change” is detected. The thermal table would switch to laptop mode or lid close mode. Once the higher environment temperatures are detected,the thermal table would switch to the corresponding power throttle table (B, D or F). Based on these table switching mechanisms, no matter how the end-user uses Chromebook,they could enjoy more humanized thermal designs. Release Over Over Release . Temp. Temp. Temp. Temp. . -------------------------------------------------------- . Desktop mode Table A Table B 50C 45C . Lid open (Default) . -------------------------------------------------------- . Desktop mode Table C Table D 55C 50C . Lid close . -------------------------------------------------------- . Laptop mode Table E Table F 45C 40C . -------------------------------------------------------- . On the proposal, the transmission rules are list below: 1. Table A is the default table after booting. 2. A, C, E (Release Temp) can switch to each other. 3. B, D, F (Over Temp) can switch to each other. 4. A and B, C and D, E and F can switch to each other. 5. If Lid open/close or mode switch event trigger, temperature release tables will translation to each other, temperature over tables will translation to each other.After that event trigger, EC will check the new temperature condition and decide if the temperature need to be trigger.For example, if table A will switch to table D, table A will switch to C with Lid close event, if temperature is over 55C, EC will trigger temperature to switch form table C to D. 6. EC will trigger 3 times body-detection events during power on boot without any body-mode and lid status change. For this case if the previous table label is on same group, we will based on the temperature to decide the table. For example, assume table A is current table. When the temperature reaches 50C, than the table is switched from A to B. The current table is B. When the temperature is downgrade below 45C, the table is switched form B to A. The same rule is for C and D, E and F. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-08mb/google/skyrim/var/winterhold: update thermal configEricKY Cheng
Enable STT and set 6 thermal table profiles for Dynamic Thermal Table Switching Proposal support. BUG=b:232946420 BRANCH=none TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Ie0740cb5bb16cd53c2ee6937e32a974346012823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-08soc/amd/common/amdblocks/gpio: update amdblocks/gpio_defs.h includeFelix Held
Include <amdblocks/gpio_defs.h> instead of "gpio_defs.h", since gpio_defs.h is not only visible in a local scope, but also as <amdblocks/gpio_defs.h>. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab3e5bb235a5b1bc995b6cf8710f0d8c1886142d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70432 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08mb/google/rex: Add MPTS method for WWAN over PCIeSubrata Banik
This patch generates the following for the mainboard: Scope (\_SB) {         Method (MPTS, 1, Serialized)         {             Local0 = \_SB.PCI0.RP06.RTD3._STA ()             If ((Local0 == One))             {                 \_SB.PCI0.RP06.PXSX.DPTS (Arg0)             }         } } Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70229 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Enable LPIT supportSubrata Banik
This patch adds SLP_S0 residency registers and enable LPIT support. Added `SLP_S0_RES` in Meteor Lake pmc.c as per MTL EDS document. TEST=Able to see LPIT Table after booting Google/Rex to ChromeOS. localhost /home # ls -lt /sys/firmware/acpi/tables/ -r--------. 1 root root 254 Dec 5 06:59 APIC -r--------. 1 root root 84 Dec 5 06:59 DBG2 -r--------. 1 root root 21819 Dec 5 06:59 DSDT -r--------. 1 root root 276 Dec 5 06:59 FACP -r--------. 1 root root 64 Dec 5 06:59 FACS -r--------. 1 root root 56 Dec 5 06:59 HPET -r--------. 1 root root 148 Dec 5 06:59 LPIT -r--------. 1 root root 60 Dec 5 06:59 MCFG -r--------. 1 root root 21078 Dec 5 06:59 SSDT -r--------. 1 root root 76 Dec 5 06:59 TPM2 Change-Id: Id2d16d8514ce4b7867c9395617ad3ac73b1b9989 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70351 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Implement SoC override to set CPU privilege levelSubrata Banik
This patch implements SoC overrides to set CPU privilege level for Meteor Lake SoC. Change-Id: I33794f51e57dd8e0ffe61dfd2f91c6ef3f9187c9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70352 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Add missing entry for GSPI2Subrata Banik
This patch adds missing ASL entry for GSPI2 device. Change-Id: I8f8410947b77d1a9bab2fa5929f30c803a78266d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70354 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans
This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-07arch/x86/ioapic.c: Move macros to compilation unitArthur Heymans
Some of these macros are too generic like "NONE" and create conflicts in other compilation units. Change-Id: I6131a576f115df20df4d3df712d4c3f59c6dceb7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70429 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07mb/google/brya/var/lisbon: Update fw_config STORAGE fieldKevin Chiu
option STORAGE_EMMC 0 option STORAGE_NVME 1 BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Idd52112743ee0d64aca630e54511503607770d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-07mb/google/glados/var/lars: Set SKU ID based on VPDMatt DeVillier
LARS has two variants, LARS and LILI, which are differentiated via the customization_id field in the VPD. To make differentiation easier outside of ChromeOS (ie, for Windows/Linux drivers), set the SKU ID based on VPD so it can be easily read via SMBIOS. Modeled after similar code in google/reef (snappy variant). TEST=build/boot lili variant, verify sku1 populated in SMBIOS tables. Change-Id: I148462b6f86b25fa8db26ea6e1537d1a5e47984b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-07soc/amd/common/block/acpi/ivrs: read IOAPIC IDs from hardwareFelix Held
TEST=IVRS table doesn't change on amd/mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5be04bc91425480992fcad12f8720738f9ca490e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70357 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07sb,soc/intel,mb: Drop leftover comments and TODOs in ASLKyösti Mälkki
Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07mb,sb,soc/intel: Drop useless IO trap handlersKyösti Mälkki
There are four requirements for the SMI to hit a printk() this commit now removes. Build must have DEBUG_SMI=y, otherwise any printk() is a no-op inside SMM. ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value. Platform needs to have IO Trap #3 enabled at IO 0x800. The SMI monitor must call io_trap_handler for IO Trap #3. At the moment, only getac/p470 would meet the above criteria with TRAP(0x32) in its DSDT _INI method. The ASL ignores any return value of TRAP() calls made. A mainboard IO trap handler should have precedence over a southbridge IO trap handler. At the moment we seem to have no cases of the latter to support, so remove the latter. Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07mb/*/smihandler.c: Drop unused <soc/nvs.h>Kyösti Mälkki
Change-Id: I4819909cf9460ca550af38ca73a50220b77a385f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07mb/lenovo/t60,x60: Split dock_(dis)connect() functionKyösti Mälkki
Avoid calling a function named mainboard_io_trap_handler() when the dock (dis)connect is not triggered from IO trap. Change-Id: Idc258a390f2de2c32d38a0e35fcce896d058d1b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07util/autoport: Drop lenovo mainboard_io_trap_handler()Kyösti Mälkki
See commit cfc93cbb660e ("mb/lenovo/{t60,x201,x60}/smihandler: Remove SMM reinitialization") Change-Id: I540c543be027410f387803e8194fb71012cc5063 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-07sb,soc/intel: Fix SMI handler IO trap data maskKyösti Mälkki
Shift is done in multiples of 8 (1 << 3) bits. It was fixed already for i82801ix/jx. Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-07vboot: Force config file inclusion with CBFS integrationJulius Werner
CONFIG_VBOOT_CBFS_INTEGRATION images are signed differently than normal images. futility needs to be able to tell this difference, and it parses the `config` file included in CBFS to do this. This change codifies that dependency in Kconfig so that nobody can accidentally break this by turning off config file inclusion. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2b2d245b850bc65abb4e72f20b4e360312c828f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70157 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07build: Combine "savedefconfig" and "stripped config" in CBFS `config`Julius Werner
The intention of CB:69710 was that the expanded config file introduced there would be a strict superset of the old version and could be used in all the same cases. This is generally true except for a small oversight: if a boolean Kconfig is `default y`, but was manually set to `n` by the user, the new `config` file does not include a line for it. Running `make olddefconfig` on such a file will again introduce the option as `y`. It turns out that `make olddefconfig` actually parses those "load-bearing comments" in that case. This patch fixes the problem by also generating the minimal defconfig (like before CB:69710), and then just appending the non-comment lines from the full config that don't appear in it already. This ensures that any "load-bearing comments" in the defconfig remain in the file and the result of Kconfig utilities regenerating a full config from there will again be the same as before CB:69710. In addition, it clearly separates the "minimal defconfig" part of the file from the rest, making it easy for people to extract that if they need it; while also keeping all the config values in one file to make it easy to grep for a certain value. Also eliminate that random backslash in the recipe that doesn't seem to have any good reason to exist and was probably a typo to begin with. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I52ba5d20d3536498fae79d529acf7135f97ef1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-06sb,soc/amd: Remove unused southbridge_io_trap_handler()Kyösti Mälkki
At the moment IO trap is not implemented for AMD platforms. Change-Id: Ib62ac4e4e418a8bab80c30dfb5183ecd8beb998d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06arch/x86/smbios.c: Allow creating entries for empty DIMM slotsAngel Pons
Properly handle meminfo DIMMs with `dimm_size` of 0, which represent empty slots. This allows platform code to create dummy meminfo DIMMs so that SMBIOS tables have type 17 entries for empty DIMM slots. Change-Id: I17ae83edf94483bd2eeef5524ff82721c196b8ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64035 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06drivers/intel/fsp2_0: Update MRC cache in ramstageReka Norman
Currently the MRC cache is updated in romstage, immediately after returning from FSP-M. Since cbmem is not cached in romstage, the update is slow (~6 ms on nissa). Specifically, the new MRC data returned by the FSP is stored in the FSP reserved memory in cbmem, so hashing the new data is slow. Move the MRC cache update to ramstage, where cbmem is cached. On nissa, this saves ~5 ms of boot time. Before: 552:finished loading ChromeOS VPD (RW) 631,667 (16) 3:after RAM initialization 637,703 (6,036) 4:end of romstage 650,307 (12,603) After: 552:finished loading ChromeOS VPD (RW) 631,832 (15) 3:after RAM initialization 633,002 (1,169) 4:end of romstage 645,582 (12,580) In ramstage, save_mrc_data() takes ~138 us. BUG=b:242667207 TEST=MRC caching still works as expected on nivviks - after clearing the MRC cache, memory is retrained on the next boot, but cached data is used on subsequent boots. Change-Id: Ie6aa2dee83a3ab8913830746593935d36a034b8d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-06soc/intel/common/block: Use readXXp/writeXXp()Elyes Haouas
Change-Id: I83d05ce0b26b01fdfc95d1442a4c930ed77bf25c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06sb/intel/bd82x6x: Use {read,write}32pElyes Haouas
While on it, sort includes. Change-Id: Iacc858fbad89b54b1f5891c18cd3043b3963d53f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06sb/amd/pi/hudson: Use {read,write}16/32p()Elyes Haouas
Change-Id: Ic8621a18a1b3c299c3d6eb7b4bff39f1ff7d8492 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/pineview: Use read32p()Elyes Haouas
Change-Id: Ie2b1131d7db4b81bd6eb2df7a5ba8a6e8b54539b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/haswell: Use {read,write}32p()Elyes Haouas
Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/x4x: Use read32p()Elyes Haouas
Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/e7505: Use read32p()Elyes Haouas
Change-Id: I78337cf822cfae177b9ef3040641057a84e90e15 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/sandybridge: Use read{8,32}p()Elyes Haouas
Change-Id: I3bbb2f02a2dc182956deffc554a6b161a93ad963 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06soc/cavium/cn81xx: Use read64p()Elyes Haouas
Change-Id: Ia79816ccc230d17dd1ce2bde7a185b4d502ad107 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>