diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-12-05 20:28:42 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-08 07:43:48 +0000 |
| commit | 2a2488fa67d253ae5ce64b39631f7e62b2ea536e (patch) | |
| tree | 0fc14e28dc8ae02c8b9d61d5d007e67aa614c68e | |
| parent | 85e619c51472940f8350ceee8c487f4e54d7a2d9 (diff) | |
soc/intel/meteorlake: Enable LPIT support
This patch adds SLP_S0 residency registers and enable LPIT support.
Added `SLP_S0_RES` in Meteor Lake pmc.c as per MTL EDS document.
TEST=Able to see LPIT Table after booting Google/Rex to ChromeOS.
localhost /home # ls -lt /sys/firmware/acpi/tables/
-r--------. 1 root root 254 Dec 5 06:59 APIC
-r--------. 1 root root 84 Dec 5 06:59 DBG2
-r--------. 1 root root 21819 Dec 5 06:59 DSDT
-r--------. 1 root root 276 Dec 5 06:59 FACP
-r--------. 1 root root 64 Dec 5 06:59 FACS
-r--------. 1 root root 56 Dec 5 06:59 HPET
-r--------. 1 root root 148 Dec 5 06:59 LPIT
-r--------. 1 root root 60 Dec 5 06:59 MCFG
-r--------. 1 root root 21078 Dec 5 06:59 SSDT
-r--------. 1 root root 76 Dec 5 06:59 TPM2
Change-Id: Id2d16d8514ce4b7867c9395617ad3ac73b1b9989
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70351
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/include/soc/pmc.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index fb99d30b53..79a51baea1 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR diff --git a/src/soc/intel/meteorlake/include/soc/pmc.h b/src/soc/intel/meteorlake/include/soc/pmc.h index 813930b1f8..e7da64236b 100644 --- a/src/soc/intel/meteorlake/include/soc/pmc.h +++ b/src/soc/intel/meteorlake/include/soc/pmc.h @@ -129,6 +129,8 @@ extern struct device_operations pmc_ops; #define HPR_CAUSE0_MI_HRPC (1 << 9) #define HPR_CAUSE0_MI_HR (1 << 8) +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) |