diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-12-03 13:31:38 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-06 19:45:59 +0000 |
| commit | 9a83eae71ef838037024f5316b0e745bc2810cd5 (patch) | |
| tree | 5debbd100bba57c99e76782319c0217364c8de29 | |
| parent | a2389ef3162be930e576af68e613d54ef4884cd4 (diff) | |
nb/intel/haswell: Use {read,write}32p()
Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/northbridge/intel/haswell/early_init.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 13c2dcd2bc..e47deb5da6 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -169,14 +169,14 @@ static void haswell_setup_iommu(void) /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ u32 reg32; - reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); - write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); + reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS); + write32p(GFXVT_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); /* Clear SPCAPCTRL */ - reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL; + reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS) & ~SPCAPCTRL; /* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */ - write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), + write32p(VTVC0_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); } diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 4980f9b7ec..ce14915b2b 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -47,7 +47,7 @@ void mainboard_romstage_entry(void) if (CONFIG(INTEL_TXT)) { printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n"); - intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + intel_txt_log_acm_error(read32p(TXT_ERROR)); intel_txt_log_spad(); |