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2021-08-04soc/intel/cannonlake/vr_config: Print configured valuesNico Huber
These values are quite important and our default tables sometimes have holes. We should at least make it visible what the resulting settings are. Change-Id: Ic716d073da1c2638c4b16f2eac01b83a0768d22f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04soc/intel/cannonlake/vr_config: Add TDC values for CFL-H 6+2Nico Huber
Values were taken from PDG (571391), 51.3 IMVP8 Voltage and Current Requirements. Change-Id: Iffa29386cb7da333353dafd0ba3a61ca61a0ccac Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04soc/mediatek/mt8195: Add devapc basic driversNina Wu
Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set domain remap. 4. Set default permission. Change-Id: I3677657a117caed0d73526f78b0ebe8180148335 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-033rdparty/qc_blobs: Uprev to new HEAD (98db386)Shelley Chen
Now that gsi_fw blob has landed, need to uprev the qc_blobs. Change-Id: I0bf67a560ee2e5d771bdb71b60e3d3d372dad567 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56776 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03mb/google/brya: Add RTD3 for WWANThejaswani Putta
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 6 and provide the reset GPIO / src clk pins. BUG=None BRANCH=None TEST=Build and boot the coreboot image, check if device is enumerated in the lspci list after warm/cold reboot cycles, run suspend cycles and check if WWAN is entering L2 LPM. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-03sc7180: Add display support for mipi panelsVinod Polimera
- configure TROGDOR_HAS_MIPI_PANEL to "n" by default, it can be updated for mipi panels. - add simple rm69299 panel as an example to append new mipi panels. - use existing edid struct to update mipi panel parameters. - add dsi command tx interface for mipi panel on commands. Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52662 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03mb/google/brya/variants/primus: configure correct type-c portScott Chao
BUG=b:195274799 TEST=USE="project_primus" emerge-brya coreboot and verify it builds without error. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I4abf7b2d98b188735ef79f8ffbee4c02099ec021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56583 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-03mb/google/brya: Introduce new baseboard braskZhuohao Lee
This patch initiates the brask setting which includes the gpio and device tree setting. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: I1bb42c7bb2492402de0810bc4ab2e8d8c0e2392b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-03Revert "mb/google/dedede/var/cret: Disable SDCard controller"Dtrain Hsu
This reverts commit f29437862269de24f85392d49f6afa6fa60ac43e. Reason for revert: It makes cret can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants. BUG=b:194961854 TEST=Build and boot to OS. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I929369c9419375e74be61a4ff3e5566b0f41ce65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-03mb/google/brya: Disable crashlog on bryaMAULIK V VAGHELA
Crashlog is a debug feature and not used in normal mode of operation. Disabling this feature will allow us to disable unused IPs and also provide boot time savings of ~5-7 ms. BUG=b:195327879 BRANCH=None TEST=Platform boots and no function impact Change-Id: I1f7def4ea41ff7a566aada080be1e791c11766e6 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56654 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03mb/google/brya: Create felwinter variantIan Feng
Create the felwinter variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:194431541 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_FELWINTER Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Iff2b9daec40995a013f9fe0dd76ad667d1807d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56765 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/brya/variants/redrix: Init devicetree for redrixWisley Chen
Init basic override devicetree based on schematics BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I9fb752fe8280893b84c172d8a519578fa4220184 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-02mb/google/brya/variants/gimble: configure correct type-c portScott Chao
Change TypeC port1 usb3 port="3". BUG=b:194472269 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Iaba27aad2adfb0a9e83058ac756ca46a762107bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/56545 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Drop early BAR macrosAngel Pons
They are used at most once. Use the actual values and drop the macros. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9c1c3ebbbfa64a5eeea3bd5551c3d0068ac0dab2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55799 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Replace soc/intel/common includeAngel Pons
Broadwell now uses the Lynx Point hda_verb.c and should thus use the corresponding header as well. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9b8ca91bed67be9c6850bd51f4c81e002a0f5aef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55797 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell/pch/pch.c: Drop unused includeAngel Pons
For some reason, this change makes ramstage slightly smaller. Change-Id: I5564e06b797d787f0d1093bd9bd572d1ee7b2d54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55583 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Drop unused function declarationsAngel Pons
These functions are never defined. Remove the unused declarations. Change-Id: I4204265680d06bf83fc42f061fd7270ff8e3305e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55798 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Rename `ramstage.h`Angel Pons
This file only contains the `broadwell_run_reference_code()` function prototype (either a declaration or an inline stub definition). Rename this file to refcode.h and only include it where necessary. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6513f45b8914a84312b27ef4860870a89fd0aab3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55582 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02payloads/tianocore: update MrChromebox UEFIPAYLOAD branchMatt DeVillier
Update tianocore branch used with default UEFIPAYLOAD option to mrchromebox/uefipayload_202107 (July 2021) branch. This branch is rebased on edk2 upstream commit 12e34cd2f7900578ee83cb01b8f1696a7bb7511b [OvmfPkg/Bhyve: clean up TPM_ENABLE remnants] vs tag edk2-stable202105. The main changes are fixes for e820 table parsing and support to disable "Above 4G decode", which is required to boot distros with bootloaders that expect to be loaded into RAM below 4G. This fixes booting with Qubes, ZorinOS, Proxmox, among others. Additionally, several commits on top of upstream have been consolidated, reworked, and/or reordered for readability and maintainability. Change-Id: I6f04fd027a0599ca6892a1376938108a2e402ac2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-02mb/siemens/mc_ehl: Enable master bit in PCI config space if allowedWerner Zeh
Some legacy devices need to have the master bit set in the PCI config due to old drivers not setting it correctly. Set the master bit if the feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE. For now, the PCI devices with the ID 110a:403e and 110a:403f needs this master bit to be set. Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56632 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scanWerner Zeh
Boards based on mc_ehl have, just like some mc_apl variants, legacy devices on the PCI bus which take longer to boot. In order to ensure that they will be enumerated correctly wait for them to come up before PCI scan starts. TEST=Checked that the new message is visible in the log. Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56631 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/kukui: Add new config 'pico' in corebootLucas Chen
Add new board 'pico' and set correct ram_id offset. BUG=b:194985056 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I33c37d99fa0451239bc6626e71bfddb29a11e97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-08-02helpers: Add GENMASK macroYu-Ping Wu
The GENMASK is defined in multiple files (with various names such as MASKBIT), which sets certain consecutive bits to 1 and leaves the others to 0. To avoid duplicate macros, add GENMASK macro to helpers.h. GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000. Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in mmio.h. BUG=none TEST=make tests/commonlib/bsd/helpers-test TEST=emerge-cherry coreboot BRANCH=none Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-08-02mb/google/brya: Update entries for UFC to support IMX208Varshit B Pandya
1. Replace OV5675 ACPI entries with IMX208 2. Replace FW_CONFIG name 3. Add support for NVM inside UFC BUG=b:190674542 TEST=Build and boot to OS on Brya, raw capture on UFC Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-02mb/google/brya: Configure H21 as GPO and A17 as lowVarshit B Pandya
As per the schematics, UFC has on card oscillator so we donot need H21 in NF1 that is IMGCLKOUT H21 is used to enable this oscialltor so configuring it as 1 A17 is configured as high while _ON method is called by driver and it is configured as low when _OFF method is called by driver. Hence coreboot should configure it as low on boot. BUG=b:190674542 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/dedede/var/cappy2: Disable external bypass VRSunwei Li
The cappy2 removed the anpec apw8738bqbi and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:194146867 BRANCH=dedede TEST=VCCIN_AUX is disable Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ieb4182a989459db629e3b69757c293ca26e8b0cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2021-08-02mb/google/dedede/var/cappy2: Add Tpm2.0 device supportSunwei Li
Using Tpm2.0 device instead of the Cr50 in cappy2 BUG=b:191743435 BRANCH=dedede TEST=tpm2.0 device function is ok Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56658 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Rename `SA_DEV_ROOT`Angel Pons
For consistency with Haswell, rename this macro to `HOST_BRIDGE`. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Drop helper functionsAngel Pons
Done for consistency with Haswell in order to ease unification. Change-Id: I445f086cfcb65a6001ced3326fb9f25a4188b888 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55527 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02nb/intel/haswell: Move MRC glue code into a subfolderAngel Pons
Put the Haswell MRC glue code inside a `haswell_mrc` subfolder. Future commits will move the Broadwell MRC/refcode glue code to be in Haswell northbridge scope, so plan in advance. Tested on Asrock B85M Pro4, still boots. Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55523 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02nb/intel/haswell/gma.c: Add ULX PCI device IDsAngel Pons
Change-Id: Ida3d2dcdf89342b084c8e1fbf3fae7e47a7238d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50137 Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/acpi: Add IVRS kconfigJason Glenesk
Add new IVRS kconfig option to control IVRS generation. BUG=b:190515051 Change-Id: Iad0c6401dbccd2f3f75464a69e4c27f64d3507a5 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-31arch/x86/acpi: Add code for KEY_MICMUTE and KEY_KBDILLUMTOGGLEScott Chao
Chromebook have some platform need support MICMUTE and KBDILLUMTOGGLE. BUG=b:194146863 BRANCH=none TEST=check on evtest type 4 (EV_MSC), code 4 (MSC_SCAN), value ab type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), 1 type 4 (EV_MSC), code 4 (MSC_SCAN), value 9b type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1 Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Ic39ecb3118e885c9e6d84d7b78bf435cb903d17e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-07-31mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0msstanley.wu
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:187801363 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.corp-partner.google.com>
2021-07-31soc/amd/common/block/gpio_banks: use unsigned int for gevent parameterFelix Held
A valid GEVENT number is never negative. The local variable in set_single_gpio still needs to be a signed integer, since the return value of get_gpio_gevent being -1 indicates that the GPIO can't generate a GEVENT. The check for that makes the function return before calling program_smi of program_sci, so the parameter of those functions can be changed to unsigned. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add missing newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I87595aea45bb3852a70c7322eae5a94abecb76a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56704 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add comment in check_gpiosFelix Held
Each bit in the GPIO wake status index registers is set to 1 when at least one of 4 corresponding GPIO pins has its wake status register set. Added the comment since the gpio_base + i * 4 in the next line looked as if it calculates some absolute register value which is not what the code does or should be doing. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: use size_t where neededFelix Held
Since the parameter the variable gets compared with is size_t type, use size_t as type for that variable too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30MAINTAINERS: Remove Aaron DurbinTim Wawrzynczak
Aaron is no longer employed at Google and is not actively working on coreboot anymore, therefore remove this account from MAINTAINERS. Change-Id: Ife7c75ab8290873da1e02332609482c407373c45 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-30soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbersFelix Held
With the addition of the remote GPIO support, the GPIO number won't fit into 8 bit any more, so use the gpio_t type instead which is an uint32_t typedef. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/gpio_banks/gpio: factor out set_gpio_muxFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: drop unused GPIO bank definesFelix Held
The offsets of all GPIOs in the up to four regular banks are all calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to tableFelix Held
GPIO bank 3 isn't used in coreboot, but the existence is documented in both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and for those two SoCs all 4 banks are covered by the corresponding Memory32Fixed region in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01Ronak Kanabar
The headers added are generated as per FSP v2265_01. Previous FSP version was v2237_00. Changes Include: - Add Irms UPD in FspsUpd.h - Adjust Reserved UPD Offset in FspsUpd.h - Few UPDs description update in FspmUpd.h BUG=b:194032028 BRANCH=None TEST=Build and boot brya Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f Cq-Depend:chrome-internal:4004482 Cq-Depend:chrome-internal:4003608 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56511 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30mb/google/brya/variants/primus: Disable PCIe6Malik_Hsu
WWAN (fibocom L850-GL) works in USB mode, so turn off PCIe 6. BUG=b:194861116 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ie04a5bb2af9ce11f57339f460a7f880bfc14b688 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-29mb/google/dedede/var/cappy2: Add I2C devicesSunwei Li
Add tp and audio devices support in devicetree. BUG=b:193099842 BRANCH=dedede TEST=i2c devices function is OK Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I995e93b5a4c4294d6f6b97c48d14fabf48004d92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56513 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai
Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-29mb/google/brya: add BASEBOARD_DIR to support different baseboardZhuohao Lee
In order to support different baseboard configuration, we add the BASEBOARD_DIR to switch the directory. The expected structure looks like: mb ..|_ google .........|_ brya .............. |_ variants .....................|_ baseboard ..............................|_ brya ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ..............................|_ brask ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ......................|_ brya_variant1 ......................|_ brya_variant2 ......................|_ ... ......................|_ brask_variant1 ......................|_ brask_variant2 ......................|_ ... ...............|_ <all mb common code> BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-29mb/google/dedede: Configure VCCIOSEL for EN_SPKR GPIO PadKarthikeyan Ramasubramanian
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Storo. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ibd3bc90bd0bbc9a35922b29e3d1e106321bc7a06 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56616 Reviewed-by: Evan Green <evgreen@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh
Latency Tolerance Reporting is yet another PCIe power management feature which can have a bad influence on realtime performance. Disable this feature for all PCIe root ports. Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh
L1 substates of a PCIe link are meant to save some power when the link is not active but have the drawback that the PCIe latency is increased as PLLs are switched on and off as needed. In order to get a better realtime performance, disable all substates for every PCIe root port. Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driverWerner Zeh
This variant uses I210 MACPHYs so enable the I210 driver in order to set the needed MAC addresses. In addition add the function to retrieve a valid MAC address for the given MACPHY. Change-Id: Id1d59349db1b86cfdd71bbe27577c0530e8f0b51 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56567 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable Siemens NC-FPGA driverWerner Zeh
All the boards based on the mc_ehl baseboard have the NC-FPGA available. Enable the appropriate driver on baseboard level. Change-Id: I40b76a837b7ddb70ceba3135996b1c1080170c4d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56566 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable SIEMENS_HWILIBWerner Zeh
All variants based on mc_ehl will use the Siemens HWILIB. Select the Kconfig switch on baseboard level. Change-Id: I940f84a4a7449487fe78c793f8dbb1c1b49fa54b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56565 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Enable In Band ECCWerner Zeh
Enable IBECC for mc_ehl1 to provide a memory failure protection. Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable System Agent dynamic frequency supportWerner Zeh
In favor of better realtime performance disable dynamic frequency support in the System Agent for mc_ehl1. Change-Id: I0e62bcf2e5efa97d89bf7192f1536747a02ad992 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56563 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable measured bootWerner Zeh
Enable measured boot for all boards based on mc_ehl baseboard. Change-Id: I3aff943305c024d1f25d2127e6f60495828da3eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-29mb/siemens/mc_ehl: Enable LPC TPMWerner Zeh
All the boards based on the mc_ehl baseboard have a TPM which is connected to SPI but mapped into the address space of the x86 so that it acts like a LPC attached TPM. Enable the TPM driver so that it will be used. In addition add the needed entry in devicetree. Change-Id: I301d0ed4a108bac45d95eced120e7ba280945d9c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-29mb/siemens/mc_ehl: Add external RTC RX6110SAWerner Zeh
All the mainboards based on mc_ehl use the external RTC RX6110SA. Enable the driver in Kconfig for all boards based on mc_ehl. In addition, as mc_ehl1 has the RTC attached to the SMBus, add the devicetree entry on behalf of the SMBus device 00:1f.4 for this variant. Change-Id: Ie1f45d0e6f9063c00253fe58a6268d40de91cf63 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56523 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29arch/x86/thread: Add #error when compiling for x86_64Raul E Rangel
The x86 thread code is all x86_32 specific. It needs to be updated to work with 64 bit. For now just throw an error when compiling. BUG=b:179699789 TEST=none Suggested-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I96187ad84bdec40c6883748afa41e217bc389b79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-29mb/google/dedede/var/storo: Set the xHCI LFPS period sampling off time to 0msTao Xia
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:193898133 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ic84dc83b749cf3c6029a06730096b64ef8cb8cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-29commonlib: Add timestamp strings for TS_FSP_MULTI_PHASE_SI_INIT_xSubrata Banik
TEST=Refer to `cbmem -t` output below: Without this code changes, timestamp ids 962 and 963 are listed as `unknown`. 962:<unknown> 1,704,863 (157) 963:<unknown> 1,704,878 (14) With this code changes, lists the timestamps along with the timestamp strings. 962:calling FspMultiPhaseSiInit 1,704,863 (157) 963:returning from FspMultiPhaseSiInit 1,704,878 (14) Change-Id: I528567e4cc630e15dffffd1c7684798fcdde4535 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56641 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/google/dedede/var/pirika: Configure I2C times to 380-400 kHz for touchpadAlex1 Kao
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Audio codec:388.91 kHz Touchpad:394.48 kHz BUG=b:193864546 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: Ia57c90ead44ceb0990878dc0566e595bae5a9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56383 Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/intel/ehlcrb: Select LPSS console by defaultLean Sheng Tan
Select `INTEL_LPSS_UART_FOR_CONSOLE` to allow using PCH UART 2 as coreboot console. Also, simplify `UART_FOR_CONSOLE` defaults. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I853777116fc541e5dc31f3ca8673f8bf66c7c9e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-29soc/intel/elkhartlake: Update UART clock divider paramsLean Sheng Tan
As EHL UART source clock is 120MHz, update the clock divider parameters (M & N) to reflect the right value. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-28util/xcompile: Allow overriding default compiler pathPatrick Georgi
When looking for C compilers, xcompile uses the "" prefix to "gcc" and "clang" as a last-resort option. This fails in environments where such default names are blocked to prevent "unclean" builds - such as Chrome OS. Allow overriding this prefix using the GENERIC_COMPILER_PREFIX variable that is hopefully both descriptive enough to suggest what it is for and unusual enough to not trigger by chance. Change-Id: I16239f66730f1dbcb7482f223cea4ee5957af10c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-28mb/google/brya/var/kano: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B H54G46CYRBX267 H54G56CYRBX247 K4U6E3S4AB-MGCL K4UBE3D4AB-MGCL BUG=b:194766276 b:194686484 b:194765811 TEST=build Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iba019c50224be8322865eee7baf81e3a574ff9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28util/spd_tools/lp4x: Add new memory parts and generate SPDsDavid Wu
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for ADL: 1. H54G46CYRBX267 2. H54G56CYRBX247 3. K4U6E3S4AB-MGCL 4. K4UBE3D4AB-MGCL BUG=b:194686484 b:194765811 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28mb/google/volteer/variants/drobit: Add Charger Performance Control table ↵Wayne3 Wang
TCHG for DPTF setting. Add Charger Performance Control table TCHG for DPTF setting. BUG=b:194256990 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by thermal team. Change-Id: I9dba3f0e75d07d8ee9656bd1ee8d6de2d3b8c152 Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Paul F Yang <paul.f.yang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
2021-07-28Update chromeec submodule to upstream mainPatrick Georgi
Updating from commit id 1e800ac83: 2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD) to commit id 4c21b57eb: 2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions) This brings in 3145 new commits. Change-Id: Iff2e9f766e750070d71644c2f9895ad10e8b1c9a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56431 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28Update arm-trusted-firmware submodule to upstream integrationPatrick Georgi
Updating from commit id 96404aa27: 2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration) to commit id 586aafa3a: 2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration) This brings in 207 new commits. Change-Id: Iaf8af5ffaf377070ee1430ed7cfdc51001a1ba6b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56416 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28mb/google/brya/variants/primus: Update NVMe clkMalik_Hsu
According to the schematic diagram of proto, modify the clock of nvme from the baseboard default to src0. BUG=b:194487277 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I41be517b434513bca2332ec37e54f56910302bb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-28Revert "soc/intel/common/block/gpio: Add support to program VCCIO selection"Karthikeyan Ramasubramanian
This reverts commit 4c569b52f6053fc39cb07eed4a0753ade567c5b6. This has introduced a regression in mainboards using JSL SoC such that it overrides the soft straps for all the GPIOs. This in turn has led to some of the peripherals not working. BUG=None TEST=Build and boot to OS in Storo. Ensure that the regressed peripherals are working back again. Change-Id: Ibfeed1075fe28051b926ddd7ca771693dc19dae8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56613 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28Revert "soc/intel/jasperlake: Enable support to program VCCIO selection"Karthikeyan Ramasubramanian
This reverts commit 16f2c5082c92ceb4defc252819aaeca96d801543. Change-Id: Id0f960fdeca5895afc22809ff3f0236d6dbe82f4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56614 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28Revert "mb/google/dedede: Program VCCIO selection for EN_SPKR GPIO"Karthikeyan Ramasubramanian
This reverts commit ce79ceec86a38145b3a27aa4c78cf83a76cd51d0. This has introduced a regression in mainboards using JSL SoC such that it overrides the soft straps for all the GPIOs. This in turn has led to some of the peripherals not working. Change-Id: Ifea5d4d0f474873f8bf4818ec1986e534f455216 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56615 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28ec/roda/it8518/acpi: Remove unnecessary assignmentsFelix Singer
Simplify some operations to get rid of unnecessary assignments. Change-Id: I02c93d42ce1de693d5d58fd9a29ccd5bff0f5978 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-28ec/roda/it8518/acpi: Use lower-case hex formatFelix Singer
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I9f08b048d41ab7a5d7d7dc735779ea019517491a Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56608 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28ec/roda/it8518/acpi: Use mathematical operatorsFelix Singer
Use mathematical operators instead of their equivalent methods. Change-Id: I5b1d5d9882eae5e8bcf2d97bcefaeea1a7ad8f4d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56607 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28ec/roda/it8518/acpi: Use bit-wise and logical operatorsFelix Singer
Use bit-wise and logical operators instead of their equivalent methods. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I30807e14b2a9a8203a76d418f586423bcaec2a3a Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-28ec/roda/it8518/acpi: Make use of the assignment operatorFelix Singer
Replace `Store()` with the assignment operator. Change-Id: I2931a3e1b9a55198ec4dacc9218b6c9028052631 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Get rid of `Index()`Felix Singer
Use `FOOO[1337]` instead of `Index(FOOO, 1337)`. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I4f5d5cb8ce8c3ae37dc44ca87bd67596af9feee8 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Use decimal integers for accessing indexesFelix Singer
Change-Id: I7d4fb69a223e3b48a790e9144d2682619c18d513 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Make use of `Printf("...")`Felix Singer
Replace `Store("...", Debug)` with `Printf("...")`. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: Ie1a1f7320ef2850e4f861b1426240e6940036844 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Don't hard-code GPE offsetNico Huber
The GPE offset of 16 is PCH specific. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I4ec38fc28d2436f84a090bb4ab38f20612cfd795 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28mb/google/dedede/var/magolor: Add custom Wifi SAR for magisterDavid Wu
Add wifi sar for magister. Due to fw-config cannot distinguish between magolor and magister. Using sku_id to decide to load magister custom wifi sar. BUG=b:192290227 TEST=build and test on magolor/magister Cq-Depend: chrome-internal:3986580 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4510cc2ad42a11ec802ecd439b353f8e87d63868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28soc/intel/jsl: Add disable_external_bypass_vr configSimon Yang
This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake. BUG=b:191691430 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28soc/intel/jasperlake: add pcie modphy settingsJamie Chen
This patch adds device tree settings to control pcie modphy tuning FSP UPDs. With this patch, the pcie modphy can be tuned per board. BUG=b:192716633 BRANCH=NONE TEST=build dedede variant coreboot with fw_debug enable and check if these settings have been changed successfully on fsp debug log. Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off time ↵Tao Xia
to 0ms LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:191426542 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chiasheng Lee <chiasheng.lee@intel.com>
2021-07-28mb/google/volteer/var/collis: Update DPTF parameters for DVT buildFrankChu
Update Passive Policy and TCHG parameters. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id75bfa74ba353f2342c95bcf8d73cd83c957deb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56512 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZEArthur Heymans
This symbol is only used in generating a default fmap. Change-Id: I8d92eba9978cdad5795b0f5755e1d75db7b3cb2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-07-28vc/mediatek/mt8195: Improve DRAM stability by impedance trackingRyan Chuang
Enable the impedance tracking for channel 2 and channel 3. The impedance tracking can compensate the settings of impedance when the temperature changes. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-27include/acpi/acpi.h: add comment about raw data in generic error statusFelix Held
Since the specification isn't very clear on this, add a comment about the optional raw data part of a acpi_generic_error_status block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6df7d2f216fe0515e89d08c8ed01f06d19461429 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-27cpu/x86/mp_init: don't wait between INIT and SIPI for X86_AMD_INIT_SIPIFelix Held
Since current AMD SoCs don't need some wait time between INIT and SIPI, we can skip the 10ms wait there, which improves the boot time a bit. before: CPU_CLUSTER: 0 init finished in 632 msecs after: CPU_CLUSTER: 0 init finished in 619 msecs mpinit still works on Mandolin and all CPU cores show up and are usable. This also doesn't change the binary in a timeless build for boards/SoCs that don't select X86_AMD_INIT_SIPI which I verified for lenovo/x230. BUG=b:193885336 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e044776f45021742a88a5e369a74383c1baaab6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26soc/amd/common/block/acpimmio: add Kconfig option for biosram accessorsFelix Held
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c is only used on Stoneyridge and the old amd/southbridge code and not on Picasso or Cezanne. It also only builds as a 32 bit binary and breaks when trying to build as a 64 bit binary, since the size of an uintptr_t is different on those two. There is no support for using the 32 bit binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP with 64 bit coreboot, so not building this for FSP-based SoC support moves us one step closer to be able to build coreboot as 64 bit binary for Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 09:50:29 +0000