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The PMC is accessed via sideband registers, so the PCI device is not
needed.
Disabling it solves a bug where the laptop cannot be powered on
without the charger connected.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I78f4aa4567dfc154ef5cb21f8746265259cd53e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64451
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF is not used, so disable the corresponding PCI device.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9e4a3bada13dcabc1af3e1e5b3c215939f8239fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Remove the subsystem device ID for HDA devices, so that the correct
Intel [8086:xxxx] is used. This was an old workaround for Windows
that is no longer required with a new driver.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I63d6a4b0f19d400d683cab5dacca787d6c6a0fdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Set S3 assertion time to 28000us as this is sufficient time for
rails to discharge.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4a14e7b30bb1fc4c0c1d3ff2f75069863458487f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64447
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The USB ports use both OC0 and OC1. Whilst they work perfectly with
OC_SKIP, set them to the correct pins.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If173b443d9770083d76519b854b513d8e47b9e71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The OC pin was set to 0, which isn't connected. All USB ports are
connected to OC1.
This solves a strange issue where the Lite can't be powered on without
the charger connected.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I700ddde291f0e4be6e3787e2da13f6d3ece736b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Based on the constraints for CML.
Fixes the following warnings in Linux on system76/oryp8 and
system76/gaze16, which have an NVIDIA GPU on the bridge.
pcieport 0000:00:01.0: can't derive routing for PCI INT A
pcieport 0000:00:01.0: can't derive routing for PCI INT B
This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack trace on every boot and on S3 suspend.
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000fb84c354>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: Ibc968aaa7bf0259879097ff69d2543dcfa2e5e4b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Correct empty tcss port to meet Moli's schematic design.
BUG=b:233834605
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Id16744655010e246c8ca8d1050f71a6c6c63d2a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable SaGv support for Banshee
BUG=b:233930777, b:233703655
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I22810f422e3f1d6dd1f64d93e6d7aff5593ff739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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This gives a warning when there's a period at the end of the commit
subject line.
Change-Id: If95bef3ba01e0ac13ce18045928081040abef4fd
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Checkpatch was looking for a 65 character length, but format-patch adds
the text "Subject: [PATCH] " before the actual subject. Checkpatch
needs to account for that when looking at the line length.
Lines 2863 & 2864 have their indentation fixed as well.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f2ee6e0f1b14ae6393ed7e64ba1266aa9debc7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The commit message wasn't being parsed because there's no filename
associated with it in the patch output. This change adds the "filename"
for the commit message in Gerrit for any errors that have a line number
but no filename.
calculations is intentionally misspelled as cacluations as a test.
Change-Id: Ie7a2ef06419c7090c8e44b3b734b1edf966597cc
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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In the last coreboot leadership meeting, the doxygen documentation was
declared to be dead. Remove it.
Doxygen style comments can still be added to files, and we may generate
doxygen based documentation, but it won't be for the entire project, but
instead just for those individual areas where it is being maintained.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8983a20793786a18d2331763660842fea836aa2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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With CBFS verification, cbfstool (CB:41121) needs bootblock to be
present in coreboot.pre in order to locate the metadata hash stored in
it. Therefore we have to ensure that bootblock is added to CBFS before
other CBFS files are added.
To solve the problem, create the 'add_bootblock' function, and call it
in the coreboot.pre recipe. Because bootblock.bin is now a prerequisite
of coreboot.pre, it will get built even if CONFIG_BOOTBLOCK_IN_CBFS=n.
BUG=b:233263447
TEST=emerge-guybrush coreboot
TEST=emerge-corsola coreboot chromeos-bootimage
TEST=cbfstool image-kingler.bin print -v
TEST=Kingler booted successfully
BRANCH=none
Change-Id: I385deb8231e44310ee139c3f69f449e75b92b2be
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the mainboard starlabs/laptop/tgl, since
it is obsolete now.
Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the following mainboards, since it is
obsolete now.
* siemens/chili
* starlabs/laptop/cml
Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Move the Kconfig option `FSP_HYPERTHREADING` to common Intel Kconfig so
that it can be reused by other SoCs. Since not all SoCs support
hyperthreading, make it conditional on `HAVE_HYPERTHREADING`. SoCs
supporting hyperthreading need to select it so that `FSP_HYPERTHREADING`
is available.
Change-Id: I892d48b488cbf828057f0e9be9edc4352c58bbe7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add support for Alder Lake as a separate parsing profile, copying the
existing 'Cannon' profile and adjusting for differences in reset mapping
and GPIO macro generation.
TEST=Generate GPIO macros for MSI PRO Z690-A
Change-Id: I5871394bcb0636c2c803607ffb129441aa934417
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Moli has USBA port4 but Brask didn't use the port4,
so enable USBA port4 in moli.
BUG=b:232656163
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I5308e3102ea9f0718802596a235c0a5cc42e30bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Add WiFi SAR table for mithrax.
BUG=b:231491014
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I847debd7c817225b5b1777c798a14ef10aee3471
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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On Guybrush, the power and lid switches are managed by the EC
and coreboot and the AP have no control over them within this
context. Remove unused GPIO's to prevent coreboot warnings
about resampling at boot.
BUG=b:233771033
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1c68fce817a2a98ce0e8f1d9771d6c630dd5e88a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The HDMI port was specified as a display port. Update to allow
for testing of 4k streaming.
BUG=b:229771029
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ib4dc8a5c6110630cea768f81e34fd7b0a5a62657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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On Skyrim, the power and lid switches are managed by the EC
and coreboot and the AP have no control over them within this
context. Remove unused GPIO's to prevent coreboot warnings
about resampling at boot.
BUG=b:233771163
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie369bb7d430bd0dd1f1c1f41bf543a9b18e34db1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64644
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Guybrush, there wasn't a need for a sleep GPIO table.
Remove the TODO and filler table and function to reduce
unnecessary function calls/overhead. Missed changes
to variant.h in initial commit(already merged)
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idba1a9eeea5ea5f5922281668ec17c4f065a654d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64643
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch skips sending DISCONNECT IPC command to PMC if system resumes
from S3.
coreboot notice DISCONNECT IPC command getting timedout during S3
resume if system has AC connected behind Type-C hub. This impacts
system resume time. Please refer TA# 730910 for more information.
coreboot need not send the DISCONNECT IPC command when system resumes
from S3 state.
TEST=Verified system boots to OS and verfied below tests on Gimble
1. coreboot doesn't send the DISCONNECT during S3 resume
2. After S3 resume, system detects the pen drive with Superspeed
3. After system resumes from S3, hot-plug the pen drive, system detects
the pen drive
3. System sends IPC commands when system boots from S0 or S5.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6ad006ae8677919c7dfeca8eec0af11454a2e89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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In order to meet the OEM's acoustic specifications, the pre-wake
randomization time (DPA) is set to 100.
BUG=b:232892200
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I65e3fef581ee06fa049e831f246da1328a08518c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The FSP includes a UPD to set the DPA (Dynamic Periodicity
Alteration) PreWake value, which can be used to set the maximum
pre-wake randomization time in "micro-ticks". This patch adds
support for configuring that value.
BUG=b:228410327
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I08897c590a88aba058cb9e364185ea0794e1e7c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3dfc5862fdcc663d9e0adbfda30c940d43b49b4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Tiger Lake SoC PCI device list.
BUG=none
TEST=Able to build and boot volteer, google board.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27a2f31aa706c4d76e9f0db202422bc129368959
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Separate and add LPDDR4X MT53E2G32D4NQ-046 WT:C support for burnet/esche
ID#1: MICRON - MT53E2G32D4NQ-046 WT:C
BUG=b:225121354
BRANCH=none
TEST=1. emerge-jacuzzi coreboot
2. power on test ok
Change-Id: If720d7bcf185c5c0149a82125ec068fc75e5b3cd
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64069
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SCP core 2 is enabled for MT8195 camera feature. It requires the same
register access permission as SCP core 1. Therefore, we configure the
same domain ID for both cores.
BRANCH=cherry
BUG=b:193814857
TEST=cherry boot ok
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Change-Id: Idf335593936b12c083c926a252fa99c3b76cda6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64575
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed or inserted.
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Id6ee977fbda3118229677aa76e5394f5592c3da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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All targets now use cbmem for the BERT region, so the implementation can
be common.
This also drops the obsolete comment about the need to have bert in a
reserved region (cbmem gets fixed to be in a reserved region).
Change-Id: I6f33d9e05a02492a1c91fb7af94aadaa9acd2931
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I54b01b1974822c155cb49634fff8616326d55705
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Currently the BSP stack overflows into the next AP stack. This symbols
needs to be a power of 2 for alignment on the legacy smp init codepath.
This fixes cpu_info on AP #1 build being broken due to stack overflow.
Change-Id: Ib59d354beabc8877f09f768004ced22234ec7d72
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This removes the need to align BERT so that TSEG remains aligned.
Change-Id: I21b55a87838dcb4bd4099f051ba0a011a4d41eea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6c5b3f83b66a2d54611ada3cb97ddda4b655d00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64606
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Chausie and Majolica boards use S0ix which is mutually exclusive
with S3, so don't select HAVE_ACPI_RESUME.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d1bf33ad017dfbf908e0a195949998668c8e137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64605
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Do this for consistency, while followup will remove the index
completely.
Change-Id: I7b4822c3909801e91627ed2ffe776d65dfab08d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add support for MB level dll tuning.
This patch sets the eMMC dll tuning parameters to default values needed.
There was issue observed on some eMMC devices which failed to boot in
HS400 mode.EV team suggested the intermediate eMMC dll tuning parameters
that needs to be set. We observed these values helped to fix the issue.
While we get the verified default values set from FSP directly, adding
it here to use it as the custom dll values needed.
BUG=b:230403441
TEST=Build and boot nivviks board. Verify the eMMC dll parameters are
overridden.
[INFO ] usha: After override dll_params
[INFO ] usha: emmc_tx_cmd_cntl=505
[INFO ] usha: emmc_tx_data_cntl1=909
[INFO ] usha: emmc_tx_data_cntl2=1c2a2828
[INFO ] usha: emmc_rx_cmd_data_cntl1=1c1b1d3c
[INFO ] usha: emmc_rx_cmd_data_cntl2=10049
[INFO ] usha: emmc_rx_strobe_cntl=11515
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I27771b663ce9808e5a5ef4b36c136ad78f924376
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Set custom_pld of each USB port (both Type A and C) with actual
physical location values.
BUG=b:214025396
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ic84b9aae1501e36c2794382aabcf8225eef7783b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Won Chung <wonchung@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Since the FIT pointer is patched at runtime there is no guarantee that
the pre-defined one will match the patched one. Add a check and print a
warning at runtime if both addresses (pre-defined and patched) do not
match as in this case an offline computed hash for the bootblock will
differ from the runtime one.
Change-Id: Ib1b02ec43af183caa9f5b08b3c485879b423c40f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Before TXE releases the CPU out of reset a pointer to the constructed
FIT in SRAM is patched into the loaded bootblock at offset 4G - 64B.
Since this patched bootblock gets measured during runtime it will not
match the one that is potentially measured from the coreboot image.
This patch adds a dedicated fit.c file for Apollo Lake where the FIT
pointer is already set to the address TXE will be using at runtime.
Test=Compare sha256 sum from coreboot runtime and coreboot.rom of the
bootblock and make sure they match.
Change-Id: Ia0fd2a19517c70f50ef37e6a2dc2408bae28df10
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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On Apollo Lake the bootblock is stitched into the IBBL IFWI region at
build time. At execution time TXE loads this IBBL into a shared SRAM
(which is read-only in this phase) and maps it at 4 GiB - 32 KiB. Then
the CPU starts to operate from this shared SRAM as it were flash space.
In order to provide a reliable CRTM init, the real executed bootblock
code needs to be measured into TPM if VBOOT is selected. This patch adds
the needed code to do this.
Change-Id: Ifb3f798de638a85029ebfe0d1b65770029297db3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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On platforms where the bootblock is not included in CBFS anymore
(because it is part of another firmware section (IFWI or a different
CBFS), the CRTM measurement fails.
This patch adds a new function to provide a way at SoC level to measure
the bootblock. Following patches will add functionality to retrieve the
bootblock from the SoC related location and measure it from there.
In this way the really executed code will be measured.
Change-Id: I6d0da1e95a9588eb5228f63151bb04bfccfcf04b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Remove the stop pin declaration for LAN. Confirmed with LAN vendor,
8111K do not need to implement stop pin. It caused S0ix fail.
BUG=b:231400227
TEST=Build and suspend_stress_test -c 5 pass
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iae33068c4622f91d5cebb867e4b10f3834ce8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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add USBC0_RETIMER into 2, 3 bits for usb retimer.
BUG=b:232486478
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idaf2e53387476d344d2c838a6e762f5a4c582989
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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This will replace LOG_{MEM/IO}_RESOURCE macros once
the new resource constructors are available.
Change-Id: I21b030dc42dcb8e462b29f49499be5fd31ea38f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add the boot flash MMIO window to the resources to report this region as
reserved to the OS. This is done to stay consistent with the reserved
memory ranges by coreboot and make the OS aware of them.
As x86 systems preserves the upper 16 MiB below 4G for BIOS flash
decoding use the complete window for reporting independent of the
actually used SPI flash size. This will block the preserved MMIO window.
Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Follow the Thermal_paramters_list-0520.xlsx to modify DPTF baseline PL1
values.
1. Modify baseline PL1 min_power from 15000 to 12000.
2. Modify baseline PL1 max_power from 17000 to 25000.
BUG=b:231380286
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibd3098ee6bbf964cffddfcc9a4600cb7d81162d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Nivviks
Add DPTF passive and critical policies for ADL-N Nivviks design.
Temperature threshold for triggering Passive Policy is set to 75C and Critical Policy is set to 85C respectively for TSR0/1.
BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board.
Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy.
Change-Id: I5c9b9e8c2489c7da501ca136e2aa6fbc764bf400
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64466
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board
Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Set PCH TSN link speed to 1 Gbps and enable MultiVC for all TSN
ports.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8d43c3ba8f02645c8ad2993f76e610d838b0151a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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All non x86 platforms use bootblock in FMAP (see Makefile.inc). Add a
build time check for that so that all the other possibilities (CBFS or
other places for the bootblock) are dropped at build time.
Change-Id: Ic18336a0b79b5d319c2cdfecb7e1eeb89d241206
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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On some platforms the bootblock is not placed in cbfs, but embedded
inside another binary that loads in into DRAM/SRAM.
e8217b11f1 (Kconfig: Add an option to skip adding a cbfs bootblock on
x86) removed adding a cbfs file containing the bootblock in that case.
Change-Id: Id47ecedbc8713ebd5d9814f1c4faf43c52780447
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the kuldax variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:233380254
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KULDAX
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I95c04768bbed8657d2858bcd66fc041f56910b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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1. Add wifi sar table for volmar
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
BUG=b:233319626
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I09069bbc3a41b66ec9a88cfede46acc067209b01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Updating from:
f4bbf5a Apollo Lake MR10 FSP
Updating to:
c607bab Whitley&CedarIsland: Fix link issue with newer toolchains
This brings in 10 new commits:
* c607bab Whitley&CedarIsland: Fix link issue with newer toolchains
* 08c041d Alder Lake - P IoT FSP PV
* a3dc6c6 Alder Lake - P IoT FSP PV
* 2cedeba Alder Lake - S IoT FSP MR1
* 72266f6 Elkhart Lake MR3 FSP
* 48d4c23 Tiger Lake - IoT FSP 4391_03
* e86327d Alder Lake - S IoT FSP PV
* 478a80a Whitley FSP 2.2.0.3A
* cb94d31 Whitley FSP 2.2.0.3A
* d678813 Alder Lake - S IoT FSP PV
Change-Id: I2473bfa5718676e5b6c90b76a3b817cd9f55da4b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Also known as "SeaGRUB", running GRUB2 atop SeaBIOS proves to be a
useful configuration, since SeaBIOS has improved its hardware
compatibility. For example, some USB drive can work under SeaBIOS but
do not work under native GRUB2, and GRUB2 can use BIOS call (provided
by SeaBIOS) as a fallback method to access hardware if it is present.
But more option is added addition to "SeaGRUB": now GRUB2 and SeaBIOS
can be built as secondary payloads, and "SeaGRUB" is now implemented
as "Primary SeaBIOS + Secondary GRUB2 (selected) + config files".
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ie681fa231abfe4a8f1e4510b3c17957550a9d2f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id5eb4823399088746a34721a9855bbaf5f97b7b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Timestamp '2000-00-00 00:00:00' is considered as the invalid format.
Enable RTC to fix incorrect timestamp format in the eventlog.
BUG=b:232035991
TEST=check the timestamp field in /var/log/eventlog.txt
Change-Id: I8d9822075377734ef4a609ddeee79385fe7af0f0
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
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This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Alder Lake SoC PCI device list.
BUG=none
TEST=Able to build and boot taeko, google board.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Since the fast SPI controller is hidden on Apollo Lake the OS cannot
probe it and is therefore unaware of the reserved resources assigned in
coreboot. Select 'FAST_SPI_GENERATE_SSDT' to enable SSDT creation to
report the reserved resources to the OS.
Change-Id: I23e77a0a01141dc4f299988d19509e6df555a654
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Currently no smihandler uses heap.
coreboot's heap manager also is quite limited in what it will
free (only the latest alloc). This makes it a bad idea to use it inside
the smihandler, as depending on the alloc usage the heap might actually
be full at some point, breaking the smihandler.
This also reduces the ramstage by 448 bytes on google/vilboz.
Change-Id: I70cd822be17c1efe13c94a9dbd2e1038808b9c56
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Disable RAPL for all mainboards based on mc_ehl for stable real time
mode of CPUs.
Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR
register are cleared.
Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.
On Elkhart Lake the way via setting relevant MSR bits does not work.
Therefore the way via MCHBAR is choosen.
Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.
Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The feature request was moved to Skyrim in the interest of time
and effort. The bug was updated to reflect this, and the comment
should be removed from the monkey island code base
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Id4ca43692aa56b6dba2f7acc1f924b30c1e966ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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On Guybrush, there wasn't a need for a sleep GPIO table.
Remove the TODO and filler table and function to reduce
unnecessary function calls/overhead.
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic51ee4845d663acf34f050f7b3abf57a7c247c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The HD audio controller of the GPU on bus A device 0 function 1 wasn't
enabled, so it didn't get resources assigned. Enable it to fix this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9a4129ce594c5dd59f70e855fef5f2c04ebb9c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ACP device on bus A device 0 function 5 wasn't enabled, so it didn't
get resources assigned. Enable the ACP device to fix this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc9376314213e9d624756519f703d508411cb1bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64553
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The crypro device on bus A device 0 function 2 wasn't enabled, so it
didn't get resources assigned resulting in this the Linux kernel error:
[ 38.582036] pci 0000:04:00.2: attach allowed to drvr ccp [internal device]
[ 38.582064] ccp 0000:04:00.2: enabling device (0000 -> 0002)
[ 38.582175] ccp 0000:04:00.2: ioremap failed
[ 38.582178] ccp 0000:04:00.2: initialization failed
[ 38.582181] ccp: probe of 0000:04:00.2 failed with error -12
Enable the crypto device to fix this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia812df6e59f3767dcbaa908fa620b62619590f85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64552
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are three external Marvell PHY 88E1512 on this mainboard. The PHY
IRQ comes with a falling edge but the EHL MAC side needs a rising edge
signal. For that reason, we need an inversion of the IRQ polarity.
Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY. The inverting can be activated via
devicetree parameter.
Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed or inserted.
BUG=b:233159811
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Icf609c647e19914684a93c89022f2cd4888a67ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I37d31598e87e5b625ded3186980e3aba7dcf6440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Hook Timer8254ClkSetting to `legacy_8254_timer` cmos option. If that
isn't set, fallback to the `USE_LEGACY_8254_TIMER` Kconfig option.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f91cc2c8f48e9da47399059386092314b631b08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
H9JCNNNBK3MLYR-N6E
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ibb111cddc00a0d066ef9792d974a6e4ad263cc99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I780e2765059ad7473fe5f33c50dd0d8a561151fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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If the SPI controller is hidden from the OS (which is default on Apollo
Lake) then OS has no chance to probe the device and therefore can not be
aware of the resources this PCI device occupies. If the OS needs to move
some resources for a reason it can happen that the new allocated window
will be shadowed by the hidden PCI device resource and hence causing a
conflict. As a result this MMIO window will be inaccessible from the OS
which will cause issues in applications. For instance on Apollo Lake
this causes flashrom to stop working.
This patch adds a SSDT extension for the PCI device if it is hidden from
the OS and reports the occupied resource via ACPI to the OS. For the
cases where the device is hidden later at coreboot runtime and therefore
is not marked as hidden in the PCI device itself a Kconfig switch called
'FAST_SPI_GENERATE_SSDT' is introduced. It defaults to 'no' and can be
set from SOC code to override it.
Since there is no defined ACPI ID for the fast SPI controller available
now, the generic one (PNP0C02) is used.
Test: Boot mc_apl4 and make sure flashrom works again.
Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ib5770f02a6d524417be6723f7f70aa80d9452f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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If the LTE USB DB is connected, enable LTE-related settings.
Otherwise, disable LTE-related settings.
BUG=b:229938024, b:229048361, b:229040345
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I37719cee48370a04534067aa64a3aa77e453948a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Enable SaGv support for crota
BUG=b:229600878
TEST=FW_NAME=crota emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ibc06ef19e9fbbc91ef650a4ac060ce2b7c5c25d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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To make sure daughter board LTE existing, we update probe to DB ports
value of FW_CONFIG field, (https://partnerissuetracker.corp.google.com/issues/226910787#comment11)
as well as, refer to Google Henry and Ivan comments (https://partnerissuetracker.corp.google.com/issues/226910787#comment14)
BRANCH=dedede
BUG=b:226910787
TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I9ab4412b614ec665fbafc998756b805591982b65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch configures external V1p05/Vnn/VnnSx rails for Nereid
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This patch configures external V1p05/Vnn/VnnSx rails for Nivviks
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If8da0dfe3059087526f74042be3c8b7e4a7ece82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:221461379
TEST=Verify the build for primus board
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I4d7d52bdeafe8b1b55822b5c8d040c94ce1f3878
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The Nvidia GPU supports another function named NBCI (NoteBook Common
Interface), which has some subfunctions which are required for the
Nvidia kernel driver to consume. The specification for this function
comes from the Nvidia GN20 Software Design Guide.
BUG=b:214581763
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The agah variant will include an Nvidia GN20 series GPU, therefore
select the INCLUDE_NVIDIA_GPU_ASL Kconfig to include the respective
ASL code into the DSDT.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Some brya variants will use a GN20 series Nvidia GPU, which requires
quite a bit of ACPI support code to be written for it. This patch
lands a decent bit of the initial code for it on the brya platform,
including:
1) PEG RTD3 methods
2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods)
3) NVOP _DSM method
There will be more support to come later, this is all written to
specifications from the Nvidia Software Design Guide for GN20.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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On some x86 targets it the bootblock is loaded via a different
mechanism, like via the AMD PSP or Intel IFWI. Some payloads need that
pointer so add it to cbfs.
Note that on Intel APL this file is not used, which is why the
bootblock still needs to contain the pointer in the ARCH_X86 part.
It is not worth it to add logic to specifically deal with APL as this is
a legacy feature anyway.
For AMD non-car platform this fixes cbfs access in SeaBIOS.
Change-Id: If46e80e3eed5cc3f59964ac58e507f927fc563c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use defines for a better reading of the code.
Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix
logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN
SGMII as the original intention is to set the PSE TSN phy
interface as RGMII.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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By right if PseTsnGbeSgmiiEnable is disable,
PseTsnGbePhyInterfaceType should use RGMII setting.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If593a5534716a9e93f99cb155fb5e86e12b1df17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to
provide common routine for reading skudid and boardid from Chrome EC.
BUG=b:229052726
TEST=emerge-skyrim coreboot chromeos-bootimage
Check the corresponding directory gets mounted to /run/chromeos-config/v1
Change-Id: I6aff02d29d44e95cd9b9e9485593c81f0d4a4b0e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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The audio codec used by crota has a level-sensitive interrupt,
therefore configure the GPIO pad as level-sensitive.
BUG=b:230418589
TEST=emerge-brya coreboot and verified pass
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I588c21e44b9bb17cd5a48bf5f22465ec328496e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Fix descriptors for USB ports to align with their function and
placement with respect to the schematics.
BUG=N/A
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If57bebf9bffd4616c437ec655b64cab3298ac08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Update the PSP header to set the SOC FW ID to 0x0149 for
this platform
BUG=b:217414563
TEST=Build and verify header is set correctly
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic604ec96560c2d4d89c48c4a27528c5cfe4ca7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I417bab99eeb7ec91fcb39d092d396580ad02ef23
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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