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authorLean Sheng Tan <sheng.tan@9elements.com>2022-05-19 09:55:20 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-05-20 11:21:11 +0000
commite1c385ebe142845012e0a844d798fa7268c1cfd8 (patch)
tree4ed8400c0ea1036f8cb218007c732456becb49aa
parent100514d8c7fdfea17de938cddc63f1457dd3af3a (diff)
mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface type
Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN SGMII as the original intention is to set the PSE TSN phy interface as RGMII. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 9883fd92e4..81f68e2314 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -102,8 +102,6 @@ chip soc/intel/elkhartlake
# TSN GBE related UPDs
register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
register "PchTsnGbeSgmiiEnable" = "1"
- register "PseTsnGbeSgmiiEnable[0]" = "1"
- register "PseTsnGbeSgmiiEnable[1]" = "1"
register "PseDmaOwn[0]" = "Host_Owned"
register "PseDmaOwn[1]" = "Host_Owned"