diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-23 16:06:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-24 22:36:17 +0000 |
| commit | dd7ec09155c8aaa527d070309a8439bff87d2985 (patch) | |
| tree | ce9215d13f1129957758d6d5d2872c78aa17bc8e | |
| parent | 743627fba20e5a7dadb165340391e4afa8ae5996 (diff) | |
soc/amd/stoneyridge: Move BERT into a cbmem region
This removes the need to align BERT so that TSEG remains aligned.
Change-Id: I21b55a87838dcb4bd4099f051ba0a011a4d41eea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/memmap.c | 27 |
2 files changed, 17 insertions, 18 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 7bc5ad9c55..0127ac3cec 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -373,4 +373,12 @@ config DISABLE_KEYBOARD_RESET_PIN functionality isn't disabled, configuring it as an output and driving it as 0 will cause a reset. +config ACPI_BERT_SIZE + hex + default 0x100000 if ACPI_BERT + default 0x0 + help + Specify the amount of DRAM reserved for gathering the data used to + generate the ACPI table. + endif # SOC_AMD_STONEYRIDGE diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 06f80de666..e411aa2ef3 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -13,24 +13,16 @@ #include <soc/iomap.h> #include <amdblocks/biosram.h> -#if CONFIG(ACPI_BERT) - #if CONFIG_SMM_TSEG_SIZE == 0x0 - #define BERT_REGION_MAX_SIZE 0x100000 - #else - /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ - #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE - #endif -#else - #define BERT_REGION_MAX_SIZE 0 -#endif - void bert_reserved_region(void **start, size_t *size) { - if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); - else + if (!CONFIG(ACPI_BERT)) { *start = NULL; - *size = BERT_REGION_MAX_SIZE; + *size = 0; + } else { + *start = cbmem_add(CBMEM_ID_ACPI_BERT, CONFIG_ACPI_BERT_SIZE); + *size = CONFIG_ACPI_BERT_SIZE; + } + printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%zx\n", *start, *size); } void *cbmem_top_chipset(void) @@ -42,13 +34,12 @@ void *cbmem_top_chipset(void) /* 8MB alignment to keep MTRR usage low */ return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); + - CONFIG_SMM_TSEG_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return (uintptr_t)cbmem_top(); } static size_t smm_region_size(void) |