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-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb27
1 files changed, 26 insertions, 1 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index fdd1a78a78..957ab1da72 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -124,11 +124,36 @@ chip soc/intel/jasperlake
register "dptf_enable" = "1"
# Add PL1 and PL2 values
- register "power_limits_config" = "{
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 20,
}"
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 20,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 20,
+ }"
+
+ register "power_limits_config[JSL_N4505_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
+ register "power_limits_config[JSL_N5105_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
+ register "power_limits_config[JSL_N6005_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
# Enable S0ix
register "s0ix_enable" = "1"