soc/intel/jasperlake: Add per-SKU power limits

Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.

BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi

Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>

1 files changed, 26 insertions, 1 deletions

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index fdd1a78a78..957ab1da72 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -124,11 +124,36 @@ chip soc/intel/jasperlake
 	register "dptf_enable" = "1"
 
 	# Add PL1 and PL2 values
-	register "power_limits_config" = "{
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
 		.tdp_pl2_override = 20,
 	}"
 
+	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+	}"
+
+	register "power_limits_config[JSL_N4505_10W_CORE]" = "{
+		.tdp_pl1_override = 10,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "power_limits_config[JSL_N5105_10W_CORE]" = "{
+		.tdp_pl1_override = 10,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "power_limits_config[JSL_N6005_10W_CORE]" = "{
+		.tdp_pl1_override = 10,
+		.tdp_pl2_override = 25,
+	}"
+
 	# Enable S0ix
 	register "s0ix_enable" = "1"