summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/include/device/pci_ids.h1
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb28
-rw-r--r--src/mainboard/google/dedede/variants/blipper/overridetree.cb5
-rw-r--r--src/mainboard/google/dedede/variants/dibbi/overridetree.cb13
-rw-r--r--src/mainboard/google/dedede/variants/drawcia/overridetree.cb5
-rw-r--r--src/mainboard/google/dedede/variants/haboki/overridetree.cb5
-rw-r--r--src/mainboard/google/dedede/variants/kracko/overridetree.cb5
-rw-r--r--src/mainboard/google/dedede/variants/lalala/overridetree.cb13
-rw-r--r--src/mainboard/google/dedede/variants/lantis/overridetree.cb13
-rw-r--r--src/mainboard/google/dedede/variants/madoo/overridetree.cb5
-rw-r--r--src/mainboard/google/dedede/variants/magolor/overridetree.cb13
-rw-r--r--src/mainboard/google/dedede/variants/metaknight/overridetree.cb13
-rw-r--r--src/mainboard/google/dedede/variants/sasukette/overridetree.cb5
-rw-r--r--src/mainboard/google/dedede/variants/shotzo/overridetree.cb13
-rw-r--r--src/mainboard/google/dedede/variants/storo/overridetree.cb13
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb27
-rw-r--r--src/soc/intel/jasperlake/chip.h34
-rw-r--r--src/soc/intel/jasperlake/systemagent.c32
18 files changed, 202 insertions, 41 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 40df090088..418f9e09dc 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4135,6 +4135,7 @@
#define PCI_DID_INTEL_JSL_ID_3 0x4e12
#define PCI_DID_INTEL_JSL_ID_4 0x4e14
#define PCI_DID_INTEL_JSL_ID_5 0x4e24
+#define PCI_DID_INTEL_JSL_ID_6 0x4e28
#define PCI_DID_INTEL_ADL_S_ID_1 0x4660
#define PCI_DID_INTEL_ADL_S_ID_2 0x4664
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 30a971c326..9f747d9b97 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -166,11 +166,37 @@ chip soc/intel/jasperlake
# Enable DPTF
register "dptf_enable" = "1"
- register "power_limits_config" = "{
+ # Power limit config
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 20,
}"
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 20,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 20,
+ }"
+
+ register "power_limits_config[JSL_N4505_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
+ register "power_limits_config[JSL_N5105_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
+ register "power_limits_config[JSL_N6005_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
register "tcc_offset" = "10" # TCC of 90C
# VR config settings
diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
index 518b962fd0..a507dd1461 100644
--- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
@@ -59,11 +59,6 @@ chip soc/intel/jasperlake
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
- register "power_limits_config" = "{
- .tdp_pl1_override = 6,
- .tdp_pl2_override = 20,
- }"
-
register "tcc_offset" = "10" # TCC of 95C
# Enable Acoustic noise mitigation and set slew rate to 1/8
diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
index e3df1f2d17..6cda5862af 100644
--- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
@@ -25,6 +25,19 @@ chip soc/intel/jasperlake
},
}"
+ # Power limit config
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 20,
+ .tdp_pl4 = 60,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 20,
+ .tdp_pl4 = 60,
+ }"
+
# Enable Root Port 3 (index 2) for LAN
# External PCIe port 7 is mapped to PCIe Root Port 3
register "PcieRpEnable[2]" = "1"
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 2eb9d814b9..e90d97ed71 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -64,11 +64,6 @@ chip soc/intel/jasperlake
},
}"
- register "power_limits_config" = "{
- .tdp_pl1_override = 6,
- .tdp_pl2_override = 20,
- }"
-
register "tcc_offset" = "20" # TCC of 85C
# Enable Acoustic noise mitigation and set slew rate to 1/4
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index cffcc9a837..704e4587b8 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -35,11 +35,6 @@ chip soc/intel/jasperlake
},
}"
- register "power_limits_config" = "{
- .tdp_pl1_override = 6,
- .tdp_pl2_override = 20,
- }"
-
register "tcc_offset" = "20" # TCC of 85C
register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0
diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
index 1ce3a8fe67..5e39c884e4 100644
--- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
@@ -65,11 +65,6 @@ chip soc/intel/jasperlake
},
}"
- register "power_limits_config" = "{
- .tdp_pl1_override = 6,
- .tdp_pl2_override = 20,
- }"
-
register "tcc_offset" = "20" # TCC of 85C
device domain 0 on
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index fe3c407d0e..7b849b2509 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -56,7 +56,18 @@ chip soc/intel/jasperlake
},
}"
- register "power_limits_config" = "{
+ # Power limit config
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 12,
+ }"
+
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 12,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
.tdp_pl1_override = 7,
.tdp_pl2_override = 12,
}"
diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
index b67bd97da7..c56840823d 100644
--- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
@@ -72,7 +72,18 @@ chip soc/intel/jasperlake
},
}"
- register "power_limits_config" = "{
+ # Power limit config
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 15,
+ }"
+
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 15,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 15,
}"
diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
index 2260652d22..437c60a5cd 100644
--- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
@@ -54,11 +54,6 @@ chip soc/intel/jasperlake
},
}"
- register "power_limits_config" = "{
- .tdp_pl1_override = 6,
- .tdp_pl2_override = 20,
- }"
-
register "tcc_offset" = "10" # TCC of 95C
# Enable Acoustic noise mitigation and set slew rate to 1/8
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index bb5bf24419..cde69ed9aa 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -95,7 +95,18 @@ chip soc/intel/jasperlake
},
}"
- register "power_limits_config" = "{
+ # Power limit config
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 12,
+ }"
+
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 12,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
.tdp_pl1_override = 7,
.tdp_pl2_override = 12,
}"
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index 75618f4505..e01dee93e8 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -64,7 +64,18 @@ chip soc/intel/jasperlake
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
- register "power_limits_config" = "{
+ # Power limit config
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 12,
+ }"
+
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 12,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 12,
}"
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
index 43a68dbb16..5e4de2ac2a 100644
--- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
@@ -87,11 +87,6 @@ chip soc/intel/jasperlake
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Camera
- register "power_limits_config" = "{
- .tdp_pl1_override = 6,
- .tdp_pl2_override = 20,
- }"
-
register "tcc_offset" = "10" # TCC of 95C
register "xhci_lfps_sampling_offtime_ms" = "0"
diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
index b454e3d2cd..0935457092 100644
--- a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
@@ -40,7 +40,18 @@ chip soc/intel/jasperlake
register "disable_external_bypass_vr" = "1" # Does not support external vnn power rail
- register "power_limits_config" = "{
+ # Power limit config
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 25,
+ }"
+
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 25,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
.tdp_pl1_override = 7,
.tdp_pl2_override = 25,
}"
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 3b1f007f16..1aa2e711a9 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -84,7 +84,18 @@ chip soc/intel/jasperlake
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
- register "power_limits_config" = "{
+ # Power limit config
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 20,
+ }"
+
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 20,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
.tdp_pl1_override = 7,
.tdp_pl2_override = 20,
}"
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index fdd1a78a78..957ab1da72 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -124,11 +124,36 @@ chip soc/intel/jasperlake
register "dptf_enable" = "1"
# Add PL1 and PL2 values
- register "power_limits_config" = "{
+ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 20,
}"
+ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 20,
+ }"
+
+ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+ .tdp_pl1_override = 6,
+ .tdp_pl2_override = 20,
+ }"
+
+ register "power_limits_config[JSL_N4505_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
+ register "power_limits_config[JSL_N5105_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
+ register "power_limits_config[JSL_N6005_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ }"
+
# Enable S0ix
register "s0ix_enable" = "1"
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index e6b8f6805e..b986f18c3a 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -3,6 +3,7 @@
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
+#include <device/pci_ids.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <gpio.h>
#include <drivers/intel/gma/gma.h>
@@ -23,13 +24,44 @@
#define MAX_HD_AUDIO_SNDW_LINKS 4
#define MAX_HD_AUDIO_SSP_LINKS 6
+/* Types of different SKUs */
+enum soc_intel_jasperlake_power_limits {
+ JSL_N4500_6W_CORE,
+ JSL_N6000_6W_CORE,
+ JSL_N5100_6W_CORE,
+ JSL_N4505_10W_CORE,
+ JSL_N5105_10W_CORE,
+ JSL_N6005_10W_CORE,
+ JSL_POWER_LIMITS_COUNT
+};
+
+/* TDP values for different SKUs */
+enum soc_intel_jasperlake_cpu_tdps {
+ TDP_6W = 6,
+ TDP_10W = 10
+};
+
+/* Mapping of different SKUs based on CPU ID and TDP values */
+static const struct {
+ unsigned int pci_did;
+ enum soc_intel_jasperlake_power_limits limits;
+ enum soc_intel_jasperlake_cpu_tdps cpu_tdp;
+} cpuid_to_jsl[] = {
+ { PCI_DID_INTEL_JSL_ID_1, JSL_N4500_6W_CORE, TDP_6W },
+ { PCI_DID_INTEL_JSL_ID_2, JSL_N6000_6W_CORE, TDP_6W },
+ { PCI_DID_INTEL_JSL_ID_3, JSL_N5100_6W_CORE, TDP_6W },
+ { PCI_DID_INTEL_JSL_ID_4, JSL_N4505_10W_CORE, TDP_10W },
+ { PCI_DID_INTEL_JSL_ID_5, JSL_N5105_10W_CORE, TDP_10W },
+ { PCI_DID_INTEL_JSL_ID_6, JSL_N6005_10W_CORE, TDP_10W },
+};
+
struct soc_intel_jasperlake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/* Common struct containing power limits configuration information */
- struct soc_power_limits_config power_limits_config;
+ struct soc_power_limits_config power_limits_config[JSL_POWER_LIMITS_COUNT];
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */
diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c
index fd04be589f..f0e9d44bbb 100644
--- a/src/soc/intel/jasperlake/systemagent.c
+++ b/src/soc/intel/jasperlake/systemagent.c
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <chip.h>
+#include <console/console.h>
#include <device/device.h>
#include <delay.h>
#include <device/pci.h>
@@ -48,6 +50,9 @@ void soc_systemagent_init(struct device *dev)
{
struct soc_power_limits_config *soc_config;
config_t *config;
+ uint16_t sa_pci_id;
+ uint8_t tdp;
+ size_t i = 0;
/* Enable Power Aware Interrupt Routing */
enable_power_aware_intr();
@@ -57,6 +62,29 @@ void soc_systemagent_init(struct device *dev)
mdelay(1);
config = config_of_soc();
- soc_config = &config->power_limits_config;
- set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
+
+ /* Get System Agent PCI ID */
+ sa_pci_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xFFFF;
+
+ if (sa_pci_id != 0xFFFF) {
+ tdp = get_cpu_tdp();
+
+ /* Choose power limits configuration based on the CPU SA PCI ID and
+ * CPU TDP value. */
+ for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) {
+ if (sa_pci_id == cpuid_to_jsl[i].pci_did &&
+ tdp == cpuid_to_jsl[i].cpu_tdp) {
+ soc_config = &config->power_limits_config[cpuid_to_jsl[i].limits];
+ set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
+ break;
+ }
+ }
+ }
+
+ if (i == ARRAY_SIZE(cpuid_to_jsl) || sa_pci_id == 0xFFFF) {
+ printk(BIOS_ERR, "unknown SA ID: 0x%4x, can't find its TDP."
+ " Skipped power limits configuration.\n",
+ sa_pci_id);
+ return;
+ }
}