diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-06 18:45:44 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 17:16:51 +0000 |
| commit | 42914feb1f3c6c90201eb3b1753495f93c759690 (patch) | |
| tree | 6ffb2e1c3619af4e1321fb4ec310e641534adf85 /src/soc/intel | |
| parent | 112ffd764299580218a2b210ddb87c047ba185e4 (diff) | |
soc/intel/apollolake: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I982f669b13f25d1d0e6dfaec2fbf50d3200f74fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/pmutil.c | 14 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 01efaff43a..aec5e2c0db 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -241,4 +241,7 @@ uint8_t *pmc_mmio_regs(void); /* STM Support */ uint16_t get_pmbase(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index fbb2345653..79ece4b2e4 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -237,3 +237,17 @@ void pmc_soc_set_afterg3_en(const bool on) reg32 |= SLEEP_AFTER_POWER_FAIL; write32p(gen_pmcon1, reg32); } + +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON1); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON1), reg_val); +} |