diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-06 18:39:54 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 17:16:32 +0000 |
| commit | 112ffd764299580218a2b210ddb87c047ba185e4 (patch) | |
| tree | 7940c5c73183d8894af965a65a9601232f272b8d /src/soc/intel | |
| parent | b09166d0e62ba8ebe0c27bb7b1e20cac4885aa08 (diff) | |
soc/intel/skylake: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.
Additionally, move the PMCON status bit clear operation to finalize.c
to cover any such chances where FSP-S NotifyPhase requested a global
reset and PMCON status bit remains set.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/pmc.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/pmutil.c | 15 |
4 files changed, 20 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 50215954b9..afa1c02f4d 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -65,6 +65,8 @@ static void pch_finalize_script(struct device *dev) /* Hide p2sb device as the OS must not change BAR0. */ p2sb_hide(); + + pmc_clear_pmcon_sts(); } static void soc_lockdown(struct device *dev) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index f0ce146562..51be0ebbe2 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -189,4 +189,7 @@ static inline int deep_s5_enabled(void) /* STM Support */ uint16_t get_pmbase(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index b9b85c2e8f..61662d2ec5 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -96,7 +96,6 @@ void pmc_soc_init(struct device *dev) config_deep_sx(config->deep_sx_config); /* Clear registers that contain write-1-to-clear bits. */ - pci_or_config32(dev, GEN_PMCON_A, 0); pci_or_config32(dev, GEN_PMCON_B, 0); pci_or_config32(dev, GEN_PMCON_B, 0); setbits32(pwrmbase + GBLRST_CAUSE0, 0); diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index fe26ebfe37..ded44dc85c 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -265,3 +265,18 @@ void pmc_soc_set_afterg3_en(const bool on) reg8 |= SLEEP_AFTER_POWER_FAIL; pci_write_config8(dev, GEN_PMCON_B, reg8); } + +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + const pci_devfn_t dev = PCH_DEV_PMC; + + reg_val = pci_read_config32(dev, GEN_PMCON_A); + /* + * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit + */ + reg_val &= ~(MS4V); + + pci_write_config32(dev, GEN_PMCON_A, reg_val); +} |