diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-08-31 07:29:00 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-09-04 01:16:40 +0000 |
| commit | 2f8b77b76bdbb6e93f1a9ca3c73f9bb38ec55b41 (patch) | |
| tree | 862af999e15ccf9df92701e3d007e2e902132ba7 /src/soc/intel/tigerlake/chip.h | |
| parent | 37c85f0cf54c992d283b5f306ce43b9522c515f2 (diff) | |
tree: Drop unnecessary "true/false" comments
Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 6785ebaaeb..6f0adcc6d0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -285,8 +285,6 @@ struct soc_intel_tigerlake_config { /* Gfx related */ uint8_t SkipExtGfxScan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ @@ -504,29 +502,8 @@ struct soc_intel_tigerlake_config { * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; - - /* - * External Clock Gate - * true = Mainboard design uses external clock gating - * false = Mainboard design does not use external clock gating - * - */ bool external_clk_gated; - - /* - * External PHY Gate - * true = Mainboard design uses external phy gating - * false = Mainboard design does not use external phy gating - * - */ bool external_phy_gated; - - /* - * External Bypass Enable - * true = Mainboard design uses external bypass rail - * false = Mainboard design does not use external bypass rail - * - */ bool external_bypass; /* i915 struct for GMA backlight control */ |