From 2f8b77b76bdbb6e93f1a9ca3c73f9bb38ec55b41 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sat, 31 Aug 2024 07:29:00 +0200 Subject: tree: Drop unnecessary "true/false" comments Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152 Tested-by: build bot (Jenkins) Reviewed-by: Jakub Czapiga Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/chip.h | 23 ----------------------- 1 file changed, 23 deletions(-) (limited to 'src/soc/intel/tigerlake/chip.h') diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 6785ebaaeb..6f0adcc6d0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -285,8 +285,6 @@ struct soc_intel_tigerlake_config { /* Gfx related */ uint8_t SkipExtGfxScan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ @@ -504,29 +502,8 @@ struct soc_intel_tigerlake_config { * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; - - /* - * External Clock Gate - * true = Mainboard design uses external clock gating - * false = Mainboard design does not use external clock gating - * - */ bool external_clk_gated; - - /* - * External PHY Gate - * true = Mainboard design uses external phy gating - * false = Mainboard design does not use external phy gating - * - */ bool external_phy_gated; - - /* - * External Bypass Enable - * true = Mainboard design uses external bypass rail - * false = Mainboard design does not use external bypass rail - * - */ bool external_bypass; /* i915 struct for GMA backlight control */ -- cgit v1.2.3