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authorAngel Pons <th3fanbus@gmail.com>2022-07-16 12:37:38 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-07-18 15:38:14 +0000
commitc7c746c3b2cab52a80719bba39cbdc9ea4babb35 (patch)
tree4cd74dcf44391337949b254f49040828b002b35f /src/soc/intel/meteorlake/include
parent10cd06b1c75e4bc69a1de7e3a70c28ff2e5195fc (diff)
soc/intel/meteorlake: Account for GSPI2 everywhere
Commit e54a8fd43247d767f16a37f3e3150b2915d809bc (soc/intel/meteorlake: Add entry for GSPI2 device) added an entry for the GSPI2 device in the devicetree, but did not add any other entries. Ensure that the rest of the code is aware of the GSPI2 device to avoid any problems. Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0 Found-by: Coverity CID 1490681 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/soc/intel/meteorlake/include')
-rw-r--r--src/soc/intel/meteorlake/include/soc/pci_devs.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h
index b139da4f4f..701faf9d62 100644
--- a/src/soc/intel/meteorlake/include/soc/pci_devs.h
+++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h
@@ -84,8 +84,10 @@
#define PCI_DEV_SLOT_ISH 0x12
#define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0)
+#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6)
#define PCI_DEVFN_UFS _PCI_DEVFN(ISH, 7)
#define PCI_DEV_ISH _PCI_DEV(ISH, 0)
+#define PCI_DEV_GSPI2 _PCI_DEV(ISH, 6)
#define PCI_DEV_UFS _PCI_DEV(ISH, 7)
#define PCI_DEV_SLOT_IOE 0x13