From c7c746c3b2cab52a80719bba39cbdc9ea4babb35 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 16 Jul 2022 12:37:38 +0200 Subject: soc/intel/meteorlake: Account for GSPI2 everywhere Commit e54a8fd43247d767f16a37f3e3150b2915d809bc (soc/intel/meteorlake: Add entry for GSPI2 device) added an entry for the GSPI2 device in the devicetree, but did not add any other entries. Ensure that the rest of the code is aware of the GSPI2 device to avoid any problems. Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0 Found-by: Coverity CID 1490681 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Tarun Tuli --- src/soc/intel/meteorlake/include/soc/pci_devs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/meteorlake/include') diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h index b139da4f4f..701faf9d62 100644 --- a/src/soc/intel/meteorlake/include/soc/pci_devs.h +++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h @@ -84,8 +84,10 @@ #define PCI_DEV_SLOT_ISH 0x12 #define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0) +#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6) #define PCI_DEVFN_UFS _PCI_DEVFN(ISH, 7) #define PCI_DEV_ISH _PCI_DEV(ISH, 0) +#define PCI_DEV_GSPI2 _PCI_DEV(ISH, 6) #define PCI_DEV_UFS _PCI_DEV(ISH, 7) #define PCI_DEV_SLOT_IOE 0x13 -- cgit v1.2.3