diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2022-01-12 12:03:41 -0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2022-01-13 18:04:13 +0000 |
| commit | 577afe62c9c7b736f1f54ee4f0bd622885ce7d9d (patch) | |
| tree | ac9f6c15aa2639798e6273629f4f6e61f5c7c3ce /src/soc/intel/baytrail/placeholders.c | |
| parent | 435e0038257a10971675fe62d9773bb1bf4c23b2 (diff) | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04
The headers added are generated as per FSP v2511_04
Previous FSP version was v2471_02
Changes include:
- UPDs description update in FspsUpd.h and FspmUpd.h
- Adjust UPD Offset in FspmUpd.h
- Name change of UPDs in FspmUpd.h and FspsUpd.h
- Copyright year is updated in FspmUpd.h and FspsUpd.h
- Updated spd_upds and dq_upds structure variables in meminit.c
- Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask
in fsp_params.c
BUG=b:213959910
BRANCH=None
TEST=Build and boot brya
Cq-Depend: chrome-internal:4448696, chrome-internal:4445910
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: I39646c6812afbf622171361b8206daeacdaafac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/placeholders.c')
0 files changed, 0 insertions, 0 deletions