vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04

The headers added are generated as per FSP v2511_04
Previous FSP version was v2471_02
Changes include:
- UPDs description update in FspsUpd.h and FspmUpd.h
- Adjust UPD Offset in FspmUpd.h
- Name change of UPDs in FspmUpd.h and FspsUpd.h
- Copyright year is updated in FspmUpd.h and FspsUpd.h
- Updated spd_upds and dq_upds structure variables in meminit.c
- Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask
  in fsp_params.c

BUG=b:213959910
BRANCH=None
TEST=Build and boot brya

Cq-Depend: chrome-internal:4448696, chrome-internal:4445910
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: I39646c6812afbf622171361b8206daeacdaafac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

4 files changed, 146 insertions, 104 deletions

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 2ab896500d..99ea2b4b35 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -663,7 +663,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 	for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
 		fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]);
 
-	s_cfg->LpmStateEnableMask = get_supported_lpm_mask();
+	s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
 
 	/* Apply minimum assertion width settings */
 	if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT)
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 44071db59b..52a816f596 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -123,14 +123,14 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
 {
 	uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
-		[0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, },
-		[1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, },
-		[2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, },
-		[3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, },
-		[4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, },
-		[5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, },
-		[6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, },
-		[7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, },
+		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
+		[1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, },
+		[2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, },
+		[3] = { &mem_cfg->MemorySpdPtr030, &mem_cfg->MemorySpdPtr031, },
+		[4] = { &mem_cfg->MemorySpdPtr100, &mem_cfg->MemorySpdPtr101, },
+		[5] = { &mem_cfg->MemorySpdPtr110, &mem_cfg->MemorySpdPtr111, },
+		[6] = { &mem_cfg->MemorySpdPtr120, &mem_cfg->MemorySpdPtr121, },
+		[7] = { &mem_cfg->MemorySpdPtr130, &mem_cfg->MemorySpdPtr131, },
 	};
 	uint8_t *disable_channel_upds[MRC_CHANNELS] = {
 		&mem_cfg->DisableMc0Ch0,
@@ -179,17 +179,17 @@ static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_dat
 				const struct mb_cfg *mb_cfg, bool auto_detect)
 {
 	void *dq_upds[MRC_CHANNELS] = {
-		&mem_cfg->DqMapCpu2DramCh0,
-		&mem_cfg->DqMapCpu2DramCh1,
-		&mem_cfg->DqMapCpu2DramCh2,
-		&mem_cfg->DqMapCpu2DramCh3,
-		&mem_cfg->DqMapCpu2DramCh4,
-		&mem_cfg->DqMapCpu2DramCh5,
-		&mem_cfg->DqMapCpu2DramCh6,
-		&mem_cfg->DqMapCpu2DramCh7,
+		&mem_cfg->DqMapCpu2DramMc0Ch0,
+		&mem_cfg->DqMapCpu2DramMc0Ch1,
+		&mem_cfg->DqMapCpu2DramMc0Ch2,
+		&mem_cfg->DqMapCpu2DramMc0Ch3,
+		&mem_cfg->DqMapCpu2DramMc1Ch0,
+		&mem_cfg->DqMapCpu2DramMc1Ch1,
+		&mem_cfg->DqMapCpu2DramMc1Ch2,
+		&mem_cfg->DqMapCpu2DramMc1Ch3,
 	};
 
-	const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0);
+	const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0);
 
 	_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!");
 
@@ -200,17 +200,17 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 				const struct mb_cfg *mb_cfg, bool auto_detect)
 {
 	void *dqs_upds[MRC_CHANNELS] = {
-		&mem_cfg->DqsMapCpu2DramCh0,
-		&mem_cfg->DqsMapCpu2DramCh1,
-		&mem_cfg->DqsMapCpu2DramCh2,
-		&mem_cfg->DqsMapCpu2DramCh3,
-		&mem_cfg->DqsMapCpu2DramCh4,
-		&mem_cfg->DqsMapCpu2DramCh5,
-		&mem_cfg->DqsMapCpu2DramCh6,
-		&mem_cfg->DqsMapCpu2DramCh7,
+		&mem_cfg->DqsMapCpu2DramMc0Ch0,
+		&mem_cfg->DqsMapCpu2DramMc0Ch1,
+		&mem_cfg->DqsMapCpu2DramMc0Ch2,
+		&mem_cfg->DqsMapCpu2DramMc0Ch3,
+		&mem_cfg->DqsMapCpu2DramMc1Ch0,
+		&mem_cfg->DqsMapCpu2DramMc1Ch1,
+		&mem_cfg->DqsMapCpu2DramMc1Ch2,
+		&mem_cfg->DqsMapCpu2DramMc1Ch3,
 	};
 
-	const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0);
+	const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0);
 
 	_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!");
 
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
index 191ef276bc..a687eb0ad1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -78,69 +78,85 @@ typedef struct {
 **/
   UINT8                       CpuCrashLogDevice;
 
-/** Offset 0x004C - MemorySpdPtr00
+/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr00;
+  UINT32                      MemorySpdPtr000;
 
-/** Offset 0x0050 - MemorySpdPtr01
+/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr01;
+  UINT32                      MemorySpdPtr001;
 
-/** Offset 0x0054 - MemorySpdPtr02
+/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr02;
+  UINT32                      MemorySpdPtr010;
 
-/** Offset 0x0058 - MemorySpdPtr03
+/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr03;
+  UINT32                      MemorySpdPtr011;
 
-/** Offset 0x005C - MemorySpdPtr04
+/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr04;
+  UINT32                      MemorySpdPtr020;
 
-/** Offset 0x0060 - MemorySpdPtr05
+/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr05;
+  UINT32                      MemorySpdPtr021;
 
-/** Offset 0x0064 - MemorySpdPtr06
+/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr06;
+  UINT32                      MemorySpdPtr030;
 
-/** Offset 0x0068 - MemorySpdPtr07
+/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr07;
+  UINT32                      MemorySpdPtr031;
 
-/** Offset 0x006C - MemorySpdPtr08
+/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr08;
+  UINT32                      MemorySpdPtr100;
 
-/** Offset 0x0070 - MemorySpdPtr09
+/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr09;
+  UINT32                      MemorySpdPtr101;
 
-/** Offset 0x0074 - MemorySpdPtr10
+/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr10;
+  UINT32                      MemorySpdPtr110;
 
-/** Offset 0x0078 - MemorySpdPtr11
+/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr11;
+  UINT32                      MemorySpdPtr111;
 
-/** Offset 0x007C - MemorySpdPtr12
+/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr12;
+  UINT32                      MemorySpdPtr120;
 
-/** Offset 0x0080 - MemorySpdPtr13
+/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr13;
+  UINT32                      MemorySpdPtr121;
 
-/** Offset 0x0084 - MemorySpdPtr14
+/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr14;
+  UINT32                      MemorySpdPtr130;
 
-/** Offset 0x0088 - MemorySpdPtr15
+/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
 **/
-  UINT32                      MemorySpdPtr15;
+  UINT32                      MemorySpdPtr131;
 
 /** Offset 0x008C - RcompResistor settings
   Indicates  RcompResistor settings: Board-dependent
@@ -152,69 +168,85 @@ typedef struct {
 **/
   UINT16                      RcompTarget[5];
 
-/** Offset 0x0098 - DqsMapCpu2DramCh0
+/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0
+  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
 **/
-  UINT8                       DqsMapCpu2DramCh0[2];
+  UINT8                       DqsMapCpu2DramMc0Ch0[2];
 
-/** Offset 0x009A - DqsMapCpu2DramCh1
+/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1
+  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
 **/
-  UINT8                       DqsMapCpu2DramCh1[2];
+  UINT8                       DqsMapCpu2DramMc0Ch1[2];
 
-/** Offset 0x009C - DqsMapCpu2DramCh2
+/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2
+  Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
 **/
-  UINT8                       DqsMapCpu2DramCh2[2];
+  UINT8                       DqsMapCpu2DramMc0Ch2[2];
 
-/** Offset 0x009E - DqsMapCpu2DramCh3
+/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3
+  Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
 **/
-  UINT8                       DqsMapCpu2DramCh3[2];
+  UINT8                       DqsMapCpu2DramMc0Ch3[2];
 
-/** Offset 0x00A0 - DqsMapCpu2DramCh4
+/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0
+  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
 **/
-  UINT8                       DqsMapCpu2DramCh4[2];
+  UINT8                       DqsMapCpu2DramMc1Ch0[2];
 
-/** Offset 0x00A2 - DqsMapCpu2DramCh5
+/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1
+  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
 **/
-  UINT8                       DqsMapCpu2DramCh5[2];
+  UINT8                       DqsMapCpu2DramMc1Ch1[2];
 
-/** Offset 0x00A4 - DqsMapCpu2DramCh6
+/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2
+  Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
 **/
-  UINT8                       DqsMapCpu2DramCh6[2];
+  UINT8                       DqsMapCpu2DramMc1Ch2[2];
 
-/** Offset 0x00A6 - DqsMapCpu2DramCh7
+/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3
+  Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
 **/
-  UINT8                       DqsMapCpu2DramCh7[2];
+  UINT8                       DqsMapCpu2DramMc1Ch3[2];
 
-/** Offset 0x00A8 - DqMapCpu2DramCh0
+/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0
+  Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
 **/
-  UINT8                       DqMapCpu2DramCh0[16];
+  UINT8                       DqMapCpu2DramMc0Ch0[16];
 
-/** Offset 0x00B8 - DqMapCpu2DramCh1
+/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1
+  Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
 **/
-  UINT8                       DqMapCpu2DramCh1[16];
+  UINT8                       DqMapCpu2DramMc0Ch1[16];
 
-/** Offset 0x00C8 - DqMapCpu2DramCh2
+/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2
+  Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependet
 **/
-  UINT8                       DqMapCpu2DramCh2[16];
+  UINT8                       DqMapCpu2DramMc0Ch2[16];
 
-/** Offset 0x00D8 - DqMapCpu2DramCh3
+/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3
+  Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
 **/
-  UINT8                       DqMapCpu2DramCh3[16];
+  UINT8                       DqMapCpu2DramMc0Ch3[16];
 
-/** Offset 0x00E8 - DqMapCpu2DramCh4
+/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0
+  Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
 **/
-  UINT8                       DqMapCpu2DramCh4[16];
+  UINT8                       DqMapCpu2DramMc1Ch0[16];
 
-/** Offset 0x00F8 - DqMapCpu2DramCh5
+/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1
+  Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
 **/
-  UINT8                       DqMapCpu2DramCh5[16];
+  UINT8                       DqMapCpu2DramMc1Ch1[16];
 
-/** Offset 0x0108 - DqMapCpu2DramCh6
+/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2
+  Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
 **/
-  UINT8                       DqMapCpu2DramCh6[16];
+  UINT8                       DqMapCpu2DramMc1Ch2[16];
 
-/** Offset 0x0118 - DqMapCpu2DramCh7
+/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3
+  Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
 **/
-  UINT8                       DqMapCpu2DramCh7[16];
+  UINT8                       DqMapCpu2DramMc1Ch3[16];
 
 /** Offset 0x0128 - Dqs Pins Interleaved Setting
   Indicates DqPinsInterleaved setting: board-dependent
@@ -899,13 +931,18 @@ typedef struct {
 **/
   UINT8                       CpuPcieRpLinkDownGpios;
 
-/** Offset 0x0271 - RpClockReqMsgEnable
+/** Offset 0x0271 - Enable ClockReq Messaging
+  ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default):
+  Enable ClockReq Messaging
+  0:Disable, 1:Enable
 **/
-  UINT8                       RpClockReqMsgEnable[3];
+  UINT8                       CpuPcieRpClockReqMsgEnable[3];
 
-/** Offset 0x0274 - RpPcieThresholdBytes
+/** Offset 0x0274 - PCIE RP Pcie Speed
+  Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
+  4: Gen4 (see: CPU_PCIE_SPEED).
 **/
-  UINT8                       RpPcieThresholdBytes[4];
+  UINT8                       CpuPcieRpPcieSpeed[4];
 
 /** Offset 0x0278 - Selection of PSMI Support On/Off
   0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
@@ -3164,7 +3201,7 @@ typedef struct {
 
 /** Offset 0x0AA8 - Reserved
 **/
-  UINT8                       Reserved45[136];
+  UINT8                       Reserved45[144];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
@@ -3183,11 +3220,11 @@ typedef struct {
 **/
   FSP_M_CONFIG                FspmConfig;
 
-/** Offset 0x0B30
+/** Offset 0x0B38
 **/
   UINT8                       UnusedUpdSpace34[6];
 
-/** Offset 0x0B36
+/** Offset 0x0B3E
 **/
   UINT16                      UpdTerminator;
 } FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
index a73fe59f1e..6e7ebfd922 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -2852,9 +2852,11 @@ typedef struct {
 **/
   UINT8                       CpuPcieRpLtrConfigLock[4];
 
-/** Offset 0x0C38 - RpPtmBytes
+/** Offset 0x0C38 - PTM for PCIE RP Mask
+  Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
+  One bit for each port, bit0 for port1, bit1 for port2, and so on.
 **/
-  UINT8                       RpPtmBytes[4];
+  UINT8                       CpuPcieRpPtmEnabled[4];
 
 /** Offset 0x0C3C - PCIE RP Detect Timeout Ms
   The number of milliseconds within 0~65535 in reference code will wait for link to
@@ -3765,9 +3767,12 @@ typedef struct {
 **/
   UINT8                       PchXhciOcLock;
 
-/** Offset 0x0F55 - LpmStateEnableMask
+/** Offset 0x0F55 - Low Power Mode Enable/Disable config mask
+  Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
+  to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
+  LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
 **/
-  UINT8                       LpmStateEnableMask;
+  UINT8                       PmcLpmS0ixSubStateEnableMask;
 
 /** Offset 0x0F56 - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.