vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04

The headers added are generated as per FSP v2511_04
Previous FSP version was v2471_02
Changes include:
- UPDs description update in FspsUpd.h and FspmUpd.h
- Adjust UPD Offset in FspmUpd.h
- Name change of UPDs in FspmUpd.h and FspsUpd.h
- Copyright year is updated in FspmUpd.h and FspsUpd.h
- Updated spd_upds and dq_upds structure variables in meminit.c
- Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask
  in fsp_params.c

BUG=b:213959910
BRANCH=None
TEST=Build and boot brya

Cq-Depend: chrome-internal:4448696, chrome-internal:4445910
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: I39646c6812afbf622171361b8206daeacdaafac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

2 files changed, 27 insertions, 27 deletions

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 2ab896500d..99ea2b4b35 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -663,7 +663,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 	for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
 		fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]);
 
-	s_cfg->LpmStateEnableMask = get_supported_lpm_mask();
+	s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
 
 	/* Apply minimum assertion width settings */
 	if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT)
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 44071db59b..52a816f596 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -123,14 +123,14 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
 {
 	uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
-		[0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, },
-		[1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, },
-		[2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, },
-		[3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, },
-		[4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, },
-		[5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, },
-		[6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, },
-		[7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, },
+		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
+		[1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, },
+		[2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, },
+		[3] = { &mem_cfg->MemorySpdPtr030, &mem_cfg->MemorySpdPtr031, },
+		[4] = { &mem_cfg->MemorySpdPtr100, &mem_cfg->MemorySpdPtr101, },
+		[5] = { &mem_cfg->MemorySpdPtr110, &mem_cfg->MemorySpdPtr111, },
+		[6] = { &mem_cfg->MemorySpdPtr120, &mem_cfg->MemorySpdPtr121, },
+		[7] = { &mem_cfg->MemorySpdPtr130, &mem_cfg->MemorySpdPtr131, },
 	};
 	uint8_t *disable_channel_upds[MRC_CHANNELS] = {
 		&mem_cfg->DisableMc0Ch0,
@@ -179,17 +179,17 @@ static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_dat
 				const struct mb_cfg *mb_cfg, bool auto_detect)
 {
 	void *dq_upds[MRC_CHANNELS] = {
-		&mem_cfg->DqMapCpu2DramCh0,
-		&mem_cfg->DqMapCpu2DramCh1,
-		&mem_cfg->DqMapCpu2DramCh2,
-		&mem_cfg->DqMapCpu2DramCh3,
-		&mem_cfg->DqMapCpu2DramCh4,
-		&mem_cfg->DqMapCpu2DramCh5,
-		&mem_cfg->DqMapCpu2DramCh6,
-		&mem_cfg->DqMapCpu2DramCh7,
+		&mem_cfg->DqMapCpu2DramMc0Ch0,
+		&mem_cfg->DqMapCpu2DramMc0Ch1,
+		&mem_cfg->DqMapCpu2DramMc0Ch2,
+		&mem_cfg->DqMapCpu2DramMc0Ch3,
+		&mem_cfg->DqMapCpu2DramMc1Ch0,
+		&mem_cfg->DqMapCpu2DramMc1Ch1,
+		&mem_cfg->DqMapCpu2DramMc1Ch2,
+		&mem_cfg->DqMapCpu2DramMc1Ch3,
 	};
 
-	const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0);
+	const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0);
 
 	_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!");
 
@@ -200,17 +200,17 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 				const struct mb_cfg *mb_cfg, bool auto_detect)
 {
 	void *dqs_upds[MRC_CHANNELS] = {
-		&mem_cfg->DqsMapCpu2DramCh0,
-		&mem_cfg->DqsMapCpu2DramCh1,
-		&mem_cfg->DqsMapCpu2DramCh2,
-		&mem_cfg->DqsMapCpu2DramCh3,
-		&mem_cfg->DqsMapCpu2DramCh4,
-		&mem_cfg->DqsMapCpu2DramCh5,
-		&mem_cfg->DqsMapCpu2DramCh6,
-		&mem_cfg->DqsMapCpu2DramCh7,
+		&mem_cfg->DqsMapCpu2DramMc0Ch0,
+		&mem_cfg->DqsMapCpu2DramMc0Ch1,
+		&mem_cfg->DqsMapCpu2DramMc0Ch2,
+		&mem_cfg->DqsMapCpu2DramMc0Ch3,
+		&mem_cfg->DqsMapCpu2DramMc1Ch0,
+		&mem_cfg->DqsMapCpu2DramMc1Ch1,
+		&mem_cfg->DqsMapCpu2DramMc1Ch2,
+		&mem_cfg->DqsMapCpu2DramMc1Ch3,
 	};
 
-	const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0);
+	const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0);
 
 	_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!");