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| author | Duncan Laurie <dlaurie@chromium.org> | 2014-04-22 10:46:06 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-10-22 03:33:20 +0200 |
| commit | d8c4f2b72462f60ae92a59a976437c2407ec6654 (patch) | |
| tree | 3a89c4830ecb16cde242f012a3d72ec81d169948 /src/soc/intel/baytrail/Kconfig | |
| parent | 3511023f341b4416ea61558bd5ecfa2ea8416782 (diff) | |
baytrail: Move MRC cache code to a common directory
This common code can be shared across Intel SOCs.
Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196263
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/baytrail/Kconfig')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index aa55444e02..3915f04d26 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -88,22 +88,6 @@ config MRC_RMT bool "Enable MRC RMT training + debug prints" default n -config CACHE_MRC_SETTINGS - bool "Save cached MRC settings" - default n - -if CACHE_MRC_SETTINGS - -config MRC_SETTINGS_CACHE_BASE - hex - default 0xffb00000 - -config MRC_SETTINGS_CACHE_SIZE - hex - default 0x10000 - -endif # CACHE_MRC_SETTINGS - endif # HAVE_MRC # Cache As RAM region layout: |