baytrail: Move MRC cache code to a common directory

This common code can be shared across Intel SOCs.

Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196263
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

10 files changed, 52 insertions, 35 deletions

diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig
index 3ddbf2841e..d8a5011060 100644
--- a/src/soc/intel/Kconfig
+++ b/src/soc/intel/Kconfig
@@ -1,2 +1,3 @@
 source src/soc/intel/baytrail/Kconfig
 source src/soc/intel/fsp_baytrail/Kconfig
+source src/soc/intel/common/Kconfig
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index aa55444e02..3915f04d26 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -88,22 +88,6 @@ config MRC_RMT
 	bool "Enable MRC RMT training + debug prints"
 	default n
 
-config CACHE_MRC_SETTINGS
-	bool "Save cached MRC settings"
-	default n
-
-if CACHE_MRC_SETTINGS
-
-config MRC_SETTINGS_CACHE_BASE
-	hex
-	default 0xffb00000
-
-config MRC_SETTINGS_CACHE_SIZE
-	hex
-	default 0x10000
-
-endif # CACHE_MRC_SETTINGS
-
 endif # HAVE_MRC
 
 # Cache As RAM region layout:
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index ce1f2433bb..f5c4c9f6e7 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,7 @@
 subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
+subdirs-y += ../common
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/smm
@@ -13,9 +14,6 @@ romstage-y += memmap.c
 ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
 smm-y += tsc_freq.c
-ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
-ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
-romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
 ramstage-y += spi.c
 smm-y += spi.c
 ramstage-y += chip.c
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index a18f312386..d5ee0317f0 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -26,7 +26,7 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <baytrail/gpio.h>
-#include <baytrail/mrc_cache.h>
+#include <soc/intel/common/mrc_cache.h>
 #include <baytrail/iomap.h>
 #include <baytrail/iosf.h>
 #include <baytrail/pci_devs.h>
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
new file mode 100644
index 0000000000..8b02a4a905
--- /dev/null
+++ b/src/soc/intel/common/Kconfig
@@ -0,0 +1,19 @@
+if HAVE_MRC
+
+config CACHE_MRC_SETTINGS
+	bool "Save cached MRC settings"
+	default n
+
+if CACHE_MRC_SETTINGS
+
+config MRC_SETTINGS_CACHE_BASE
+	hex
+	default 0xffb00000
+
+config MRC_SETTINGS_CACHE_SIZE
+	hex
+	default 0x10000
+
+endif # CACHE_MRC_SETTINGS
+
+endif # HAVE_MRC
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
new file mode 100644
index 0000000000..b32255ae42
--- /dev/null
+++ b/src/soc/intel/common/Makefile.inc
@@ -0,0 +1,3 @@
+ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
+ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
diff --git a/src/soc/intel/baytrail/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index f12f3ef0ea..8f0d18f8b3 100644
--- a/src/soc/intel/baytrail/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,7 +24,7 @@
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/fmap.h>
 #endif
-#include <baytrail/mrc_cache.h>
+#include "mrc_cache.h"
 
 #define MRC_DATA_ALIGN           0x1000
 #define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -117,6 +117,7 @@ static int __mrc_cache_get_current(const struct mrc_data_region *region,
 {
 	const struct mrc_saved_data *msd;
 	const struct mrc_saved_data *verified_cache;
+	int slot = 0;
 
 	msd = region->base;
 
@@ -126,12 +127,15 @@ static int __mrc_cache_get_current(const struct mrc_data_region *region,
 	       mrc_cache_valid(region, msd)) {
 		verified_cache = msd;
 		msd = next_cache_block(msd);
+		slot++;
 	}
 
 	if (verified_cache == NULL)
 		return -1;
 
 	*cache = verified_cache;
+	printk(BIOS_DEBUG, "MRC cache slot %d @ %p\n", slot-1, verified_cache);
+
 	return 0;
 }
 
@@ -146,7 +150,10 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache)
 }
 
 #if defined(__PRE_RAM__)
-/* romstage code */
+
+/*
+ * romstage code
+ */
 
 /* Fill in mrc_saved_data structure with payload. */
 static void mrc_cache_fill(struct mrc_saved_data *cache, void *data,
@@ -186,9 +193,13 @@ int mrc_cache_stash_data(void *data, size_t size)
 }
 
 #else
-/* ramstage code */
+
+/*
+ * ramstage code
+ */
+
 #include <bootstate.h>
-#include <baytrail/nvm.h>
+#include "nvm.h"
 
 static int mrc_slot_valid(const struct mrc_data_region *region,
                           const struct mrc_saved_data *slot,
diff --git a/src/soc/intel/baytrail/baytrail/mrc_cache.h b/src/soc/intel/common/mrc_cache.h
index 6791ec4a82..14767e52b3 100644
--- a/src/soc/intel/baytrail/baytrail/mrc_cache.h
+++ b/src/soc/intel/common/mrc_cache.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef _MRC_CACHE_H_
-#define _MRC_CACHE_H_
+#ifndef _COMMON_MRC_CACHE_H_
+#define _COMMON_MRC_CACHE_H_
 
 #include <stddef.h>
 #include <stdint.h>
@@ -37,4 +37,5 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache);
 
 /* Stash the resulting MRC data to be saved in non-volatile storage later. */
 int mrc_cache_stash_data(void *data, size_t size);
-#endif /* _MRC_CACHE_H_ */
+
+#endif /* _COMMON_MRC_CACHE_H_ */
diff --git a/src/soc/intel/baytrail/nvm.c b/src/soc/intel/common/nvm.c
index 0cd42ccd52..791422fe30 100644
--- a/src/soc/intel/baytrail/nvm.c
+++ b/src/soc/intel/common/nvm.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <spi-generic.h>
 #include <spi_flash.h>
-#include <baytrail/nvm.h>
+#include "nvm.h"
 
 /* This module assumes the flash is memory mapped just below 4GiB in the
  * address space for reading. Also this module assumes an area it erased
diff --git a/src/soc/intel/baytrail/baytrail/nvm.h b/src/soc/intel/common/nvm.h
index d0cbf7b0e6..d332d831f7 100644
--- a/src/soc/intel/baytrail/baytrail/nvm.h
+++ b/src/soc/intel/common/nvm.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef _NVM_H_
-#define _NVM_H_
+#ifndef _COMMON_NVM_H_
+#define _COMMON_NVM_H_
 
 #include <stddef.h>
 
@@ -31,4 +31,4 @@ int nvm_erase(void *start, size_t size);
 /* Write data to NVM. Returns 0 on success < 0 on error.  */
 int nvm_write(void *start, const void *data, size_t size);
 
-#endif /* _NVM_H_ */
+#endif /* _COMMON_NVM_H_ */