From d8c4f2b72462f60ae92a59a976437c2407ec6654 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 22 Apr 2014 10:46:06 -0700 Subject: baytrail: Move MRC cache code to a common directory This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/soc/intel/baytrail/Kconfig | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'src/soc/intel/baytrail/Kconfig') diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index aa55444e02..3915f04d26 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -88,22 +88,6 @@ config MRC_RMT bool "Enable MRC RMT training + debug prints" default n -config CACHE_MRC_SETTINGS - bool "Save cached MRC settings" - default n - -if CACHE_MRC_SETTINGS - -config MRC_SETTINGS_CACHE_BASE - hex - default 0xffb00000 - -config MRC_SETTINGS_CACHE_SIZE - hex - default 0x10000 - -endif # CACHE_MRC_SETTINGS - endif # HAVE_MRC # Cache As RAM region layout: -- cgit v1.2.3