diff options
| author | Tracy Wu <tracy.wu@intel.corp-partner.google.com> | 2021-09-27 16:48:32 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-29 10:07:00 +0000 |
| commit | 697d6a81c26b775b166dd9e69a46fe5d2d1843c9 (patch) | |
| tree | d5996ed8409bb94694d15476e10dc9e23be100f1 /src/soc/intel/alderlake/chipset.cb | |
| parent | dee834aafcccf79f9d6c3319ead6212fced004a6 (diff) | |
soc/intel/alderlake: Add ADLP 242 power configurations
Add ADLP 242 sku power related settings, which follow the settings of
ADLP 282 sku (both are 15w).
BUG=b:201253904
TEST=Build and check fsp log to confirm the settings are set properly.
Change-Id: I829dd690c22d167a507b1910106da06b275cec09
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index c89fe6ae06..d70d9390a2 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -37,6 +37,11 @@ chip soc/intel/alderlake .tdp_pl4 = 68, }" + register "power_limits_config[ADL_P_242_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + .tdp_pl4 = 123, + }" device domain 0 on device gpio 0 alias pch_gpio on end |