diff options
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 5 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/vr_config.c | 4 |
4 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 47f6d59bc6..6308094de8 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -27,6 +27,7 @@ enum soc_intel_alderlake_power_limits { ADL_P_682_45W_CORE, ADL_M_282_CORE, ADL_M_242_CORE, + ADL_P_242_CORE, ADL_POWER_LIMITS_COUNT }; @@ -45,6 +46,7 @@ static const struct { enum soc_intel_alderlake_cpu_tdps cpu_tdp; } cpuid_to_adl[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_242_CORE, TDP_15W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index c89fe6ae06..d70d9390a2 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -37,6 +37,11 @@ chip soc/intel/alderlake .tdp_pl4 = 68, }" + register "power_limits_config[ADL_P_242_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + .tdp_pl4 = 123, + }" device domain 0 on device gpio 0 alias pch_gpio on end diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index a92883cb50..8003471128 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -41,6 +41,7 @@ #define MILLIAMPS_TO_AMPS 1000 #define ICC_MAX_ID_ADL_P_3_MA 34250 #define ICC_MAX_ID_ADL_P_5_MA 32000 +#define ICC_MAX_ID_ADL_P_6_MA 32000 #define ICC_MAX_ID_ADL_P_7_MA 32000 /* @@ -305,6 +306,8 @@ static uint16_t get_vccin_aux_imon_iccmax(void) return ICC_MAX_ID_ADL_P_3_MA; case PCI_DEVICE_ID_INTEL_ADL_P_ID_5: return ICC_MAX_ID_ADL_P_5_MA; + case PCI_DEVICE_ID_INTEL_ADL_P_ID_6: + return ICC_MAX_ID_ADL_P_6_MA; case PCI_DEVICE_ID_INTEL_ADL_P_ID_7: return ICC_MAX_ID_ADL_P_7_MA; default: diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index ab84c15a94..2180fc5c8f 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -50,24 +50,28 @@ static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, c static const struct vr_lookup vr_config_ll[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, }; static const struct vr_lookup vr_config_icc[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_ICC(109, 50) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, }; static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, }; static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, }; |