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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-23 13:23:37 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-29 10:06:01 +0000 |
| commit | dee834aafcccf79f9d6c3319ead6212fced004a6 (patch) | |
| tree | bd9b503c240823a32bae7c4c54a6272c9c73ec5c /src/soc/intel/alderlake/chipset.cb | |
| parent | ab0e0813b669c6f2af3c9400e403cb5850a7af92 (diff) | |
mb/google/brya: Update PCH power cycle related durations
The voltage rail discharge times have been measured, so therefore
the boot time on a cold boot when the CSE must go through a global reset
and thus a trip to S5 can be optimized. Select the lowest applicable
value for each PchPmSlp UPD that can be used with these measurements.
This is programmed in the baseboard because the measured discharge times
leave (what should be) plenty of margin for variants to also not violate
any power sequencing guidelines from the PDG.
BUG=b:184799383
TEST=verified time in S5 during a global reset is ~1s instead of 4s
Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
0 files changed, 0 insertions, 0 deletions