diff options
| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-08 12:28:03 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-09 19:08:33 +0000 |
| commit | 66ff4fb1a565fe5f040e893bd02e52fed3ad2771 (patch) | |
| tree | 3ed0fe8c1b0d4837300cca53d5648a575cf7ef13 /src/soc/amd/stoneyridge/acpi | |
| parent | d59c79987df0498de7ee847f41782457a5320141 (diff) | |
soc/amd/stoneyridge: use SoC common uart ops
Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI
_STA in asl since now handled by common SSDT generator. Implement
wait_for_aoac_enabled() since required by SoC common code, and ensure
compiled during all stages necessary.
TEST=build/boot google/liara, verify console UART still functional.
Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/mmio.asl | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/mmio.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl index ef2b4eab62..b6f4fc37a3 100644 --- a/src/soc/amd/stoneyridge/acpi/mmio.asl +++ b/src/soc/amd/stoneyridge/acpi/mmio.asl @@ -47,10 +47,6 @@ Device (FUR0) IRQ (Edge, ActiveHigh, Exclusive) { 10 } Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000) }) - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } } Device (FUR1) { @@ -61,10 +57,6 @@ Device (FUR1) { IRQ (Edge, ActiveHigh, Exclusive) { 11 } Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000) }) - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } } Device (I2CA) { |