From 66ff4fb1a565fe5f040e893bd02e52fed3ad2771 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 8 Aug 2023 12:28:03 -0500 Subject: soc/amd/stoneyridge: use SoC common uart ops Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI _STA in asl since now handled by common SSDT generator. Implement wait_for_aoac_enabled() since required by SoC common code, and ensure compiled during all stages necessary. TEST=build/boot google/liara, verify console UART still functional. Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/acpi/mmio.asl | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src/soc/amd/stoneyridge/acpi') diff --git a/src/soc/amd/stoneyridge/acpi/mmio.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl index ef2b4eab62..b6f4fc37a3 100644 --- a/src/soc/amd/stoneyridge/acpi/mmio.asl +++ b/src/soc/amd/stoneyridge/acpi/mmio.asl @@ -47,10 +47,6 @@ Device (FUR0) IRQ (Edge, ActiveHigh, Exclusive) { 10 } Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000) }) - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } } Device (FUR1) { @@ -61,10 +57,6 @@ Device (FUR1) { IRQ (Edge, ActiveHigh, Exclusive) { 11 } Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000) }) - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } } Device (I2CA) { -- cgit v1.2.3