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authorMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-08-08 12:28:03 -0500
committerFelix Held <felix-coreboot@felixheld.de>2023-08-09 19:08:33 +0000
commit66ff4fb1a565fe5f040e893bd02e52fed3ad2771 (patch)
tree3ed0fe8c1b0d4837300cca53d5648a575cf7ef13 /src
parentd59c79987df0498de7ee847f41782457a5320141 (diff)
soc/amd/stoneyridge: use SoC common uart ops
Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI _STA in asl since now handled by common SSDT generator. Implement wait_for_aoac_enabled() since required by SoC common code, and ensure compiled during all stages necessary. TEST=build/boot google/liara, verify console UART still functional. Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/Makefile.inc1
-rw-r--r--src/soc/amd/stoneyridge/acpi/mmio.asl8
-rw-r--r--src/soc/amd/stoneyridge/aoac.c6
-rw-r--r--src/soc/amd/stoneyridge/chipset_cz.cb2
-rw-r--r--src/soc/amd/stoneyridge/chipset_st.cb2
5 files changed, 11 insertions, 8 deletions
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 33328fa958..5c0a31296b 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -28,6 +28,7 @@ verstage-y += i2c.c
postcar-y += memmap.c
postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
+ramstage-y += aoac.c
ramstage-y += BiosCallOuts.c
ramstage-y += i2c.c
ramstage-y += chip.c
diff --git a/src/soc/amd/stoneyridge/acpi/mmio.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl
index ef2b4eab62..b6f4fc37a3 100644
--- a/src/soc/amd/stoneyridge/acpi/mmio.asl
+++ b/src/soc/amd/stoneyridge/acpi/mmio.asl
@@ -47,10 +47,6 @@ Device (FUR0)
IRQ (Edge, ActiveHigh, Exclusive) { 10 }
Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000)
})
- Method (_STA, 0x0, NotSerialized)
- {
- Return (0x0F)
- }
}
Device (FUR1) {
@@ -61,10 +57,6 @@ Device (FUR1) {
IRQ (Edge, ActiveHigh, Exclusive) { 11 }
Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000)
})
- Method (_STA, 0x0, NotSerialized)
- {
- Return (0x0F)
- }
}
Device (I2CA) {
diff --git a/src/soc/amd/stoneyridge/aoac.c b/src/soc/amd/stoneyridge/aoac.c
index 7c1d12ddc1..505b2c80f6 100644
--- a/src/soc/amd/stoneyridge/aoac.c
+++ b/src/soc/amd/stoneyridge/aoac.c
@@ -21,6 +21,12 @@ static const unsigned int aoac_devs[] = {
FCH_AOAC_DEV_I2C3,
};
+void wait_for_aoac_enabled(unsigned int dev)
+{
+ while (!is_aoac_device_enabled(dev))
+ udelay(100);
+}
+
void enable_aoac_devices(void)
{
bool status;
diff --git a/src/soc/amd/stoneyridge/chipset_cz.cb b/src/soc/amd/stoneyridge/chipset_cz.cb
index a3bd85c19f..004ff9134c 100644
--- a/src/soc/amd/stoneyridge/chipset_cz.cb
+++ b/src/soc/amd/stoneyridge/chipset_cz.cb
@@ -43,4 +43,6 @@ chip soc/amd/stoneyridge
device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
+ device mmio 0xfedc6000 alias uart_0 off ops amd_uart_mmio_ops end
+ device mmio 0xfedc8000 alias uart_1 off ops amd_uart_mmio_ops end
end
diff --git a/src/soc/amd/stoneyridge/chipset_st.cb b/src/soc/amd/stoneyridge/chipset_st.cb
index c78da61766..34a0384e34 100644
--- a/src/soc/amd/stoneyridge/chipset_st.cb
+++ b/src/soc/amd/stoneyridge/chipset_st.cb
@@ -37,4 +37,6 @@ chip soc/amd/stoneyridge
device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
+ device mmio 0xfedc6000 alias uart_0 off ops amd_uart_mmio_ops end
+ device mmio 0xfedc8000 alias uart_1 off ops amd_uart_mmio_ops end
end