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author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-11-21 12:51:20 +0100 |
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committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-06-15 14:14:05 +0000 |
commit | 3d51e833478005196b5e0e01bb60878a76274a3d (patch) | |
tree | ce66d04562804e9a3f056695042c25bc6a8d6345 /src/soc/amd/glinda | |
parent | c68456ee4b03051f24de3cf57cdb8e0ea1be99fb (diff) |
soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bits
Based on:
- Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
- 7th Generation Intel Processor Families I/O for U/Y Platforms
Datasheet Vol.2 August 2017:
https://cdrdv2.intel.com/v1/dl/getContent/334659
- edk2-platforms source for Whitley and Purley platforms (Xeon SP)
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/soc/amd/glinda')
0 files changed, 0 insertions, 0 deletions