diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-11-21 12:51:20 +0100 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-06-15 14:14:05 +0000 |
| commit | 3d51e833478005196b5e0e01bb60878a76274a3d (patch) | |
| tree | ce66d04562804e9a3f056695042c25bc6a8d6345 /src/soc | |
| parent | c68456ee4b03051f24de3cf57cdb8e0ea1be99fb (diff) | |
soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bits
Based on:
- Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
- 7th Generation Intel Processor Families I/O for U/Y Platforms
Datasheet Vol.2 August 2017:
https://cdrdv2.intel.com/v1/dl/getContent/334659
- edk2-platforms source for Whitley and Purley platforms (Xeon SP)
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pmc.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/lbg/include/soc/pmc.h | 5 |
3 files changed, 17 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index dc1419f35a..d86e87da89 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -172,7 +172,12 @@ #define BIOS_PCI_EXP_EN (1 << 10) #define PWRBTN_LVL (1 << 9) #define SMI_LOCK (1 << 4) -#define PER_SMI_SEL (1 << 0) +#define PER_SMI_SEL_MASK (3 << 0) +#define SMI_RATE_64S (0 << 0) +#define SMI_RATE_32S (1 << 0) +#define SMI_RATE_16S (2 << 0) +#define SMI_RATE_8S (3 << 0) + #define GEN_PMCON3 0x1028 #define SLP_S3_ASSERT_WIDTH_SHIFT 10 #define SLP_S3_ASSERT_MASK (0x3 << SLP_S3_ASSERT_WIDTH_SHIFT) diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 165d57170e..50f605f09e 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -35,6 +35,12 @@ #define ALLOW_L1LOW_C0 (1 << 7) #define ALLOW_L1LOW_OPI_ON (1 << 6) #define SMI_LOCK (1 << 4) +#define PER_SMI_SEL_MASK (3 << 0) +#define SMI_RATE_64S (0 << 0) +#define SMI_RATE_32S (1 << 0) +#define SMI_RATE_16S (2 << 0) +#define SMI_RATE_8S (3 << 0) + #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h index d49986339c..88a9b10606 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h @@ -25,6 +25,11 @@ #define MS4V (1 << 18) #define GBL_RST_STS (1 << 16) #define SMI_LOCK (1 << 4) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) |